JP2009252874A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device or the like for preventing disturbance. <P>SOLUTION: The semiconductor device includes at least one transistor of at least one nonvolatile storage cell. At least the one transistor of at least the one nonvolatile storage cell has: a first gate insulating layer 22a'; a gate charge storage layer 22b' having charge storage capability formed on the first gate insulating layer 22a'; and a second gate insulating layer 22c' formed on the gate charge storage layer 22b'. The first charge storage capability of one portion 31 of the gate charge storage layer 22b' is smaller than the second charge storage capability in a remaining section 32 of the gate charge storage layer 22b'. The first charge storage capability of one portion 31 of the gate charge storage layer 22b' is reduced by ion implantation using fluorine gas and/or hydrogen-based gas. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

Nonvolatile memory devices included in a semiconductor device include, for example, a flat-plate MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) and a split-gate MONOS. MONOS is sometimes called SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor). Currently, flat type MONOS has attracted more attention than split gate type MONOS because it leads to simplification of the manufacturing process and reduction in chip size. In the flat type MONOS, generally, an FN (Fowler Nordheim) current is controlled to write / erase charges, and a hot carrier (Hot Carrier) is used to control high energy electrons to change the write / erase state. It is classified into what is realized. MONOS using hot carriers has the advantage of not requiring a high bias compared to MONOS using FN current. Furthermore, MONOS using hot carriers has an advantage that the read current value can be set high and is easy to handle because the equivalent oxide thickness (EOT) is set relatively thin.
A semiconductor device including a nonvolatile memory device (nonvolatile memory area) is disclosed in, for example, Patent Document 1.

In order to improve the reliability of the semiconductor device, a dangling bond in the vicinity of the interface (Si-SiO ₂ interface) between the semiconductor substrate (silicon substrate) and the oxide film (silicon oxide film) of the semiconductor device. For example, Patent Literature 2, Patent Literature 3, and Patent Literature 4 disclose a technique for terminating.
JP 2004-296683 A JP 2000-174030 A JP 2006-319186 A JP 07-058313 A

FIG. 1 shows an example of circuit arrangement equivalent to a memory cell of a nonvolatile memory device.
In FIG. 1, source lines SL0 and SL1 and word lines WL0 and WL1 are arranged in parallel. When writing charges (hot electrons) to the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 is connected, for example, the voltage of the bit line BL0 is set to 0 [V], and the voltage of the source line SL1 is set. Is set to 5 [V], and the voltage of the word line WL0 is set to 7 [V]. The voltage of the source line SL0 is set to 0 [V] and the voltage of the word line WL1 is set to 0 [V] so that charges (hot electrons) are not written into the memory cell MC00. The voltage of the bit line BL1 is set to 5 [V] so that charges (hot electrons) are not written in the memory cell MC11. When the voltage of the bit line BL1 is set to 5 [V] and the voltage of the source line SL0 is set to 0 [V], the charge storage layer on the source / drain region side to which the bit line BL1 of the memory cell MC01 is connected is applied. Electric charges (hot holes) are written.

When determining whether or not charges (hot electrons) are written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC01 is connected, for example, the voltage of the bit line BL1 is set to 1 [V]. Then, the voltage of the source line SL0 is set to 0 [V], and the voltage of the word line WL1 is set to 2 [V]. At this time, if charges (hot holes) are written in the charge storage layer on the source / drain region side to which the bit line BL1 of the memory cell MC01 is connected, the reading of the memory cell MC01 cannot be performed normally.
Therefore, when charges (hot electrons) are written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 (selected memory cell) is connected, disturbance to the memory cell MC01 (non-selected memory cell) is disturbed. In order to prevent this, it is necessary to adjust the voltage of the bit line BL1. That is, it is necessary to change the voltage of the bit line BL1 from, for example, 5 [V] to 3 [V] so that no charge (hot hole) is written in the memory cell MC01. Note that if the voltage of the bit line BL1 is too low, there is a problem that charges (hot electrons) are written in the memory cell MC11.

In order to prevent disturbance to the memory cell MC01 (non-selected memory cell) when the charge (hot electron) is written in the memory cell MC10 (selected memory cell) by adjusting the voltage of the bit line BL1 as described above. In addition, the number of voltages used is three (0 [V], 5 [V], 7 [V]) to four (0 [V], 3 [V], 5 [V], 7 [V]) ) Will increase.
Those skilled in the art will appreciate that even in other arrangements not shown in FIG. 1, disturbances to unselected memory cells occur when writing charge to selected memory cells.

  Hereinafter, a plurality of embodiments according to the present invention will be exemplified. Several aspects illustrated below are used in order to understand this invention easily. Thus, those skilled in the art should note that the present invention is not unduly limited by the aspects illustrated below.

A first aspect of the present invention is a semiconductor device,
Including at least one transistor of at least one non-volatile storage cell;
The at least one transistor of the at least one nonvolatile memory cell includes a first gate insulating layer, a gate charge storage layer having a charge storage capability formed on the first gate insulating layer, and the gate. A second gate insulating layer formed on the charge storage layer,
The first charge storage capability of a part of the gate charge storage layer is lower than the second charge storage capability of the remaining part of the gate charge storage layer, and the first charge storage capability of the part of the gate charge storage layer. Relates to a semiconductor device that is lowered by ion implantation using a fluorine-based gas and / or a hydrogen-based gas.
According to the first aspect of the present invention, it is possible to provide a semiconductor device that prevents disturbance.

In the first aspect of the present invention, the at least one transistor of the at least one nonvolatile memory cell includes:
It may have a semiconductor layer,
The first gate insulating layer may be formed on the semiconductor layer,
The semiconductor layer of the at least one transistor may have a first source / drain region connected to the bit line and a second source / drain region connected to the source line,
The part of the gate charge storage layer may be present on the first source / drain region side,
The remaining portion of the gate charge storage layer may be present on the second source / drain region side.

  In the first aspect of the present invention, the first gate insulating layer may be a silicon oxide layer, the gate charge storage layer may be a silicon nitride layer, and the second gate insulating layer may be a silicon oxide layer. Good.

  In the first aspect of the present invention, the remaining portion of the gate charge storage layer may be capable of storing hot carriers.

  In the first aspect of the present invention, the remaining part of the gate charge storage layer may store hot carriers more easily than the part of the gate charge storage layer.

  In the first aspect of the present invention, the dose amount of the dopant in the second source / drain region may be larger than the dose amount of the dopant in the first source / drain region.

A second aspect of the present invention is a semiconductor device,
Including at least one transistor of at least one non-volatile storage cell;
The at least one transistor of the at least one nonvolatile memory cell includes a first gate insulating layer, a gate charge storage layer having a charge storage capability formed on the first gate insulating layer, and the gate. A second gate insulating layer formed on the charge storage layer,
The first defect density of a part of the gate charge storage layer is related to the semiconductor device, which is lower than the second defect density of the remaining part of the gate charge storage layer.

A third aspect of the present invention is a method of manufacturing a semiconductor device,
Preparing a semiconductor layer,
Forming a first insulating layer on the semiconductor layer;
Forming a charge storage layer on the first insulating layer;
Forming a second insulating layer on the charge storage layer;
Forming a conductive layer on the second insulating layer;
A portion of the conductive layer; a portion of the second insulating layer formed under the portion of the conductive layer; and the charge storage formed under the portion of the second insulating layer. A portion of the layer is etched to form the remaining portion of the conductive layer, the remaining portion of the second insulating layer, and the remaining portion of the charge storage layer as a gate conductive layer, a second gate insulating layer, and a gate charge storage layer, respectively. And a resist that exposes a part of the gate conductive layer is formed on at least the remaining part of the gate conductive layer, and the gate charge storage layer formed below the part of the gate conductive layer is formed. Performing ion implantation using fluorine gas and / or hydrogen gas in part,
Including
The remaining portion of the gate charge storage layer relates to a method for manufacturing a semiconductor device, which is easier to store hot carriers than the part of the gate charge storage layer.

In a third aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may have a range from the other end of the gate conductive layer to 1/5 of the gate length of the gate conductive layer.

In a third aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may be in a range from the other end of the gate conductive layer to 1/2 of the gate length of the gate conductive layer.

In a third aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may have a range from the other end of the gate conductive layer to 4/5 of the gate length of the gate conductive layer.

A fourth aspect of the present invention is a method of manufacturing a semiconductor device,
Preparing a semiconductor layer,
Forming a first insulating layer on the semiconductor layer;
Forming a charge storage layer on the first insulating layer;
Forming a second insulating layer on the charge storage layer;
Forming a conductive layer on the second insulating layer;
A portion of the conductive layer; a portion of the second insulating layer formed under the portion of the conductive layer; and the charge storage formed under the portion of the second insulating layer. A portion of the layer 22b is etched to form the remaining portion of the conductive layer, the remaining portion of the second insulating layer, and the remaining portion of the charge storage layer as a gate conductive layer, a second gate insulating layer, and a gate charge storage layer, respectively. To do,
On both sides exposed by the etching of the gate conductive layer, both sides exposed by the etching of the second gate insulating layer, and both sides exposed by the etching of the gate charge storage layer; Forming a third insulating layer; and forming a resist exposing at least a part of the gate conductive layer and the part of the gate conductive layer on at least the remaining part of the gate conductive layer; Performing ion implantation on a part of the gate charge storage layer formed below the part of the layer using a fluorine-based gas and / or a hydrogen-based gas;
Including
The remaining portion of the gate charge storage layer relates to a method for manufacturing a semiconductor device, which is easier to store hot carriers than the part of the gate charge storage layer.

In a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, ion implantation is performed using a fluorine-based gas and / or a hydrogen-based gas for the third insulating layer in contact with the part of the gate charge storage layer. To do,
May be included.

In a fourth aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may have a range from the other end of the gate conductive layer to 1/5 of the gate length of the gate conductive layer.

In a fourth aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may be in a range from the other end of the gate conductive layer to 1/2 of the gate length of the gate conductive layer.

In a fourth aspect of the present invention, a method for manufacturing a semiconductor device includes: a first source / drain region sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; Forming two source / drain regions in the upper layer of the semiconductor layer;
May include
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side. Well,
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side The gate conductive layer may have a range from the other end of the gate conductive layer to 4/5 of the gate length of the gate conductive layer.

  Those skilled in the art will readily understand that the embodiments according to the present invention described above can be modified without departing from the spirit of the present invention. For example, at least one element making up one aspect according to the present invention may be added to another aspect according to the present invention. Alternatively, at least one element constituting one aspect according to the present invention can be recombined with at least one element constituting another aspect according to the present invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Structure of Semiconductor Device FIG. 2A is a schematic view of the structure of the semiconductor device of this embodiment.
FIG. 2A illustrates one transistor of one nonvolatile memory cell, but this embodiment is not limited to this. That is, this embodiment can employ a plurality of transistors. In addition, this embodiment can employ a plurality of nonvolatile memory cells in which each nonvolatile memory cell includes one transistor or a plurality of transistors. In FIG. 2A, a transistor which is a semiconductor device (nonvolatile storage region) includes a first gate insulating layer 22a ′ and a gate having a charge storage capability formed over the first gate insulating layer 22a ′. It has a charge storage layer 22b ′ and a second gate insulating layer 22c ′ formed on the gate charge storage layer 22b.
The first charge storage capability of the portion 31 of the gate charge storage layer 22b ′ is lower than the second charge storage capability of the remaining portion 32 of the gate charge storage layer 22b ′, and the first charge storage capability of the portion 31 of the gate charge storage layer 22b ′. One charge storage capability is reduced by ion implantation using a fluorine-based gas and / or a hydrogen-based gas. As another expression, the first defect density of the part 31 of the gate charge storage layer 22b ′ may be lower than the second defect density of the remaining part 32 of the gate charge storage layer 22b ′. The fluorine-based gas includes not only fluorine (F ₂ ) but also boron fluoride (BF ₂ ), hydrogen fluoride (HF), and the like. The hydrogen-based gas includes not only H ₂ (hydrogen) but also hydrogen chloride (HCl), borohydride (B ₂ H ₆ ), hydrogen phosphide (PH ₃ ), hydrogen fluoride (HF), and the like.

In FIG. 2A, the semiconductor device includes a semiconductor layer 10. The first gate insulating layer 22 a ′ is formed on the semiconductor layer 10. The semiconductor layer 10 includes first source / drain regions 12 'and 18 connected to bit lines (not shown), and second source / drain regions 13' and 19 connected to source lines (not shown). Have A part of the gate charge storage layer 22b ′ (region indicated by the arrow 31) exists on the first source / drain region 12 ′, 18 side, and the remaining part of the gate charge storage layer 22b ′ (region indicated by the arrow 32) is It exists on the second source / drain region 13 ', 19 side. The first source / drain regions 12 ′ and 18 and the second source / drain regions 13 ′ and 19 are formed in the upper layer of the semiconductor layer 10. The first source / drain regions 12 ′ and 18 and the second source / drain regions 13 ′ and 19 are formed in the channel region of the semiconductor layer 10 located below the gate conductive layer 14 ′ in the direction of the gate length of the gate conductive layer 14 ′. Sandwiched between.
Side surfaces of both the first source / drain region 12 ′, 18 side and the second source / drain region 13 ′, 19 side of the gate conductive layer 14 ′, the first source / drain region 12 of the second gate insulating layer 22c ′. ', The side surfaces on both the 18 side and the second source / drain region 13', 19 side, and the first source / drain regions 12 ', 18 side and the second source / drain region 13' on the gate charge storage layer 22b '. The third insulating layers 16 and 17 are formed on both side surfaces on the 19 side. The third insulating layers 16 and 17 are formed on the first gate insulating layer 22a ′.

  The first source / drain regions 12 ′ and 18 are connected to the bit line and the first source / drain extension region 12 ′ formed shallowly in the upper layer of the semiconductor layer 10 on the channel region side, and are connected to the semiconductor on the channel region side. The first source / drain contact region 18 that is deeply formed in the upper layer of the layer 10 may be called separately. The second source / drain regions 13 ′ and 19 are connected to the source line and the second source / drain extension region 13 ′ shallowly formed in the upper layer of the semiconductor layer 10 on the channel region side, and are connected to the semiconductor on the channel region side. It may be called separately from the second source / drain contact region 19 formed deep in the upper layer of the layer 10.

FIG. 2B shows an example of a plan view of the gate charge storage layer 22b ′ of FIG. 2A, and FIG. 2C is a plan view of the gate charge storage layer 22b ′ of FIG. FIG. 2D shows another example of a plan view of the gate charge storage layer 22b ′ shown in FIG.
2B, FIG. 2C, and FIG. 2D are plan views of the gate charge storage layer 22b ′ in FIG. 2A (specifically, with the first gate insulating layer 22a ′. 2 is a plan view of the gate charge storage layer 22b ′ in the vicinity of the interface. A portion 31 of the gate charge storage layer 22b ′ in FIG. 2A corresponds to the black region 31 in FIGS. 2B, 2C, and 2D, and corresponds to the gate in FIG. The remaining portion 32 of the charge storage layer 22b ′ is the entire region 32 of the gate charge storage layer 22b ′ except for the black region 31 of FIGS. 2B, 2C, and 2D, that is, FIG. B), corresponding to the white area 32 in FIG. 2 (C) and FIG. 2 (D).

The black region 31 and the white region 32 do not represent the actual color of the gate charge storage layer 22b ′, and the region 31 and the region in FIG. 2B, FIG. 2C, and FIG. 32 is used to distinguish.
In FIG. 2B, FIG. 2C, and FIG. 2D, the first source / drain is formed on the plane of the gate charge storage layer 22b ′ in the vicinity of the interface with the first gate insulating layer 22a ′. Contact region 18 and second source / drain contact region 19 do not actually exist. The first source / drain contact region 18 and the second source / drain contact region 19 surrounded by a broken line in FIGS. 2B, 2C, and 2D correspond to the first source / drain contact region 18. This is used to describe one end 34 of the gate charge storage layer 22b ′ on the side and the other end 35 of the gate charge storage layer 22b ′ on the second source / drain contact region 19 side. The one end 34 and the other end 35 face each other in the direction of the gate length 33.

  In FIG. 2B, a part 31 of the gate charge storage layer 22b ′ has the entire one end 34 of the gate charge storage layer 22b ′, as shown in FIGS. 2C and 2D. In addition, the part 31 of the gate charge storage layer 22b ′ may have only a part of one end 34 of the gate charge storage layer 22b ′. The part 31 of the gate charge storage layer 22b 'may have a charge storage capability on the first source / drain contact region 18 side lower than the charge storage capability on the second source / drain contact region 19 side.

The fact that the charge storage capability of the gate charge storage layer 22b ′ on the first source / drain contact region 18 side connected to the bit line is reduced means that the voltage of the bit line BL1 in FIG. Even when the charge (hot electrons) is written in the charge storage layer in the source / drain region to which the source line SL1 side of the memory cell MC10 (selected memory cell) is connected without adjusting to 3 [V] from the memory cell MC01. This means that it is difficult for charges (hot holes) to be written in the charge storage layer on the source / drain region side to which the bit line BL1 of the (non-selected memory cell) is connected. That is, the number of voltages used when writing electric charges (hot electrons) to the memory cell MC10 (selected memory cell) is three (0 [V], 5 [V], 7 [V]). However, disturbance to the memory cell MC01 (non-selected memory cell) can be prevented.
Further, in FIG. 1, the voltage used when writing the electric charge (hot electrons) to the memory cell MC10 (selected memory cell) by adjusting the voltage of the bit line BL1 from 5 [V] to 3 [V], for example. Even if the number of memory cells is four (0 [V], 3 [V], 5 [V], 7 [V]), the disturbance to the memory cell MC01 (non-selected memory cell) is more reliably prevented. be able to.

2. Manufacturing Method of Semiconductor Device FIG. 3 is a diagram for explaining the outline of the manufacturing method of the semiconductor device shown in FIG.
First, the semiconductor layer 10 (for example, a (P-type) silicon substrate) is prepared, and the first insulating layer 22 a is formed on the semiconductor layer 10. The first insulating layer 22a is, for example, a silicon oxide layer (for example, a SiO ₂ layer). The SiO ₂ layer is formed by, for example, an oxidation process such as a thermal oxidation process, a CVD (chemical vapor deposition) process, or an anodic oxidation process on a silicon substrate. The thermal oxidation treatment includes, for example, dry oxidation treatment using dry oxygen (O ₂ ) as an oxidizing gas, and steam oxidation using water vapor (H ₂ O) and oxygen containing water vapor or nitrogen (N ₂ ). The temperature range of the thermal oxidation treatment is, for example, 650 ° C to 900 ° C.

Thereafter, the charge storage layer 22b is formed on the first insulating layer 22a. The charge storage layer 22b is, for example, a silicon nitride layer (for example, a Si ₃ N ₄ layer). The Si ₃ N ₄ layer is formed, for example, by a CVD process using ammonia (NH ₃ ) and dichlorosilane (Dichrosilane (DCS), SiH ₂ Cl ₂ ) as reaction gases. In addition, before forming the charge storage layer 22b on the first insulating layer 22a, the first insulating layer 22a may be heat-treated (annealed) in an ammonia atmosphere, for example, at 800 ° C. to 1000 ° C. The dichlorosilane may be changed to, for example, hexachlorodisilane (Hexachlorodisilane (HCD), Si ₂ Cl ₆ ). Specifically, the Si ₃ N ₄ layer may be formed by a CVD process using ammonia and hexachlorodisilane as reaction gases. Also, some the _Si 3 _{N 4} layer (e.g., lower layer) is formed by a first CVD process using ammonia and dichlorosilane, then the remainder the _Si 3 _{N 4} layer (e.g., upper layer) is ammonia and You may form by the 2nd CVD process using hexachlorodisilane.

Thereafter, a second insulating layer 22c is formed on the charge storage layer 22b. The second insulating layer 22c is, for example, a silicon oxide layer (for example, a SiO ₂ layer). The SiO ₂ layer is formed by, for example, a CVD process using dichlorosilane and nitrogen monoxide (NO) as a reaction gas. The SiO ₂ layer formed by the CVD process at a high temperature is sometimes referred to as an HTO (high temperature oxide) layer. Dichlorosilane may be changed to hexachlorodisilane, for example. Nitric oxide may be changed to, for example, nitrogen dioxide (NO ₂ ). Note that after the second insulating layer 22c is formed, the second insulating layer 22c may be heat-treated (annealed) in an oxygen atmosphere or a nitrogen atmosphere, for example, at 800 ° C. to 1000 ° C.

  The total thickness range of the thickness of the first insulating layer 22a, the thickness of the charge storage layer 22b, and the thickness of the second insulating layer 22c is, for example, 100 [Å] to 130 [Å]. If charges are appropriately written (erased) in the charge storage layer 22b, the thickness of the first insulating layer 22a, the thickness of the charge storage layer 22b, and the thickness of the second insulating layer 22c The range of the total thickness is not limited to 100 [Å] to 130 [Å]. When the first insulating layer 22a, the charge storage layer 22b, and the second insulating layer 22c are a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, respectively, the first insulating layer 22a, the charge storage layer 22b, and the second insulating layer 22c The insulating layer 22c is sometimes called an ONO layer.

Thereafter, the conductive layer 14 is formed on the second insulating layer 22c. The conductive layer 14 is, for example, a polysilicon layer (for example, a non-doped polysilicon layer). The non-doped polysilicon layer is formed by, for example, a CVD process using silane (SiH ₄ ) as a reaction gas. Thereafter, a dopant (for example, arsenic) necessary for forming the doped polysilicon layer is ion-implanted into the non-doped polysilicon layer.
The conductive layer 14 may be formed on the second insulating layer 22c as a doped polysilicon layer by a CVD process using silane (SiH ₄ ) and phosphine (PH ₃ ) as reaction gases.

FIG. 4 is another view for explaining the outline of the method for manufacturing the semiconductor device shown in FIG.
Thereafter, a gate conductive layer 14 ′ is formed from the conductive layer 14. The gate conductive layer 14 ′ is formed by, for example, resist processing and dry etching processing. Specifically, a resist (not shown) is applied to the entire surface of the conductive layer 14, a part of the resist (not shown) applied so as to expose a part of the conductive layer 14 is removed, and the conductive A resist (not shown) having an exposed portion that exposes a part of the layer 14 is formed on the remaining portion of the conductive layer 14. The exposed conductive layer 14 is dry-etched using a resist having an exposed portion as a mask. When the exposed conductive layer 14 is removed by dry etching, a part of the second insulating layer 22c is exposed. When the exposed second insulating layer 22c is removed by dry etching, a part of the charge storage layer 22b is exposed. When the exposed charge storage layer 22b is removed by dry etching, a part of the first insulating layer 22a is exposed, and at this time, dry etching is terminated. In practice, the exposed surface of the first insulating layer 22a is also dry etched. By dry etching, as shown in FIG. 4, the gate conductive layer 14 ′, the second gate insulating layer 22c ′ formed under the gate conductive layer 14 ′, and the second gate insulating layer 22c ′ are formed. The formed gate charge storage layer 22b ′ is formed.

Note that dry etching may be terminated when a part of the second insulating layer 22c is exposed. That is, only the gate conductive layer 14 ′ is formed by this dry etching, and a part of the second insulating layer 22c and the charge storage layer 22b (portions unnecessary as the gate insulating layer and the gate charge storage layer) is left temporarily. Also good. In this case, parts of the second insulating layer 22c and the charge storage layer 22b (portions unnecessary as the gate insulating layer and the gate charge storage layer) form the subsequent third insulating layers 16 and 17 (sidewalls). The gate insulating layer and the gate charge storage layer are formed by removing the step.
Alternatively, dry etching may be terminated when a part of the charge storage layer 22b is exposed.
Gate conductive layer 14 ′, second gate insulating layer 22c ′ and gate charge storage layer 22b ′ (or only gate conductive layer 14 ′ and second gate insulating layer 22c ′, or only gate conductive layer 14 ′) When forming, wet etching may be used instead of dry etching.

Thereafter, as shown in FIG. 4, source / drain regions 12 and 13 facing each other are formed in the upper layer of the semiconductor layer 10 with the channel region of the semiconductor layer 10 positioned below the gate conductive layer 14 ′ interposed therebetween. For example, a dopant (for example, arsenic) necessary for forming the source / drain regions 12 and 13 is ion-implanted into the semiconductor layer 10. The angle of ion implantation with respect to the normal of the surface of the semiconductor layer 10 is, for example, approximately 0 degrees. In other words, the angle of ion implantation with respect to the surface of the semiconductor layer 10 is approximately 90 degrees, for example. As indicated by solid arrows in FIG. 4, ion implantation in which the angle of ion implantation is approximately 0 degrees with respect to the normal of the surface of the semiconductor layer 10 is referred to as vertical ion implantation in this specification. As indicated by the dashed arrows in FIG. 4, ion implantation in which the angle of ion implantation with respect to the normal of the surface of the semiconductor layer 10 is less than 90 degrees excluding 0 degrees is referred to as oblique ion implantation in this specification. Arsenic may be changed to phosphorus, for example. In the present embodiment, in order to inject hot carriers into the gate charge storage layer 22b ′, the range of the dopant dose in the source / drain regions 12 and 13 is, for example, 7 × 10 ¹⁴ atoms / cm ² or more.
As shown in FIG. 2A, source / drain regions 18 and 19 are formed under part of the source / drain regions 12 and 13 in the subsequent steps. In FIG. 2A, the source / drain regions 12 and 13 are sometimes referred to as source / drain extension regions. The source / drain regions 18 and 19 are sometimes called source / drain contact regions.

Thereafter, in order to increase the efficiency of hot carrier injection (HCI, Hot Carrier Injection) into the gate charge storage layer 22b ′, a dopant (for example, boron) necessary for adjusting the impurity concentration in the semiconductor layer 10 is added. A part (not shown) of the upper layer of the semiconductor layer 10 located below the gate conductive layer 14 ′, a region located near the source / drain region 12 and a region located near the source / drain region 13. The oblique ion implantation is performed on a part of the upper layer of the semiconductor layer 10 having the same. The range of the angle of oblique ion implantation with respect to the normal of the surface of the semiconductor layer 10 is, for example, 10 degrees to 30 degrees. Such ion implantation is sometimes called Halo (Pocket) ion implantation.
Thereafter, the resist (not shown) having an exposed portion on the gate conductive layer 14 ′ is removed.

FIG. 5 is another view for explaining the outline of the manufacturing method of the semiconductor device shown in FIG.
Thereafter, a resist R is formed at least in a partial region 42 of the gate conductive layer 14 ′. Preferably, the resist R is a partial region 47 of the first insulating layer 22a located above the one of the source / drain regions 13 of the source / drain regions 12 and 13 from the partial region 42 of the gate conductive layer 14 ′. Extend to.
Specifically, the entire surface of the gate conductive layer 14 ′ and the entire surface of the first insulating layer 22a, the entire exposed side surfaces of the gate conductive layer 14 ′, and the exposed second gate insulating layer 22c ′ are exposed. A resist (not shown) is applied to both the entire side surfaces and both exposed side surfaces of the gate charge storage layer 22b ′. Thereafter, a part of the gate conductive layer 14 ′ (the remaining region 41 of the gate conductive layer 14 ′ excluding the partial region 42) and a part of the first insulating layer 22a (the first insulation excluding the partial region 47). Part of the applied resist (not shown) is removed so that the remaining region 46) of the layer 22a is exposed. As a result, a part (41) of the gate conductive layer 14 ', a part (46) of the first insulating layer 22a, and one of the gate conductive layers 14' on the part (41) side of the gate conductive layer 14 ' Side surface, one side surface of the second gate insulating layer 22c ′ on the side (41) side of the gate conductive layer 14 ′, and one side of the gate charge storage layer 22b ′ on the side (41) side of the gate conductive layer 14 ′ The resist R having an exposed portion that exposes the side surfaces of the gate conductive layer 14 ′ is the remaining portion (42) of the gate conductive layer 14 ′, the remaining portion (47) of the first insulating layer 22a, and the gate on the remaining portion (42) side of the gate conductive layer 14 ′. The other side surface of the conductive layer 14 ', the other side surface of the second gate insulating layer 22c' on the remaining portion (42) side of the gate conductive layer 14 ', and the gate charge accumulation on the remaining side (42) side of the gate conductive layer 14' Formed on the other side of layer 22b '. The remaining part (42) of the gate conductive layer 14 ′ is the entire region of the gate conductive layer 14 ′ except for a part (41) of the gate conductive layer 14 ′.

  Thereafter, using the resist R having an exposed portion as a mask, vertical ion implantation using, for example, fluorine (fluorine gas in a broad sense) is performed on at least a part (41) of the gate conductive layer 14 '. A part (41) of the exposed gate conductive layer 14 'is located on the source / drain region 12 side. The remaining part (42) of the gate conductive layer 14 'covered with the resist R is located on the source / drain region 13 side.

The second gate insulating layer is interposed through a part (41) of the gate conductive layer 14 ′ and a part of the second gate insulating layer 22c ′ formed under the part (41) of the gate conductive layer 14 ′. Vertical ion implantation using fluorine is performed with energy reaching a part of the gate charge storage layer 22b ′ formed under a part of 22c ′. Specifically, the position where the distribution of implanted fluorine ions is maximized in the normal direction of the surface of the semiconductor layer 10 is the interface between the first insulating layer 22a and the gate charge storage layer 22b ′ (for example, Vertical ion implantation of fluorine ions so that a trap level is formed in the gate charge storage layer 22b ′ in the vicinity of the SiO ₂ —Si ₃ N ₄ interface) (hereinafter referred to as a trap position 48). Determine the energy of time. The large number of dangling bonds present at the trap position 48 near the interface between the first insulating layer 22a and the gate charge storage layer 22b ′ on which the vertical ion implantation using fluorine is partially performed Terminated by In addition, since the number of dangling bonds existing at the trap position 48 near the SiO ₂ —Si ₃ N ₄ interface is very large, all of the dangling bonds existing at the trap position 48 are completely terminated. Really impossible.

  Since the dangling bond existing at the trap position 48 near the interface between the first insulating layer 22a and the gate charge storage layer 22b ′ in which the vertical ion implantation using fluorine is performed is partially terminated, The ability to store charges (hot holes, hot electrons) in the gate charge storage layer 22b ′ on the source / drain region 12 side to which the bit line of one memory cell is connected is reduced. On the other hand, the ability to store charges in the gate charge storage layer 22b 'on the source / drain region 13 side to which the source line of the memory cell of FIG. That is, vertical ion implantation using fluorine is not performed on the remaining portion (42) of the gate conductive layer 14 'located below the resist R. Therefore, a large number of dangling bonds existing at the trap positions near the interface between the first insulating layer 22a and the gate charge storage layer 22b 'where the vertical ion implantation using fluorine is not performed are not terminated. Thereby, the ability to accumulate charges in the gate charge accumulation layer 22b 'on the source / drain region 13 side to which the source line of the memory cell of FIG. 1 is connected is maintained. Thus, the charge storage capability of the part 31 of the gate charge storage layer 22b 'is lower than the charge storage capability of the remaining portion 32 of the gate charge storage layer 22b'.

This is because the source line SL1 of the memory cell MC10 (selected memory cell) is connected without adjusting the voltage of the bit line BL1 from 5 [V] to 3 [V], for example, in FIG. When writing charges (hot electrons) to the charge storage layer on the drain region side, charges (hot holes) are written to the charge storage layer on the source / drain region side to which the bit line BL1 of the memory cell MC01 (non-selected memory cell) is connected. It means that it is difficult to do it. That is, the number of voltages used when writing electric charges (hot electrons) to the memory cell MC10 (selected memory cell) is three (0 [V], 5 [V], 7 [V]). However, disturbance to the memory cell MC01 (non-selected memory cell) can be prevented.
Further, in FIG. 1, the voltage used when writing the electric charge (hot electrons) to the memory cell MC10 (selected memory cell) by adjusting the voltage of the bit line BL1 from 5 [V] to 3 [V], for example. Even if the number of memory cells is four (0 [V], 3 [V], 5 [V], 7 [V]), the disturbance to the memory cell MC01 (non-selected memory cell) is more reliably prevented. be able to.

  Incidentally, FIG. 2 and paragraph [0045] of Patent Document 2 (Japanese Patent Laid-Open No. 2000-174030) disclose a capacitive insulating film 11 made of ONO. Paragraph [0045] of Patent Document 2 is a stack of FIG. It only discloses hydrogen annealing the entire type DRAM. In other words, hydrogen reaches the capacitive insulating film 11 uniformly. Further, paragraph [0005] of Patent Document 2 discloses that dangling bonds of a silicon nitride film are not terminated by hydrogen annealing.

  FIG. 1 and paragraph [0054] of Patent Document 3 (2006-319186) show a silicon oxide film (first insulating film 3) -silicon nitride film (charge holding film 4) -silicon oxide film (second insulating film 5). However, paragraph [0061] of Patent Document 3 merely discloses that the moisture contained in the third insulating film 11 is diffused by heat treatment. In other words, moisture uniformly reaches the silicon nitride film (charge holding film 4). Further, paragraph [0061] of Patent Document 3 implies that dangling bonds of the silicon nitride film (charge holding film 4) are not terminated by thermal diffusion of moisture contained in the third insulating film 11.

FIG. 2 and paragraph [0024] of Patent Document 4 (Japanese Patent Laid-Open No. 07-058313) disclose a silicon oxide film 4-nitride film 5-oxynitride film 6, but paragraph [0028] of Patent Document 4. Only discloses that fluorine ions 10 are implanted into the silicon oxide film. Further, paragraph [0010] of Patent Document 4 teaches that fluorine ions 10 are allowed to pass uniformly through the nitride film 5.
As described above, in Patent Document 2, Patent Document 3, and Patent Document 4, the charge storage capability of the part 31 of the gate charge storage layer 22b ′ is different from that of the gate charge storage layer 22b by ion implantation of fluorine as in the present embodiment. It is not disclosed that the charge storage capacity of the remaining part 32 is reduced.

6A shows a modification of the resist R shown in FIG. 5, FIG. 6B shows another modification of the resist R shown in FIG. 5, and FIG. 5 shows an example of the resist R shown in FIG. 5, FIG. 6D shows another modification of the resist R shown in FIG. 5, and FIG. 6E shows the resist R shown in FIG. Another modification is shown, and FIG. 6F shows another modification of the resist R shown in FIG.
As shown in FIG. 6A (and FIG. 6D), the range of the resist R is the gate on the source / drain region 12 side in the source / drain region 13 side to which the source line is connected (FIG. 6D). From the other end 45) of the gate conductive layer 14 'on the source / drain region 13 side facing the one end 44 of the conductive layer 14', the gate length of the gate conductive layer 14 'may be 1/5. As shown in FIG. 6D, the gate conductive layer 14 ′ positioned above the trap position on the source / drain region 13 side in the vicinity of the interface between the first insulating layer 22a and the gate charge storage layer 22b ′. The resist R may be formed only on the remaining portion (42). The ability to store charges in the charge storage layer 22b ′ on the source / drain region 13 side to which the source line of the memory cell of FIG.
Further, as shown in FIG. 6C, the range of the resist R is, for example, from the side of the source / drain region 13 to which the source line of the gate conductive layer 14 ′ is connected to 4 / of the gate length of the gate conductive layer 14 ′. Up to 5. As shown in FIG. 6F, the range of the resist R may be, for example, from the other end 45 of the gate conductive layer 14 ′ on the source / drain region 13 side to 4/5 of the gate length of the gate conductive layer 14 ′. Good. In other words, a portion (41) of the gate conductive layer 14 ′ located above the trap position 48 on the source / drain region 13 side in the vicinity of the interface between the first insulating layer 22a and the gate charge storage layer 22b ′. It is only necessary to perform ion implantation using fluorine only on the top. The ability to store charges in the gate charge storage layer 22b ′ on the source / drain region 12 side to which the bit line of the memory cell of FIG. 1 is connected can be reduced.
Furthermore, as shown in FIG. 6B (and FIG. 6E), the range of the resist R is, for example, the source / drain region on the source / drain region 13 side to which the source line is connected (FIG. 6E). The other end 45) of the gate conductive layer 14 'on the 13th side may be ½ of the gate length of the gate conductive layer 14'. In consideration of variations in the formation of the resist R (photomask placement accuracy for the resist R), the charge in the gate charge storage layer 22b ′ on the source / drain region 13 side to which the source line of the memory cell in FIG. 1 can be reliably maintained, and the ability to store the charge in the gate charge storage layer 22b ′ on the source / drain region 12 side to which the bit line of the memory cell of FIG. 1 is connected can be reliably reduced.

  In FIG. 6A and FIG. 6D, the length of the resist R on the gate conductive layer 14 ′ along the gate length direction can be set to 50 [nm], for example. In FIG. 6B and FIG. 6E, the length of the resist R on the gate conductive layer 14 ′ along the gate length direction can be set to 125 [nm], for example. 6C and 6F, the length of the resist R on the gate conductive layer 14 ′ along the gate length direction can be set to 200 [nm], for example.

When the range of the resist R conforms to FIGS. 6A, 6B, and 6C, the ion implantation using fluorine is vertical ion implantation or oblique ion implantation using fluorine. Specifically, oblique ion implantation using fluorine may be performed instead of vertical ion implantation using fluorine. Further, for example, vertical ion implantation using fluorine may be performed, and then oblique ion implantation using fluorine may be performed.
The range of the angle of oblique ion implantation with respect to the normal of the surface of the semiconductor layer 10 is, for example, 10 degrees to 30 degrees. Specifically, the energy at the time of oblique ion implantation using fluorine is determined so that the distribution of implanted fluorine ions becomes maximum at the trap position 48. In the oblique ion implantation, the fluorine ion reach distance to the trap position 48 near the interface between the first insulating layer 22a and the gate charge storage layer 22b ′ is shorter than the vertical ion implantation. The energy used for the oblique ion implantation may be lower than the energy used for the vertical ion implantation using fluorine.

When the range of the resist R conforms to FIG. 6D, FIG. 6F, and FIG. 6G, the ion implantation using fluorine is the vertical ion implantation using fluorine or the gate on the source / drain region 13 side. This is oblique ion implantation using fluorine to such an extent that the charge storage capability of the charge storage layer 22b ′ does not substantially decrease. Regarding the fluorine-based gas used for ion implantation, fluorine (F ₂ ) may be changed to, for example, boron fluoride (BF ₂ ), hydrogen fluoride (HF), or the like. In addition, ion implantation using a fluorine-based gas (for example, fluorine) is performed using a hydrogen-based gas (for example, hydrogen (H ₂ ), hydrogen chloride (HCl), borohydride (B ₂ H ₆ ), hydrogen phosphide (PH ₃ ), Hydrogen fluoride (HF), or the like). For example, only ion implantation of hydrogen ions using hydrogen may be performed. Alternatively, for example, only ion implantation of fluorine ions using BF ₂ may be performed. Further, for example, ion implantation of fluorine ions using fluorine may be performed, and thereafter ion implantation of hydrogen ions using hydrogen may be performed. For example, when ion implantation of fluorine ions using BF ₂ is performed, ion implantation of boron ions may adversely affect the source / drain regions 12 and 13.
Thereafter, the resist R is removed.

Thereafter, as shown in FIG. 2 (A), the third surface is formed on both side surfaces of the gate conductive layer 14 ′, both side surfaces of the second gate insulating layer 22c ′, and both side surfaces of the gate charge storage layer 22b ′. Insulating layers 16 and 17 are formed. The third insulating layers 16 and 17 are, for example, silicon nitride layers (for example, SiN layers). As shown in FIG. 2A, the cross section of each of the third insulating layers 16 and 17 is one side surface on the side of the gate conductive layer 14 ′ and one side perpendicular to the top surface of the semiconductor layer It has a side surface, the other side surface having a curved surface opposite to the one side surface, and a bottom surface parallel to the top surface of the semiconductor layer 10.
Specifically, after the resist R is removed, the SiN layer (not shown) is formed by, for example, a CVD process on the entire surface of the gate conductive layer 14 and the entire surface of the first insulating layer 22a, and the gate conductive layer. 14 ′ is formed on both exposed side surfaces, on both exposed side surfaces of the second gate insulating layer 22 c ′, and on both exposed side surfaces of the gate charge storage layer 22 b ′. Thereafter, a resist (not shown) is applied to the entire surface of the SiN layer. Thereafter, a part of the resist (not shown) applied so as to expose a part of the SiN layer located above the gate conductive layer 14 is removed, and a resist having an exposed part exposing a part of the SiN layer. (Not shown) is formed on the remainder of the SiN layer. A resist having an exposed portion is used as a mask, and a part of the exposed SiN layer is anisotropically dry etched. When a part of the first insulating layer 22a is removed and the first gate insulating layer 22a ′ is formed, the anisotropic dry etching is finished. In this way, for example, anisotropic dry-etched SiN layers are formed as the third insulating layers 16 and 17. The third insulating layers 16 and 17 are sometimes called sidewalls. In FIG. 2A, the first gate insulating layer 22a ′ is located only under the gate charge storage layer 22b ′ and the third insulating layers 16 and 17, but in reality, the anisotropic dry layer A part of the first insulating layer 22a that is not completely removed by etching remains thin on the semiconductor layer 10 (the semiconductor layer 10 corresponding to the regions 18 and 19 in FIG. 2A).
Thereafter, the resist having the exposed portion is removed.

Thereafter, source / drain regions 18 and 19 are formed in the upper layer of the semiconductor layer 10 (specifically, the semiconductor layer 10 positioned below a part of the source / drain regions 12 and 13 and a part of the source / drain regions 12 and 13). To do. The source / drain regions 18 and 19 have a dose amount similar to that of the source / drain regions 12 and 13, and a dopant of the same type as the dopant of the source / drain regions 12 and 13 (for example, arsenic) is used. Ions are implanted deeper than 13.
Specifically, the entire surface of the gate conductive layer 14, the entire surface of the third insulating layer (the other side surface having a curved surface), and the exposed semiconductor layer 10 (exposed source / drain regions 12, 13 (actually Applies a resist (not shown) to the entire surface of the first insulating layer 22a that is not completely removed by anisotropic dry etching. Thereafter, the applied resist so as to expose the semiconductor layer 10 (the source / drain regions 12 and 13 exposed until the resist is applied) excluding the semiconductor layer 10 located under the first gate insulating layer 22a ′. A part of (not shown) is removed. As a result, a resist (not shown) having an exposed portion that exposes the semiconductor layer 10 excluding the semiconductor layer 10 located under the first gate insulating layer 22a ′ is formed on the gate conductive layer 14 and the third insulating layer. To form. Using the resist having an exposed portion as a mask, ion implantation of the same type of dopant as the dopant of the source / drain regions 12 and 13 is performed on the semiconductor layer 10 except for the semiconductor layer 10 located under the first gate insulating layer 22a ′. carry out. As a result, source / drain regions 12 ′ and 13 ′ and source / drain regions 18 and 19 are formed. The source / drain regions 12 ′ and 13 ′ may be referred to as source / drain extension regions 12 ′ and 13 ′. The source / drain regions 18 and 19 are sometimes referred to as source / drain contact regions 18 and 19.

The exposed source / drain contact regions 18, 19 preferably have a silicide layer (not shown) (eg, a CoSi ₂ layer) on their surface. Specifically, the CoSi ₂ layer can be formed by, for example, a sputtering apparatus.
Thereafter, the resist having the exposed portion is removed.

  Although not shown in FIG. 2A, a word line is connected to the gate conductive layer 14 ′, a bit line is connected to the source / drain contact region 18, and a source line is connected to the source / drain contact region 19 by a known method. For example, as shown in FIG. 1, it is arranged as one of a plurality of memory cells. The remaining memory cells of the plurality of memory cells are formed in the same process at the same time when forming one transistor of FIG. Further, each of the remaining memory cells of the plurality of memory cells is simultaneously connected to one corresponding word line, one corresponding bit line, and one corresponding source line in the same process. Each of the plurality of memory cells is driven by a peripheral circuit (not shown) via one corresponding word line, one corresponding bit line, and one corresponding source line. As a whole, it functions as a NOR type memory device.

FIG. 7 is a diagram for explaining an outline of another method for manufacturing the semiconductor device shown in FIG.
In the outline of the method for manufacturing a semiconductor device described above, in FIG. 5 or FIG. 6, before forming the third insulating layers 16 and 17 (sidewalls), the charge storage layer 22b ′ is integrated by vertical ion implantation using, for example, fluorine. The ability of the part 31 (41) to accumulate electric charge was reduced. In another outline of the manufacturing method of the semiconductor device, vertical ion implantation using fluorine in the process of FIG. 5 or 6 is not performed. In another outline of the manufacturing method of the semiconductor device, as shown in FIG. 7, vertical ion implantation using fluorine is performed after the third insulating layers 16 and 17 and the source / drain regions 18 and 19 are formed. . In other words, the outline of another method for manufacturing a semiconductor device differs from the outline of the method for manufacturing a semiconductor device described above in the timing of performing vertical ion implantation using fluorine.

In another outline of the manufacturing method of the semiconductor device, the steps up to the step shown in FIG.
Thereafter, the step of FIG. 5 or FIG. 6 is not performed, and as shown in FIG. 7, both side surfaces of the gate conductive layer 14 ′, both side surfaces of the second gate insulating layer 22c ′, and the gate charge storage layer 22b. The third insulating layers 16 and 17 are formed on both sides of '.
Thereafter, source / drain regions 18 and 19 are formed in the upper layer of the semiconductor layer 10 (specifically, the semiconductor layer 10 positioned below a part of the source / drain regions 12 and 13 and a part of the source / drain regions 12 and 13). To do. Thereby, source / drain regions 12 ′ and 13 ′ are also formed.

  After the third insulating layers 16 and 17 and the source / drain regions 18 and 19 are formed, a resist R is formed at least in a partial region 42 of the gate conductive layer 14 '. Preferably, the resist R is formed from the partial region 42 of the gate conductive layer 14 ′ to the entire surface of the third insulating layer 17 located above the source / drain region 13 ′, the first surface on the third insulating layer 17 side. Extends to one side surface of the gate insulating layer 22 a and the entire surface of the source / drain region 18. The exposed portion of the resist R includes the remaining region 41 of the gate conductive layer 14 ′ excluding the partial region 42, the entire surface of the third insulating layer 16 positioned above the source / drain region 12 ′, and the third insulating layer 16. The other side surface of the first gate insulating layer 22a on the side and the entire surface of the source / drain region 19 are exposed.

Thereafter, using the resist R having an exposed portion as a mask, vertical ion implantation using, for example, fluorine is performed on at least a part (41) of the gate conductive layer 14 ′. A part (41) of the exposed gate conductive layer 14 ′ is located on the source / drain region 12 ′, 18 side. The remaining part (42) of the gate conductive layer 14 ′ covered with the resist R is located on the source / drain regions 13 ′ and 19 side.
The second gate insulating layer 22c is interposed through a part (41) of the gate conductive layer 14 'and a part of the second gate insulating layer 22c' formed under the part (41) of the gate conductive layer 14 '. Vertical ion implantation using fluorine is performed with energy reaching a part of the gate charge storage layer 22b 'formed under a part of'.

The ion implantation using fluorine is vertical ion implantation or oblique ion implantation using fluorine. In the case of oblique ion implantation, using the resist R having an exposed portion as a mask, at least a part (41) of the gate conductive layer 14 ′ and the third insulating layer 16 positioned above the source / drain region 12 ′ For example, fluorine ions are implanted. In the oblique ion implantation, the fluorine ion reach distance to the trap position 48 near the interface between the first insulating layer 22a and the gate charge storage layer 22b ′ is shorter than the vertical ion implantation. The energy used for the oblique ion implantation may be lower than the energy used for the vertical ion implantation using fluorine. However, in the oblique ion implantation in the process of FIG. 7, fluorine ions reach the trap position 48 via the third insulating layer 16. Therefore, the energy at the time of oblique ion implantation using fluorine in the process of FIG. 7 is made higher than the energy at the time of oblique ion implantation using fluorine in the process of FIG.
In the oblique ion implantation in the step of FIG. 7, fluorine ions are also implanted into the third insulating layer 16. Therefore, fluorine ions captured by the third insulating layer 16 near the trap position 48 are introduced into the trap position 48 in the subsequent thermal process. This means that the charge storage capability of the portion 31 of the gate charge storage layer 22b ′ can be reduced by the amount of fluorine ions introduced from the third insulating layer 16.

Regarding the fluorine-based gas used for ion implantation in the process of FIG. 7, fluorine (F ₂ ) may be changed to, for example, boron fluoride (BF ₂ ), hydrogen fluoride (HF), or the like. In addition, ion implantation using a fluorine-based gas (for example, fluorine) is performed using a hydrogen-based gas (for example, hydrogen (H ₂ ), hydrogen chloride (HCl), borohydride (B ₂ H ₆ ), hydrogen phosphide (PH ₃ ), Hydrogen fluoride (HF), or the like).
The length of the resist R in FIG. 7 may be changed as shown in FIG. 6B, for example.

Thereafter, the resist R is removed.
Thereafter, a silicide layer (for example, a CoSi ₂ layer) can be formed on the surface of the source / drain contact regions 18 and 19 by resist treatment and sputtering treatment.
Although not shown in FIG. 2A, a word line is connected to the gate conductive layer 14 ′, a bit line is connected to the source / drain contact region 18, and a source line is connected to the source / drain contact region 19 by a known method. For example, as shown in FIG. 1, it is arranged as one of a plurality of memory cells.

FIG. 8A is a plan view illustrating the outline of the exposed portion of the resist R in FIG. 5 or FIG. 7, and FIG. 8B is an auxiliary diagram for explaining the plan view in FIG. 8A. is there.
When one memory cell is constituted by one transistor, the exposed portion of the resist R in FIG. 5 or FIG. 7 is, for example, one of a plurality of exposed portions RA shown in FIG. 8 (A) and FIG. 8 (B). Can be applied. In FIG. 5, the source / drain region 12, the gate conductive layer 14 ′ and the source / drain region 13 are not actually located on the same plane, but in FIG. The source / drain region 12, the gate conductive layer 14 ′, and the source / drain region 13 projected on are shown by broken lines. 8A, the source / drain regions 12 ′ and 18 and the source / drain regions 13 ′ and 19 in FIG. 7 are not shown, but correspond to the source / drain regions 12 and 13 in FIG.

  FIG. 8B shows bit lines BL0 to BL3, source lines SL0 to AL3, and word lines WL0 to WL3 that are formed after the step of FIG. The bit lines BL0 to BL3, the source lines SL0 to AL3, and the word lines WL0 to WL3 are actually formed in a layer above the transistor of FIG. 5 or FIG. In FIG. 8B, the source / drain region 12, the gate conductive layer 14 ′ and the source / drain region 13 virtually projected on the same plane are represented by broken lines and virtually projected on the same plane. A plurality of exposed portions RA are represented by solid lines. Further, in FIG. 8B, the bit line BL0 and the source / drain region 12 (specifically, the source / drain region 18) are electrically connected to one memory cell specified by the bit line BL0, the source line SL0, and the word line WL3. Bit line contact BC for electrically connecting, gate line contact GC for electrically connecting word line WL3 and gate conductive layer 14 ', and source line SL0 and source / drain region 13 (specifically source / drain region 13) A source line contact SC for electrically connecting the region 19) is also represented by a broken line.

As shown in FIG. 8A and FIG. 8B, one exposed portion RA of the resist R has a plurality of memory cells adjacent to each other in the gate width direction, that is, in the direction parallel to the word line or the source line. A part (41) of the plurality of gate conductive layers 14 ′ can be exposed. On the other hand, one exposed portion RA of the resist R exposes a part (41) of the plurality of gate conductive layers 14 ′ of the plurality of memory cells adjacent in the gate length direction, that is, in the direction parallel to the bit line. Can not.
For example, one first memory cell specified by the bit line BL0, source line SL0, and word line WL3 has one second memory cell specified by the bit line BL0, source line SL1, and word line WL2 in the gate length direction. When adjacent to the memory cell, one exposed portion RA that exposes a part (41) of the gate conductive layer 14 ′ of the second memory cell does not expose the source / drain region 13 of the first memory cell.

FIG. 9A is another plan view showing the outline of the exposed portion of the resist R in FIG. 5 or FIG. 7, and FIG. 9B is a diagram for explaining the plan view in FIG. It is an auxiliary figure.
When one memory cell is constituted by two transistors, the exposed portion of the resist R in FIG. 5 or FIG. 7 is, for example, one of a plurality of exposed portions RA shown in FIG. 8 (A) and FIG. 8 (B). Can be applied. In FIG. 8A, the source / drain region 12 is shared by two transistors.
As shown in FIG. 9A and FIG. 9B, one exposed portion RA of the resist R has a plurality of memory cells adjacent in the gate width direction, that is, in the direction parallel to the word line or the source line. A part (41) of the plurality of gate conductive layers 14 ′ can be exposed. On the other hand, one exposed portion RA of the resist R exposes a part (41) of the plurality of gate conductive layers 14 ′ of the plurality of memory cells adjacent in the gate length direction, that is, in the direction parallel to the bit line. Can not. However, one exposed portion RA of the resist R can expose a part (41) of the plurality of gate conductive layers 14 ′ of one memory cell.
For example, one first memory cell specified by the bit line BL0, the source line SL0, and the word line WL1 has one second memory cell specified by the bit line BL0, the source line SL1, and the word line WL0 in the gate length direction. One exposed portion RA that exposes a part (41) of the plurality of gate conductive layers 14 ′ of the second memory cell when the adjacent memory cell is adjacent to the memory cell of the first memory cell. Not exposed.

3. Operation of Memory Cell In the arrangement example as shown in FIG. 1, when charge (hot electrons) is written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 is connected, for example, the voltage of the bit line BL0 Is set to 0 [V], the voltage of the source line SL1 is set to 5 [V], and the voltage of the word line WL0 is set to 7 [V]. Further, the voltage of the bit line BL1 is set to 5 [V], the voltage of the source line SL0 is set to 0 [V], and the voltage of the word line WL1 is set to 0 [V]. In the present embodiment, even if the number of voltages used is three (0 [V], 5 [V], 7 [V]), the source / drain region side to which the bit line BL1 of the memory cell MC01 is connected It is difficult for charges (hot holes) to be written in the charge storage layer.
If the voltage of the bit line and the voltage of the source line are interchanged, that is, the voltage of the bit line BL0 is set to 5 [V], the voltage of the source line SL1 is set to 0 [V], and the word When the voltage of the line WL0 is set to 7 [V], the speed (time constant) for writing charges (hot electrons) in the charge storage layer on the source / drain region side to which the bit line BL0 of the memory cell MC10 is connected is two digits. It will be slower. The speed (time constant) at which charges (hot electrons) are written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 is connected is, for example, 10 [μsec], while the bit line BL0 of the memory cell MC10 The speed (time constant) at which charges (hot electrons) are written in the charge storage layer on the source / drain region side to which is connected is, for example, 1 [msec].

FIG. 10 is a diagram for explaining the erase operation of the memory cell of the nonvolatile memory device.
In the case where charges (hot holes) are written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 is connected and the written charges (hot electrons) are canceled, for example, the voltage of the bit line BL0 is set to It is set to 0 [V], the voltage of the source line SL1 is set to 5 [V], and the voltage of the word line WL0 is set to 0 [V]. Further, the voltage of the bit line BL1 is set to 5 [V], the voltage of the source line SL0 is set to 0 [V], and the voltage of the word line WL1 is set to 0 [V].

FIG. 11 is a diagram for explaining the read operation of the memory cell of the nonvolatile memory device.
When determining whether or not charges (hot electrons) are written in the charge storage layer on the source / drain region side to which the source line SL1 of the memory cell MC10 is connected, for example, the voltage of the bit line BL0 is set to 1 [V]. Then, the voltage of the source line SL1 is set to 0 [V], and the voltage of the word line WL0 is set to 2 [V]. In this embodiment, it corresponds to a so-called reverse read. Further, the voltage of the bit line BL1 is set to 0 [V], the voltage of the source line SL0 is set to 1 [V], and the voltage of the word line WL1 is set to 0 [V].

In the present embodiment, disturbance to unselected memory cells can be prevented. Therefore, the structure of the semiconductor device of this embodiment can be applied to an arrangement example other than the arrangement example shown in FIG. For example, the bit line and the word line may be arranged in parallel. Further, the structure of the semiconductor device of this embodiment can be flexibly applied to other arrangements.
The structure of the semiconductor device of this embodiment can also be applied to a nonvolatile memory device as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-296683). That is, in FIG. 4, the dose amount of the source / drain region 13 on the source line side can be made larger than the dose amount of the source / drain region 12 on the bit line side. Disturbance to unselected memory cells can be further prevented. For example, the dose amount of the source / drain region 13 on the source line side may be 1.5 times or more the dose amount of the source / drain region 12 on the bit line side.
Also, the structure of the semiconductor device of this embodiment can be applied to a twin memory cell as disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-273254. That is, one of the twin memory cells may not function by ion implantation using fluorine or the like.

  Those skilled in the art will readily understand that the above-described embodiments can be modified (possibly by referring to common general knowledge) without departing from the spirit of the present invention. The scope of the present invention includes all or part of the present embodiment and modifications thereof, and is defined by the scope of the claims and the equivalent scope thereof.

7 is an example of circuit arrangement equivalent to a memory cell of a nonvolatile memory device. FIG. 2A is a schematic diagram of a structural example of the semiconductor device of this embodiment. FIG. 2B is an example of a plan view of the gate charge storage layer 22b ′ of FIG. FIG. 2C is another example of a plan view of the gate charge storage layer 22b ′ of FIG. FIG. 2D is another example of a plan view of the gate charge storage layer 22b ′ of FIG. FIG. 3 is a view for explaining the outline of the method for manufacturing the semiconductor device shown in FIG. FIG. 3 is another view for explaining the outline of the method for manufacturing the semiconductor device shown in FIG. FIG. 3 is another view for explaining the outline of the method for manufacturing the semiconductor device shown in FIG. FIG. 6A shows a modification of the resist R shown in FIG. FIG. 6B shows another modification of the resist R shown in FIG. FIG. 6C shows an example of the resist R shown in FIG. FIG. 6D shows another modification of the resist R shown in FIG. FIG. 6E shows another modification of the resist R shown in FIG. FIG. 6F shows another modification of the resist R shown in FIG. FIG. 3 is a view for explaining an outline of another method for manufacturing the semiconductor device shown in FIG. FIG. 8A is a plan view schematically showing the exposed portion of the resist R in FIG. 5 or FIG. FIG. 8B is an auxiliary diagram for explaining the plan view of FIG. FIG. 9A is another plan view showing an outline of the exposed portion of the resist R in FIG. 5 or FIG. FIG. 9B is an auxiliary diagram for explaining the plan view of FIG. 4A and 4B illustrate an erase operation of a memory cell in a nonvolatile memory device. 4A and 4B illustrate a read operation of a memory cell in a nonvolatile memory device.

Explanation of symbols

10 semiconductor layer, 12, 13, 18, 19 source / drain region, 14 conductive layer,
16, 17, 22a, 22c insulating layer, 22b charge storage layer, BL bit line,
MC memory cell, R resist, RA resist exposure part, SL source line,
WL Word line

Claims (16)

A semiconductor device,
Including at least one transistor of at least one non-volatile storage cell;
The at least one transistor of the at least one nonvolatile memory cell includes a first gate insulating layer, a gate charge storage layer having a charge storage capability formed on the first gate insulating layer, and the gate. A second gate insulating layer formed on the charge storage layer,
The first charge storage capability of a part of the gate charge storage layer is lower than the second charge storage capability of the remaining part of the gate charge storage layer, and the first charge storage capability of the part of the gate charge storage layer. Is reduced by ion implantation using a fluorine-based gas and / or a hydrogen-based gas. In claim 1,
The at least one transistor of the at least one non-volatile memory cell is
Having a semiconductor layer,
The first gate insulating layer is formed on the semiconductor layer;
The semiconductor layer of the at least one transistor has a first source / drain region connected to the bit line and a second source / drain region connected to the source line;
The part of the gate charge storage layer exists on the first source / drain region side,
The semiconductor device, wherein the remaining portion of the gate charge storage layer exists on the second source / drain region side. In claim 1 or 2,
The semiconductor device, wherein the first gate insulating layer is a silicon oxide layer, the gate charge storage layer is a silicon nitride layer, and the second gate insulating layer is a silicon oxide layer. In any one of Claims 1 thru | or 3,
The remaining part of the gate charge storage layer is a semiconductor device capable of storing hot carriers. In any one of Claims 1 thru | or 3,
The remaining part of the gate charge storage layer is a semiconductor device in which hot carriers are easily stored as compared with the part of the gate charge storage layer. In any one of Claims 1 thru | or 5,
The semiconductor device wherein the dose amount of the dopant in the second source / drain region is larger than the dose amount of the dopant in the first source / drain region. A semiconductor device,
Including at least one transistor of at least one non-volatile storage cell;
The at least one transistor of the at least one nonvolatile memory cell includes a first gate insulating layer, a gate charge storage layer having a charge storage capability formed on the first gate insulating layer, and the gate. A second gate insulating layer formed on the charge storage layer,
The semiconductor device, wherein a first defect density of a part of the gate charge storage layer is lower than a second defect density of the remaining part of the gate charge storage layer. A method for manufacturing a semiconductor device, comprising:
Preparing a semiconductor layer;
Forming a first insulating layer on the semiconductor layer;
Forming a charge storage layer on the first insulating layer;
Forming a second insulating layer on the charge storage layer;
Forming a conductive layer on the second insulating layer;
A portion of the conductive layer; a portion of the second insulating layer formed under the portion of the conductive layer; and the charge storage formed under the portion of the second insulating layer. A portion of the layer is etched to form the remaining portion of the conductive layer, the remaining portion of the second insulating layer, and the remaining portion of the charge storage layer as a gate conductive layer, a second gate insulating layer, and a gate charge storage layer, respectively. And a resist that exposes a part of the gate conductive layer is formed on at least the remaining part of the gate conductive layer, and the gate charge storage layer formed below the part of the gate conductive layer is formed. Performing ion implantation using fluorine gas and / or hydrogen gas in part,
Including
The remaining part of the gate charge storage layer is a method for manufacturing a semiconductor device, in which hot carriers are easily stored compared to the part of the gate charge storage layer. In claim 8,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in 1 to 1/5 of the gate length of the gate conductive layer. In claim 8,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in the region to ½ of the gate length of the gate conductive layer. In claim 8,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in the region to 4/5 of the gate length of the gate conductive layer. A method for manufacturing a semiconductor device, comprising:
Preparing a semiconductor layer,
Forming a first insulating layer on the semiconductor layer;
Forming a charge storage layer on the first insulating layer;
Forming a second insulating layer on the charge storage layer;
Forming a conductive layer on the second insulating layer;
A portion of the conductive layer; a portion of the second insulating layer formed under the portion of the conductive layer; and the charge storage formed under the portion of the second insulating layer. A portion of the layer is etched to form the remaining portion of the conductive layer, the remaining portion of the second insulating layer, and the remaining portion of the charge storage layer as a gate conductive layer, a second gate insulating layer, and a gate charge storage layer, respectively. thing,
On both sides exposed by the etching of the gate conductive layer, both sides exposed by the etching of the second gate insulating layer, and both sides exposed by the etching of the gate charge storage layer; Forming a third insulating layer; and forming a resist exposing at least a part of the gate conductive layer and the part of the gate conductive layer on at least the remaining part of the gate conductive layer; Performing ion implantation on a part of the gate charge storage layer formed below the part of the layer using a fluorine-based gas and / or a hydrogen-based gas;
Including
The remaining part of the gate charge storage layer is a method for manufacturing a semiconductor device, in which hot carriers are easily stored compared to the part of the gate charge storage layer. In claim 12,
Performing ion implantation on the third insulating layer in contact with the part of the gate charge storage layer using a fluorine-based gas and / or a hydrogen-based gas;
A method of manufacturing a semiconductor device including: In claim 12 or 13,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in 1 to 1/5 of the gate length of the gate conductive layer. In claim 12 or 13,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in the region to ½ of the gate length of the gate conductive layer. In claim 12 or 13,
Forming a first source / drain region and a second source / drain region on an upper layer of the semiconductor layer sandwiching a channel region of the semiconductor layer located below the gate conductive layer in a gate length direction of the gate conductive layer; ,
Including
The part of the gate conductive layer exposed by the resist formed on the remaining portion of the gate conductive layer has one end of the gate conductive layer existing on the first source / drain region side;
The range of the resist formed on the remaining portion of the gate conductive layer is at least the other end of the gate conductive layer facing the one end of the gate conductive layer, and the second source / drain region side A method of manufacturing a semiconductor device having a range from the other end of the gate conductive layer existing in the region to 4/5 of the gate length of the gate conductive layer.

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