JP2006319186A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance memory characteristics, especially the data retention characteristics, of a semiconductor memory device in which a sidewall-like charge storage 8 is arranged on at least any one side of the opposite sidewalls of a gate electrode 6, by efficiently and rigidly terminating a dangling bond generated on a tunnel oxide film 3, under the charge storage 8 or the interface of the tunnel oxide film 3 and a semiconductor substrate with hydrogen. <P>SOLUTION: An insulating film 11, containing water molecules of at least 2×10<SP>21</SP>/cm<SP>3</SP>during film deposition, is formed in a charge storage 8, or on the surface thereof. Furthermore, a film 12 of a substance that reacts with moisture to oxidize is formed at a position touching the insulating film 11. Moisture supplied from the insulating film 11 is decomposed, to produce hydrogen used for terminating dangling bonds. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more specifically to a nonvolatile semiconductor memory device including a MOSFET-structure nonvolatile memory cell having a charge storage portion capable of holding charges in a third wall portion of a gate electrode.

  Nonvolatile memories represented by flash memories and the like are widely used in the fields of computers, communications, measuring instruments, automatic control devices, and household devices used in general households as large-capacity and small-sized information recording media. ing. The demand for cheaper and larger capacity non-volatile memories is enormous and is being actively developed.

  Non-volatile memories that can be electrically rewritten many times include a floating gate (FG) type flash memory, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type structure MONOS type memory (or MNOS type) Memory), a new memory using a new material such as a ferroelectric material, and the like. The most widely used is a floating gate type flash memory because it can realize a large capacity and can be manufactured at low cost. Other new memories are limited only to applications requiring high-speed reading and writing taking advantage of their characteristics due to immaturity of manufacturing technology and high manufacturing cost. In the new memory, the multi-value per memory cell, which is one means for reducing the bit cost, has hardly progressed. On the other hand, although the MONOS type memory has been proposed in the past, it has not been widely used due to poor data retention characteristics and difficulty in device design.

  In a floating gate type memory such as a flash memory, the charge storage portion is formed of a conductor such as polycrystalline silicon, and even in a part of the tunnel oxide film that insulates the charge storage portion of the floating gate from the substrate, there is an insulation failure. If there is, all accumulated charges are lost. Therefore, if the tunnel oxide film is thinned, the memory characteristics are deteriorated in some memory cells. Therefore, it is difficult to reduce the thickness of the tunnel oxide film. This suggests that miniaturization of the memory cell itself will be difficult in the future.

  On the other hand, the MONOS type memory is also called NROM (Nitride ROM), and its charge storage portion is generally composed of a silicon nitride film. The charge storage part is an insulating film, and electrons are discretely captured by traps of the silicon nitride film. Therefore, even if there is a defect in the tunnel oxide film between the substrate and the charge storage part, all charges are not released at once, and the tunnel oxide film can be made thin, which is advantageous for miniaturization. . However, as described above, since charges are gradually removed at a certain rate, it is necessary to devise a method for maintaining data retention characteristics.

  Data writing to the MONOS type memory includes a method using an FN (Fowler-Nordheim) tunnel current and a method using hot carrier injection narrowed down to a narrow region unique to the MONOS type, as in the floating gate type memory. is there. When an FN tunnel current is used, a high voltage is required for writing / erasing, whereas when hot carrier injection is used, a high voltage is not required. This eliminates the need for a booster circuit or a high-voltage circuit. In addition to the small number of process steps, the hot carrier injection type MONOS type memory can reduce the chip area, thereby reducing the cost and incorporating it with a logic circuit. Is also easier. Therefore, the expectation as a successor memory of flash memory is increasing.

  In general, the bit capacity of a so-called planar type memory having a charge holding portion directly below a gate electrode for forming a memory cell in a plane on a semiconductor substrate has a minimum processing dimension (Feature Size) which is a resolution limit of photolithography technology. It is rate-limited. As a means for achieving a high degree of integration in the next generation and a reduction in manufacturing cost per bit without depending on the improvement of the photolithography technology, a multilevel technology for memory cells has been studied.

  The memory cell multi-value technology is a threshold control type in which the threshold distribution of the memory cells is set to three or more types, and a region for holding charges is made discrete in one memory cell, and charges are stored independently in each region. The charge storage region is roughly divided into discrete types. The former threshold control type can be employed in both a floating gate type memory such as a flash memory and a MONOS type memory, while the latter charge storage region discrete type is particularly suitable for a MONOS type memory. Examples of the charge storage region discrete type MONOS type multi-level memory include those disclosed in Patent Document 1 and Patent Document 2 below.

  FIG. 8 is a schematic cross-sectional view of a memory cell of a charge storage region discrete type MONOS type multi-value memory disclosed in Patent Document 1, in which the charge storage unit is directly under the gate electrode 26, and the oxide film 23-nitridation. A diffusion layer region 22 is formed on both sides of the gate electrode 26 on the surface of the semiconductor substrate 21. In this conventional example, by forming the charge storage portion with an oxide film-nitride film-oxide film (ONO film), a region for holding two charges is arranged in one memory cell, and 2 bits per memory cell. The information can be stored.

  FIG. 9 is a schematic cross-sectional view of a memory cell of a MONOS type multi-valued memory of a charge storage region discrete type disclosed in Patent Document 2. Side wall-shaped charge storage portions 8 are formed on both side walls of the gate electrode 6. Arranged so that 2-bit information can be stored per memory cell. In this conventional example, unlike the MONOS type multi-value memory illustrated in FIG. 8, the charge storage portion 8 disposed on both side walls of the gate electrode 6 is formed of an oxide film 3 -nitride film 4 -oxide film 5 (ONO film). For example, it may be formed by a floating gate of a conductor such as polycrystalline silicon, and there is an advantage that the material and shape of the charge storage portion are not limited to one form.

  In the charge storage region discrete type MONOS type multi-value memory cell shown in FIG. 9, since the insulating film under the gate electrode is not used as the charge storage portion, the gate electrode length can be reduced even if the gate electrode length is reduced. It is possible to secure a sufficient distance between the charge storage units arranged on both sides. Therefore, it is possible to maintain the separated state without interfering with the 2-bit information stored in the charge storage portions arranged on both sides of the gate electrode, which is very advantageous in terms of miniaturization. .

  In addition, since the memory cell has a structure capable of operating at a low voltage, it has good compatibility with the existing logic circuit manufacturing process, and a nonvolatile memory can be easily added to the existing manufacturing process at low cost. This is also advantageous.

  On the other hand, since the tunnel oxide film formed under the charge storage portion is formed by oxidizing the Si substrate that has been damaged by the processing when forming the gate electrode, the interface between the semiconductor substrate and the tunnel oxide film, or the tunnel The oxide film is susceptible to damage such as formation of dangling bonds (unbonded hands) in which Si bonds are broken.

JP 2001-77220 A International Publication No. 03/044868 Pamphlet

  As described above, when a charge storage region discrete type MONOS type multi-valued memory is provided with sidewall-shaped charge storage portions on both sides of the gate electrode, the Si substrate is damaged when forming the gate electrode. As a result, the tunnel oxide film is formed by oxidizing the semiconductor substrate, and there is a problem in that a dangling bond in which a Si bond is broken is formed in the interface between the semiconductor substrate and the tunnel oxide film. Dangling bonds are the formation of unpaired electrons, increasing the interface state and trap density, deteriorating device characteristics, especially data retention characteristics, and making controllability of memory characteristics difficult, increasing the capacity. It was inhibiting. In a planar MONOS type memory that is disadvantageous in improving the degree of integration, the charge storage portion is not exposed to processing damage such as plasma, and such a problem hardly occurs.

More specifically, when the MONOS type multi-valued memory is manufactured with a conventional sidewall structure, and the tunnel oxide film of the charge storage portion, the semiconductor substrate, and their interface are evaluated by an electron spin resonance method, it is about 10 ¹⁴ unpaired electrons / cm ² were observed. If the unpaired electron exists, the charge moves through this level, and the retention characteristic of the charge held in the nitride film of the charge storage portion deteriorates, and the charge is injected into and released from the nitride film. It becomes difficult to accurately control. Therefore, it is desirable to eliminate these unpaired electrons in order to manufacture a device with higher reliability and higher yield. Therefore, the unpaired electron density has to be suppressed to about 10 ¹² / cm ^2, which is the lower limit of detection in the electron spin resonance method, and preferably less than that.

  In general, a silicon nitride film has a property that it is difficult for hydrogen to permeate. In particular, a high-quality silicon nitride film used for a memory film (charge holding film that holds charges) in a charge storage portion is called an LP (Low Pressure) -SiN film because of its manufacturing method, and is very dense. Even hydrogen with a small particle diameter is difficult to permeate.

  Further, as shown in FIG. 10, in the charge storage region discrete type MONOS type multi-level memory in which the side wall-like charge storage portions are arranged on both sides of the gate electrode, the contact hole 10 is opened to the interlayer insulating film 13. In order to serve as an etching stopper, the silicon nitride film 9 covers the gate electrode 6 and the charge storage portion 8 thickly. The silicon nitride film 9 is called a P (Plasma) -SiN film because of its manufacturing method, and is formed in plasma at a lower temperature than the LP-SiN film using silane and ammonia gas as raw materials. The P-SiN film can be thicker than the LP-SiN film. Therefore, even if a normal hydrogen sintering process is performed after the formation of the silicon nitride film 9, hydrogen does not sufficiently diffuse and penetrate to a desired location, and the dangling bonds at the lower part inside the silicon nitride film 9 are formed. It was difficult to terminate.

  The dangling bond described above can be eliminated by forming a Si—H bond with hydrogen and terminating it. However, the Si—H bond has a relatively small bond energy. Hydrogen atoms terminated at a relatively low temperature of about 400 ° C. are dissociated due to external factors such as temperature, light, and electrical stress. Therefore, even if hydrogen sintering is performed at a low temperature of about 400 ° C., which is a temperature range that does not damage the metal wiring formed in the subsequent process, the subsequent heat energy and ultraviolet light irradiation are performed in the subsequent process. It is known that the dissociation easily occurs due to external factors such as the above, and the effect of the hydrogen sinter is not fully utilized. In general, this problem can be suppressed to some extent by performing hydrogen sintering at a high temperature of about 800 ° C. before forming the metal wiring.

  However, when high-temperature hydrogen sintering is actually performed in a hydrogen atmosphere of 800 to 850 ° C., the fluctuation of the threshold value of the transistor in the circuit portion embedded in the memory device and the short channel effect due to the deeper junction position of the transistor are prominent. This has hindered circuit operation. As a result, it has become necessary to reassemble a manufacturing process for forming a new embedded circuit section. When such a problem occurs, the great advantage that a nonvolatile memory can be easily added to an existing logic manufacturing process at a low cost is lost.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor such as a MONOS type in which a side wall-like charge storage portion is disposed on at least one side wall portion of a gate electrode. In the memory device, the tunnel oxide film under the charge storage section or the dangling bond generated at the interface between the tunnel oxide film and the semiconductor substrate is effectively and strongly hydrogen-terminated to improve the memory characteristics, particularly the data retention characteristics. It is in.

In order to achieve the above object, a semiconductor memory device according to the present invention is a semiconductor memory device including at least one nonvolatile memory cell, and the nonvolatile memory cell is disposed on a semiconductor substrate and the semiconductor substrate. A gate insulating film formed; a gate electrode formed on the gate insulating film; a charge storage portion capable of storing charges formed on at least one side wall of the gate electrode; and the gate A channel region located under the electrode, and two diffusion layer regions formed on the semiconductor substrate surface on both sides of the channel region, from one of the two diffusion layer regions by applying a voltage to the gate electrode The amount of current flowing to the other side can be changed depending on the amount of charge accumulated in the charge accumulation unit, and is formed inside or on the surface of the charge accumulation unit during film formation. It is a first feature of the insulating film is formed comprising a water molecule at least 2 × 10 ²¹ atoms / cm ³ Te.

Furthermore, in the semiconductor memory device according to the first feature, in the nonvolatile memory cell, the charge storage unit is stacked in order of a first insulating film, a charge holding film, and a second insulating film from the semiconductor substrate side. A second feature is that the second insulating film includes at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation.

Furthermore, in the semiconductor memory device according to the first feature, the nonvolatile memory cell further includes a third insulating film that covers the charge storage unit, and the charge storage unit includes a first insulating film from the semiconductor substrate side, The charge holding film and the second insulating film are stacked in this order, and at least one of the second insulating film and the third insulating film is at least 2 × 10 ²¹ / cm at the time of film formation. ^{The third} feature is that it contains ^three water molecules.

  Furthermore, the semiconductor memory device according to the second or third feature is characterized in that the second insulating film, or the second insulating film and the third insulating film are silicon oxide films.

  Furthermore, in the semiconductor memory device according to the second or third feature, at least one of the second insulating film and the third insulating film uses tetraethoxysilane (TEOS) as a raw material and reacts with ozone. It is a silicon oxide film formed by a phase deposition method.

  Further, in the semiconductor memory device according to the second feature, at least one of the second insulating film and the third insulating film is in a position in contact with the second insulating film and not in contact with the charge retention film. A fourth feature is that an oxidizable material film that can be oxidized by reacting with moisture contained in one side is formed.

  Further, in the semiconductor memory device according to the third feature, the second insulating film and the third insulating film are in a position in contact with the second insulating film or the third insulating film and not in contact with the charge retention film. A fifth feature is that an oxidizable substance film that can be oxidized by reacting with moisture contained in at least one of the above is formed.

  Furthermore, the semiconductor memory device according to the fourth or fifth feature is characterized in that the oxidized material film is a metal or a metal compound.

  Further, the semiconductor memory device according to the fourth or fifth feature is characterized in that a silicon nitride film is formed so as to cover the oxidized material film.

  Furthermore, in the semiconductor memory device according to the fourth or fifth feature, the material film to be oxidized is at least one selected from titanium, tantalum, aluminum, nickel, cobalt, silicon, chromium, magnesium, and tungsten. A substance including a seed element, or the film to be oxidized is a nitride or oxide of at least one element selected from titanium, tantalum, and aluminum, or a combination thereof It is a metal compound comprised by these.

  Furthermore, the semiconductor memory device according to any one of the second to fifth features is characterized in that the charge retention film is a silicon nitride film.

  Furthermore, the semiconductor memory device having any one of the above characteristics is characterized in that a noble metal film having a hydrogen activation ability by catalytic action is formed on or near the surface of the charge storage portion.

  Furthermore, a semiconductor memory device according to the present invention for achieving the above object is a semiconductor memory device comprising at least one nonvolatile memory cell, wherein the nonvolatile memory cell includes a semiconductor substrate and the semiconductor substrate. A gate insulating film formed on the gate insulating film; a gate electrode formed on the gate insulating film; a charge storage portion formed on at least one of both side walls of the gate electrode; and under the gate electrode. A channel region that is positioned, and two diffusion layer regions formed on the surface of the semiconductor substrate on both sides of the channel region, and flows from one of the two diffusion layer regions to the other by applying a voltage to the gate electrode The amount of current is configured to be variable depending on the amount of charge held in the charge storage unit, and the hydrogen activity by the catalytic action on or near the surface of the charge storage unit That noble metal film having a capacity is formed to a sixth aspect of.

  Furthermore, the semiconductor memory device according to the sixth aspect is characterized in that the noble metal film is made of any one of platinum, rhodium, and palladium, or a combination thereof.

  Furthermore, the semiconductor memory device of the sixth feature is characterized in that a silicon nitride film is formed so as to cover the noble metal film.

Furthermore, a semiconductor memory device manufacturing method according to the present invention for achieving the above object is a method for manufacturing a semiconductor memory device according to the fourth or fifth feature, wherein at least 2 × 10 ²¹ semiconductor films are formed at the time of film formation. In the step after forming the insulating film and the oxidizable material film formed to contain water molecules of / cm ³ , heat treatment is performed, moisture contained in the insulating film is released and diffused to the surroundings, It is characterized in that hydrogen is generated by reacting with the oxidizable material film.

According to the semiconductor memory device having any one of the first to third characteristics, the charge storage unit such as the second insulating film or the third insulating film formed on the charge holding film holding the charge and performing the memory function. Since the insulating film formed inside or on the surface contains at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation, the moisture in the insulating film is decomposed and below the charge storage portion Therefore, it is possible to improve the memory characteristics, particularly the data retention characteristics of the semiconductor memory device, because the tunnel oxide film or the dangling bond generated at the interface between the tunnel oxide film and the semiconductor substrate can be terminated. Here, the number of water molecules when the second insulating film or the third insulating film is formed is higher than the TDS (Thermal Desorption Spectrometer) described later with respect to the insulating film exhibiting a significant improvement effect in the data retention characteristic experiment. As a result of the desorption gas analysis by the (thermal desorption gas analysis) method, 2 × 10 ²¹ molecules / cm ³ or more water molecules are detected. It is a requirement of the present invention that the insulating film formed inside or on the surface of the charge storage portion such as an insulating film contains at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation.

Furthermore, according to the semiconductor memory device of the fourth or fifth feature, the moisture in the second insulating film or the third insulating film containing at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation In the heat treatment, the material diffuses in the surrounding charge holding film and the first insulating film and comes into contact with the oxidizable material film such as a metal or a metal compound to oxidize the oxidizable material film and simultaneously generate hydrogen. . Compared with hydrogen diffused from the outside by hydrogen sinter or the like, hydrogen generated by oxidation of the material film to be oxidized is a charge holding film, a first insulating film that becomes a tunnel oxide film, a semiconductor substrate, and these Since it is generated and diffused in the vicinity of the interface, it is expected that many dangling bonds generated at the tunnel oxide film or the interface between the tunnel oxide film and the semiconductor substrate are terminated efficiently and firmly. In particular, when the charge retention film is a dense film, or when the charge storage portion or the gate electrode is covered with a P-SiN film or the like in order to realize precise processing such as a contact hole, that is, an oxidized material film In the case where there is a silicon nitride film covering the film, this characteristic configuration is very effective for diffusion of hydrogen into the shadowed portion. That is, by covering the charge storage portion and the like with a P-SiN film or the like, the silicon nitride film exhibits a conventional function as an etching stopper and is generated at or near the charge storage portion inside the silicon nitride film. Hydrogen is prevented from diffusing outward, and hydrogen is supplied to desired locations such as the first insulating film, the semiconductor substrate, and their interfaces, which efficiently become tunnel oxide films, and many dangling bonds Can be terminated more efficiently.

  As the material to be oxidized, a material such as titanium, tantalum, aluminum, nickel, cobalt, silicon chrome, magnesium, and tungsten, or a metal compound of nitride or oxide such as titanium, tantalum, or aluminum is used. Is used. These oxidizable material films come into contact with moisture at a temperature of 400 ° C. to 1000 ° C. to easily oxidize and generate hydrogen, and the generated hydrogen can be used for termination of dangling bonds.

  Furthermore, according to the semiconductor memory device of the sixth feature, since the noble metal film having the hydrogen activation ability by the catalytic action is formed on the surface of the charge storage portion or in the vicinity thereof, the active hydrogen is reduced in the vicinity of the charge storage portion. The dangling bonds can be efficiently terminated by the active hydrogen, and the memory characteristics, particularly the data retention characteristics, of the semiconductor memory device can be improved. Active hydrogen having a large diffusion coefficient diffuses to the periphery thereof, so that dangling bonds are effectively hydrogen-terminated. In addition, according to the semiconductor memory device of the sixth feature, even when the moisture in the charge storage portion or the insulating film thereover is small, the hydrogen termination of the dangling bond is promoted by the hydrogen activation ability of the noble metal film. The In the semiconductor memory device of this feature, there is no catalyst poison that deactivates the catalyst around the charge storage part. Therefore, the catalyst is generated by temperature during the manufacturing process, visible light, ultraviolet light generated from plasma in the dry etching process, or the like. It is possible to maintain the action.

In the semiconductor memory device of the sixth feature, when platinum is used as the noble metal film, the tunnel oxide film in the charge storage portion, the semiconductor substrate, and the interface between them have a mismatch of about 10 ¹³ / cm ² . Electrons were observed and an improvement was seen compared to the conventional unpaired electrons of about 10 ¹⁴ / cm ² .

Further, when the semiconductor memory device having the sixth feature and the semiconductor memory device having the second or third feature are combined, when platinum is used as the noble metal film, the tunnel oxide film of the charge storage portion, the semiconductor substrate, and The number of unpaired electrons at these interfaces was 10 ¹² / cm ² or less, which is the lower limit of detection in the electron spin resonance method, and a significant improvement was observed. For example, when platinum-titanium oxide or the like is provided on or near the surface of the charge storage portion, the charge storage portion or an insulating film above the charge storage portion (the second insulating film or the second insulating film in the semiconductor memory device having the first or second characteristics described above) Moisture diffusing from inside is adsorbed to titanium oxide and hydrogen is generated, while hydrogenation is promoted by a reduction reaction with platinum to generate active hydrogen.

  In addition, according to the semiconductor memory device having any one of the first to sixth features, a hydrogen barrier property such as a silicon nitride film is used as an etching stopper when a contact hole is opened to the diffusion layer region of the memory cell. Even when the gate electrode and the charge storage portion are thickly covered with a material excellent in hydrogen, hydrogen can be supplied not only from the hydrogen diffused by the hydrogen sinter or the like from the outside, but also inside the charge storage portion. Due to the effect of each feature, it is possible to prevent deterioration of the charge retention characteristics of the charge storage portion and provide a highly reliable semiconductor memory device having excellent data retention characteristics.

  Embodiments of a semiconductor memory device and a method for manufacturing the same according to the present invention (hereinafter abbreviated as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings. The same components as those of the memory cell of the conventional semiconductor memory device shown in FIGS. 9 and 10 will be described with the same reference numerals.

<First Embodiment>
FIG. 1 is an element cross-sectional view showing a schematic structure after formation of metal wiring of a nonvolatile memory cell of the device of the present invention. FIGS. 2A and 2B are a plan view and a sectional view schematically showing the active region 15 and the element isolation region 16 before the memory cell of the device of the present invention is formed. 2B is a cross-sectional view taken along line AA ′ of FIG. 2A, and FIG. 1 is a cross-sectional view taken along line BB ′ of FIG. It is sectional drawing in the extending | stretching direction.

  In the nonvolatile memory cell according to the present embodiment, as shown in FIGS. 1 and 2, at least a part of the semiconductor substrate 1 is an active region 15, and a gate insulating film 7 is formed on at least a part of the surface of the active region 15. A gate electrode 6 made of, for example, polycrystalline silicon is formed so as to cover at least a part of the gate insulating film 7, a channel region 16 is formed below the gate insulating film 7, and a semiconductor is formed on both sides of the channel region 17. A diffusion layer region 2 having a conductivity type opposite to that of the substrate 1 is formed. Further, sidewall-shaped charge storage portions 8 are formed on both side walls of the gate electrode 6. The charge storage unit 8 is formed from the semiconductor substrate 1 side, for example, an L-shaped first insulating film 3 made of a silicon oxide film by thermal oxidation, for example, an L-shaped charge holding film 4 made of a silicon nitride film, and, for example, The second insulating film 5 made of a silicon oxide film is stacked in this order and formed in a sidewall shape. Further, a third insulating film 11 made of a silicon oxide film containing a large amount of water is formed so as to cover a part of the gate electrode 6 and the side wall-shaped charge storage portion 8, and a part of the surface of the third insulating film 11 is formed. An oxidizable material film 12 made of a metal film is formed, and these are covered with a silicon nitride film 9. Further, an interlayer insulating film 13 is formed thereon, a contact hole 10 for connecting to the diffusion layer region 2 is opened in the interlayer insulating film 13, and a metal wiring 14 is formed.

  Next, the process of forming the memory cell shown in FIG. 1 will be described in the order of processes. In the following description, the description of general steps such as the steps of applying, exposing, developing, and removing the photoresist, and the cleaning step are well known, and thus detailed description thereof is omitted.

  First, as a semiconductor substrate, for example, an element isolation region 16 is formed on a p-type silicon substrate 1 by a known technique. The element isolation region 16 is formed by LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation) or the like. In the present embodiment, the element isolation region 16 can achieve the purpose of element isolation regardless of its cross-sectional shape. The cross-sectional shape and manufacturing method are not limited. A region excluding the element isolation region 16 of the p-type silicon substrate 1 is an active region 15.

  Next, if necessary, impurities are introduced into the surface of the active region 15 of the silicon substrate 1 by ion implantation, for example, so that the surface or bulk of the silicon substrate 1 has a desired impurity concentration. Subsequently, a silicon oxide film to be the gate insulating film 7 is formed by, for example, thermally oxidizing the surface of the silicon substrate 1.

  Next, for example, polycrystalline silicon to be the gate electrode 6 is deposited to a thickness of 300 nm and patterned by a known photolithography technique, and then the polycrystalline silicon and the gate insulating film 7 below the polycrystalline silicon are subjected to, for example, reactive ion etching or the like. The gate electrode 6 is formed by etching by anisotropic etching. The width of the gate electrode 6 (which defines the gate length) is preferably about 50 nm to 300 nm, for example, but the range is not particularly limited.

  Next, a silicon oxide film serving as a first insulating film 3 called a tunnel oxide film serving as an energy barrier between the gate electrode 6 and the charge holding film 4 is formed on both side walls of the gate electrode 6. This forms a silicon oxide film having a thickness of 5 nm by thermally oxidizing the polycrystalline silicon on the side wall surface of the gate electrode 6 and the surface of the silicon substrate 1 below both side wall portions of the gate electrode 6.

  Next, a silicon nitride film to be the charge holding film 4 is reacted by thermal decomposition at low pressure using dichlorosilane and ammonia gas to form a film having a thickness of 10 nm. The silicon nitride film preferably has a thickness of about 5 to 50 nm. Further, silane and nitrogen monoxide are reacted at a temperature of about 800 ° C. under a low pressure to form a silicon oxide film to be the second insulating film 5 on the charge retention film 4.

  In this state, etching back is performed by anisotropic etching over a wide range including at least all of the memory cell portion, and etching is performed sequentially from the upper layer portion, so that only the step portions (both side wall portions) on both sides of the gate electrode 6 are obtained. A side wall-like silicon oxide film (first insulating film 3) -silicon nitride film (charge holding film 4) -silicon oxide film (second insulating film 5) is left, and side wall-like shapes are formed on both side walls of the gate electrode 6. The charge storage unit 8 is formed. As a result, the first insulating film 3 and the charge holding film 4 are formed in an L shape.

  Next, using the gate electrode 6 and the charge storage portions 8 on both sides thereof as a mask, impurities are implanted, for example, by ion implantation to form the n-type diffusion layer region 2. FIG. 1 shows a schematic cross-sectional shape when the n-type diffusion layer region 2 is formed, for example, by ion implantation after the above etchback. The diffusion layer region 2 may be formed by, for example, an ion implantation method before or after the formation of the silicon oxide film to be the second insulating film 5 or after the deposition of the silicon nitride film 4.

  Subsequently, as a third insulating film 11, a silicon oxide film formed by thermal decomposition of TEOS (tetraethoxysilane) and reacting with ozone is formed on the second insulating film 5 so as to cover the gate electrode 6 and the charge storage portion 8. Is formed with a film thickness of 300 nm. At least one of the second insulating film 5 and the third insulating film 11 needs to be formed by a CVD method in which TEOS is used as a raw material and mixed with ozone and oxygen to perform vapor phase growth. It was found by desorption gas analysis by the TDS method that such a film contains a large amount of moisture.

  Next, anisotropic etching is performed on the silicon oxide film to be the third insulating film 11 to form the third insulating film 11 that covers only the surface of the charge storage portion 8 and the upper portion of the side wall surface of the gate electrode 6. As a result, the surface exposed without being covered with the third insulating film 11 is the upper surface of the gate electrode 6, the diffusion layer region 2 of the active region 15, and the surface of the element isolation region 16.

  Further, a metal titanium film is deposited to a thickness of 10 nm as the oxidizable material film 12 by sputtering, and heat treatment is performed to salicide the silicon substrate in the active region 15 and the polycrystalline silicon surface of the gate electrode 6. The metal titanium film 12 covering the surface of the third insulating film 11 remains in a metal state without being reacted by the heat treatment. In this state, the diffusion layer region 2 and the gate electrode 6 are electrically connected through the metal titanium film 12, so that the remaining portion of the metal titanium film 12 is not immersed in heated sulfuric acid or the like. By performing isotropic etching, both ends of the third insulating film 11 are removed while leaving a little on the surface. Thereby, conduction between the diffusion layer region 2 and the gate electrode 6 is prevented in advance. In the present embodiment, a metal titanium film is used as the oxidizable material film 12, but the same effect can be obtained even if a material other than titanium is used as long as it is a metal that can be oxidized at a heat treatment temperature in a later step.

  Next, silane and ammonia are decomposed and reacted with plasma to deposit a silicon nitride film 9 (P-SiN), which is formed so as to cover only the gate electrode 6 and its side wall portions (both side wall portions). In this state, the gate electrode 6, the charge storage film 8, the third insulating film 11 containing a lot of moisture, and the oxidizable material film 12 made of metal titanium are covered with the silicon nitride film 9 having a good hydrogen barrier property. become.

  Subsequently, a silicon oxide film (BPSG film) to which boron and phosphorus are added is deposited as the interlayer insulating film 13, and a heat treatment at about 800 ° C. is performed, and the flatness is improved by utilizing the fluidity at that time. As will be described later, this heat treatment also functions to generate hydrogen. Further, the interlayer insulating film 13 is planarized by using, for example, CMP (Chemical Mechanical Polish). Next, a contact hole 10 for connection with the diffusion layer region 2 is formed. At this time, the silicon nitride film 9 is used for unnecessary etching of the charge storage film 8, the third insulating film 11, the oxidized material film 12, and the like by dry etching when the contact hole 10 is opened on the diffusion layer region 2. It is used to perform the etching with high accuracy so as not to proceed.

  Here, the moisture contained in the third insulating film 11 reacts with the metal titanium of the oxidizable material film 12 during the heat treatment performed to improve the flatness of the interlayer insulating film 13, and the silicon substrate 1 and the silicon nitride. Hydrogen generated in the region surrounded by the film 9 is sufficiently diffused into the sidewall portion centering on the charge storage portion 8. Here, in addition to the above function as an etching stopper, the silicon nitride film 9 having an excellent hydrogen barrier property prevents hydrogen generated in the region from diffusing outwardly, so that the hydrogen is effectively side-exposed. It functions to promote diffusion into the wall. As a result, the dangling bonds generated at the first insulating film 3 (tunnel oxide film) of the charge storage portion 8, the semiconductor substrate 1, and the interface between them are hydrogen-terminated, and the dangling bond is caused by dangling bonds. The number of electrons can be reduced, the charge can be prevented from moving to the outside through the level due to unpaired electrons, and the charge retention characteristics are improved.

  The silicon nitride film 9 is formed so as to cover the sidewall portion including the charge storage portion 8, and even if hydrogen sintering is performed after the formation of the silicon nitride film 9 and before formation of a metal wiring such as aluminum, the silicon nitride film 9 is formed. Therefore, the effect of the hydrogen sinter on the sidewall portion is not sufficiently exhibited. However, after the metal wiring is formed, hydrogen is cut off by the thicker metal wiring itself, so the hydrogen sintering process is performed at 400 ° C. in a 2% hydrogen atmosphere. Thereafter, the metal wiring 14 mainly composed of aluminum is formed by a known technique.

  Through the above steps, the semiconductor substrate 1, the gate insulating film 7 formed on the semiconductor substrate 1, the gate electrode 6 formed on the gate insulating film 7, and both side walls of the gate electrode 6 are arranged from the semiconductor substrate 1 side. 1 is an insulating film 3, a charge holding film 4, and a second insulating film 5, which are stacked in this order, a channel region 17 located under the gate electrode 6, and the surface of the semiconductor substrate 1 on both sides of the channel region 17. The nonvolatile memory cell of the device of the present invention comprising the two diffusion layer regions 2 formed in the above is formed. Note that the contact hole 10 and the metal wiring 14 for connection to the diffusion layer region 2 exemplified in the above description are not necessarily provided for each memory cell, and are not limited to the configuration shown in FIG.

  In the nonvolatile memory cell of the device of the present invention formed through the above steps, the amount of current flowing from one (drain region) to the other (source region) of the two diffusion layer regions 2 by applying a voltage to the gate electrode 6 is reduced. This changes depending on the amount of charge held in the charge holding film 4 of the charge storage section 8. Here, depending on which diffusion layer region 2 is on the drain side, it is determined which charge accumulation amount of the charge accumulation unit 8 affects the current amount of the drain-source current, and by switching the current direction, 2-bit data can be read. The device according to the present invention includes at least one memory cell array in which a plurality of the nonvolatile memory cells are arranged in the row direction and the column direction, and performs memory reading, writing, and erasing operations on the memory cell array. A peripheral circuit to be executed is provided. Each memory operation for reading, writing, and erasing data is described in detail in Patent Document 2, and the peripheral circuit is configured based on a known technique based on the processing of the memory operation. Detailed explanation is omitted.

In the present embodiment, a silicon oxide film containing a large amount of moisture is used as the third insulating film 11, but in order to compare and examine the effect of improving the charge retention characteristics due to the difference in the amount of moisture in the third insulating film 11, A film in the case of using a silicon oxide film in which the deposition temperature of the silicon oxide film as the insulating film 11 is changed to change the water content, and a silicon oxide film deposited at a high temperature using silane and nitrogen monoxide The correlation between the amount of water in the medium and the number of unpaired electrons measured by the electron spin resonance method was investigated. As shown in FIG. 3, when the water content (number of water molecules per unit volume) is 2 × 10 ²¹ molecules / cm ³ or more, the number of unpaired electrons decreases rapidly. This means that in order to improve the charge retention characteristics, dangling bonds are not effectively diffused unless moisture is retained in the film at least about 2 × 10 ²¹ pieces / cm ^3. It is suggested that hydrogen does not terminate sufficiently and unpaired electrons do not disappear.

In the present embodiment, the third insulating film 11 is formed at a film formation temperature of 400 ° C. using a CVD method (chemical vapor deposition method) that reacts with ozone using TEOS as a raw material. The moisture content of the third insulating film 11 is 2 × 10 ²¹ pieces / cm ³ by desorption gas analysis by the TDS method, and the number of unpaired electrons measured by the electron spin resonance method is about 5 × 10 ¹² pieces / cm ^3. cm ² . In the conventional MONOS type multi-valued memory having a sidewall structure, the number of unpaired electrons is about 10 ¹⁴ / cm ² , and therefore the effect of improving the charge retention characteristics by using the third insulating film 11 containing a large amount of moisture. Was confirmed.

Second Embodiment
Next, a second embodiment of the nonvolatile memory cell of the device of the present invention will be described with reference to FIG. FIG. 4 is an element cross-sectional view showing a schematic structure after metal wiring formation of the nonvolatile memory cell according to the second embodiment. The cross-sectional view of FIG. 4 is a cross-sectional view in the BB ′ cross section (the extending direction of the active region 15) of FIG.

  In the nonvolatile memory cell according to the second embodiment, as shown in FIGS. 4 and 2, at least a part of the semiconductor substrate 1 is an active region 15, and a gate insulating film 7 is formed on at least a part of the surface of the active region 15. Then, a gate electrode 6 made of, for example, polycrystalline silicon is formed so as to cover at least a part of the gate insulating film 7, and a channel region 16 is formed below the gate insulating film 7, and on both sides of the channel region 17. A diffusion layer region 2 having a conductivity type opposite to that of the semiconductor substrate 1 is formed. Further, sidewall-shaped charge storage portions 8 are formed on both side walls of the gate electrode 6. The charge storage unit 8 is formed from the semiconductor substrate 1 side, for example, an L-shaped first insulating film 3 made of a silicon oxide film by thermal oxidation, for example, an L-shaped charge holding film 4 made of a silicon nitride film, and, for example, The second insulating film 5 made of a silicon oxide film is stacked in this order and formed in a sidewall shape. Further, an oxidizable material film 12 made of a metal film is formed at a position in contact with the second insulating film 5 on the surface of the charge storage portion 8 and not in contact with the charge holding film 4. A third insulating film 11 made of a silicon oxide film containing a large amount of water is formed so as to cover the material film 12 and the gate electrode 6, and is covered with the silicon nitride film 9. Further, an interlayer insulating film 13 is formed thereon, a contact hole 10 for connecting to the diffusion layer region 2 is opened in the interlayer insulating film 13, and a metal wiring 14 is formed. In addition, since the formation method of each part is the same as 1st Embodiment, the overlapping description is abbreviate | omitted.

  The difference from the nonvolatile memory cell of the first embodiment is that, in the first embodiment, the oxidizable material film 12 is formed on the third insulating film 11, whereas in the second embodiment, the oxidizable material film 12 is formed. The oxide material film 12 is different in that it is formed between the third insulating film 11 and the second insulating film 5. However, also in the second embodiment, the third insulating film 11 and the oxidized material film 12 containing a large amount of moisture are present in the region surrounded by the silicon substrate 1 and the silicon nitride film 9, and thus generated in the region. The hydrogen thus diffused sufficiently into the sidewall portion centered on the charge storage portion 8, and similarly to the first embodiment, the first insulating film 3 (tunnel oxide film) of the charge storage portion 8, the semiconductor substrate 1, and , Dangling bonds generated at the interface between them can be hydrogen-terminated to reduce the number of unpaired electrons caused by the dangling bonds and prevent the charge from moving outside through the level due to the unpaired electrons Charge retention characteristics are improved.

  The location where the oxidizable material film 12 is formed is not limited to the position shown in FIGS. 1 and 4, and moisture in the region covered with the silicon nitride film 9 having excellent hydrogen barrier properties can be removed. Any position may be used as long as it is in contact with the third insulating film 11 including many and not in contact with the charge holding film 4.

<Third Embodiment>
Next, a third embodiment of the nonvolatile memory cell of the device of the present invention will be described with reference to FIG. FIG. 5 is an element cross-sectional view showing a schematic structure after metal wiring formation of the nonvolatile memory cell according to the third embodiment. The cross-sectional view of FIG. 5 is a cross-sectional view in the BB ′ cross section (the extending direction of the active region 15) of FIG.

  In the nonvolatile memory cell according to the third embodiment, as shown in FIGS. 5 and 2, at least a part of the semiconductor substrate 1 is an active region 15, and a gate insulating film 7 is formed on at least a part of the surface of the active region 15. Then, a gate electrode 6 made of, for example, polycrystalline silicon is formed so as to cover at least a part of the gate insulating film 7, and a channel region 16 is formed below the gate insulating film 7, and on both sides of the channel region 17. A diffusion layer region 2 having a conductivity type opposite to that of the semiconductor substrate 1 is formed. Further, sidewall-shaped charge storage portions 8 are formed on both side walls of the gate electrode 6. The charge storage unit 8 is formed from the semiconductor substrate 1 side, for example, an L-shaped first insulating film 3 made of a silicon oxide film by thermal oxidation, for example, an L-shaped charge holding film 4 made of a silicon nitride film, and, for example, The second insulating film 5 made of a silicon oxide film containing a large amount of moisture is laminated in this order, and is formed in a sidewall shape. Further, an oxidizable material film 12 made of a metal film is formed at a position in contact with the second insulating film 5 on the surface of the charge storage portion 8 and not in contact with the charge holding film 4. The material film 12 and the gate electrode 6 are covered with a silicon nitride film 9. Further, an interlayer insulating film 13 is formed thereon, a contact hole 10 for connecting to the diffusion layer region 2 is opened in the interlayer insulating film 13, and a metal wiring 14 is formed. In addition, since the formation method of each part is the same as 1st Embodiment, the overlapping description is abbreviate | omitted.

  The difference from the nonvolatile memory cell of the first embodiment is that in the first embodiment, the third insulating film 11 covers a part of the gate electrode 6 and the side wall-shaped charge storage portion 8 although it contains a lot of moisture. In contrast, in the third embodiment, the third insulating film 11 containing a large amount of moisture is not formed. Instead, the second insulating film 5 of the charge storage portion 8 contains silicon containing a lot of moisture. It differs in that it is formed of an oxide film. However, also in the third embodiment, since the second insulating film 5 and the oxidizable material film 12 containing a large amount of water exist in the region surrounded by the silicon substrate 1 and the silicon nitride film 9, they are generated in the region. The hydrogen thus diffused sufficiently into the sidewall portion centered on the charge storage portion 8, and similarly to the first embodiment, the first insulating film 3 (tunnel oxide film) of the charge storage portion 8, the semiconductor substrate 1, and , Dangling bonds generated at the interface between them can be hydrogen-terminated to reduce the number of unpaired electrons caused by the dangling bonds and prevent the charge from moving outside through the level due to the unpaired electrons Charge retention characteristics are improved.

  The advantage of providing the third insulating film 11 in the first embodiment and the second embodiment is that the third insulating film 11 can be grown at a lower temperature (about 400 ° C.) than the second insulating film 5. This is advantageous in that it can contain a large amount of water and can generate a large amount of hydrogen accordingly.

<Fourth embodiment>
Next, a non-volatile memory cell according to a fourth embodiment of the device of the present invention will be described with reference to FIG. 1, FIG. 4, and FIG.

  The nonvolatile memory cell according to the fourth embodiment is oxidized in the nonvolatile memory cell according to the first embodiment, the second embodiment, or the third embodiment shown in FIG. 1, FIG. 4, or FIG. Instead of the material film 12, a noble metal film having a hydrogen activating ability by catalytic action such as platinum is formed. Except that the oxidizable material film 12 is replaced with a noble metal film, the components of the nonvolatile memory cells of the first embodiment, the second embodiment, or the third embodiment and the formation process thereof are the same. A duplicate description is omitted.

  In the nonvolatile memory cell according to the fourth embodiment, since a noble metal film having a hydrogen activation ability by catalytic action is formed on or near the surface of the charge storage unit 8, active hydrogen is generated in the vicinity of the charge storage unit 8. The dangling bonds can be effectively terminated by the active hydrogen, and the memory characteristics, particularly the data retention characteristics, of the semiconductor memory device can be improved. Active hydrogen having a large diffusion coefficient diffuses to the periphery thereof, so that dangling bonds are effectively hydrogen-terminated. Even when the moisture in the third insulating film 11 or the second insulating film 5 is small, the hydrogen termination of the dangling bond is promoted by the hydrogen activation ability of the noble metal film. That is, even when the amount of moisture desorbed from the third insulating film 11 or the second insulating film 5 is small, if the normal low-temperature hydrogen sintering process is performed, the hydrogen diffused from the outside is more efficiently dangling. It becomes possible to bond to the bond, and the effect of the hydrogen sintering treatment can be obtained.

<Fifth Embodiment>
Next, a fifth embodiment of the non-volatile memory cell of the device of the present invention will be described with reference to FIG. 1, FIG. 4, and FIG.

  The nonvolatile memory cell according to the fifth embodiment is oxidized in the nonvolatile memory cell according to the first embodiment, the second embodiment, or the third embodiment shown in FIG. 1, FIG. 4, or FIG. In addition to the material film 12, a noble metal film having a hydrogen activation ability by catalytic action such as platinum is further formed. The formation position of the noble metal film is the same as the formation position of the oxidizable material film 12, and the oxidizable material film 12 and the noble metal film do not necessarily have to be formed at the same position. For example, a noble metal film may be formed at the formation position of the oxidizable material film 12 of the nonvolatile memory cell of the second embodiment with respect to the nonvolatile memory cell of the first embodiment. The nonvolatile memory cell according to the fifth embodiment is a component of each nonvolatile memory cell according to the first embodiment, the second embodiment, or the third embodiment, and the formation process thereof, except that a noble metal film is added. Are the same, and redundant description is omitted.

  In the nonvolatile memory cell according to the fifth embodiment, an oxidizable material film 12 for decomposing moisture in the silicon oxide film and a noble metal film having a hydrogen activation ability by catalytic action are formed on or near the surface of the charge storage unit 8. Since both are formed, active hydrogen can be easily generated in the vicinity of the charge storage portion 8 as compared with the fourth embodiment, and the dangling bond can be terminated more efficiently and firmly by the active hydrogen. Thus, the memory characteristics of the semiconductor memory device, particularly the data retention characteristics can be greatly improved. Active hydrogen having a large diffusion coefficient diffuses to the periphery thereof, so that dangling bonds are effectively hydrogen-terminated. Even when the moisture in the third insulating film 11 or the second insulating film 5 is small, the hydrogen termination of the dangling bond is promoted by the hydrogen activation ability of the noble metal film.

  Next, the charge retention characteristics in the above embodiments are compared and evaluated. In FIG. 6, each non-volatile in 1st Embodiment (arrow A), 4th Embodiment (arrow B), 5th Embodiment (arrow C), and two conventional examples (arrow D, E) Each of the charge retention characteristics of a single type of memory cell is shown. The conventional example of arrow D is a conventional MONOS type multi-valued memory having a sidewall-like structure, and the conventional example of arrow E is a case where hydrogen sintering at 850 ° C. is performed with respect to the conventional example of arrow D. Charge retention characteristics.

  In FIG. 6, the horizontal axis represents a current difference obtained by subtracting the read current before charge injection from the read current in a state where electrons are injected into the charge holding film 4 on one side of the charge storage unit 8 for 1-bit writing. In other words, it indicates a single-bit read operation margin. The vertical axis shows the amount of fluctuation in the read current indicating how much the read current in the write (electron injection) state has changed before and after the acceleration test after baking at 250 ° C. for 15 minutes, which is a kind of acceleration test. is there. FIG. 6 shows the charge retention characteristics with a single bit. When operating a large number of memory cells like a memory cell array, it is necessary to consider the characteristic variation between the memory cells. In addition, 60 μA is required as a read operation margin with a single bit because of circuit requirements such as a sense amplifier for detecting a difference in read current. In this case, in order to ensure the reliability of the device, the current change before and after the acceleration test is preferably 1 μA or less.

  In the charge retention characteristic of the conventional example indicated by the arrow D, there is a current change of 25 μA with respect to the writing amount of 60 μA, which is insufficient to ensure the desired data retention characteristic. Although the conventional example of arrow E shows an improvement in charge retention characteristics as compared with the conventional example of arrow D, it is difficult to realize in practice due to undesired transistor threshold fluctuations and the like.

  In the first embodiment (arrow A), the fourth embodiment (arrow B), and the fifth embodiment (arrow C) of the present invention indicated by arrows A to C, the effect of improving the charge retention characteristics is obtained. It has been. In particular, in the charge retention characteristics of the fifth embodiment indicated by arrow C, the current change before and after the acceleration test shows a very good result of 0.72 μA, which sufficiently satisfies the desired data retention characteristics requirement. .

  In addition, the table of FIG. 7 shows the current change of the read current before and after the acceleration test with respect to the write amount of 60 μA in the charge retention characteristics of each series A to E of FIG. 6 and the number of unpaired electrons measured by the electron spin resonance method. Show. From the table of FIG. 7, a strong correlation is observed between the number of unpaired electrons and the change in the read current, and the same conclusion as described above can be obtained from this result.

  Next, another embodiment of the device of the present invention and the method of the present invention will be described.

  <1> In each of the above embodiments, a silicon nitride film is used as the charge retention film 4 that retains charges and performs the memory function. This is because it is easy to introduce into a mass production factory and is very preferable. However, the film configuration and material of the charge accumulating portion 8 are not limited to the above embodiment, but a film or material having a charge holding function, for example, a silicate glass containing impurities such as a silicon nitride film and phosphorus-boron, As long as silicon carbide, alumina, hafnium oxide, zirconium oxide, tantalum oxide, zinc oxide, ferroelectric material, etc., a laminated structure film of an insulating film or a material having a discrete charge holding function is included in the insulator Basically, it is possible to realize the nonvolatile memory cell of the device of the present invention.

  <2> In each of the above embodiments, the case where the charge storage portion 8 is formed on each side wall portion of the gate electrode 6 has been described. However, the charge storage portion 8 is on either side of the both side wall portions of the gate electrode 6. The present invention can also be applied to a memory cell structure existing only in the memory cell, and the effect of improving the data retention characteristics according to the present invention can be sufficiently expected.

  <3> In the first, second, third, or fifth embodiment, the metal titanium film is used as the material of the oxidizable material film 12, but the material of the oxidizable material film 12 is limited to the above embodiment. Any material that can react with moisture and oxidize to generate hydrogen may be used. For example, the material film 12 to be oxidized includes a material including at least one element selected from tantalum, aluminum, nickel, cobalt, silicon, chromium, magnesium, and tungsten in addition to titanium, or It is also preferred that the metal compound be composed of a nitride or oxide of at least one element selected from titanium, tantalum, and aluminum, or a combination thereof. Note that, when a metal titanium film is used as the material of the oxidizable substance film 12, it is easy to oxidize at a low temperature as compared with other materials, which is preferable because the processing temperature can be lowered.

  <4> In the fourth or fifth embodiment, platinum is exemplified as an example of a noble metal film having a hydrogen activation ability by catalytic action. However, the noble metal film may have a hydrogen activation ability by catalytic action. For example, it is not limited to platinum. For example, in addition to platinum alone, the noble metal film may be rhodium, palladium, or a combination of two or more of platinum, rhodium, and palladium.

  <5> In each of the above embodiments, the case where the p-type silicon substrate 1 is used as the semiconductor substrate has been described. However, the conductivity type of the semiconductor substrate 1 is not limited to the p-type, and may be an n-type. Absent. Needless to say, when the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layer region 2 is p-type. Further, the semiconductor substrate 1 is not limited to a bulk substrate, and may be a semiconductor substrate crystal-grown on an insulator or a well formed by impurity implantation on a bulk substrate.

  <6> In each of the above embodiments, a second-layer metal wiring may be formed above the metal wiring 14 via another interlayer insulating film and a via hole, and the number of metal wiring layers is not particularly limited. . In general, if the number of metal wiring layers increases, the effect of the hydrogen sintering performed in the final process is that the diffusion distance until reaching the desired location increases and the metal wiring itself inhibits hydrogen diffusion. Since it becomes difficult to obtain the effect, the effect of introducing the present invention becomes more remarkable.

  <7> In each of the above embodiments, the gate electrode 6 is made of polycrystalline silicon. However, the material of the gate electrode 6 is not limited to polycrystalline silicon. For example, aluminum, tungsten, copper, etc. You may use the metal containing these elements. By using metal for the gate electrode 6, it is possible to reduce the word line resistance when a memory cell array is configured, to suppress signal delay on the word line, and to improve electrical characteristics in memory operation.

  INDUSTRIAL APPLICABILITY The semiconductor memory device and the manufacturing method thereof according to the present invention can be used for a non-volatile semiconductor memory device. Data retention characteristics can be improved by using the nonvolatile semiconductor memory device including the nonvolatile memory cells.

Sectional drawing which shows schematic structure in 1st Embodiment of the memory cell of the semiconductor memory device based on this invention The top view which shows the planar structure before memory cell formation in one Embodiment of the memory cell of the semiconductor memory device based on this invention The figure which shows the relationship between the water concentration in the 3rd insulating film in 1st Embodiment of the memory cell of the semiconductor memory device based on this invention, and the number of unpaired electrons. Sectional drawing which shows schematic structure in 2nd Embodiment of the memory cell of the semiconductor memory device based on this invention Sectional drawing which shows schematic structure in 3rd Embodiment of the memory cell of the semiconductor memory device based on this invention 6 is a characteristic diagram showing an example of charge retention characteristics in each memory cell of a semiconductor memory device according to the present invention and a conventional charge storage region discrete type MONOS type multi-value memory. Comparison table showing the correlation between the number of unpaired electrons and the change in read current in each memory cell of the semiconductor memory device according to the present invention and the conventional charge storage region discrete type MONOS type multi-value memory Element sectional view showing a schematic configuration of a memory cell of a charge storage region discrete type MONOS type multi-value memory disclosed in Patent Document 1 Device sectional view showing a schematic configuration of a memory cell of a MONOS type multi-valued memory of a charge storage region discrete type disclosed in Patent Document 2 FIG. 9 is an element cross-sectional view showing a schematic configuration in a state in which a P-SiN film, an interlayer insulating film, and a contact hole are formed above the memory cell of the conventional example shown in FIG.

Explanation of symbols

1: Semiconductor substrate 2: Diffusion layer region 3: First insulating film (tunnel oxide film)
4: Charge holding film 5: Second insulating film 6: Gate electrode 7: Gate insulating film 8: Charge storage portion 9: Silicon nitride film 10: Contact hole
11: Third insulating film 12: Oxidized material film (titanium film)
13: Interlayer insulating film (BPSG film)
14: Metal wiring 15: Active region 16: Element isolation region 17: Channel region 21: Semiconductor substrate 22: Diffusion layer region 23: First insulating film (oxide film)
24: Charge retention film (nitride film)
25: Second insulating film (oxide film)
26: Gate electrode

Claims (21)

A semiconductor memory device comprising at least one nonvolatile memory cell,
The nonvolatile memory cell is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A charge accumulating portion capable of accumulating charges formed on at least one of both side walls of the gate electrode;
A channel region located under the gate electrode;
Two diffusion layer regions formed on the surface of the semiconductor substrate on both sides of the channel region,
The amount of current flowing from one of the two diffusion layer regions to the other by voltage application to the gate electrode is configured to be variable depending on the amount of charge accumulated in the charge accumulation unit,
A semiconductor memory device, wherein an insulating film containing at least 2 × 10 ²¹ molecules / cm ³ of water molecules is formed inside or on the surface of the charge storage portion during film formation. In the nonvolatile memory cell,
The charge storage portion is formed by laminating a first insulating film, a charge holding film, and a second insulating film in this order from the semiconductor substrate side,
2. The semiconductor memory device according to claim 1, wherein the second insulating film contains at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation.   The semiconductor memory device according to claim 2, wherein the second insulating film is a silicon oxide film.   4. The semiconductor memory device according to claim 3, wherein the silicon oxide film is formed by a chemical vapor deposition method using tetraethoxysilane (TEOS) as a raw material and reacting with ozone. The nonvolatile memory cell further includes a third insulating film that covers the charge storage portion,
The charge storage portion is formed by laminating a first insulating film, a charge holding film, and a second insulating film in this order from the semiconductor substrate side,
2. The device according to claim 1, wherein at least one of the second insulating film and the third insulating film contains at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation. Semiconductor memory device.   6. The semiconductor memory device according to claim 5, wherein the second insulating film and the third insulating film are silicon oxide films.   At least one of the second insulating film and the third insulating film is a silicon oxide film formed by a chemical vapor deposition method using tetraethoxysilane (TEOS) as a raw material and reacting with ozone. A semiconductor memory device according to claim 5 or 6.   An oxidizable material film that can be oxidized by reacting with moisture contained in the second insulating film is formed at a position in contact with the second insulating film and not in contact with the charge retention film. The semiconductor memory device according to claim 2.   Reaction with moisture contained in at least one of the second insulating film and the third insulating film at a position in contact with the second insulating film or the third insulating film and not in contact with the charge retention film 8. The semiconductor memory device according to claim 5, wherein an oxidizable material film that can be oxidized is formed.   10. The semiconductor memory device according to claim 8, wherein the oxidizable material film is a metal or a metal compound.   The oxidizable material film is a material including at least one element selected from titanium, tantalum, aluminum, nickel, cobalt, silicon, chromium, magnesium, and tungsten. The semiconductor memory device according to claim 8 or 9.   The oxidizable material film is a metal compound composed of a nitride or oxide of at least one element selected from titanium, tantalum, and aluminum, or a combination thereof. 10. The semiconductor memory device according to claim 8 or 9.   13. The semiconductor memory device according to claim 8, wherein a silicon nitride film is formed so as to cover the oxidizable material film.   The semiconductor memory device according to claim 2, wherein the charge retention film is a silicon nitride film.   15. The semiconductor memory device according to claim 1, wherein a noble metal film having a hydrogen activation ability by catalytic action is formed on or near the surface of the charge storage portion.   The semiconductor memory device according to claim 15, wherein the noble metal film is made of any one of platinum, rhodium, and palladium, or a combination thereof. A semiconductor memory device comprising at least one nonvolatile memory cell,
The nonvolatile memory cell is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A charge storage portion formed on at least one of both side walls of the gate electrode;
A channel region located under the gate electrode;
Two diffusion layer regions formed on the surface of the semiconductor substrate on both sides of the channel region,
The amount of current flowing from one of the two diffusion layer regions to the other by applying a voltage to the gate electrode can be changed depending on the amount of charge held in the charge storage unit,
A semiconductor memory device, wherein a noble metal film having a hydrogen activating ability by catalytic action is formed on or near the surface of the charge storage portion.   18. The semiconductor memory device according to claim 17, wherein the noble metal film is made of any one of platinum, rhodium, and palladium, or a combination thereof.   19. The semiconductor memory device according to claim 17, wherein a silicon nitride film is formed so as to cover the noble metal film. 14. A method of manufacturing a semiconductor memory device according to claim 8, wherein
In the step after forming the insulating film and the oxidizable material film including at least 2 × 10 ²¹ molecules / cm ³ of water molecules at the time of film formation, heat treatment is performed and the insulating film is included in the insulating film. A method of manufacturing a semiconductor memory device, characterized in that moisture is released and diffused to the surroundings to react with the oxidized material film to generate hydrogen. 21. The method of manufacturing a semiconductor memory device according to claim 20, wherein the heat treatment is a heat treatment in a planarization process at the time of forming an interlayer insulating film after forming the oxidizable material film.