JP2009246456A - Logic module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic module capable of easily accelerating the operation frequency of signals. <P>SOLUTION: The logic module 100 includes FPGAs 101 and 102, connectors 105(107) and 106(108), and a connection switching circuit 103(104). When the FPGA 101 is connected through the connection switching circuit 103(104) to the FPGA 102 or the connector 106(108), a bus terminating resistor 131(133) is connected to the inner side of the connection pin of the FPGA 101 connected with the connection switching circuit 103(104). Also, when the FPGA 102 is connected through the connection switching circuit 103(104) to the FPGA 101 or the connector 105(107), a bus terminating resistor 134(135) is connected to the inner side of the connection pin of the FPGA 102 connected with the connection switching circuit 103(104). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a logic module for hardware emulation in which logic to be verified is programmed in a plurality of programmable logic elements and logic of a large scale integrated circuit is verified.

  In recent years, large-scale integrated circuits (LSIs) applied to information processing apparatuses such as servers and networks have been increased in scale, multi-pins, and downsized. When designing such an LSI, in order to improve the logic verification accuracy of the LSI, in addition to conventional software emulation technology, hardware emulation using a programmable logic element FPGA (Field Programmable Gate Array) is used. A method applied to LSI logic verification is used. However, with the recent increase in LSI gate scale, logic verification has required a large number of FPGAs.

  In order to meet this requirement, a plurality of logic modules equipped with a plurality of FPGAs are prepared, the logic to be verified is logically divided into a plurality of logic modules, and these logic modules are connected via connectors for external connection of the logic modules. It is necessary to construct a hardware emulation device by connecting in multiple stages and to connect it to a system board subject to logic verification.

As an example of the verification logic module, for example, a technique described in JP 2001-318124 A can be cited. In the conventional technique, a plurality of logic modules are connected in multiple stages via external connection connectors of the logic modules, and the logic modules are stacked in the upper or lower stage to cope with the increase in the gate scale. An example of a verification logic module that improves this is disclosed in, for example, Japanese Patent Application Laid-Open No. 2007-201843.
JP 2001-318124 A JP 2007-201843 A

In order to construct a hardware emulation device as described above and verify a logic circuit in a shorter time, it is necessary to further increase the operating frequency of signals between a plurality of FPGAs.
Accordingly, an object of the present invention is to provide a logic module that can easily realize an increase in the operating frequency of a signal.

  In the present invention, when a plurality of logic modules are connected in one logic module or in multiple stages, the connection path is switched according to the circuit configuration of the logic to be verified by a connection switching circuit that switches the connection path between logic elements. Yes, configure the circuit so that logic elements are arranged on both sides of this connection switching circuit, and add termination resistors in the logic elements to improve the waveform quality of the signal and easily increase the operating frequency of the signal It is something that is going to be realized.

  The logic module according to the present invention includes programmable first and second logic elements, first and second connectors for connecting to the outside, the first logic element and the second logic element, Connection, connection between the first connector and the second connector, connection between the first logic element and the second connector, and connection between the second logic element and the first connector And a connection switching circuit that enables connection of at least one of the first and the connection switching circuit, and a wiring that connects the first connector and the connection switching circuit, and a connection pin of the first logic element. A first stub resistor connected between, a second stub resistor connected between a wiring connecting the second connector and the connection switching circuit, and a connection pin of the second logic element; The first logic element is the A bus termination resistor connected inside the connection pin of the first logic element connected to the connection switching circuit when connected to the second logic element or the second connector via a connection switching circuit; A connection pin of the second logic element connected to the connection switching circuit when the second logic element is connected to the first logic element or the first connector via the connection switching circuit And a bus termination resistor connected to the inside.

  Two logic modules are provided, and the second connector of one logic module and the first connector of the other logic module are connected to form a logic module having a multi-stage configuration. Also, three logic modules are provided, the second connector of the first logic module is connected to the first connector of the second logic module, and the second connector of the second logic module is connected to the third connector. A logic module having a multi-stage configuration can be obtained by connecting the first connector of the logic module. In this case, the second logic module forms a bridge circuit by connecting the first logic element and the second connector and connecting the second logic element and the first connector in the connection switching circuit. can do. A connection switching control signal output circuit that generates a connection switching control signal for switching the connection switching circuit can be provided in the first or second logic element.

  The logic module includes first and second memory modules, and the first and second logic elements respectively have first and second memory control circuits for accessing the first and second memory modules. Can have. Further, the logic module includes first and second memory modules, and the first and second logic elements allow the first or second logic element to access the first and second memory modules. Can have.

  According to the present invention, it is possible to obtain a logic module that can easily realize an increase in the operating frequency of a signal. Conventionally, when connecting a plurality of FPGAs in a plurality of logic modules with a signal, it is difficult to add a termination resistor in the FPGA which becomes both ends of the signal, and it is difficult to improve the waveform quality of the signal. . In the present invention, the stub resistance is added to the wiring between the connector for connecting to the outside and the logic element, and the termination resistance is added in the logic element at both ends of the connection signal, so that the waveform quality is improved. The operating frequency of these signals is increased.

  In addition, by connecting two or more logic modules in multiple stages, the required number of logic modules can be used according to the logic scale to be verified, and by switching the connection switching circuit with a connection switching control signal, All programmable logic elements in a module can be configured with bus connections or pin-to-pin connections. In addition, when many logic modules are connected in multiple stages, if the number of logic elements connected by the bus is too large, the waveform quality of the signal may be deteriorated and the operating frequency may not be increased. In this case, by incorporating a bridge circuit and a terminating resistor in the logic module in the middle of the bus connection, the logic elements connected to the bus can be appropriately separated, and the signal quality can be reduced without degrading the signal waveform quality. It is possible to increase the operating frequency.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a logic module according to the present invention. The logic module is a board provided with a connector for connecting a plurality of programmable logic elements and the outside, and a connection switching circuit for connecting the plurality of programmable logic elements and the connector. As shown in the figure, the logic module 100 of this example uses an FPGA as a programmable logic element, and includes two FPGAs 101 and 102.

  In FIG. 1, a logic signal wiring (hereinafter simply referred to as “wiring”) connection switching circuit 103 is connected between the external connection socket connector 105 and the external connection header connector 106 via the wiring 110 and the wiring 111. Is done. The connection switching circuit 103 is connected between the FPGA 101 and the FPGA 102 via the wiring 112 and the wiring 113. Similarly, the connection switching circuit 104 is connected between the external connection socket connector 107 and the external connection header connector 108 via the wiring 120 and the wiring 121. The connection switching circuit 104 is connected between the FPGA 101 and the FPGA 102 via a wiring 122 and a wiring 123. That is, the connection switching circuit 103 (104) connects the FPGA 101 and the FPGA 102, connects the external connection socket connector 105 (107) and the external connection header connector 106 (108), and connects the FPGA 101 and the external connection header connector 106 ( 108) and the connection between the FPGA 102 and the external connection socket connector 105 (107).

  FIG. 2 is a diagram for explaining the connection switching circuit of FIG. In FIG. 2, MOSFETs 401, 402, 403, 404 are mounted between wirings 410, 411 and 420, 421, respectively. By connecting connection switching control signals (High, Low) to the connection switching control pins 430, 431, and 432 and via the signal decoding circuit 440, the connection paths of the wirings 410, 411, 420, and 421 can be switched. FIG. 8 is a diagram showing the relationship between the input signal of the connection switching control pin in FIG. 2 and ON / OFF of each MOSFET. According to the signal decoding circuit truth table shown in FIG. 8, for example, when the connection switching control pin 430 is “High” and the connection switching control pins 431 and 432 are “Low”, the MOSFET 401 is turned on and the MOSFETs 402, 403, and 404 are turned off. As a result, the wirings 410 and 420 are connected. For example, when the connection switching control pin 432 is “High” and the connection switching control pins 430 and 431 are “Low”, the MOSFET 404 is turned on, and the MOSFETs 401, 402, and 403 are turned off. As a result, the signal groups 411 and 421 are turned on. Is connected. In accordance with this signal decode circuit truth table, the connection state of wirings 410, 411 and 420, 421 is controlled.

  In FIG. 1, connection switching control signals 114, 115, and 116 input to the connection switching circuit 103 correspond to connection switching control signals input to the connection switching control pins 430, 431, and 432 shown in FIG. In this example, a connection switching control signal output circuit 180, which is a circuit for generating a connection switching control signal, is mounted on the FPGA 101, and "High" or "Low" is output according to the circuit configuration of the verification target logic. When the connection switching control signal 116 is “High” and the signals 114 and 115 are “Low”, the wiring 112 and the wiring 113 are connected via the wiring pin 192 and the wiring pin 193 of the connection switching circuit 103 as shown in FIG. Connected.

  Similarly, the connection switching control signal output circuit 180 outputs “High” or “Low” as the connection switching control signals 124, 125, 126 input to the connection switching circuit 104 in accordance with the circuit configuration of the verification target logic. To do. When the connection switching control signal 126 is “High” and the signals 124 and 125 are “Low”, the wiring 122 and the wiring 123 are connected via the wiring pin 194 and the wiring pin 195 of the connection switching circuit 104 as shown in FIG. Connected.

  A stub resistor 170 (172) is connected between the wiring 110 (120) for connecting the external connection socket connector 105 (107) and the connection switching circuit 103 (104) and the connection pin (IO pin) of the FPGA 101. . A stub resistor 171 (173) is connected between the wiring 111 (121) connecting the external connection header connector 106 (108) and the connection switching circuit 103 (104) and the connection pin of the FPGA 102. Further, when the FPGA 101 is connected to the FPGA 102 or the external connection header connector 106 (108) via the connection switching circuit 103 (104), the FPGA 101 is connected to the inside of the connection pin of the FPGA 101 connected to the connection switching circuit 103 (104). A bus termination resistor 131 (133) is connected. When the FPGA 102 is connected to the FPGA 101 or the external connection socket connector 105 (107) via the connection switching circuit 103 (104), the FPGA 102 is connected to the inside of the connection pin of the FPGA 102 connected to the connection switching circuit 103 (104). A bus termination resistor 134 (135) is connected. As a result, a faster operating frequency of the logic module can be realized. The connection between the bus termination resistor and the stub resistor is based on the SSTL circuit configuration described below.

  FIG. 3 shows a general circuit configuration diagram of SSTL (stub series terminated logic) defined in JEDEC JESD8-15. As illustrated, an FPGA 901 including a first circuit is connected to both ends of a wiring 930 and an FPGA 904 including a fourth circuit, and an FPGA 902 including a second circuit is provided in the middle of the wiring 930 and a third circuit. Connect the FPGA 903. The FPGA 901 and the FPGA 904 corresponding to both ends of the wiring 930 add bus termination resistors 910 and 911 between the first circuit and the IO pin (connection pin) 941 and between the fourth circuit and the IO pin 944, respectively. The FPGA 902 connected in the middle of the wiring 930 is connected to the wiring 931 through the stub resistor 920, and similarly, the FPGA 903 is connected to the wiring 932 through the stub resistor 921. Here, since the FPGA 902 and the FPGA 903 are connected via the stub resistors 920 and 921, no bus termination resistor is added between the second and third circuits and the IO pins 942 and 943. The wirings 931 and 932 between the wiring 930 and the stub resistors 920 and 921 are arranged to be as short as possible.

  FIG. 4 is a diagram showing another embodiment of the logic module according to the present invention. In this example, two stages of logic modules are mounted, and an example of the best connection form that eliminates signal taps when the logic modules are connected in multiple stages is shown. As shown in the figure, the logic module 100 is almost the same as that shown in FIG. 1 except that the wiring pins 191 and 192 are connected in the connection switching circuit 103 and the wiring pins 194 and 197 are connected in the connection switching circuit 104. Is different. The logic module 200 is substantially the same as that shown in FIG. 1 except that the wiring pins 290 and 293 are connected in the connection switching circuit 203 and the wiring pins 295 and 296 are connected in the connection switching circuit 204. Different. Reference numerals 201 to 297 in the logic module 200 are components corresponding to the reference numerals 101 to 197 in the logic module 100 of FIG. The two logic modules 100 and 200 are connected by an external connection header connector 106 and an external connection socket connector 205, and an external connection header connector 108 and an external connection socket connector 207, respectively.

  When the connection switching control signal 215 of the logic module 200 corresponding to the logic module connected to the upper stage in the figure is “High” and the connection switching control signals 214 and 216 are “Low” among the plurality of logic modules connected in multiple stages, the connection switching is performed. The wiring pin 290 and the wiring pin 293 of the circuit 203 are connected. Thereby, the wiring 210 connected to the stub resistor 270 and the FPGA 202 having the bus termination resistor 234 are connected. When the connection switching control signal 225 of the logic module 200 is “High” and the connection switching control signals 224 and 226 are “Low”, the wiring pin 295 and the wiring pin 296 of the connection switching circuit 204 are connected. As a result, the wiring 220 connected to the stub resistor 272 and the FPGA 202 having the bus termination resistor 235 are connected. On the other hand, when the connection switching control signals 114 and 115 are “High” and the connection switching control signal 116 is “Low”, the logic module 100 corresponding to the logic module connected to the lower stage in the drawing is connected to the wiring pin 191 of the connection switching circuit 103. Pin 192 is connected. As a result, the wiring 111 connected to the stub resistor 171 and the FPGA 101 having the bus termination resistor 131 are connected. When the connection switching control signals 124 and 125 of the logic module 100 are “High” and the connection switching control signal 126 is “Low”, the wiring pin 194 and the wiring pin 197 of the connection switching circuit 104 are connected. As a result, the wiring 121 connected to the stub resistor 173 and the FPGA 101 having the bus termination resistor 133 are connected. In this manner, the bus termination resistor 131 (133) and the bus termination resistor 234 (235) are added to the FPGA 101 and the FPGA 202 corresponding to both ends of the wiring, and the wiring 211 (wiring 221) and the external connection header connector 206 (208) are connected. This makes it possible to reduce the number of signal taps and realize a higher operating frequency.

  FIG. 5 is a diagram showing another embodiment of the logic module according to the present invention. In this example, three logic modules are mounted. As shown, the logic module 100 is similar to that shown in FIG. The logic module 300 is similar to the connection state of the logic module 200 shown in FIG. On the other hand, the logic module 200 is almost the same as the logic module 100 of FIG. 1, but the connection state of the connection switching circuit 203 is different. Here, the wiring pins 290 and 293 and 291 and 292 of the connection switching circuit 203 are connected. Also, the wiring pins 294 and 295 of the connection switching circuit 204 are connected. Thus, a bridge circuit of 210-290-293-213-202-223-295-294-222-201-212-292-291-211 is established.

  As described above, in this example, in order to operate at a higher frequency, a bridge circuit is formed in the logic module 200 in the middle stage, and the logic module 100 and the logic module 300 are connected via the bridge circuit. . Reference numerals 301 to 397 in the logic module 300 are components corresponding to the reference numerals 101 to 197 and 201 to 297 in the logic modules 100 and 200 of FIG. The logic modules 100 and 200 are connected by an external connection header connector 106 and an external connection socket connector 205, and an external connection header connector 108 and an external connection socket connector 207, respectively. The logic modules 200 and 300 are connected to each other by an external connection header connector 206 and an external connection socket connector 305, and an external connection header connector 208 and an external connection socket connector 307, respectively. In this example, the bridge circuit is formed as described above, and the bus termination resistor is added to a predetermined portion of the logic module, so that the logic module can operate at a higher operating frequency.

  FIG. 6 is a diagram showing another embodiment of the logic module according to the present invention. This example differs from the logic module 100 of FIG. 1 in the following points. This example includes a memory module 500 having a memory element 502 and a bus termination resistor 136, and a memory module 501 having a memory element 503 and a bus termination resistor 137. The FPGAs 101 and 102 have memory control circuits 520 and 521, respectively. As a result, the FPGA 101 can access the memory module 501, and the FPGA 102 can access the memory module 500. In this example, the connection switching circuit control signal 114 (124) is “High”, the connection switching circuit control signals 115 and 116 (125, 126) are “Low”, and the wiring pin 190 of the connection switching circuit 103 (104). And 191 (wiring pins 196 and 197) are connected. In comparison with FIG. 1, in this example, the FPGA 101 does not have the wiring 112 connected to the wiring pin 192 and does not have the bus termination resistor 131. Regarding the FPGA 102, there is no wiring 123 connected to the wiring pin 195, and there is no bus termination resistor 135. The other points are almost the same as those of FIG. In this example, this connection form allows the FPGA 101 to access the memory module 501 and the FPGA 102 to access the memory module 500.

  FIG. 7 is a diagram showing another embodiment of the logic module according to the present invention. This example differs from the logic module 100 of FIG. 6 in the following points. This example is a connection form in which a plurality of FPGAs mounted on the logic module 100 can simultaneously access a plurality of memory modules from one FPGA. In this example, the FPGA 102 has two memory control circuits 520 and 521, but the FPGA 101 does not have this memory control circuit. Thereby, in this example, two memory modules 500 and 501 can be accessed from one FPGA 102. Therefore, control is performed so that the wiring pins 194 and 195 of the connection switching circuit 104 are connected. It is also possible to provide the memory control circuits 520 and 521 and the bus termination resistors 131 and 133 on the FPGA 101 instead of the FPGA 102. Also in this case, the connection switching circuit is appropriately controlled. By doing so, a plurality of memory modules 500 and 501 can be simultaneously accessed from one FPGA in the logic module 100.

  The present invention relates to a logic module for hardware emulation in which logic to be verified is programmed in a plurality of programmable logic elements to verify the logic of a large-scale integrated circuit, and has industrial applicability. .

It is a figure which shows one Example of the logic module which concerns on this invention. It is a figure for demonstrating the connection switching circuit of FIG. It is a general circuit block diagram of SSTL. It is a figure which shows the other Example of the logic module which concerns on this invention. It is a figure which shows the other Example of the logic module which concerns on this invention. It is a figure which shows the other Example of the logic module which concerns on this invention. It is a figure which shows the other Example of the logic module which concerns on this invention. It is a truth table of the signal decoding circuit of MOSFET.

Explanation of symbols

100: Logic modules 101, 102: FPGA
103, 104 ... connection switching circuits 105, 107 ... external connection socket connectors 106, 108 ... external connection header connectors 110, 111, 112, 113, 120, 121, 122, 123 ... wiring 114, 115, 116, 124, 125, 126 ... connection switching control signals 131, 133, 134, 135, 136, 137 ... bus termination resistors 170, 171, 172, 173 ... stub resistors 180 ... Connection switching control signal circuit 190, 191, 192, 193, 194, 195, 196, 197 ... wiring pin 200 ... logic module 201, 202 ... FPGA
203, 204... Connection switching circuit 205, 207... External connection socket connector 206, 208... External connection header connector 210, 211, 212, 213, 220, 221, 222, 223. 214, 215, 216, 224, 225, 226 ... connection switching control signals 231, 233, 234, 235 ... bus termination resistors 270, 271, 272, 273 ... stub resistors 280 ... connection switching control Signal circuit 290, 291, 292, 293, 294, 295, 296, 297 ... wiring pin 300 ... logic module 301, 302 ... FPGA
303, 304... Connection switching circuit 305, 307... External connection socket connectors 306, 308... External connection header connectors 310, 311, 312, 313, 320, 321, 322, 323. 314, 315, 316, 324, 325, 326... Connection switching control signals 331, 333, 334, 335... Bus termination resistors 370, 371, 372, 373. Signal circuit 390, 391, 392, 393, 394, 395, 396, 397 ... wiring pin 400 ... connection switching circuit for explanation 401, 402, 403, 404 ... MOSFET
410, 411, 420, 421 ... wiring pins 430, 431, 432 ... connection switching control pins 440 ... signal decoding circuits 500, 501 ... memory modules 502, 503 ... memory elements 510, 511 ... Wiring 520,521 ... Memory control circuit 901,902,903,904 ... FPGA
910, 911 ... Bus termination resistors 920, 921 ... Stub resistors 930, 931, 932 ... Wiring 941, 942, 943, 944 ... IO pins

Claims (7)

  Programmable first and second logic elements, first and second connectors for external connection, connection between the first logic element and the second logic element, the first connector And at least one of connection between the first logic element and the second connector, and connection between the second logic element and the first connector A logic module including a connection switching circuit that enables connection, wherein a first module is connected between a wiring connecting the first connector and the connection switching circuit and a connection pin of the first logic element. A stub resistor, a second stub resistor connected between a wiring connecting the second connector and the connection switching circuit, and a connection pin of the second logic element; and the first logic element includes the first logic element Through the connection switching circuit. When connected to a logic element or the second connector, a bus terminator connected inside a connection pin of the first logic element connected to the connection switching circuit, and the second logic element connected to the connection terminal A bus termination resistor connected inside a connection pin of the second logic element connected to the connection switching circuit when connected to the first logic element or the first connector via a switching circuit; A logic module characterized by comprising.   A logic module comprising two logic modules according to claim 1, wherein a second connector of one of the logic modules and a first connector of the other logic module are connected to form a multistage configuration.   3. Three logic modules according to claim 1, wherein a second connector of the first logic module is connected to a first connector of the second logic module, and a second of the second logic module is connected. A logic module characterized in that a multi-stage configuration is formed by connecting the connector of No. 1 and the first connector of the third logic module.   The second logic module bridges the connection switching circuit by connecting the first logic element and the second connector, and connecting the second logic element and the first connector. 4. The logic module according to claim 3, wherein the logic module forms a circuit.   5. The connection switching control signal output circuit for generating a connection switching control signal for switching the connection switching circuit is provided in the first or second logic element. 6. Logical module.   A first and a second memory module, wherein the first and second logic elements each have a first and a second memory control circuit for accessing the first and second memory modules; The logic module according to claim 1.   A first and second memory module, wherein the first or second logic element has first and second memory control circuits for accessing the first and second memory modules; The logic module according to claim 1.

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