JP2009246245A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defects from occurring in a semiconductor substrate in a semiconductor device, in a method of manufacturing the same. <P>SOLUTION: A semiconductor device has a silicon substrate 20 in which an active area AR is defined by an element isolating trench 20a and an element isolating insulation film 23 formed in the element isolating trench 20a. The upper face of the element isolating insulation film 23 is lower than that of the silicon substrate 20 in the active area AR. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a manufacturing process of a semiconductor device such as an LSI, an element isolation insulating film is formed on a semiconductor substrate, and an element such as a transistor is formed in an active region of the semiconductor substrate defined by the element isolation insulating film. As element isolation structures, there are LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). Recently, STI useful for miniaturization of semiconductor devices is often used.

  STI has a structure in which elements are separated from each other by forming an element isolation trench in a semiconductor substrate and forming an element isolation insulating film therein. In such a structure, it is known that stress is applied from the element isolation insulating film to the active region defined by the element isolation insulating film, and crystal defects are generated in the semiconductor substrate (Patent Document 1).

  Crystal defects in the semiconductor substrate cause a leakage current in an element such as a transistor, which becomes a factor that hinders a reduction in power consumption of the semiconductor device.

In addition, techniques related to the present application are also disclosed in Patent Documents 2 and 3.
JP 2004-221484 A JP 2004-221543 A JP 2005-101596 A

  In a semiconductor device and a manufacturing method thereof, an object is to prevent a defect from entering a semiconductor substrate.

  According to one aspect of the disclosure below, a semiconductor substrate having an active region defined by an element isolation trench, and an element isolation insulating film formed in the element isolation trench, the upper surface of the element isolation insulating film is A semiconductor device lower than the upper surface of the semiconductor substrate in the active region is provided.

  According to another aspect of the disclosure, a step of forming an element isolation groove for defining an active region in a semiconductor substrate, and the element isolation groove has an upper surface lower than the upper surface of the semiconductor substrate in the active region. There is provided a method of manufacturing a semiconductor device including a step of forming an element isolation insulating film.

  According to the semiconductor device and the manufacturing method thereof described above, the upper surface of the element isolation insulating film is lower than the upper surface of the semiconductor substrate in the active region, and a step is generated between these upper surfaces. According to the investigation results, it has been clarified that providing such a step makes it difficult for defects to enter the semiconductor substrate on which the element isolation trench is formed.

(1) Survey Results Prior to the description of the embodiments of the present invention, the surveys conducted by the present inventors will be described.

  FIG. 1A is a diagram drawn based on an image obtained by observing a sample used in the investigation with a transmission electron microscope, and is a cross-sectional view along the gate length direction of a MOS transistor. Equivalent to.

  FIG. 1B is a drawing based on an image obtained by observing a cross section in the gate width direction of the same sample as FIG. 1A with a transmission electron microscope.

  As shown in FIGS. 1A and 1B, a plurality of element isolation trenches 1a for STI are formed in the silicon substrate 1. An element isolation insulating film 2 made of silicon oxide is buried in the element isolation trench 1a, and an active region of the transistor is defined by the element isolation insulating film 2.

  As shown in FIG. 1A, a gate electrode 4 and an insulating sidewall 5 are formed in the active region, and an interlayer insulating film 6 made of silicon oxide is formed so as to cover the gate electrode 4.

  A contact hole is formed in the interlayer insulating film 6 on the source / drain region 3 next to the gate electrode 4 and a conductive plug 7 is embedded therein.

  Various thermal processes are performed when producing such a sample.

  For example, when impurities are ion-implanted into the silicon substrate 1, a thermal oxide film is formed in advance as a sacrificial insulating film for protecting the surface of the silicon substrate 1, and the silicon substrate 1 is 1000 in order to form the thermal oxide film. It is heated to a high temperature around ℃. In this case, the ion implantation includes an implantation for forming the source / drain region 3 and an implantation for forming a well which is not shown in FIG.

  In addition, the silicon substrate 1 is also heated to a high temperature of about 1000 ° C. even in the annealing for adjusting the impurity profile of the well by thermally diffusing the impurities of the well.

  Thus, when heated to a high temperature of about 1000 ° C., the silicon substrate 1 warps. Then, in the process in which the heated silicon substrate 1 is naturally cooled to room temperature and the warp is eliminated, stress is applied to the silicon substrate 1 to generate crystal defects 8 as shown. The crystal defect 8 increases, for example, a leakage current between the two source / drain regions 3 and prevents a reduction in power consumption of the semiconductor device.

  According to Patent Document 1, the magnitude of the stress can be reduced by adjusting the ratio of the depth and width of the element isolation trench 1a.

  Therefore, the inventor of the present application investigated how the leakage current between the source / drain regions 3 changes in accordance with various changes in the depth of the element isolation trench 1a while keeping the width constant.

  The result is shown in FIG.

  In FIG. 2, the horizontal axis represents the depth of the element isolation trench 1 a, and the vertical axis represents the leakage current between the two source / drain regions 3.

  If the element isolation trench 1a is made shallow and the volume of the element isolation insulating film 2 embedded therein is reduced, the stress applied to the silicon substrate 1 from the element isolation insulating film 2 is relieved. It becomes difficult to reduce the leakage current.

  However, according to the results of FIG. 2, it was found that the leakage current hardly changed even when the element isolation trench 1a was shallow, and the depth of the element isolation trench 1a did not contribute to the reduction of the leakage current.

  Based on such investigation results, the inventor of the present application has come up with an embodiment as described below.

(2) Embodiment of the Present Invention FIGS. 3 to 22 are cross-sectional views of the semiconductor device according to this embodiment in the middle of manufacture.

  First, steps required until a sectional structure shown in FIG.

  First, the surface of the p-type silicon (semiconductor) substrate 20 is thermally oxidized in an oxidizing atmosphere at a substrate temperature of about 900 ° C. to form a thermal oxide film 21 having a thickness of about 15 nm.

  Next, a silicon nitride film having a thickness of about 150 nm is formed on the thermal oxide film 21 by CVD, and the silicon nitride film is used as a mask film 22.

  Then, after forming an opening 22a in the mask film 22 by photolithography and etching, the thermal oxide film 21 and the silicon substrate 20 are dry-etched through the opening 22a, thereby forming an element isolation groove 20a having a depth of about 390 nm. Form.

The dry etching is performed by, for example, RIE (Reactive Ion Etching), and a gas combining CHF ₃ , HBr, Cl ₂ , CF ₄ , and O ₂ is used as an etching gas.

  As a result, the active region AR of the silicon substrate 20 is defined by the element isolation trench 20a.

  In order to recover the damage received on the inner surface of the element isolation groove 20a by dry etching, the inner surface may be slightly thermally oxidized.

  Further, by forming the mask film 22 on the silicon substrate 20 through the thermal oxide film 21 in this way, it is possible to prevent the strong stress of the mask film 22 made of silicon nitride from being applied directly to the silicon substrate 20.

  Next, as shown in FIG. 4, a silicon oxide film is formed as an element isolation insulating film 23 on the mask film 20 by using an HDPCVD (High Density Plasma CVD) method having excellent embeddability, and this element isolation insulation. The element isolation trench 20a is completely filled with the film 23. The thickness of the element isolation insulating film 23 is, for example, about 40 nm on the mask film 22.

  Subsequently, as shown in FIG. 5, the element isolation insulating film 23 is polished by CMP (Chemical Mechanical Polishing) method to remove the excess element isolation insulating film 23 on the mask film 20, and the element isolation groove 23. The element isolation insulating film 23 is left only inside.

  In this CMP, a slurry for a silicon oxide film, for example, a silica-based slurry is used. As a result, the polishing rate of the element isolation insulating film 23 made of silicon oxide is faster than that of the mask film 22 made of silicon nitride, and the upper surface of the element isolation insulating film 23 is lower than that of the mask film 22.

  In this embodiment, by further advancing such CMP, the upper surface 23a of the element isolation insulating film 23 is lowered than the upper surface 20b of the silicon substrate 20 in the active region AR. As a result, a step D is formed on these upper surfaces 20b and 23a.

  The size of the step D can be controlled by the CMP polishing time in this step.

  Subsequently, as shown in FIG. 6, the thermal oxide film 21 and the mask film 22 are removed by wet etching to expose the clean surface of the silicon substrate 1. At this time, a phosphoric acid solution is used as the etchant for the mask film 22 made of silicon nitride, and a hydrofluoric acid solution is used as the etchant for the thermal oxide film 21.

  Next, steps required until a sectional structure shown in FIG.

  First, the substrate temperature is set to about 900 ° C. in an oxidizing atmosphere to form a thermal oxide film having a thickness of about 10 nm on the surface of the silicon substrate 20, and the thermal oxide film is used as the sacrificial insulating film 25.

  Next, while protecting the silicon substrate 20 with the sacrificial insulating film 25, first and second n wells 31 and 32 and a first p well 33 are formed as shown in the figure by ion implantation.

  Among these, the first and second n wells 31 and 32 are formed in separate steps by implanting phosphorus ions into the silicon substrate 1. Further, simultaneously with the formation of the first n well 31, an impurity diffusion region 34 for element isolation formed by ion implantation of phosphorus under the element isolation insulating film 23 is formed.

  The first p well 33 is formed by ion implantation of boron.

  Subsequently, as shown in FIG. 8, the thickness of the sacrificial insulating film 25 is increased to about 15 nm by thermally oxidizing the surface of the silicon substrate 20 in an oxidizing atmosphere. At this time, the substrate temperature at the time of thermal oxidation is not particularly limited.

  Then, while protecting the silicon substrate 20 with the sacrificial insulating film 25, the second p well 35 and the third n well 36 are formed as illustrated. Of these, the second p well 35 is formed by boron ion implantation, and the third n well 36 is formed by phosphorus ion implantation.

  After this ion implantation is completed, the sacrificial insulating film 25 is removed by wet etching with a hydrofluoric acid solution, and the clean surface of the silicon substrate 1 is exposed.

  By the way, in the ion implantation for forming the wells 31 to 33, 35, and 36, the impurities for the wells 31 to 36 are insufficient or excessive in the site where the silicon single crystal in the silicon substrate 20 is present. In some cases, the distribution of impurities becomes non-uniform.

  Therefore, in the next step, as shown in FIG. 9, the silicon substrate 20 is annealed to thermally diffuse the impurities in the wells 31 to 36, and the distribution of these impurities is uniformly adjusted. The impurity concentration profile is brought close to the design value.

  Although the annealing conditions are not particularly limited, in the present embodiment, the annealing is performed in a nitrogen atmosphere under conditions of a substrate temperature of 1000 ° C. and a processing time of 10 seconds.

  Next, as shown in FIG. 10, the silicon substrate 1 is thermally oxidized in an oxidizing atmosphere to form a thermal oxide film as a first gate insulating film 41 on the silicon substrate 1 to a thickness of about 15 nm. The temperature of the thermal oxidation is not particularly limited, but is about 800 ° C., for example.

  Subsequently, as shown in FIG. 11, the first gate insulating film 41 on the second p well 35 and the third n well 36 is removed by wet etching while using a resist pattern (not shown) as a mask. In this case, a hydrofluoric acid solution is used as the etching solution.

  After the wet etching is finished, the resist pattern used for the mask is removed.

  Next, as shown in FIG. 12, the surface of the silicon substrate 1 is thermally oxidized again to form a second gate made of a thermal oxide film having a thickness of about 3.2 nm on the second p well 35 and the third n well 36. The insulating film 42 is formed and the thickness of the first gate insulating film 41 is increased. This thermal oxidation is performed in an oxidizing atmosphere at a substrate temperature of about 750.degree.

  As a result, two types of gate insulating films 41 and 42 having different thicknesses are formed on the silicon substrate 1.

  Next, as shown in FIG. 13, a polysilicon film is formed as a conductive film 45 on the entire upper surface of the silicon substrate 1. The polysilicon film is formed to a thickness of about 180 nm by the CVD method.

  Thereafter, the conductive film 45 is patterned to form gate electrodes 45a on the first and second gate insulating films 41 and 42 as shown in FIG.

  Subsequently, as shown in FIG. 15, impurities are ion-implanted into the silicon substrate 20 using the gate electrode 45a as a mask, and first to third n-type source / drain extensions 47 to 49, first and second p-type source / Drain extensions 51 and 52 are formed.

  In the ion implantation, boron is used as a p-type impurity and arsenic is used as an n-type impurity. The p-type impurity and n-type impurity are separated using a resist pattern (not shown).

  Next, steps required until a sectional structure shown in FIG.

  First, an insulating film is formed on the entire upper surface of the silicon substrate 20 and etched back to leave an insulating sidewall 60 beside the gate electrode 45a. As the insulating film, a silicon oxide film is formed by, for example, a CVD method.

  Then, impurities are ion-implanted into the silicon substrate 20 using the insulating sidewall 60 and the gate electrode 45a as a mask, and the first to third n-type source / drain regions 53 to 55, the first and second p-type source / Drain regions 56 and 57 are formed.

  In this ion implantation, boron is used as a p-type impurity and phosphorus is used as an n-type impurity.

Through the steps so far, the silicon substrate 20 includes the first to third n-type MOS transistors TR _{n1 to} TR _n3 including the gate electrode 45a and the source / drain regions 53 to 57, and the first and second p-type MOS transistors. The basic structure of TR _p1 and TR _p2 was completed.

Among these, the transistors TR _n1 , TR _n2 , TR _p1 having the first gate insulating film 41 thicker than the second gate insulating film 42 are more than the transistors TR _n3 , TR _p2 having the second gate insulating film 42. Operates with high drive voltage.

  Next, as shown in FIG. 17, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 20 by sputtering, and the refractory metal film is annealed and reacted with silicon to form a refractory metal silicide layer. 61 is formed. Thereafter, the refractory metal film that has not reacted on the element isolation insulating film 23 and the like is removed by wet etching.

  Such a refractory metal silicide layer 61 reduces the resistance of the source / drain regions 53 to 57 and the gate electrode 45a.

  Next, as shown in FIG. 18, a silicon nitride film is formed as a cover insulating film 63 on the entire upper surface of the silicon substrate 20 to a thickness of about 80 nm by the CVD method.

  Subsequently, as shown in FIG. 19, a silicon oxide film is formed on the cover insulating film 63 to a thickness of about 1100 nm, and the silicon oxide film is used as a first interlayer insulating film 64. Then, in order to flatten the unevenness formed on the upper surface of the first interlayer insulating film 64 reflecting the gate electrode 45a, the upper surface is polished by the CMP method.

  Next, as shown in FIG. 20, the first interlayer insulating film 64 and the cover insulating film 63 are patterned to form contact holes 64a on the first and third n-type source / drain regions 53 and 55 and the gate electrode 45a. To do. Then, a first conductive plug 65 mainly made of tungsten is formed in the contact hole 64a.

  Further, a metal laminated film including an aluminum film is formed on the first interlayer insulating film 64 by sputtering, and is patterned to form a first metal wiring 66.

  Next, steps required until a sectional structure shown in FIG.

  First, a silicon oxide film is formed as a first buried insulating film 68 on the first layer metal wiring 66 and the first interlayer insulating film 64 by HDPCVD. Further, a second interlayer insulating film 69 is formed on the first buried insulating film 68 by a plasma CVD method using TEOS gas.

  Then, these insulating films 68 and 69 are patterned to form holes, and second conductive plugs 70 mainly composed of tungsten are formed therein, and aluminum is formed on the second interlayer insulating film 69. A second-layer metal wiring 75 made of a metal laminated film including the film is formed.

  Thereafter, by repeating the same process, the second to fourth buried insulating films 73, 77, 81, the third to fifth interlayer insulating films 74, 78, 82, and the third to fifth conductive plugs are performed. 76, 80, 84 and third to fifth layer metal wirings 79, 83, 85 are formed.

  Subsequently, as shown in FIG. 22, a silicon oxide film is formed as a first passivation film 91 on the fifth interlayer insulating film 82 and the fifth-layer metal wiring 85 by the HDPCVD method. Further, a silicon nitride film having excellent moisture blocking properties is formed on the first passivation film 91 by the CVD method, and the silicon nitride film is used as the second passivation film 92.

  Thus, the basic structure of this semiconductor device is completed.

  According to the above-described embodiment, as described with reference to FIG. 5, the element isolation insulating film 23 is polished by the CMP method so that the upper surface 23a is lower than the upper surface 20b of the silicon substrate 20, and these upper surfaces are removed. Steps D were provided at 23a and 20b.

As a result, the volume of the element isolation insulating film 23 occupying the element isolation trench 20a is reduced as compared with the case where there is no step D, so that stress applied from the element isolation insulating film 23 to the silicon substrate 20 during the thermal process is reduced. This reduces the risk of crystal defects entering the silicon substrate 20 due to stress, and the source / drain of each MOS transistor TR _{n1 to} TR _n3 , TR _p1 , TR _p2 (see FIG. 16) due to crystal defects. In the meantime, an increase in leakage current is prevented, and as a result, an increase in power consumption of the semiconductor device can be suppressed.

  In particular, the step of thermally oxidizing the silicon substrate 20 (FIGS. 7, 10, and 12) and the step of annealing the wells 31 to 36 (FIG. 9) are more than the step of forming an insulating film or a conductive film. A high heat load is applied to the silicon substrate 20, and stress is easily applied to the silicon substrate 20. Therefore, this embodiment is particularly beneficial in manufacturing processes involving such thermal processes.

  The inventor of the present application investigated how much the leakage current between the source and the drain of the MOS transistor is reduced by providing the step D as described above.

  The survey results are shown in FIG.

  In FIG. 23, the horizontal axis indicates the step D, and the vertical axis indicates the source-drain leakage current in one MOS transistor.

  As shown in this figure, when the step D is 10 nm to 20 nm, the leakage current is greatly reduced as compared with the case where there is no step (0 nm).

  From this, it was actually confirmed that providing the step D on the upper surfaces of the element isolation insulating film 23 and the silicon substrate 20 is effective in reducing the leakage current. Further, since the leakage current is reduced in this manner, crystal defects that are sources of leakage current hardly occur in the silicon substrate 20.

  Incidentally, as shown in FIG. 5, the step D is obtained by polishing the element isolation insulating film 23 by CMP. However, if the polishing time is made too long in order to increase the step D, the silicon substrate 20 may be damaged.

  24A and 24B are diagrams obtained by investigating what difference appears in the surface state of the silicon substrate 20 in the active region due to the difference in the level difference D. FIG.

  These drawings are drawn based on the SEM image. FIG. 24A shows the case where the step D is 20 nm, and FIG. 24B shows the case where the step D is 30 nm.

  As shown in FIG. 24A, when the step D is 20 nm, the surface of the silicon substrate 20 in the active region is clean, and there is no particular problem.

  On the other hand, as shown in FIG. 24B, when the step D is 30 nm, the roughness 100 is generated on the surface of the silicon substrate 20.

  The inventor of the present application considers the cause of the roughness 100 as follows.

  That is, when CMP is performed on the element isolation insulating film 23 for a long time to increase the step D, the film thickness of the mask film 22 (see FIG. 5) also decreases by polishing, and in an extreme case, the mask film 22 disappears. Thus, the thermal oxide film 21 is exposed. In this case, mechanical damage of CMP enters the thermal oxide film 21, and the damage is transferred to the silicon substrate 20 when the thermal oxide film 21 is removed.

  Therefore, it is preferable to stop the polishing for the element isolation insulating film 23 before the mask film 22 disappears. The height difference between the upper surfaces of the element isolation insulating film 23 and the silicon substrate 20 immediately before the mask film 22 disappears becomes the upper limit value of the step D that can prevent the roughness 100.

  The aspects of the present invention are summarized in the following supplementary notes.

(Appendix 1) a semiconductor substrate in which an active region is defined by an element isolation trench;
An element isolation insulating film formed in the element isolation trench;
A semiconductor device, wherein an upper surface of the element isolation insulating film is lower than an upper surface of the semiconductor substrate in the active region.

  (Additional remark 2) The semiconductor device of Additional remark 1 characterized by the upper surface of the said element isolation insulating film being lower in the range of 10 nm or more and 20 nm or less than the upper surface of the said semiconductor substrate in the said active region.

(Additional remark 3) The gate insulating film formed in the upper surface of the said semiconductor substrate in the said active region,
The semiconductor device according to appendix 1 or appendix 2, further comprising a gate electrode formed on the gate insulating film.

(Additional remark 4) The process of forming the element isolation groove which defines an active region in a semiconductor substrate,
Forming an element isolation insulating film having an upper surface lower than the upper surface of the semiconductor substrate in the active region in the element isolation trench;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 5) In the step of forming the element isolation insulating film, the upper surface of the element isolation insulating film is made lower in a range of 10 nm to 20 nm than the upper surface of the semiconductor substrate in the active region. 5. A method for manufacturing a semiconductor device according to 4.

(Appendix 6) The step of forming the element isolation groove is performed by etching the semiconductor substrate using a mask film formed on the semiconductor substrate via a thermal oxide film as a mask,
The step of forming the element isolation insulating film includes forming the element isolation insulating film in the element isolation trench and on the mask film, and polishing and removing the element isolation insulating film from the mask film. Done,
5. The semiconductor according to appendix 4, wherein the element isolation insulating film is polished so that the upper surface of the element isolation insulating film is lower than the upper surface of the semiconductor substrate and the mask film is not lost by polishing. Device manufacturing method.

  (Supplementary note 7) The method for manufacturing a semiconductor device according to any one of supplementary notes 4 to 6, further comprising a step of thermally oxidizing the surface of the semiconductor substrate after forming the element isolation insulating film.

  (Supplementary note 8) Any one of Supplementary notes 4 to 7, further comprising a step of forming a well in the semiconductor substrate and a step of annealing the well after forming the element isolation insulating film. A method for manufacturing the semiconductor device according to claim 1.

FIG. 1 (a) is a drawing based on an image obtained by observing a cross section along the gate length of a sample used for the investigation by the inventor of the present application with a transmission microscope, and FIG. It is the figure drawn based on the image obtained by observing the cross section along the gate width direction of the sample with a transmission microscope. FIG. 2 is a graph obtained by investigating the leakage current of the sample of FIG. FIG. 3 is a cross-sectional view (part 1) of the semiconductor device according to the embodiment of the present invention during manufacture. FIG. 4 is a cross-sectional view (part 2) of the semiconductor device according to the embodiment of the present invention during manufacture. FIG. 5 is a sectional view (No. 3) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 6 is a cross-sectional view (part 4) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture. FIG. 7 is a cross-sectional view (part 5) of the semiconductor device according to the embodiment of the present invention during manufacture. FIG. 8 is a sectional view (No. 6) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture. FIG. 9 is a sectional view (No. 7) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 10 is a cross-sectional view (No. 8) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture. FIG. 11 is a sectional view (No. 9) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 12 is a sectional view (No. 10) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 13 is a sectional view (No. 11) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture. FIG. 14 is a sectional view (No. 12) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 15 is a sectional view (No. 13) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 16 is a cross-sectional view (No. 14) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 17 is a cross-sectional view (No. 15) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 18 is a cross-sectional view (No. 16) of the semiconductor device according to the embodiment of the present invention during manufacturing. FIG. 19 is a sectional view (No. 17) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 20 is a cross-sectional view (No. 18) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 21 is a sectional view (19) during the manufacture of the semiconductor device according to the embodiment of the present invention. FIG. 22 is a sectional view (No. 20) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 23 is a graph obtained by investigating the leakage current of the semiconductor device according to the embodiment of the present invention. FIG. 24A is a diagram drawn based on the SEM image of the surface of the silicon substrate when the step between the element isolation insulating film and the upper surface of the silicon substrate is 30 nm, and FIG. It is a figure when a level | step difference is 30 nm.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,20 ... Silicon substrate, 1a, 20a ... Element isolation groove, 2, 23 ... Element isolation insulating film, 3 ... Source / drain region, 4 ... Gate electrode, 6 ... Interlayer insulating film, 7 ... Conductive plug, 8 ... Crystal defects, 21 ... thermal oxide film, 22 ... mask film, 25 ... sacrificial insulating film, 31, 32 ... first and second n wells, 33 ... first p well, 34 ... element isolation region, 35 ... second p well, 36 ... 3rd n well, 41, 42 ... 1st, 2nd gate insulating film, 45 ... Conductive film, 45a ... Gate electrode, 47-49 1st-3rd n-type source / drain extension, 51, 52 ... 1st, 1st 2p type source / drain extensions, 53 to 55, first to third n type source / drain regions, 56, 57 ... first and second p type source / drain regions, 60 ... insulating sidewall, 61 ... refractory metal silicide Layer, 63 ... Bar insulating film, 64 ... first interlayer insulating film, 64a ... contact hole, 65 ... first conductive plug, 66 ... first layer metal wiring, 68 ... first buried insulating film, 69 ... second interlayer insulating film, 70 ... Second conductive plug, 73 ... second buried insulating film, 74 ... third interlayer insulating film, 75 ... second layer metal wiring, 76 ... third conductive plug, 77 ... third buried insulating film, 81 ... fourth Embedded insulating film, 82 ... fifth interlayer insulating film, 84 ... fifth conductive plug, 85 ... fifth layer metal wiring, 91 ... first passivation film, 92 ... second passivation film.

Claims (5)

A semiconductor substrate in which an active region is defined by an element isolation trench;
An element isolation insulating film formed in the element isolation trench;
A semiconductor device, wherein an upper surface of the element isolation insulating film is lower than an upper surface of the semiconductor substrate in the active region.   2. The semiconductor device according to claim 1, wherein the upper surface of the element isolation insulating film is lower than the upper surface of the semiconductor substrate in the active region in a range of 10 nm to 20 nm. Forming an isolation trench for defining an active region in a semiconductor substrate;
Forming an element isolation insulating film having an upper surface lower than the upper surface of the semiconductor substrate in the active region in the element isolation trench;
A method for manufacturing a semiconductor device, comprising:   4. The step of forming the element isolation insulating film, wherein the upper surface of the element isolation insulating film is made lower in the range of 10 nm or more and 20 nm or less than the upper surface of the semiconductor substrate in the active region. Semiconductor device manufacturing method. The step of forming the element isolation trench is performed by etching the semiconductor substrate using a mask film formed on the semiconductor substrate via a thermal oxide film as a mask,
The step of forming the element isolation insulating film includes forming the element isolation insulating film in the element isolation trench and on the mask film, and polishing and removing the element isolation insulating film from the mask film. Done,
The element isolation insulating film is polished so that an upper surface of the element isolation insulating film is lower than an upper surface of the semiconductor substrate and the mask film is not lost by polishing. A method for manufacturing a semiconductor device.

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