JP2011035181A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent degradation of withstand voltage between the adjacent same-conductivity type diffusion layers interposing a trench groove. <P>SOLUTION: On a semiconductor substrate 100, a PMOS region A and an NMOS region B are formed. The PMOS region A and the NMOS region B are zoned by a first trench groove 105 filled with an insulation film for electrically isolating the PMOS region A from the NMOS region B. The width of the bottom of the first trench groove 105 is larger than the width of the upper part thereof. Thereby, degradation of withstand voltage between the PMOS region A and the NMOS region B can be prevented. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a shallow trench isolation (STI) structure and a manufacturing method thereof.

In recent years, the STI structure has been widely used for element isolation of semiconductor devices. The STI structure is formed by forming a trench groove in an element isolation region of a semiconductor substrate and embedding a silicon oxide film or the like serving as an element isolation insulating film in the formed trench groove. However, as the semiconductor device is miniaturized, the width of the STI is reduced. Therefore, conventionally used ozone (O ₃ ) -TEOS (Tetra Ethyl Ortho-Silicate) film or high density plasma chemical vapor deposition (HDP- In a silicon oxide film formed by the CVD method, it has become difficult to embed without generating voids or seams in the STI.

  For this reason, a method of forming an isolation insulating film using a coating-type solution has been proposed as a method for forming an STI structure with a generation of 100 nm or less (see, for example, Patent Document 1).

  Hereinafter, a method for forming the STI structure described in Patent Document 1 will be described with reference to FIGS. 5 (a) to 5 (d).

  First, as shown in FIG. 5A, a first silicon oxide film 201 and a silicon nitride film 202 are sequentially deposited on the upper surface of a semiconductor substrate 200 made of silicon or the like. Subsequently, the silicon nitride film 202, the first silicon oxide film 201, and the semiconductor substrate 200 are sequentially processed using a lithography technique and a dry etching technique based on a reactive ion etching (RIE) method, so that a plurality of STI element isolations are obtained. The trench groove 200 a is formed in the semiconductor substrate 200. Subsequently, the inner surface of each trench groove 200a is oxidized by a thermal oxidation method, and a second silicon oxide film 204 is formed on the inner surface. Thereafter, the silicon nitride film 202 is etched using a so-called pull back method.

Next, as shown in FIG. 5B, a perhydrogenated silazane polymer ((SiH ₂ NH) _n ) solution is applied by spin coating so as to cover the silicon nitride film 202 and fill the trench groove 200a. To do. Subsequently, baking is performed at a temperature of about 150 ° C. for about 3 minutes to volatilize the solvent, and a polysilazane (PSZ) film 205 is obtained.

  Next, as shown in FIG. 5C, the PSZ film 205 on the silicon nitride film 202 is selectively removed by chemical mechanical polishing (CMP) to expose the silicon nitride film 202. As a result, the PSZ film 205 with only the upper surface exposed is formed in the trench 200a. Subsequently, oxidation is performed for about 30 minutes in a steam atmosphere at a temperature of 800 ° C., and a third silicon oxide film 205 A is formed from the PSZ film 205. Further, the third silicon oxide film 205A is densified by performing a heat treatment for about 30 minutes in an oxidizing atmosphere at a temperature of 900 ° C. or an inert gas atmosphere such as nitrogen. .

  Next, as shown in FIG. 5D, the silicon nitride film 202 is removed to obtain a desired STI structure.

Japanese Patent No. 4018596

  However, in the conventional method for manufacturing a semiconductor device, the width dimension of the STI becomes smaller as the semiconductor device becomes finer. Therefore, in particular, in a region where a PMOS (P-type Metal Oxide Semiconductor) transistor and an NMOS (N-type Metal Oxide Semiconductor) transistor are adjacent to each other, the source or drain (hereinafter abbreviated as PD) of the PMOS transistor and the NMOS. The distance between the well of the transistor (hereinafter abbreviated as PW) and the source or drain of the NMOS transistor (hereinafter abbreviated as ND) and the well of the PMOS transistor (hereinafter abbreviated as NW) are close. Become. That is, as shown in FIG. 6, there is a problem that the breakdown voltage between the PD and PW and between the ND and NW decreases, and the leakage current increases, resulting in malfunction of the semiconductor device.

  In the region where the PMOS transistor and the NMOS transistor are adjacent to each other, the boundary between the PW and the NW is designed to be the center position of the STI width that electrically separates them. However, in the manufacturing process, misalignment with the underlying pattern occurs during mask alignment in the lithography process for forming PW and NW. Furthermore, in order to ensure the STI burying property, a forward taper shape in which the width of the upper portion of the trench groove is larger than the width of the bottom portion is used as the trench shape. As a result, as shown in FIG. 7B, in the miniaturized semiconductor device, the bottom of the STI in which the boundary between PW and NW is electrically separated from PW and NW by the mask misalignment amount X It becomes easy to come off. That is, since the distance between PD-PW or ND-NW becomes remarkably close, there is a problem that the breakdown voltage between both is reduced.

  In view of the above problems, the present invention can prevent a decrease in breakdown voltage between diffusion layers of the same conductivity type adjacent to each other across a trench (for example, PD-PW or ND-NW in the case of a MOS transistor). The purpose is to do so.

  In order to achieve the above object, according to the present invention, a semiconductor device is configured such that the width of the element isolation (STI) formed in the element formation regions having different conductivity types is larger on the bottom surface than on the top surface.

  Specifically, a semiconductor device according to the present invention includes a first element formation region formed in a semiconductor region and having a first conductivity type, and a second element formed in the semiconductor region and having a second conductivity type. Insulation for electrically separating the first element formation region and the second element formation region formed between the formation region and the first element formation region and the second element formation region in the semiconductor region A first trench groove filled with a film, wherein the first trench groove has a bottom width greater than an upper width.

  According to the semiconductor device of the present invention, the bottom width of the first trench groove formed between the first element formation region and the second element formation region in the semiconductor region and filled with the insulating film is the upper portion. Greater than the width of Accordingly, for example, the distance between adjacent diffusion layers of the same conductivity type with the first trench groove interposed therebetween is increased, thereby preventing a decrease in breakdown voltage between the diffusion layers of the same conductivity type. it can.

  The semiconductor device of the present invention is particularly useful when the width of the upper portion of the first trench is 60 nm or less.

  The semiconductor device of the present invention further includes a second trench groove formed in the first element formation region or the second element formation region in the semiconductor region and filled with an insulating film, and the depth of the first trench groove is The depth may be deeper than the depth of the second trench groove.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first trench groove between a first element formation region and a second element formation region in a semiconductor region, and the first trench groove. A step (b) of forming a protective insulating film on the side surface, and a step of expanding the bottom of the first trench groove in the depth direction and a direction perpendicular to the depth direction by etching using the protective insulating film as a mask ( c), forming an element isolation film in the first trench groove by forming an insulating film so as to fill the first trench groove, and after the step (d), the first A step (e) of selectively injecting a first conductivity type impurity into the element formation region, and a step of selectively injecting a second conductivity type impurity into the second element formation region after the step (d). And (f).

  According to the method for manufacturing a semiconductor device of the present invention, the first trench groove is formed between the first element formation region and the second element formation region in the semiconductor region, and is formed on the side surface of the formed first trench groove. A protective insulating film is formed. Thereafter, using the protective insulating film as a mask, the bottom of the first trench groove is expanded in the depth direction and in a direction perpendicular to the depth direction, and then the insulating film is formed so as to fill the first trench groove. . For this reason, for example, the distance between the diffusion layers of the same conductivity type that are adjacent to each other with the first trench groove interposed therebetween increases, so that it is possible to prevent a decrease in breakdown voltage between the diffusion layers of the same conductivity type. it can.

  In the method for manufacturing a semiconductor device of the present invention, a step of forming a second trench groove in the first element formation region or the second element formation region in the semiconductor region between step (c) and step (d). (G) may be further provided, and the step (d) may include a step of forming an element isolation film in the second trench groove by filling the second trench groove with an insulating film.

  In the method for manufacturing a semiconductor device of the present invention, the step (a) includes a step of forming a second trench groove in the first element formation region or the second element formation region in the semiconductor region, and the step (b) ) Includes a step of forming a protective insulating film on the side surface and the bottom surface of the second trench groove, and the step (d) fills the second trench groove by filling the second trench groove with the insulating film. A step of forming an element isolation film may be included.

  In the method for manufacturing a semiconductor device of the present invention, in step (c), the etching is isotropic using an etching gas of xenon difluoride, chlorine trifluoride, bromine trifluoride, or fluorine. Dry etching can be used.

  In the method for manufacturing a semiconductor device of the present invention, in the step (d), the insulating film is formed by applying a perhydrogenated silazane polymer solution on the semiconductor region, and heating the perhydrogenated silazane polymer solution. You may form by the process of forming a polysilazane film | membrane and the process of oxidizing a polysilazane film | membrane by volatilizing a solvent.

  In this manner, the insulating film can be reliably embedded even if the STI is miniaturized.

  In this case, the step of oxidizing the polysilazane film may be a step of performing the polysilazane film in a water vapor atmosphere at a temperature of 400 ° C. for 30 minutes, and further performing a process at a temperature of 700 ° C. for 30 minutes.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to prevent the breakdown voltage from decreasing between the diffusion layers of the same conductivity type that are adjacent to each other with the trench groove interposed therebetween.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. (A)-(d) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing of the order of a process which shows the principal part of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(d) is sectional drawing of the order of a process which shows the manufacturing method of the conventional semiconductor device. It is a figure explaining the subject of this invention, Comprising: It is a figure which shows the relationship between the distance of PD-PW or ND-NW, and isolation | separation breakdown voltage. It is a figure explaining the subject of this invention, Comprising: It is a figure which shows PD-PW or ND-NW withstand pressure | voltage accompanying refinement | miniaturization of a semiconductor device.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, a PMOS region A and an NMOS region B are formed in a semiconductor substrate (or semiconductor region) 100 made of, for example, silicon (Si), and the PMOS region A and the NMOS region B are formed on a semiconductor substrate. The first trench groove 105 is formed in the upper part of 100 and filled with silicon oxide.

  An N-type well (NW) 111 is formed in the PMOS region A of the semiconductor substrate 100, and a P-type well (PW) 112 is formed in the NMOS region B of the semiconductor substrate 100. In the NW 111 and the PW 112, a second trench 107 spaced from the first trench groove 105 is filled with silicon oxide.

  A PMOS transistor is formed between the first trench groove 105 and the second trench groove 107 in the PMOS region A of the semiconductor substrate 100. The PMOS transistor has a gate insulating film 113 and a gate electrode 114 that are sequentially formed on the semiconductor substrate 100. On both side surfaces of the gate insulating film 113 and the gate electrode 114, a first side wall 117 having a L-shaped cross section made of TEOS and a second side made of silicon nitride formed outside the first side wall 117 are formed. Side walls 118 are formed respectively. P-type extension diffusion layers 115 are formed on both sides of the gate electrode 114 above the NW 111, and P-type source / drain diffusion layers 119 are formed on both sides of the second sidewall 118 above the NW 111. ing. Further, a metal silicide layer 121 made of nickel silicide or the like is formed on the gate electrode 114 and on each P-type source / drain diffusion layer 119.

  On the other hand, an NMOS transistor is formed between the first trench groove 105 and the second trench groove 107 in the NMOS region B of the semiconductor substrate 100. The difference between the NMOS transistor and the PMOS transistor is that an N-type extension diffusion layer 116 is formed on both sides of the gate electrode 114 above the PW 112, and an N-type is formed on both sides of the second sidewall 118 above the PW 112. The source / drain diffusion layer 120 is formed.

  An interlayer insulating film 122 made of silicon oxide or the like is formed on the semiconductor substrate 100 so as to cover each gate electrode 114 with the upper surface being flattened.

  In the interlayer insulating film 122, a plurality of contact plugs 123 connected to the metal silicide layers 121 respectively formed on the gate electrodes 114, the P-type source / drain diffusion layers 119 and the N-type source / drain diffusion layers 120 are formed. ing. On the interlayer insulating film 122, a plurality of wirings 124 connected to the respective contact plugs 123 are selectively formed.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS. 2 (a) to 2 (d) and FIGS. 3 (a) to 3 (d).

  First, as shown in FIG. 2A, a first silicon oxide film having a thickness of about 10 nm is formed on the main surface of a semiconductor substrate 100 made of silicon by a chemical vapor deposition (CVD) method or the like. A film 101 and a silicon nitride film 102 having a thickness of about 120 nm, which will be a stopper film in a later process, are sequentially deposited. Subsequently, a first resist pattern (not shown) having a plurality of openings for partitioning each active region of the transistor is formed on the silicon nitride film 102 by lithography. At this time, the first resist pattern is formed so that the upper width of the first trench groove formed in the region where the PMOS region A and the NMOS region B are adjacent to each other is 60 nm. Subsequently, using the formed first resist pattern as a mask, the silicon nitride film 102 is etched by dry etching by a reactive ion etching (RIE) method. Thereafter, the first resist pattern is removed by ashing and cleaning.

  Next, on the exposed silicon nitride film 102 including the first silicon oxide film 101, a second resist pattern (opening a first trench groove forming portion in the first silicon oxide film 101 is formed by a lithography technique. (Not shown). Subsequently, using the formed second resist pattern and the silicon nitride film 102 as a mask, the first silicon oxide film 101 and the semiconductor substrate 100 are sequentially etched by dry etching by RIE, as shown in FIG. Thus, the first trench groove 105 having a taper angle of about 90 ° and a depth of about 250 nm is formed. Thereafter, the second resist pattern is removed by ashing and cleaning.

Next, an HTO (High Temperature Oxid) film 106 having a thickness of 5 nm is deposited on the silicon nitride film 102 including the first trench groove 105 by low pressure CVD. Thereafter, as shown in FIG. 2C, the HTO film 106 is etched back by a dry etching technique, and the wall surface of the opening portion of the first trench groove 105 and the silicon nitride film 102 where the second trench groove is formed. Only the HTO film 106 is left. At this time, it is necessary to prevent the first silicon oxide film 101 on the semiconductor substrate 100 from being removed by etch back. Thereafter, using a reactive gas such as xenon difluoride (XeF ₂ ), the bottom of the first trench groove 105 in the semiconductor substrate 100 is dug down by about 50 nm by isotropic dry etching. As a result, the bottom portion of the first trench groove 105 extends downward and laterally of the semiconductor substrate 100. At this time, since the etching gas XeF ₂ has a selectivity ratio of silicon (Si) and silicon oxide (SiO ₂ ) of 1000 or more, only the bottom of the first trench groove 105 made of Si is etched, and HTO The film 106 is hardly etched. Thereafter, the remaining HTO film 106 is removed by wet etching.

  Next, as shown in FIG. 2D, a third resist pattern (not shown) is formed by lithography to fill the first trench groove 105 and open the second trench groove formation portion. . Subsequently, using the formed third resist pattern and silicon nitride film 102 as a mask, the first silicon oxide film 101 and the semiconductor substrate 100 are sequentially etched by dry etching by RIE so that the taper angle is 90 ° or less. A second trench groove 107 having a depth of about 300 nm is formed. Thereafter, the third resist pattern and the HTO film 106 are removed by ashing, cleaning, and wet etching.

Next, as shown in FIG. 3A, a film thickness of about 10 nm is formed on the bottom and wall surfaces of the first trench groove 105 and the second trench groove 107 by, for example, a thermal oxidation method at a temperature of 1050 ° C. A second silicon oxide film 108 is formed, and the upper corners of the first trench groove 105 and the second trench groove 107 are rounded. Thereafter, a perhydrogenated silazane polymer ((SiH ₂ NH) _n ) solution is applied by spin coating so as to cover the silicon nitride film 102 and fill the first trench groove 105 and the second trench groove 107. To do. Subsequently, baking is performed at a temperature of 150 ° C. for about 3 minutes to volatilize the solvent to form a polysilazane (PSZ) film. Thereafter, in a water vapor atmosphere, oxidation is performed at a temperature of 400 ° C. for 30 minutes, followed by oxidation at a temperature of 700 ° C. for 30 minutes, whereby the PSZ film is transformed into the third silicon oxide film 110.

  Next, the third silicon oxide film 110 on the silicon nitride film 102 is selectively removed by chemical mechanical polishing (CMP) to expose the silicon nitride film 102. Subsequently, heat treatment is performed for 30 minutes in a nitrogen atmosphere at a temperature of 1150 ° C. to densify the third silicon oxide film 110. Thereafter, a silicon oxide film (not shown) formed on the surface of the silicon nitride film 102 is removed by hydrofluoric acid or the like, and then the silicon nitride film 102 is removed by hot phosphoric acid or the like, so that FIG. The STI structure shown in FIG.

Next, as shown in FIG. 3C, a fourth resist pattern (not shown) covering the PMOS region A is formed by lithography. Subsequently, using the formed fourth resist pattern as a mask, boron (B) ions are implanted by ion implantation, for example, with an implantation energy of 220 KeV and a dose of 2.2 × 10 ¹³ cm ⁻² , and acceleration energy Is implanted under the conditions of 80 KeV and a dose of 2.0 × 10 ¹³ cm ⁻² . Thereafter, the fourth resist pattern is removed by ashing and cleaning, and a PW 112 is formed in the NMOS region B.

Next, as shown in FIG. 3D, a fifth resist pattern (not shown) covering the NMOS region B is formed by lithography. Subsequently, using the formed fifth resist pattern as a mask, phosphorus (P) ions are implanted by an ion implantation method, for example, with an acceleration energy of 320 KeV and a dose of 3 × 10 ¹³ cm ⁻² , and an acceleration energy of 210 KeV. Then, ion implantation is performed under an implantation condition of a dose amount of 5.4 × 10 ¹² cm ⁻² . Thereafter, the fifth resist pattern is removed by ashing and cleaning, and an NW 111 is formed in the PMOS region A. Note that the order of forming the PW 112 and the NW 111 is not particularly limited.

  After this, ion implantation into the channel region, removal of the sacrificial oxide film (first silicon oxide film 101), formation of the gate insulating film 113, formation of the gate electrode 114, formation of the extension diffusion layers 115 and 116, sidewalls 117, 118, source / drain diffusion layers 119, 120, metal silicide layer 121, interlayer insulating film 122, contact plug 123 and wiring 124 are formed, and a passivation film (not shown) is formed. The semiconductor device shown in FIG. 1 is completed through formation and pad formation.

As described above, according to the first embodiment, the formation of the third silicon oxide film 110 filling the first trench groove 105 and the second trench groove 107 is performed using a coating type solution ((SiH ₂ NH)). _n solution). For this reason, even if the trench grooves 105 and 107 have a small width and a fine STI structure, the third silicon oxide film 110 does not generate voids or seams in the trench grooves 105 and 107. Can be embedded reliably.

  In addition, in the first embodiment, the first trench groove 105 formed at the boundary between the NW 111 and the PW 112 is formed such that the bottom width is larger than the upper width. For this reason, even when mask misalignment occurs between the NW 111 and the PW 112 when the NW 111 and the PW 112 are formed, the boundary between the NW 111 and the PW 112 does not deviate from the bottom of the first trench groove 105. As a result, a decrease in breakdown voltage between the P-type source / drain diffusion layer 119 and the PW 112 (between PD and PW) or between the N-type source / drain diffusion layer 120 and the NW 111 (between ND and NW) can be prevented. .

  In the first embodiment, the width of the upper portion of the first trench groove 105 is set to 60 nm, and the taper angle of the groove when the first trench groove 105 is formed by dry etching by the RIE method is set to 90 °. Although the depth is 250 nm and the etching amount when the semiconductor substrate 100 is isotropically dry-etched from the bottom of the first trench groove 105 is about 50 nm, it is not limited to this. The first trench groove 105 is more useful as the width of the upper portion is smaller. Further, the etching amount of the isotropic dry etching needs to be determined so that the bottom width of the first trench groove 105 is larger than the top width.

In the first embodiment, the HTO film is used as the protective film for the wall surface of the first trench groove 105. However, the present invention is not limited to this. For example, a silicon oxide insulating film such as a TEOS film may be used as long as a sufficient selection ratio (100 or more) with silicon can be obtained when etching silicon (semiconductor substrate 100). A membrane may be used. In addition, although xenon difluoride (XeF ₂ ) is used as an isotropic dry etching gas for silicon, chlorine trifluoride (ClF ₃ ), bromine trifluoride (BrF ₃ ), or fluorine (F ₂ ) is used. However, the same effect can be obtained. Further, isotropic etching by wet etching may be used for etching for expanding the bottom of the first trench groove 105.

  In the first embodiment, the first trench groove 105 and the second trench groove 107 are formed to have the same depth. However, the depth of each trench groove may be different. Note that it is preferable that the first trench is deeper because the breakdown voltage between PD and PW or between ND and NW is improved.

  In the first embodiment, when the first trench groove 105 is formed, the taper angle is larger than 90 ° by dry etching by the RIE method (in this case, the width of the bottom portion is larger than the width of the upper portion). 2 (c), the step of expanding the bottom portion of the first trench groove 105 shown in FIG. 2C may be omitted.

(Second Embodiment)
Hereinafter, a method for fabricating a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 4 (a) to 4 (d).

  In the manufacturing method according to the first embodiment, the first trench groove 105 and the second trench groove 107 are formed in different steps. However, in the second embodiment, the first trench groove 105 (at the bottom) The second trench groove 107 and the second trench groove 107 are formed in the same process.

  First, as shown in FIG. 4A, a first silicon oxide film 101 having a thickness of about 10 nm and a thickness of about 120 nm are formed on the main surface of a semiconductor substrate 100 made of silicon by a CVD method or the like. A silicon nitride film 102 serving as a stopper film is sequentially deposited. Subsequently, a first resist pattern (not shown) having a plurality of openings for partitioning each active region of the transistor is formed on the silicon nitride film 102 by lithography. At this time, the first resist pattern is formed so that the upper width of the first trench groove formed in the region where the PMOS region A and the NMOS region B are adjacent to each other is 60 nm. Subsequently, the silicon nitride film 102 is etched by dry etching by RIE using the formed first resist pattern as a mask. Thereafter, the first resist pattern is removed by ashing and cleaning.

  Next, as shown in FIG. 4B, the first silicon oxide film 101 and the semiconductor substrate 100 are sequentially etched by dry etching by the RIE method using the silicon nitride film 102 as a mask. A first trench groove 105 and a second trench groove 107 having a depth of 90 ° and a depth of about 300 nm are formed.

  Next, as shown in FIG. 4C, an HTO film 106 having a thickness of 5 nm is formed on the silicon nitride film 102 including the first trench groove 105 and the second trench groove 107 by low pressure CVD. accumulate. Subsequently, a second resist pattern (not shown) that opens the first trench groove 105 is formed on the HTO film 106 by lithography. Thereafter, the HTO film 106 is etched back by a dry etching technique, whereby the HTO film 106 remains on the wall surface of the first trench groove 105 and the semiconductor substrate 100 is exposed from the bottom surface of the first trench groove 105. To do. Thereafter, the second resist pattern is removed by ashing and cleaning.

Next, as shown in FIG. 4D, the bottom of the first trench groove 105 in the semiconductor substrate 100 is dug down by isotropic dry etching by about 50 nm using a reactive gas such as XeF ₂ . As a result, the bottom portion of the first trench groove 105 extends downward and laterally of the semiconductor substrate 100. At this time, since the etching gas XeF ₂ has a selectivity ratio of Si and SiO ₂ of 1000 or more, only the bottom portion of the first trench groove 105 made of Si is etched, and the HTO film 106 is hardly etched. Thereafter, the HTO film 207 remaining on the side surfaces of the first trench groove 105 and the side surfaces and bottom surface of the second trench groove 107 is removed by wet etching.

  Since the steps after the step shown in FIG. 4D are the same as the steps shown in FIGS. 3A to 3D according to the manufacturing method of the first embodiment, the description thereof is omitted.

Thus, according to the second embodiment, the coating solution ((SiH ₂ NH) _n solution) is used to form the silicon oxide film filling the first trench groove 105 and the second trench groove 107. . For this reason, even if the trench grooves 105 and 107 have a small width and a fine STI structure, the silicon oxide film is reliably buried without generating voids or seams in the trench grooves 105 and 107. be able to.

  In addition, in the second embodiment, the first trench groove 105 formed at the boundary between the NW 111 and the PW 112 is formed such that the bottom width is larger than the upper width. For this reason, even when mask misalignment occurs between the NW 111 and the PW 112 when the NW 111 and the PW 112 are formed, the boundary between the NW 111 and the PW 112 does not deviate from the bottom of the first trench groove 105. As a result, for example, a decrease in breakdown voltage between the P-type source / drain diffusion layer 119 and the PW 112 (between PD and PW) or between the N-type source / drain diffusion layer 120 and the NW 111 (between ND and NW) can be prevented. Can do.

  Furthermore, since the number of steps in the second embodiment is smaller than that in the first embodiment, the manufacturing cost can be reduced.

  In the second embodiment, the width of the upper portion of the first trench groove 105 is set to 60 nm, and the taper angle of the groove when the first trench groove 105 is formed by dry etching by the RIE method is set to 90 °. Although the depth is 300 nm and the amount of etching when the semiconductor substrate 100 is isotropically dry-etched from the bottom of the first trench groove 105 is about 50 nm, the present invention is not limited to this. The first trench groove 105 is more useful as the width of the upper portion is smaller. Further, the etching amount of the isotropic dry etching needs to be determined so that the bottom width of the first trench groove 105 is larger than the top width.

Also in the second embodiment, the HTO film is used as the protective film for the wall surface of the first trench groove 105, but the present invention is not limited to this. For example, a silicon oxide insulating film such as a TEOS film may be used as long as a sufficient selection ratio (100 or more) with silicon can be obtained when etching silicon (semiconductor substrate 100). A membrane may be used. In addition, although XeF ₂ is used as an isotropic dry etching gas for silicon, similar effects can be obtained by using ClF ₃ , BrF _3, or F ₂ . Further, isotropic etching by wet etching may be used for etching for expanding the bottom of the first trench groove 105.

  In the second embodiment, when the first trench groove 105 and the second trench groove 107 are formed, the taper angle is larger than 90 ° by dry etching by RIE (so-called reverse taper shape). 4C and 4D, the step of expanding the bottom portion of the first trench groove 105 shown in FIGS. 4C and 4D may be omitted. However, when this reverse tapered shape is used, the width of silicon constituting the active region of the transistor becomes small at the location where the first trench groove 105 and the second trench groove 107 are arranged close to each other, Since there is a risk of pattern collapse, it is not preferable in a miniaturized semiconductor device.

  The semiconductor device and the manufacturing method thereof according to the present invention can prevent the breakdown voltage between adjacent diffusion layers of the same conductivity type across the trench, and particularly the semiconductor device having the STI structure and the manufacture thereof. Useful for methods and the like.

A PMOS region B NMOS region 100 Semiconductor substrate (semiconductor region)
101 First silicon oxide film 102 Silicon nitride film 105 First trench groove 106 HTO film 107 Second trench groove 108 Second silicon oxide film 110 Third silicon oxide film 111 N-type well (NW)
112 P-type well (PW)
113 Gate insulating film 114 Gate electrode 115 P-type extension diffusion layer 116 N-type extension diffusion layer 117 First sidewall 118 Second sidewall 119 P-type source / drain diffusion layer (PD)
120 N-type source / drain diffusion layer (ND)
121 Metal silicide layer 122 Interlayer insulating film 123 Contact plug 124 Wiring

Claims (9)

A first element formation region formed in the semiconductor region and having a first conductivity type;
A second element formation region formed in the semiconductor region and having a second conductivity type;
Formed between the first element formation region and the second element formation region in the semiconductor region, for electrically separating the first element formation region and the second element formation region A first trench groove filled with an insulating film,
The semiconductor device according to claim 1, wherein a width of a bottom portion of the first trench groove is larger than a width of an upper portion thereof.   The semiconductor device according to claim 1, wherein a width of an upper portion of the first trench groove is 60 nm or less. A second trench groove formed in the first element formation region or the second element formation region in the semiconductor region and filled with the insulating film;
The semiconductor device according to claim 1, wherein a depth of the first trench groove is deeper than a depth of the second trench groove. A step (a) of forming a first trench groove between a first element formation region and a second element formation region in the semiconductor region;
A step (b) of forming a protective insulating film on the side surface of the first trench groove;
(C) expanding the bottom of the first trench groove in the depth direction and in a direction perpendicular to the depth direction by etching using the protective insulating film as a mask;
Forming an isolation film in the first trench groove by forming an insulating film so as to fill the first trench groove (d);
A step (e) of selectively injecting a first conductivity type impurity into the first element formation region after the step (d);
A method of manufacturing a semiconductor device, comprising: a step (f) of selectively injecting a second conductivity type impurity into the second element formation region after the step (d). Between the step (c) and the step (d),
A step (g) of forming a second trench in the first element formation region or the second element formation region in the semiconductor region;
The step (d) includes a step of forming an element isolation film in the second trench groove by filling the insulating film also in the second trench groove. Semiconductor device manufacturing method. The step (a) includes a step of forming a second trench groove in the first element formation region or the second element formation region in the semiconductor region,
The step (b) includes a step of forming a protective insulating film on a side surface and a bottom surface of the second trench groove,
The step (d) includes a step of forming an element isolation film in the second trench groove by filling the insulating film also in the second trench groove. Semiconductor device manufacturing method.   In the step (c), the etching is isotropic dry etching using an etching gas of xenon difluoride, chlorine trifluoride, bromine trifluoride, or fluorine. The manufacturing method of the semiconductor device of any one of Claims 4-6. In the step (d), the insulating film is
Applying a perhydrogenated silazane polymer solution on the semiconductor region;
Forming a polysilazane film by heating the perhydrogenated silazane polymer solution to volatilize the solvent;
The method for manufacturing a semiconductor device according to claim 4, wherein the method is formed by oxidizing the polysilazane film.   9. The semiconductor according to claim 8, wherein the step of oxidizing the polysilazane film is a step of performing the polysilazane film in a water vapor atmosphere at a temperature of 400 ° C. for 30 minutes, and further at a temperature of 700 ° C. for 30 minutes. Device manufacturing method.

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