JP2009239983A - Method of manufacturing surface acoustic wave device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a surface acoustic wave (SAW) device that can be miniaturized and thinned, can be easily packaged, and has high reliability. <P>SOLUTION: The method of manufacturing the SAW device 10 with an interdigital IDT electrode 60 formed on a surface of a semiconductor substrate 20, includes the steps of: forming insulation layers 21-23 on an active-side surface of the semiconductor substrate 20; forming a base layer 30 all over the insulation layer 23; performing a flattening process on the surface of the base layer 30; forming a piezoelectric body 51 on the surface of the base layer 30 on which the flattening process has been performed; forming the IDT electrode 60 on the surface of the piezoelectric body 51; and forming a bank 41, which is higher than a height from the surface of the base layer 30 to the surface of the IDT electrode 60 and surrounds the piezoelectric body 51 and the IDT electrode 60, along a surface edge portion of the base layer 30. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a surface acoustic wave element, and a surface acoustic wave element manufactured by the manufacturing method, and more specifically, a bank is formed in the peripheral edge portion of the surface of a semiconductor substrate, and a recess is provided in the center. The present invention relates to a method for manufacturing a surface acoustic wave element in which an IDT electrode is formed inside and a structure of the surface acoustic wave element.

Recently, portable electronic devices typified by mobile phones have become widespread, and high functionality and downsizing are required. Accordingly, the electronic device used in the portable electronic device is naturally required to be downsized.
As a technique for miniaturizing such an electronic device, conventionally, in a functional device unit including a semiconductor element chip, an insulating substrate having a recess formed on the surface, and the substrate is silicon (Si substrate). An insulating film is formed on the bottom surface, side surface, and top surface of the substrate, and a patterned wiring layer is formed in the groove formed by the insulating film so as to continue from the bottom surface of the recess through the side surface to the top surface. In a recess, a semiconductor device chip is flip-chip mounted between the wiring layer and a functional device unit formed by resin-sealing the above-described recess, and a method of manufacturing the functional device unit is known (for example, Patent Document 1).

  In addition, a surface acoustic wave element (chip state) is disposed in a recess provided in a ceramic module substrate, and the sub-board on which the peripheral circuit is mounted is electrically connected to the surface acoustic wave element, and the sub-board A method of manufacturing a surface acoustic wave element module that seals a surface acoustic wave element in a recess is also known (see, for example, Patent Document 2).

JP 2002-33410 A (5th and 6th pages, FIG. 2) JP-A-5-152881 (pages 3, 4 and 2, 3)

  In Patent Document 1, such a functional device unit is formed by flip-chip mounting a semiconductor element chip in a recess of an insulating substrate and then sealing with a resin. Even if the semiconductor element chip is accommodated in the semiconductor element chip, the thickness of the bottom of the substrate and the thickness of the sealing resin layer are increased with respect to the semiconductor element chip, and the size is increased by the amount of the substrate. End up. Although this semiconductor element chip can be considered by replacing it with the surface acoustic wave element of the present invention to be described later, it is difficult to realize a thin and small surface acoustic wave element for the reasons described above.

  In addition, when mounting this semiconductor element chip on a functional device unit in an electronic device or the like, it must be further connected to an external circuit, and after being flip-chip mounted on a substrate, it is again connected to the external circuit. A process is performed, and at least two mounting processes are required. Therefore, the manufacturing process becomes longer and the cost reduction is difficult because the semiconductor element chip is mounted on the substrate.

  According to Patent Document 2 described above, the surface acoustic wave element (chip state) is disposed in the recess provided in the module substrate, and the surface acoustic wave element is sealed in the recess by the sub-substrate. The surface of the surface acoustic wave element can be protected from contamination, etc., but in order to configure the surface acoustic wave element module by mounting the module substrate, the surface acoustic wave element, and the sub-substrate in a single state, There is a limit to the reduction in thickness, and there is a problem that the manufacturing process such as a mounting process is increased.

  Further, it is known that flatness and smoothness are important elements in the IDT electrode formation region of the surface acoustic wave element in order to obtain predetermined resonance characteristics. It is presumed that it is difficult to obtain the flatness and smoothness of the surface of the wiring pattern provided at the bottom of the concave portion of the substrate, and it is considered difficult to realize characteristics such as a highly accurate resonance frequency.

  An object of the present invention is to solve the above-described problems, and to provide a surface acoustic wave device that is small and thin, that can be easily packaged, and that has high reliability, and a method for manufacturing the same. That is.

  A method of manufacturing a surface acoustic wave device according to the present invention is a method of manufacturing a surface acoustic wave device in which comb-shaped IDT electrodes are formed on the surface of a semiconductor substrate, and an insulating layer is provided on the active surface side surface of the semiconductor substrate. A step of forming, a step of forming a base layer on the entire surface of the insulating layer, a step of flattening the surface of the base layer, and a piezoelectric body on the surface of the base layer that has been flattened A step of forming the IDT electrode on the surface of the piezoelectric body, a surface peripheral edge of the base layer being higher than a height from the surface of the base layer to the surface of the IDT electrode, and And forming a bank surrounding the piezoelectric body.

Here, the semiconductor substrate includes, for example, a circuit element such as an oscillation circuit using Si as a base material, and the surface acoustic wave element is configured by forming a piezoelectric body and an IDT electrode on the semiconductor substrate. In the surface acoustic wave device according to the present invention, since the piezoelectric body and the IDT electrode are formed in the recess surrounded by the bank, the IDT electrode surface does not protrude from the bank surface. It is possible to provide a highly reliable surface acoustic wave device by reducing the chance that a jig or the like contacts the IDT electrode and damages the IDT electrode.
Further, the outer shape is within the range of the semiconductor substrate, and there is no projecting thing, so that downsizing can be realized.

  The manufacturing method described above can be manufactured consistently in a semiconductor manufacturing process in the state of a wafer. Also, as described in Patent Document 2, a surface acoustic wave element, a sub substrate, and a module substrate that are formed into chips can be manufactured. The mounting process is unnecessary, and the manufacturing process can be shortened and the manufacturing cost can be reduced.

Furthermore, since the base layer on which the piezoelectric body is formed is formed over the entire surface of the insulating layer having no protrusions, the surface of the base layer is flattened. By obtaining smoothness, highly accurate resonance characteristics can be realized.
As the planarization process, it is preferable to employ means such as CMP (Chemical and Mechanical Polishing).

  The step of forming the base layer is preferably a step of forming a single insulating layer. As the insulating layer forming the base layer, for example, silicon nitride (SiN) is used.

The base layer is formed on the surface of an insulating layer provided on the active surface side surface of the semiconductor substrate. If this insulating layer is made of silicon oxide (SiO ₂ ), SiN can be easily formed by a normal semiconductor manufacturing process. SiN is a material that is generally easy to perform planarization by CMP.

  Moreover, it is desirable that the step of forming the base layer includes a step of stacking and forming an Al layer and the insulating layer, and a step of planarizing at least the surface of the Al layer.

Here, the Al layer and the SiN layer forming the base layer are composed of an Al layer, a SiN layer, or a SiN layer and an Al layer in order from the uppermost surface of the insulating layer (SiO ₂ ) on the surface of the semiconductor substrate. Alternatively, a three-layer structure including a SiN layer, an Al layer, and a SiN layer can be employed. The Al layer is often used as a metal stopper for flattening and smoothing in a semiconductor manufacturing process, and has excellent flatness and smoothness due to the flattening. By obtaining excellent flatness and smoothness in the surface acoustic wave element formation region, it is possible to realize even more accurate resonance characteristics.
In addition to the Al layer, the SiN layer is more preferably planarized.

Further, the step of forming the bank includes a step of forming a bank layer having the same height as the bank on the surface of the base layer, and a region where the piezoelectric body is disposed on the surface of the base layer. Removing the bank layer by etching to form a recess, and forming the piezoelectric body at the bottom of the recess; and forming the IDT electrode on the surface of the piezoelectric body; It is preferable to contain.
In addition, the peripheral part of a recessed part is a bank.

In this way, since the flattened base layer surface is exposed at the bottom of the recess, the flatness of the piezoelectric body itself can be obtained, and high-accuracy resonance characteristics can be realized. it can.
This bank can also be formed easily and accurately by a semiconductor manufacturing process when the semiconductor substrate is in a wafer state.

In addition, after the step of forming the IDT electrode on the surface of the piezoelectric body, the step of forming the bank has a step of forming the bank, wherein the step of forming the bank includes the formation region of the bank at the peripheral edge of the surface of the base layer It is preferable that the range includes a step of forming a liquid containing a precursor compound of SiO ₂ in a predetermined shape of the bank using a droplet discharge method and a step of solidifying the liquid by heat treatment.

  By forming the bank using a droplet discharge method, it is possible to form a bank having an arbitrary shape. Although details will be described in an embodiment described later, a via hole is formed in a part of the bank. Through holes can be formed in the same process, and the manufacturing process can be shortened.

  In addition, since the piezoelectric body and the IDT electrode are formed on the same plane of the flattened base layer, there are no protrusions in the periphery as compared with the method of forming in the previously formed recess, as described above. The piezoelectric body and the IDT electrode can be easily formed.

Further, in the step of forming the bank, a liquid containing a precursor compound of SiO ₂ is applied to a predetermined region of the bank using a droplet discharge method in a region where the bank is formed in the peripheral region of the surface of the base layer. And forming a bank including a step of solidifying the liquid material by heat treatment, and after the step of forming the bank, planarization in a recess formed by the bank Preferably, the method includes a step of forming a piezoelectric body on the surface of the treated base layer and a step of forming the IDT electrode on the surface of the piezoelectric body.

As a post-process for forming a bank using a droplet discharge method, the same method as the post-process for forming a recess by etching, that is, a method for forming a bank can be employed.
According to such a method, since the etching solution or the like does not come into contact with the surface of the base layer at the time of forming the bank, the surface of the base layer is kept flattened. The reliability of joining with can be improved.

Further, the bank is made of SiO ₂ , and the precursor compound of SiO ₂ is an organometallic compound containing Si (OR) ₄ (R = CH ₃ , C ₂ H ₅ , C ₃ H ₇ , C ₄ H _9. It is preferable that the bank is formed by solidifying the liquid by heat treatment.

With the above-described constitution of the precursor compound of SiO ₂ , it can be freely formed into a desired bank shape and height by the droplet discharge method, and then is made of SiO ₂ by solidifying by heat treatment. A bank having a desired shape can be easily formed.

  Furthermore, the temperature of the heat treatment is desirably in the range of 350 ° C to 400 ° C.

  By setting the temperature within such a range, the liquid material can be solidified reliably, and thermal influences on circuit elements and wirings in the semiconductor substrate can be eliminated.

  The surface acoustic wave device of the present invention is a surface acoustic wave device in which a comb-shaped IDT electrode is formed on the surface of a semiconductor substrate, and an insulating layer formed on the active surface side surface of the semiconductor substrate; A base layer formed on the entire surface of the insulating layer and subjected to the planarization process, a piezoelectric body formed on the surface of the base layer subjected to the planarization process, and the IDT on the surface of the piezoelectric body A step of forming an electrode, and a bank formed on the periphery of the surface of the base layer so as to surround the piezoelectric body higher than the height from the surface of the base layer to the surface of the IDT electrode. It is characterized by that.

According to the present invention, since the piezoelectric body and the IDT electrode are formed in the recess surrounded by the bank, the IDT electrode surface does not protrude from the bank surface, and in subsequent processes such as circuit mounting. It is possible to provide a highly reliable surface acoustic wave device by reducing the chance that a jig or the like contacts the IDT electrode and damages the IDT electrode during packaging.
Further, the thickness and the outer shape are also within the range of the semiconductor substrate, and there is no protrusion and a reduction in size can be realized.

  Furthermore, since the base layer on which the piezoelectric body is formed is formed over the entire surface of the insulating layer without protrusions and the surface of the base layer is flattened, the surface acoustic wave element forming region is excellent in flatness. Therefore, highly accurate resonance characteristics can be realized.

  Furthermore, it is preferable that a sealing member for hermetically sealing the inside of the recess formed by the bank is further provided on the upper surface of the bank and packaged.

  By sealing the recess formed by the bank with a sealing member, the IDT electrode can be protected from moisture and dust from the outside.

BRIEF DESCRIPTION OF THE DRAWINGS The schematic structure of the surface acoustic wave element which concerns on this invention is represented typically, (a) is the top view, (b) is sectional drawing which shows the AA cut surface of (a). FIG. 3 is a partial cross-sectional view schematically showing a manufacturing process of the surface acoustic wave element according to the first embodiment of the present invention. FIG. 3 is a partial cross-sectional view schematically showing a manufacturing process of the surface acoustic wave element according to the first embodiment of the present invention. The fragmentary sectional view which shows a part of manufacturing method which concerns on Embodiment 2 of this invention typically. The fragmentary sectional view which shows a part of modification of Embodiment 2 of this invention typically. The fragmentary sectional view which shows typically the main manufacturing process of the manufacturing method of the surface acoustic wave element concerning Embodiment 3 of this invention. The fragmentary sectional view which shows typically the main manufacturing process of the manufacturing method of the surface acoustic wave element concerning Embodiment 4 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the structure of a surface acoustic wave device according to the present invention, FIGS. 2 and 3 show a method for manufacturing a surface acoustic wave device according to Embodiment 1 of the present invention, and FIGS. 4 and 5 show Embodiment 2 and its modifications. FIG. 6 shows a method for manufacturing a surface acoustic wave device according to Embodiment 3 and FIG.
(Structure of surface acoustic wave element)

1A and 1B schematically show a schematic structure of a surface acoustic wave device according to the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 1A shows a state in which the lid 90 is seen through. 1A and 1B, a surface acoustic wave element 10 of the present invention is made of silicon oxide (SiO ₂ ) formed on the active surface side surface of a semiconductor substrate 20 based on silicon (Si). Insulating layers 21 to 23, a base layer 30 formed over the entire surface of the uppermost insulating layer 23, and a piezoelectric material typified by zinc oxide (ZnO) formed on the surface of the base layer 30 The piezoelectric body 51 and an IDT electrode (Interdigital Transducer) 60 made of comb-shaped Al formed on the upper surface of the piezoelectric body 51 are configured.

The semiconductor substrate 20 includes circuit elements (not shown) such as an oscillation circuit. Interlayer electrodes (not shown) are formed between the insulating layers 21 to 23, and pads 81 to 86 are formed on each interlayer electrode. The upper and lower interlayer electrodes are electrically connected to each other through via holes (contact holes). Connected. These interlayer electrodes are also connection electrodes for connecting circuit elements and the like in the semiconductor substrate 20. The surface of each of the insulating layers 21 to 23 is flattened and smoothed by a flattening process such as CMP (Chemical and Mechanical Polishing).
Note that a passivation film is preferably formed on the surface of the semiconductor substrate 20. In FIG. 1B, the insulating layer has a three-layer structure, but is not particularly limited, and may be one layer or more.

  A base layer 30 made of SiN is formed on the surface of the insulating layer 23. The surface of the base layer 30 is flattened by a CMP method. A piezoelectric body 51 is formed on the surface of the base layer 30, and a comb-like IDT electrode 60 is formed on the surface of the piezoelectric body 51.

  A bank 41 surrounding the piezoelectric body 51 and the IDT electrode 60 is formed on the outer peripheral portion of the surface of the insulating layer 23. The bank 41 is formed higher than the height from the surface of the base layer 30 to the surface of the IDT electrode 60.

  A lid 90 as a sealing member is fixed to the upper surface of the bank 41, and the space in the recess 42 formed by the bank 41 is hermetically sealed. Although the material of the lid 90 is not particularly limited, metal, glass, ceramic, or the like can be employed, and a metal material has a shielding effect.

Pads 87 are provided on the surface of the bank 41 outside the lid 90, and in FIG. 1A, six pads 87a to 87f are shown. Here, the pads 87a to 87f include at least a power supply electrode pad for driving the oscillation circuit, a GND connected to the IDT electrode 60, an input / output signal electrode pad, and the like.
Hereinafter, the pads 87a to 87f are collectively referred to as a pad 87.

  The IDT electrode 60 is made of Al, and a comb-like GND electrode 61 and an input electrode (common to output electrodes) 62 are formed on the surface of the piezoelectric body 51 so as to cross each other. The connection electrodes 61 a and 62 a are extended to the portion, and are extended to the via holes 71 a and 71 b and connected to the pad 86. The via holes 71a and 71b may be collectively referred to as the via hole 71.

  The pads 87 are also connected to the pads 83 provided between the insulating layers via the via holes 72. In FIG. 1B, the pads 83 and 86 are shown one by one. However, the pad 83 is at least the power supply electrode for driving the oscillation circuit, and the pad 86 is GND and the input / output signal electrode. It is provided corresponding to. Similarly, the pads 81, 82, 84, 85 are provided corresponding to the pads 83, 86.

  Here, the formation range from the semiconductor substrate 20 to the insulating layers 21 to 23 is a conventional semiconductor manufacturing process region, and the range from the base layer 30 to the piezoelectric body 51, the IDT electrode 60, and the bank 41 is the elasticity according to the present invention. This will be described as a manufacturing process area of the surface acoustic wave device.

Therefore, in the surface acoustic wave device 10 according to the present invention described above, the piezoelectric body 51 and the IDT electrode 60 are formed in the recess 42 surrounded by the bank 41, so that the surface of the IDT electrode 60 is more than the surface of the bank 41. In the subsequent packaging process, the jig or the like or the back surface of the lid 90 comes into contact with the IDT electrode to reduce the chance of damaging the IDT electrode, making packaging easier and more reliable. A surface acoustic wave element having high performance can be provided.
Further, the outer shape is within the range of the semiconductor substrate 20, and there is no projecting part, so that downsizing can be realized.

  Further, since the base layer 30 on which the piezoelectric body 51 is formed is formed over the entire surface of the insulating layer 23 having no protrusions, and the surface of the base layer 30 is flattened, the surface acoustic wave element is formed. Stable resonance characteristics can be realized by obtaining excellent flatness and smoothness in the region.

Furthermore, the recess 42 formed by the bank 41 is hermetically sealed by the lid 90, whereby the IDT electrode 60 can be protected from external moisture and dust, and the highly reliable surface acoustic wave element 10 is provided. can do.
(Embodiment 1)

Next, a method for manufacturing a surface acoustic wave device according to the present invention will be described with reference to the drawings.
2 and 3 are partial cross-sectional views schematically showing the manufacturing process of the surface acoustic wave device 10 according to the first embodiment of the present invention. The description and illustration of the process in the conventional semiconductor manufacturing process region described above are shown in FIGS. The main steps in the manufacturing process area of the surface acoustic wave element 10 according to the present invention will be shown and described.
First, the insulating layers 21 to 23 and the pads 81 to 86 are formed on the upper surface of the semiconductor substrate 20 by using the manufacturing process in the conventional semiconductor manufacturing process region, and the surface of the insulating layer 23 is formed as shown in FIG. After the planarization process by the CMP method, the base layer 30 is formed over the entire surface of the insulating layer 23.

After the surface of the base layer 30 is flattened by the CMP method, the bank layer 40 made of SiO ₂ is formed over the entire surface of the base layer 30 (FIG. 2B). The height (thickness) of the bank layer 40 is higher than the surface of the IDT electrode 60 (see FIG. 1B), and is about 4 μm in this embodiment.
Next, the bank 41 is formed by etching.

FIG. 2C shows a bank forming process. First, the resist layer 101 is formed on the surface of the bank layer 40. Then, the resist layer 101 is exposed and developed, and an opening 101a corresponding to the recess 42 for forming the bank 41 and an opening 101b corresponding to the via hole 72 (see FIG. 1B) connected to the pad 87 are formed. The resist pattern is formed, and the concave portion 42 and the through hole 43 for forming the via hole 72 are formed by wet etching or dry etching. The peripheral edge of the recess 42 is a bank 41.
Thereafter, the resist layer 101 is peeled off and washed, and the resist layer 102 is formed again.

  FIG. 2D shows a resist layer 102 forming step. The resist layer 102 is formed up to the surface of the bank 41, the recess 42, and the inside of the through hole 43. Subsequently, through holes 44 and 45 are formed in the base layer 30.

  FIG. 2E shows a process for opening the through holes 44 and 45. First, the resist layer 102 is exposed and developed to form a resist pattern having openings 102a and 102b corresponding to the through holes 44 and 45, respectively. Then, the through holes 44 and 45 are formed in the base layer 30 by etching. Open. Then, the process proceeds to a step of opening through holes 46 and 47 in the insulating layer 23.

  As shown in FIG. 2F, a resist layer 103 is further formed on the upper surface of the resist layer 102 (here, a resist pattern is shown). The resist layer 103 penetrates into the upper surface of the resist layer 102 and the inside of the through holes 44 and 45. Then, as shown in FIG. 3G, a resist pattern having openings 103a and 103b is formed by exposure and development processes, and through holes 46 and 47 communicating with the surfaces of the pads 83 and 86 in the insulating layer 23 by etching. Open and wash.

The above-described through holes 43, through holes 44 and 45, and through holes 46 and 47 are formed by alternately stacking different materials such as SiO ₂ , SiN, and SiO ₂ , and correspond to the respective materials. Since the etchant is different, a separate process is required.
Next, the piezoelectric layer 50 is formed.

FIG. 3H shows a process for forming the piezoelectric layer 50. The piezoelectric layer 50 is formed over the entire surface of the bank 41 and the bottom 42 a of the recess 42. Piezoelectric material also enters each of the through holes 43 to 47 established in the previous step.
Subsequently, the piezoelectric body 51 is formed.

  3 (i) and 3 (j) show the piezoelectric body forming process. First, a resist layer 104 is formed on the surface of the piezoelectric layer 50, and a resist pattern is formed by removing the surrounding resist layer in accordance with the shape of the piezoelectric body 51 by exposure and development processes (see FIG. 3I). ).

  As shown in FIG. 3J, the piezoelectric body 51 is formed into a desired shape by etching. At this time, the piezoelectric material that has entered the through holes is also removed. An IDT electrode 60 and via holes (via holes 71 and 72 are exemplified) are formed on the surface of the piezoelectric body 51 formed in this way.

  FIG. 3K shows a process for forming the IDT electrode 60. An IDT electrode 60 is formed on the surface of the piezoelectric body 51. The IDT electrode 60 includes a GND electrode 61 and an input electrode (common to output electrodes) 62 shown in FIG. The IDT electrode 60 is formed by means such as vapor deposition or CVD. One end of the bus bar becomes connection electrodes 61 a and 62 a extending to the end of the piezoelectric body 51, and extends to the via hole 71 (71 a and 71 b) to connect to the pad 86. Further, the other via hole 72 is connected to the pad 87 and the pad 83.

Then, as shown in FIG. 1B, a lid 90 as a sealing member is fixed to the upper surface of the bank 41 and packaged. Since the surface of the bank 41 is higher than the surface of the IDT electrode 60, the lower surface of the lid 90 does not come into contact with the IDT electrode 60.
Through the steps as described above, the surface acoustic wave element 10 is formed.

Therefore, according to the first embodiment described above, since the piezoelectric body 51 and the IDT electrode 60 are formed in the recess 42 surrounded by the bank 41, the surface of the IDT electrode 60 protrudes from the surface of the bank 41. In the subsequent process such as circuit mounting, the chance that the jig or the like contacts the IDT electrode 60 and is damaged can be reduced, and the highly reliable surface acoustic wave device 10 can be provided.
Further, the outer shape is also within the range of the semiconductor substrate 20, and there is no projecting thing, so that downsizing can be realized.

  Further, in such a manufacturing method, it is possible to manufacture the wafer consistently in the semiconductor manufacturing process in the state of the wafer. Further, as in the above-described Patent Document 2, the surface acoustic wave element formed in the chip, the sub-substrate The process of mounting the module substrate is unnecessary, and the manufacturing process can be shortened and the manufacturing cost can be reduced.

  Furthermore, since the base layer 30 is formed over the entire surface of the insulating layer 23 having no protrusions, the surface of the base layer 30 is flattened, so that the surface acoustic wave element forming region has excellent flatness. By obtaining smoothness, highly accurate resonance characteristics can be realized.

Further, the base layer 30 is formed on the surface of the insulating layer 23 provided on the active surface side surface of the semiconductor substrate 20. Since the insulating layer 23 is silicon oxide (SiO ₂ ), SiN can be easily formed by a normal semiconductor manufacturing process. SiN is a material that is generally easy to perform planarization by CMP.
(Embodiment 2)

Then, the manufacturing method of the surface acoustic wave element concerning Embodiment 2 of this invention is demonstrated with reference to drawings. The second embodiment is characterized in that the configuration of the base layer 30 is changed based on the manufacturing method according to the first embodiment described above, and only different portions are shown and described.
FIG. 4 is a partial cross-sectional view schematically showing a part of the manufacturing method according to the second embodiment. In the second embodiment, the base layer 30 is composed of an Al layer 35 and a SiN layer 36.

  First, an Al layer 35 is formed on the surface of the insulating layer 23, and after planarizing by a CMP method, an SiN layer 36 is formed. It is even better if the surface of the SiN layer 36 is planarized. The processes after the formation process of the base layer 30 are performed through the same process as that of the first embodiment (see FIGS. 2B to 3K), and the surface acoustic wave element 10 is formed.

  Note that when the Al layer 35 is employed as the base layer, since the Al layer 35 is a conductor, the via holes 71 and 72 are not connected to anything other than GND, and are simply configured as through holes.

  FIG. 5 shows a modification of the second embodiment. In this modification, the structure of the base layer 30 is the SiN layer 36 and the Al layer 35 from the insulating layer 23 side. The surface of the Al layer 35 is characterized by a three-layer structure in which a SiN layer 37 is further formed. Here, the surface of the Al layer 35 is flattened. The SiN layer 37 is not necessarily required, but is formed as a protective layer when the piezoelectric body 51 is formed.

Therefore, according to the second embodiment described above and the modification thereof, the Al layer is often used as a metal stopper for performing planarization and smoothing processing in the semiconductor manufacturing process, and excellent flatness is achieved by the planarization processing. The surface acoustic wave element can be formed with excellent flatness and smoothness, so that even more accurate resonance characteristics can be realized.
(Embodiment 3)

  Then, the manufacturing method of the surface acoustic wave element 10 which concerns on Embodiment 3 of this invention is demonstrated with reference to drawings. In the third embodiment, the manufacturing method according to the first embodiment (see FIGS. 2 and 3) forms the bank 41 by forming the bank 42 and then forming the bank 41 by etching. A feature is that the banks 41 are stacked and formed by a droplet discharge method. Note that the completed form of the surface acoustic wave element 10 is substantially the same as that of the first embodiment (see FIG. 1), and thus the description thereof is omitted, and the same functional elements are denoted by the same reference numerals.

FIG. 6 is a partial cross-sectional view schematically showing main manufacturing steps of the method for manufacturing the surface acoustic wave device 10 according to the third embodiment. Insulating layers 21 to 23 and pads 81 to 86 are formed on the upper surface of the semiconductor substrate 20 by using a process in a conventional semiconductor manufacturing process region, and the surface of the insulating layer 23 is formed by CMP as shown in FIG. After the planarization process, the base layer 30 made of SiN is formed over the entire surface of the insulating layer 23.
Then, after planarizing the surface of the base layer 30 by CMP, through holes 44 to 47 communicating with the surfaces of the pads 83 and 86 are opened.

FIG. 6A shows a state in which through holes 44 and 45 and through holes 46 and 47 are opened in the base layer 30 and the insulating layer 23, respectively. First, a resist layer 101 is formed on the surface of the base layer 30, a resist pattern having openings 101a and 101b corresponding to the through holes 44 and 45 is formed by exposure and development processes, and then the through holes 44 and 45 are etched. Open. Subsequently, although not shown in the drawing, another resist layer is formed on the surface of the resist layer 101 (showing a resist pattern), a resist pattern having openings corresponding to the through holes 46 and 47 is formed, and through-holes are formed by etching. Halls 46 and 47 are opened.
FIG. 6B shows a state where the through holes 44 to 47 are opened. In addition, the opening method of the through holes 44-47 is based on the process shown in FIG.2 (e)-FIG.3 (g) in Embodiment 1 mentioned above.

After opening the through holes 44 to 46, the piezoelectric layer 50 is formed.
FIG. 6C shows a process for forming the piezoelectric layer 50. The piezoelectric layer 50 is formed on the entire surface of the base layer 30 with a predetermined thickness. At this time, a part of the piezoelectric layer 50 penetrates into the through holes 44 to 47.
Next, the piezoelectric body 51 is formed in a predetermined shape.

  FIG. 6D and FIG. 6E show the formation process of the piezoelectric body 51. First, as shown in FIG. 6D, a resist layer 104 is formed on the entire surface of the piezoelectric layer 50, a resist pattern corresponding to the piezoelectric body 51 is formed by exposure and development processes, and the resist pattern outside is formed by etching. Remove the resist. Subsequently, a predetermined shape of the piezoelectric body 51 is formed by etching.

FIG. 6E shows a state where the piezoelectric body 51 is formed. As shown in FIG. 6E, a piezoelectric body 51 is formed on the surface of the base layer 30, and through holes 44 to 47 are opened.
Subsequently, the IDT electrode 60 is formed.

FIG. 6F shows a process for forming the IDT electrode 60. An IDT electrode 60 is formed on the surface of the piezoelectric body 51. The IDT electrode 60 includes a GND electrode 61 and an input electrode (common to output electrodes) 62 shown in FIG. The IDT electrode 60 is formed by means such as vapor deposition or CVD. One end of the bus bar becomes connection electrodes 61 a and 62 a extending to the end of the piezoelectric body 51, and extends to the via hole 71 (71 a and 71 b) to connect to the pad 86.
Subsequently, the bank 41 is formed.

FIG. 6G shows a process for forming the bank 41. The bank 41 is formed by stacking SiO ₂ in a predetermined shape by a liquid discharge method so as to surround the outside of the region including the piezoelectric body 51 and the IDT electrode 60 and solidifying it by heat treatment. At this time, a through hole 43 communicating with the pad 83 is also formed in the bank 41.

  A method for forming the bank 41 will be described in more detail. The formation of the bank 41 in the present embodiment is performed using a liquid ejection method. The droplet discharge method is a method for forming a desired pattern on a substrate by discharging droplets made of a liquid material into a desired pattern, and is a general term for an ink jet method, and uses a droplet discharge device. Done.

As the droplet discharge device, an electromechanical transducer using a piezoelectric element (piezo element) as a droplet discharge head, a method using an electrothermal transducer as an energy generating element, a charge control type, a pressure vibration It is also possible to employ a continuous method such as a mold, an electrostatic suction method, or a method in which an electromagnetic wave such as a laser is irradiated to generate heat and the liquid material is discharged by the action of this heat generation.
(Method for forming bank 41)

First, a liquid containing a precursor material of SiO ₂ is disposed at a bank forming position by the above-described droplet discharge method (inkjet method). Examples of the SiO ₂ precursor material contained in the liquid include Si alkoxide Si (OR) ₄ (R = CH ₃ , C ₂ H ₅ , C ₃ H ₇ , C ₄ H ₉ ). Similar ones may be used.

As the solvent or dispersion medium for dispersing the liquid containing the SiO ₂ precursor material, those having a vapor pressure at room temperature of 0.001 mmHg to 200 mmHg are preferable. This is because if the vapor pressure exceeds 200 mmHg, the dispersion medium evaporates first when a coating film is formed by discharge, and it becomes difficult to form a good coating film. On the other hand, if the vapor pressure at room temperature is less than 0.001 mmHg, the drying rate is slow, and the dispersion medium tends to remain in the coating film, making it difficult to obtain a high-quality coating film after the subsequent heat-light treatment. Because. In particular, when the vapor pressure of the dispersion medium is 50 mmHg or less, nozzle clogging due to drying hardly occurs when droplets are ejected from the droplet ejection head, which is more preferable.

  The solvent to be used is not particularly limited as long as it can be dispersed well without causing aggregation of the liquid. Specifically, in addition to water, alcohols such as methanol, ethanol, propanol, butanol, n-heptane, n-octane, decane, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene, decahydronaphthalene , Hydrocarbon solvents such as cyclohexylbenzene, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, 1,2-dimethoxyethane, bis (2-methoxy Ethyl) ether, ether solvents such as p-dioxane, propylene carbonate, γ-butyrolactone, N-methyl 2-pyrrolidone, dimethylformamide, dimethyl sulfoxide, can be mentioned polar solvents such as cyclohexanone. Of these, water, alcohols, hydrocarbon solvents, ether solvents are preferred, and more preferred solvents are the dispersibility of the metal fine particles, the stability of the dispersion, and the ease of application to the ink jet method. Can include water and hydrocarbon-based dispersion media. These dispersion media can be used alone or as a mixture of two or more.

When the above-mentioned SiO ₂ precursor material is dispersed in a dispersion medium to form a liquid, the concentration of the precursor compound in the liquid is preferably 1% by weight to 80% by weight, In this range, it is desirable to adjust according to the film thickness of the SiO ₂ bank to be formed. If it exceeds 80% by weight, cracks of the coating film tend to occur, and if it is less than 1% by weight, it takes a long time for drying to evaporate the dispersion medium, thereby reducing productivity. .

In addition, in the liquid containing the SiO ₂ precursor material, a small amount of a surface tension adjusting material such as a fluorine-based material, a silicon-based material, or a non-ionic material may be added as long as the target function is not impaired. Also good.
Nonionic surface tension modifiers improve the wettability of the dispersion to the object to be applied, improve the leveling of the applied film, and help prevent the occurrence of coating crushing and distortion skin. Become. The metal fine particle dispersion prepared by adding this nonionic surface tension adjusting agent preferably has a viscosity of 1 mPa · s to 50 mPa · s. When the viscosity is less than 1 mPa · s, the peripheral portion of the nozzle of the droplet discharge head is easily contaminated by the outflow of the liquid material, and when the viscosity exceeds 50 mPa · s, the nozzle hole is frequently clogged. Because it becomes.

Further, the liquid containing the SiO ₂ bank precursor compound thus prepared preferably has a surface tension in the range of 20 dyn / cm to 70 dyn / cm. When the surface tension is less than 20 dyn / cm, the wettability of the ink composition with respect to the nozzle surface increases, and thus flight bending easily occurs. When the surface tension exceeds 70 dyn / cm, the shape of the meniscus at the nozzle tip is not stable. This is because it becomes difficult to control the discharge amount and discharge timing of the composition.

Such a liquid material is disposed at a desired position by the droplet discharge head so as to have a uniform thickness. The disposed liquid is subjected to heat treatment. Next, drying is performed at a predetermined temperature for a predetermined time, and the liquid content in the liquid is removed. Further, after this drying, degreasing is performed at a predetermined high temperature (for example, 300 ° C.) for a predetermined time (for example, 30 minutes) in an air atmosphere, thereby thermally decomposing the organic component coordinated to Si, and (—O—Si -O) n polymer. And each process of such application | coating → drying → degreasing is repeated predetermined times, and a polymer is made into desired thickness.
Thereafter, heat treatment is performed at a predetermined temperature, preferably 350 ° C. to 400 ° C., more preferably 400 ° C. while oxygen flows in an RTA (Rapid Thermal Annealing) furnace, and the polymer is baked, as shown in FIG. 6 (g). An SiO ₂ bank is formed to a thickness of about 4 μm.

  The conditions for the heat treatment are not particularly limited, and general conditions can be adopted. For example, the heat treatment atmosphere may be performed in the air, or may be performed in an inert gas atmosphere such as nitrogen, argon, or helium as necessary. The heat treatment temperature is appropriately determined in consideration of the boiling point (vapor pressure) of the dispersion medium, the pressure, and the thermal behavior of the metal fine particles, but is preferably 400 ° C. or less. By setting the temperature to 400 ° C. or lower, the thermal influence on the circuit elements and the Al wiring in the semiconductor substrate 20 can be reduced.

As a heating method in the heat treatment, lamp annealing can be performed in addition to the treatment by a normal hot plate, electric furnace or the like.
The light source used for lamp annealing is not particularly limited, but excimers such as infrared lamps, xenon lamps, YAG lasers, argon lasers, carbon dioxide lasers, XeF, XeCl, XeBr, KrF, KrCl, ArF, ArCl, etc. A laser or the like can be used as a light source. In general, these light sources have an output in the range of 10 W to 5000 W, but in the present embodiment, a range of 100 W to 1000 W is sufficient.

  After the bank 41 is formed in this manner, as shown in FIG. 6H, via holes 72 and pads 87 connected to the pads 87 from the surface of the bank 41 are formed, and as shown in FIG. The lid 90 is fixed and packaged to form the surface acoustic wave element 10.

  Therefore, according to the third embodiment described above, it is possible to form the bank 41 of any shape by forming the bank 41 using the droplet discharge method, and the via hole 72 is formed in a part of the bank 41. The through hole 43 for forming can be formed in the same process, and the manufacturing process can be shortened.

  Further, since the piezoelectric body 51 and the IDT electrode 60 are formed on the same plane without the protruding portion of the base layer 30 that has been flattened, the piezoelectric body 51 and the IDT electrode 60 are formed in a recess formed in advance as in the first embodiment described above. The piezoelectric body 51 and the IDT electrode 60 can be formed more easily than the method.

Further, the precursor compound of SiO ₂ is a liquid containing an organometallic compound Si (OR) ₄ (R = CH ₃ , C ₂ H ₅ , C ₃ H ₇ , C ₄ H ₉ ) containing Si, By the above-described droplet discharge method, a desired bank shape and height can be easily formed, and then a bank having a desired shape made of SiO ₂ can be easily formed by solidifying by heat treatment.

Furthermore, since the temperature of the heat treatment is in the range of 350 ° C. to 400 ° C., the liquid material can be solidified reliably, and the thermal influence on the circuit elements and Al wiring in the semiconductor substrate 20 is eliminated. can do.
(Embodiment 4)

Then, the manufacturing method of the surface acoustic wave element 10 concerning Embodiment 4 of this invention is demonstrated with reference to drawings. In the fourth embodiment, the method for forming the bank 41 conforms to the manufacturing method according to the third embodiment described above, but is characterized in that the piezoelectric body 51 and the IDT electrode 60 are formed after the bank 41 is formed. . It demonstrates centering on a different process and attaches | subjects and demonstrates the same code | symbol about the same functional element.
FIG. 7 is a partial cross-sectional view schematically showing the method for manufacturing the surface acoustic wave element 10 according to the present embodiment.

FIG. 7A shows a process for forming the bank 41. The bank 41 is formed on the periphery of the surface of the base layer 30 with a predetermined shape and height using a droplet discharge method. For the droplet discharge method, the same method and conditions as in the third embodiment described above are used. A recess 42 is formed by the bank 41, and a part of the surface of the base layer 30 that has been flattened is exposed on the bottom surface of the recess 42. The through hole 43 communicating with the pad 83 is also formed by the same process.
Next, through holes that communicate with the pads 83 and 86 are formed in the base layer 30.

  FIG. 7B to FIG. 7E show a process for forming the through holes 44 to 47. First, as shown in FIG. 7B, a resist layer 102 is formed over the bottom surface of the recess 42 (that is, the surface of the base layer 30) and the surface of the bank 41, and the through holes 44 and 45 are formed by exposure and development processes. A resist pattern having corresponding openings 102a and 102b is formed.

Then, as shown in FIG. 7C, a process of opening the through holes 44 and 45 is shown. Through holes 44 and 45 are formed by etching, and the resist layer 102 is removed and washed.
Next, through holes 46 and 47 are formed in the insulating layer 23.

First, as shown in FIG. 7D, a resist layer 103 is formed over the bottom surface of the recess 42 (that is, the surface of the base layer 30) and the surface of the bank 41, and openings corresponding to the through holes are formed by exposure and development processes. A resist pattern having portions 103a and 103b is formed.
Then, through holes 46 and 47 are formed in the insulating layer 23 by etching (FIG. 7E).

Subsequently, the piezoelectric layer 50 is formed on the surface of the base layer 30 in the recess 42. FIG. 7 (f) shows the state.
Next, after a resist layer (not shown) is formed on the surface of the piezoelectric layer 50, a resist pattern corresponding to the shape of the piezoelectric body 51 is formed by exposure and development processes, and the piezoelectric body 51 is formed by etching (see FIG. See FIG. 7 (g). Then, the resist layer is removed and the IDT electrode 60 is formed.

  A process of forming the IDT electrode is shown in FIG. The IDT electrode forming process is formed by the same method and process as those of the first embodiment (see FIG. 3K). That is, here, the IDT electrode 60, the connection electrodes 61a and 62a, the via holes 71 and 72, and the pad 87 are formed. Then, the lid 90 is fixed and packaged (see FIG. 1B), and the surface acoustic wave element 10 is completed.

Therefore, according to the manufacturing method according to the fourth embodiment, the surface acoustic wave element 10 having the same configuration as that of the first embodiment (see FIGS. 1A and 1B) can be formed as a finished product. And similar effects can be obtained.
In addition, since the order of steps for forming the piezoelectric body 51 and the IDT electrode 60 is formed after the bank 41 is formed, an etching solution or the like does not come into contact with the surface of the base layer 30 when the bank 41 is formed. Since the surface of the base layer 30 remains flattened, the reliability of bonding with the piezoelectric body 51 can be improved.

  Furthermore, when the bank 41 is formed, the surface of the base layer 30 has no protrusion such as the IDT electrode 60 and is in the same plane state. When the bank is formed, for example, the head nozzle contacts the IDT electrode 60 on the IDT electrode. This has the effect of not damaging the surface.

  In the third and fourth embodiments described above, the configuration of the base layer 30 can be a laminated structure of SiN and Al as in the second embodiment and the modification (see FIGS. 4 and 5). .

  It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.

  As described above, according to the above-described first to fourth embodiments, a method for manufacturing a surface acoustic wave device that is small and thin, easy to package, and highly reliable, and its manufacturing. A surface acoustic wave device manufactured by the method can be provided.

  DESCRIPTION OF SYMBOLS 10 ... Surface acoustic wave element, 20 ... Semiconductor substrate, 21-23 ... Insulating layer, 30 ... Base layer, 41 ... Bank, 51 ... Piezoelectric body, 60 ... IDT electrode.

Claims (10)

A method of manufacturing a surface acoustic wave device in which comb-shaped IDT electrodes are formed on the surface of a semiconductor substrate,
Forming an insulating layer on the active surface side surface of the semiconductor substrate;
Forming a base layer on the entire surface of the insulating layer;
Flattening the surface of the base layer;
Forming a piezoelectric body on the surface of the base layer that has been planarized;
Forming the IDT electrode on the surface of the piezoelectric body;
Forming a bank at a peripheral edge of the surface of the base layer that is higher than the height from the surface of the base layer to the surface of the IDT electrode and that surrounds the piezoelectric body;
A method for manufacturing a surface acoustic wave device, comprising: In the manufacturing method of the surface acoustic wave element according to claim 1,
The method of manufacturing a surface acoustic wave element, wherein the step of forming the base layer is a step of forming a single insulating layer. In the manufacturing method of the surface acoustic wave element according to claim 1,
The step of forming the base layer includes a step of laminating and forming an Al layer and the insulating layer, and a step of planarizing at least the surface of the Al layer. Device manufacturing method. In the manufacturing method of the surface acoustic wave element according to claim 1,
In the step of forming the bank, a step of forming a bank layer having the same height as the bank on the surface of the base layer, and a region where the piezoelectric body is disposed, until the surface of the base layer is reached. Removing the bank layer by etching to form a recess, and
Forming the piezoelectric body at the bottom of the recess;
A method for manufacturing a surface acoustic wave device, comprising: In the manufacturing method of the surface acoustic wave element according to claim 1,
A step of forming the bank after the step of forming the IDT electrode on the surface of the piezoelectric body;
The step of forming the bank uses a droplet discharge method to form a liquid containing a precursor compound of SiO ₂ in a predetermined shape of the bank in the bank formation region range of the surface peripheral portion of the base layer. A method of manufacturing a surface acoustic wave device, comprising: a step of forming; and a step of solidifying the liquid by heat treatment. In the manufacturing method of the surface acoustic wave element according to claim 1,
In the step of forming the bank, a liquid material containing a precursor compound of SiO ₂ is applied to a predetermined shape of the bank using a droplet discharge method in a region where the bank is formed in a peripheral region of the surface of the base layer. Forming a bank including a step of forming the liquid body and a step of solidifying the liquid by heat treatment,
After the step of forming the bank, a step of forming a piezoelectric body on the surface of the base layer that has been flattened inside the recess formed by the bank, and forming the IDT electrode on the surface of the piezoelectric body And a method of manufacturing a surface acoustic wave device. In the manufacturing method of the surface acoustic wave element according to claim 5 or 6,
The bank is made of SiO _2, precursor compound of SiO ₂ is an organometallic compound containing Si Si a _{(OR) 4 (R = CH} 3, C 2 H 5, C 3 H 7, C 4 H 9) A method of manufacturing a surface acoustic wave device, comprising: forming a bank by solidifying the liquid by heat treatment. In the manufacturing method of the surface acoustic wave element according to any one of claims 5 to 7,
The method of manufacturing a surface acoustic wave element, wherein the temperature of the heat treatment is in a range of 350 ° C to 400 ° C. A surface acoustic wave device in which comb-shaped IDT electrodes are formed on the surface of a semiconductor substrate,
An insulating layer formed on the active surface side surface of the semiconductor substrate;
A base layer formed on the entire surface of the insulating layer and subjected to a planarization treatment;
A piezoelectric body formed on the surface of the base layer subjected to the planarization treatment;
Forming the IDT electrode on the surface of the piezoelectric body;
A bank formed on the periphery of the surface of the base layer, which is higher than the height from the surface of the base layer to the surface of the IDT electrode and surrounds the piezoelectric body;
A surface acoustic wave device comprising: The surface acoustic wave device according to claim 9, wherein
A surface acoustic wave device, wherein a sealing member that hermetically seals the inside of the recess formed by the bank is further provided on the upper surface of the bank and packaged.

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