JP2009239094A - Surface-mounted type electronic component array and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface-mounted type electronic component array that sufficiently prevents a plating liquid from penetrating an element body and relaxes stress to the element body while preventing solder from excessively creeping up. <P>SOLUTION: A surface-mounted type capacitor array 1 includes a dielectric element body 10, and an external electrode 16A<SB>1</SB>disposed on the dielectric element body 10. The external electrode 16A<SB>1</SB>has a baked electrode layer 18A<SB>1</SB>, a resin electrode layer 20A<SB>1</SB>, a first plating layer 22A<SB>1</SB>, and a second plating layer 24A<SB>1</SB>. The resin electrode layer 20A<SB>1</SB>includes wide portions 201A<SB>1</SB>and 202A<SB>1</SB>and a narrow portion 203A<SB>1</SB>. The wide portions 201A<SB>1</SB>, narrow portion 203A<SB>1</SB>, and wide portion 202A<SB>1</SB>are disposed in this order in the extending direction of the resin electrode layer 20A<SB>1</SB>. The narrow portion 203A<SB>1</SB>is provided with a recess. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a surface mount electronic component array and a method for manufacturing the same.

  Conventionally, what was described in following patent document 1 is known as a surface mount type capacitor array. The surface-mounted capacitor array described in Patent Document 1 includes a rectangular parallelepiped element formed by laminating a plurality of dielectric layers with two internal electrodes provided on the surface, and four elements arranged on the outer surface of the element body. An external electrode.

  The element body includes a pair of first main surface and second main surface facing each other, a pair of first main surface and second side surface opposing each other and connecting the first main surface and second main surface to each other, and a first The main surface, the second main surface, and the first side surface and the second side surface are connected to each other and have a pair of third side surface and fourth side surface facing each other. The two external electrodes are formed so as to go from the first main surface to the first side surface and the second side surface, respectively, and the other two external electrodes go from the second main surface to the first side surface and the second side surface. Are formed respectively.

Each external electrode includes a baked electrode layer formed on the surface of the element body, a pair of resin electrode layers formed so as to cover the vicinity of the ridge portion of the element body, and a baked electrode layer and a pair of baked electrode layers. And a plating layer formed so as to cover the resin electrode layer. Therefore, each baking electrode layer has a part which is not covered with a pair of resin electrode layers in the 1st principal surface side or the 2nd principal surface side, and the boundary part of the part concerned and the resin electrode layer is a level difference. It has become.
JP 2004-296936 A

  By the way, when mounting the surface mount capacitor array on the circuit board, the external electrode of the surface mount capacitor array and the circuit board are mounted with the mounting surface of the surface mount capacitor array facing the main surface of the circuit board. The signal electrode formed on the main surface is soldered. At this time, the solder crawls up the surface of the external electrode. If the solder covers most of the external electrode surface, the surface-mounted capacitor array is strongly fixed to the circuit board by the solder.

  Here, after mounting the surface mount type capacitor array on the circuit board, an external force is applied to the circuit board, or the surface mount type capacitor array itself expands / contracts due to heat generated during operation of the surface mount type capacitor array. Then, the stress from the solder acts on the element body of the surface mount capacitor array, and a crack may occur in the element body. When a crack occurs in the element body, the internal electrodes arranged in the element body may be short-circuited. For this reason, in the surface mount capacitor array described in Patent Document 1, an excess of solder is caused by a step provided at a boundary portion between the portion of the baked electrode layer that is not covered with the pair of resin electrode layers and the resin electrode layer. Prevents a crawl up.

  However, the surface-mounted capacitor array described in Patent Document 1 has a portion of the baked electrode layer that is not covered with the pair of resin electrode layers. Therefore, when the plating layer is formed so as to cover the baked electrode layer and the pair of resin electrode layers, the inside of the element body is plated through the baked electrode layer and the internal electrode physically and electrically connected to the baked electrode layer. There is a problem that the liquid may infiltrate and the characteristics of the surface mount capacitor array deteriorate. In addition, since the resin electrode layer is easily deformed as compared with the baked electrode layer, the resin electrode layer can absorb the stress acting on the element body. In the surface mount type capacitor array, since the entire baked electrode layer was not covered with the resin electrode layer, there was a problem that the stress relaxation by the resin electrode layer was not sufficiently performed.

  Accordingly, the present invention provides a surface-mount type electronic component array capable of sufficiently preventing the penetration of the plating solution into the element body and relaxing the stress on the element body, while preventing excessive creeping of the solder. It aims at providing the manufacturing method.

  A surface-mount electronic component array according to the present invention is a surface-mount electronic component array including an element body and a first external electrode disposed on the element body, the element body including a first main surface, The first external electrode includes a metal as a main component, and includes a first baking electrode layer formed on the first main surface, and a conductive material. A first resin electrode layer that covers the entire surface of the first baked electrode layer and is formed over the first main surface and side surfaces; and a first resin electrode layer that contains the metal as a main component and covers the first resin electrode layer. A portion of the first resin electrode layer located on the first main surface side includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion; The -1 wide portion, the first narrow portion, and the 1-2 wide portion are arranged in this order in the extending direction of the first resin electrode layer. In the vicinity of the first narrow portion of the first resin electrode layer, the surface height in the direction orthogonal to the first main surface of the portion of the first resin electrode layer located on the first main surface side. Is provided with a first step formed by being higher on the side farther from the side than on the side closer to the side.

  In the surface mount electronic component array according to the present invention, the first external electrode has a first resin electrode layer that covers the entire surface of the first baking electrode layer and is formed over the first main surface and the side surface. In the vicinity of the first narrow portion of the first resin electrode layer, the surface height in the direction perpendicular to the first main surface of the portion of the first resin electrode layer located on the first main surface side is on the side far from the side surface. A first step formed by being higher than the side close to the side surface is provided. That is, the surface height in the direction orthogonal to the first main surface of the first resin electrode layer (first external electrode) changes in the extending direction. Therefore, when mounting the surface-mounted electronic component array on the circuit board with the side surface as the mounting surface, even if the solder crawls up the surface of the first external electrode, the crawl-up of the solder is suppressed by the first step. It becomes. As a result, it is possible to prevent the solder from creeping up excessively on the surface of the first external electrode, and to reduce the possibility of cracks in the element body.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion, and the 1-1 wide width portion. Portion, the first narrow portion, and the first-second wide portion are arranged in this order in the extending direction of the first resin electrode layer. That is, the width of the first resin electrode layer (first external electrode) changes in the extending direction. Therefore, when the surface-mounted electronic component array is mounted on the circuit board with the side surface as the mounting surface, even if the solder crawls up the surface of the first external electrode, the 1-1 wide portion and the 1-2 wide portion On the other hand, since the width of the first narrow portion is narrow, the creeping of the solder is suppressed by the first narrow portion. As a result, it is possible to further prevent the solder from creeping up the surface of the first external electrode, and to further reduce the possibility of cracks in the element body.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer. Here, the first resin electrode layer is easily deformed as compared with the first baking electrode layer. For this reason, after mounting the surface mount electronic component array on the circuit board, an external force is applied to the circuit board, or the surface mount electronic component array itself expands and contracts due to heat generated during operation of the surface mount electronic component array. Even if it is, the stress which acts on an element | base_body can be absorbed by the 1st resin electrode layer.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer. The layer is not formed on the first baked electrode layer. That is, in forming the first plating layer, the entire surface of the first baking electrode layer is covered with the first resin electrode layer, so that the plating solution penetrates into the element body through the first baking electrode layer and the like. It has become difficult. As a result, it is possible to sufficiently suppress the characteristic deterioration of the surface mount electronic component array due to the penetration of the plating solution into the element body.

  Preferably, in the vicinity of the first narrow portion, the portion of the first resin electrode layer located on the first main surface side is thick on the side far from the side surface and thin on the side near the side surface, One step is formed. If it does in this way, the steep 1st level | step difference will be comprised in the boundary of a thick part and a thin part. As a result, it is possible to further prevent the solder from creeping up excessively on the surface of the first external electrode.

  Preferably, the semiconductor device further includes a second external electrode disposed on the element body, the element body further including a second main surface adjacent to the side surface, and the second external electrode contains the metal as a main component and the second main electrode. A second baked electrode layer formed on the two main surfaces, a second resin electrode layer containing a conductive material, covering the entire surface of the second baked electrode layer, and formed over the second main surface and side surfaces; And a second plating layer that contains the metal as a main component and covers the second resin electrode layer, and the portion of the second resin electrode layer located on the second main surface side is the second -1 wide portion, 2-2 wide portion, and second narrow portion, the 2-1 wide portion, the second narrow portion, and the 2-2 wide portion are extending directions of the second resin electrode layer Are arranged in this order, and in the vicinity of the second narrow portion, a portion of the second resin electrode layer located on the second main surface side The second step is provided in which the surface height in a direction perpendicular to the second main surface is configured by is higher than the side closer to the side surface of the side farther from the side.

  More preferably, in the vicinity of the second narrow portion, the portion located on the second main surface side of the second resin electrode layer is thin on the side close to the side surface and thick on the side far from the side surface, A second step is formed.

  The surface mount electronic component array according to the present invention is a surface mount electronic component array including an element body and a first external electrode disposed on the element body, wherein the element body is a first main surface. And a pair of first side surfaces and second side surfaces that are adjacent to each other and face each other, and the first external electrode contains metal as a main component and is formed on the first main surface. A first baked electrode layer, a first resin electrode layer containing a conductive material, covering the entire surface of the first baked electrode layer and formed over the first side surface, the first main surface, and the second side surface; A first plating layer that contains a metal as a main component and covers the first resin electrode layer, and a portion of the first resin electrode layer located on the first main surface side has a first 1- 1 wide part, 1st-2 wide part, and 1st narrow part, 1st-1 wide part, 1st narrow part, and The 1-2 wide portions are arranged in this order in the extending direction of the first resin electrode layer, and in the vicinity of the first narrow portion, the first resin electrode in the direction orthogonal to the first main surface. A first step formed by changing the surface height of the layer in the extending direction of the first resin electrode layer is provided.

  In the surface-mount type electronic component array according to the present invention, the first external electrode covers the entire surface of the first baked electrode layer and is formed over the first side surface, the first main surface, and the second side surface. The surface height of the first resin electrode layer in the direction orthogonal to the first main surface is in the extending direction of the first resin electrode layer in the vicinity of the first narrow portion of the first resin electrode layer. A first step formed by changing is provided. Therefore, even when the solder crawls up the surface of the first external electrode when mounting the surface-mount type electronic component array on the circuit board using the first side surface or the second side surface as the mounting surface, the first step causes the scooping of the solder. The rise will be suppressed. As a result, it is possible to prevent the solder from creeping up excessively on the surface of the first external electrode, and to reduce the possibility of cracks in the element body.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion, and the 1-1 wide width portion. Portion, the first narrow portion, and the first-second wide portion are arranged in this order in the extending direction of the first resin electrode layer. That is, the width of the first resin electrode layer (first external electrode) changes in the extending direction. Therefore, when the surface-mounted electronic component array is mounted on the circuit board with the side surface as the mounting surface, even if the solder crawls up the surface of the first external electrode, the 1-1 wide portion and the 1-2 wide portion On the other hand, since the width of the first narrow portion is narrow, the creeping of the solder is suppressed by the first narrow portion. As a result, it is possible to further prevent the solder from creeping up the surface of the first external electrode, and to further reduce the possibility of cracks in the element body.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer. Here, the first resin electrode layer is easily deformed as compared with the first baking electrode layer. For this reason, after mounting the surface mount electronic component array on the circuit board, an external force is applied to the circuit board, or the surface mount electronic component array itself expands and contracts due to heat generated during operation of the surface mount electronic component array. Even if it is, the stress which acts on an element | base_body can be absorbed by the 1st resin electrode layer.

  In the surface mount electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer. The layer is not formed on the first baked electrode layer. That is, in forming the first plating layer, the entire surface of the first baking electrode layer is covered with the first resin electrode layer, so that the plating solution penetrates into the element body through the first baking electrode layer and the like. It has become difficult. As a result, it is possible to sufficiently suppress the characteristic deterioration of the surface mount electronic component array due to the penetration of the plating solution into the element body.

  Preferably, in the vicinity of the first narrow portion, the thickness of the portion of the first resin electrode layer located on the first main surface side changes in the extending direction of the first resin electrode layer, whereby the first step Is configured. If it does in this way, the steep 1st level | step difference will be comprised in the boundary where the thickness of the part located in the 1st main surface side among 1st resin electrode layers is changing. As a result, it is possible to further prevent the solder from creeping up excessively on the surface of the first external electrode.

  Preferably, the first narrow portion is located substantially at the center of the first main surface in the facing direction of the first side surface and the second side surface. In this way, when mounting the surface-mounted electronic component array on the circuit board, it is possible to prevent the solder from creeping up due to the first narrow portion and the first step regardless of which of the first side surface or the second side surface is used as the mounting surface. The effect will be exhibited equally.

  Preferably, the battery further includes a second external electrode disposed on the element body, and the element body further includes a second main surface adjacent to the first side surface and the second side surface and facing the first main surface, The second external electrode contains a metal as a main component, and includes a second baked electrode layer formed on the second main surface, a conductive material, covers the entire surface of the second baked electrode layer, and includes a second baked electrode layer. A second resin electrode layer formed over one side surface, the second main surface and the second side surface; and a second plating layer which contains metal as a main component and is formed so as to cover the second resin electrode layer. The portion of the second resin electrode layer located on the second main surface side includes a 2-1 wide portion, a 2-2 wide portion, and a second narrow portion, and includes a 2-1 wide portion, a second wide portion, and a second wide portion. The narrow part and the 2-2 wide part are arranged in this order in the extending direction of the second resin electrode layer. In the vicinity of the narrow portion, a second step formed by changing the surface height of the second resin electrode layer in the direction orthogonal to the second main surface in the extending direction of the second resin electrode layer is provided. Yes.

  More preferably, in the vicinity of the second narrow portion, the thickness of the portion of the second resin electrode layer located on the second main surface side changes in the extending direction of the second resin electrode layer, so that the second A step is formed.

  More preferably, the 2nd narrow part is located in the approximate center of the 2nd main surface in the opposing direction of the 1st side and the 2nd side.

  On the other hand, a method for manufacturing a surface-mounted electronic component array according to the present invention includes an element body preparing step of preparing an element body having a first main surface and a side surface adjacent to the first main surface; 1st external electrode formation process which forms 1 external electrode, and the 1st external electrode formation process applies the conductive paste which contains a metal as a main component to the 1st principal surface, and is baked by baking. Step 1-1 of forming a layer, and a conductive resin paste containing a conductive material and a thermosetting resin material are applied over the entire surface of the first baked electrode layer and applied over the first main surface and side surfaces and heated. And a first step of forming a first resin electrode layer by metal plating so as to cover the first resin electrode layer. In the first-second step, the first main surface side of the first resin electrode layer The part located includes a 1-1 wide part, a 1-2 wide part, and a 1 narrow part, and the 1-1 wide part, the 1st narrow part, and the 1-2 wide part are the first. In the direction in which the resin electrode layer extends, the resin electrode layers are arranged side by side in this order, and in the direction orthogonal to the first main surface of the portion of the first resin electrode layer located on the first main surface side in the vicinity of the first narrow portion. The first resin electrode layer is formed so that the first step formed by the surface height being higher on the side far from the side than on the side near the side is located.

  In the method for manufacturing a surface-mounted electronic component array according to the present invention, in step 1-2, the entire surface of the first baked electrode layer is covered and a conductive resin paste is applied over the first main surface and side surfaces and cured by heating. The first resin electrode layer is formed, and in the vicinity of the first narrow portion of the first resin electrode layer, the first main surface of the portion of the first resin electrode layer located on the first main surface side A first step formed by the surface height in the direction orthogonal to the side being higher on the side farther from the side than on the side closer to the side is provided. That is, the surface height in the direction orthogonal to the first main surface of the first resin electrode layer (first external electrode) changes in the extending direction. Therefore, when the surface-mount type electronic component array manufactured by the manufacturing method according to the present invention is mounted on the circuit board with the side surface as the mounting surface, even if the solder crawls up the surface of the first external electrode, the first The stepping up of the solder is suppressed by the step. As a result, it is possible to prevent the solder from creeping up excessively on the surface of the first external electrode, and to reduce the possibility of cracks in the element body.

  In the method for manufacturing the surface-mounted electronic component array according to the present invention, the first resin electrode layer includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion. The -1 wide portion, the first narrow portion, and the 1-2 wide portion are arranged in this order in the extending direction of the first resin electrode layer. That is, the width of the first resin electrode layer (first external electrode) changes in the extending direction. Therefore, when the surface-mount type electronic component array manufactured by the manufacturing method according to the present invention is mounted on the circuit board with the side surface as the mounting surface, even if the solder crawls up the surface of the first external electrode, the first Since the width of the first narrow portion is narrower than that of the -1 wide portion and the 1-2 wide portion, the first narrow portion suppresses the solder creeping up. As a result, it is possible to further prevent the solder from creeping up the surface of the first external electrode, and to further reduce the possibility of cracks in the element body.

  In the method for manufacturing a surface-mounted electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer in the step 1-2. is doing. Here, the first resin electrode layer is easily deformed as compared with the first baking electrode layer. Therefore, after mounting the surface mounted electronic component array manufactured by the manufacturing method according to the present invention on the circuit board, external force is applied to the circuit board, or surface mounting is performed by heat generated during operation of the surface mounted electronic component array. Even when the mold electronic component array itself expands and contracts, the stress acting on the element body can be absorbed by the first resin electrode layer.

  In the method for manufacturing a surface-mounted electronic component array according to the present invention, the first resin electrode layer is formed on the first baked electrode layer so as to cover the entire surface of the first baked electrode layer in the step 1-2. As a result, the first plating layer is not formed on the first baking electrode layer. That is, in forming the first plating layer in the first to third steps, since the entire surface of the first baking electrode layer is covered with the first resin electrode layer, the inside of the element body passes through the first baking electrode layer and the like. It is difficult for the plating solution to permeate. As a result, it is possible to sufficiently suppress the characteristic deterioration of the surface mount electronic component array due to the penetration of the plating solution into the element body.

  Preferably, in the first-second step, the first-first coating film is formed on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. The 1-1 coating film is formed on the first main surface by applying a 1-1 coating film forming step and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including a first-second coating film forming step, wherein the first-first coating film has a taper that becomes narrower and thinner as the distance from the side surface increases. The taper has a taper that becomes narrower and thinner as it gets closer, and the taper of the 1-1 coating and the tape of the 1-2 coating are in contact with each other. The first narrow portion and the first step are constituted by the taper and the taper of the 1-2 coating film. In this way, the first narrow portion can be easily formed, and the first step can be easily formed in the vicinity of the first narrow portion.

  Preferably, in the first-second step, the first-first coating film is formed on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. The 1-1 coating film is formed on the first main surface by applying a 1-1 coating film forming step and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including a first-second coating film forming step, wherein the first-first coating film has a taper that becomes narrower and thinner as the distance from the side surface increases. As it gets closer, it has a taper that becomes narrower and thinner, and the film thickness is different from that of the 1-1 paint film. The taper of the 1-1 paint film and the taper of the 1-2 paint film Are in contact with each other, and the first narrow portion and the first step due to the taper of the 1-1 coating and the tape of the 1-2 coating It is configured. In this way, the first narrow portion can be easily formed, and the first step can be easily formed in the vicinity of the first narrow portion. In this case, a steep first step is formed at the boundary where the thickness of the portion located on the first main surface side of the first resin electrode layer is changing. As a result, it is possible to further prevent the solder from creeping up excessively on the surface of the first external electrode.

  Preferably, in the first-second step, the first-first coating film is formed on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. The 1-1 coating film is formed on the first main surface by applying a 1-1 coating film forming step and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. The first-second coating film is formed on the first main surface by applying a first-second coating film forming step and a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including a first-third coating film forming step, wherein the first-first coating film extends in a direction away from the side surface on the first main surface, and the first-second coating film and the first-third coating film are , Both are wider than the 1-1 coating film, and are separated from each other in the extending direction of the 1-1 coating film And overlapped with the 1-1 coating so as to protrude from the 1-1 coating in the width direction of the 1-1 coating, and the 1-2 coating among the 1-1 coatings. The first narrow portion is constituted by the portion located between the first coating film and the first-third coating film, and the boundary portion between the first-first coating film and the first-second coating film and the first-first coating film The 1st level | step difference is comprised by the boundary part with 1-3 coating films. In this way, the first narrow portion can be easily formed, and the first step can be easily formed in the vicinity of the first narrow portion. Further, in this case, steep first steps are respectively present at the boundary portion between the 1-1 coating film and the 1-2 coating film and at the boundary portion between the 1-1 coating film and the 1-3 coating film. Will be composed. As a result, it is possible to further prevent the solder from creeping up excessively on the surface of the first external electrode.

  Preferably, the method further includes a second external electrode forming step of forming a second external electrode on the element body, the element body further including a second main surface adjacent to the side surface, and the second external electrode forming step includes a metal And a conductive resin containing a conductive material and a thermosetting resin material, the step 2-1 of forming a second baked electrode layer by applying and baking a conductive paste containing as a main component to the second main surface A second step of forming a second resin electrode layer by covering the entire surface of the second baked electrode layer and applying the paste over the second main surface and side surfaces and curing the paste by heating; a second resin electrode layer; And a second plating process for forming a second plating layer by performing metal plating so as to cover the metal layer. In the second to second process, the second resin electrode layer is positioned on the second main surface side. The portion to be included includes a 2-1 wide portion, a 2-2 wide portion, and a second narrow portion, The first wide portion, the second narrow portion, and the 2-2 wide portion are arranged in this order in the extending direction of the second resin electrode layer, and in the vicinity of the second narrow electrode portion, Among these, the second step formed by the surface height in the direction orthogonal to the second main surface of the portion located on the second main surface side being higher on the side far from the side surface than on the side close to the side surface is located. Thus, the second resin electrode layer is formed.

  More preferably, in step 2-2, a conductive resin paste containing a conductive material and a thermosetting resin material is applied and dried by heating, so that the 2-1 coating film is formed on the second main surface. A 2-1 coating film is formed on the second main surface by applying a 2-1 coating film forming step to be formed and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. 2-2 coating film forming step, and the 2-1 coating film has a taper that becomes narrower and thinner as it gets away from the side surface. The taper has a taper that becomes narrower and thinner as it approaches, and the taper of the 2-1 coating film and the taper of the 2-2 coating film are in contact with each other. The second narrow portion and the second step are constituted by the taper of the film and the taper of the 2-2 coating film.

  More preferably, in step 2-2, a conductive resin paste containing a conductive material and a thermosetting resin material is applied and dried by heating, so that the 2-1 coating film is formed on the second main surface. A 2-1 coating film is formed on the second main surface by applying a 2-1 coating film forming step to be formed and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. 2-2 coating film forming step, and the 2-1 coating film has a taper that becomes narrower and thinner as it gets away from the side surface. As the thickness approaches, the width becomes narrower and the thickness becomes thinner, and the film thickness is different from that of the 2-1 coating film. Are in contact with each other, and the second narrow portion and the second portion are formed by the taper of the 2-1 coating film and the taper of the 2-2 coating film. The difference is configured.

  More preferably, in step 2-2, a conductive resin paste containing a conductive material and a thermosetting resin material is applied and dried by heating, so that the 2-1 coating film is formed on the second main surface. A 2-1 coating film is formed on the second main surface by applying a 2-1 coating film forming step to be formed and applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. 2-2 coating film forming step to be formed on, and applying a conductive resin paste containing a conductive material and a thermosetting resin material, and drying by heating, the second-3 coating film is the second main surface Including a second-third coating film forming step, wherein the second-first coating film extends in a direction away from the side surface on the second main surface, and the second-second coating film and the second-third coating film Are both wider than the 2-1 coating film and are separated from each other in the extending direction of the 2-1 coating film. And overlapped with the 1-1 coating so as to protrude from the 2-1 coating in the width direction of the 2-1 coating, and the 2-2 coating among the 2-1 coatings. The second narrow portion is constituted by the portion located between the film and the 2-3 coating film, the boundary between the 2-1 coating film and the 2-2 coating film and the 2-1 coating film The 2nd level | step difference is comprised by the boundary part with the 2-3rd coating film.

  According to the present invention, there is provided a surface-mount type electronic component array capable of sufficiently preventing the penetration of the plating solution into the body and alleviating the stress on the body while preventing the solder from excessively rising. A manufacturing method thereof can be provided.

  Preferred embodiments of the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

[1] First Embodiment [1.1] Configuration of Surface-Mounted Electronic Component Array A configuration of a surface-mounted electronic component array according to the first embodiment will be described with reference to FIGS. In the following description, the surface-mounted capacitor array 1 is described as an example of the surface-mounted electronic component array.

Surface mount capacitor 1, the dielectric body (element body) 10 having a rectangular parallelepiped shape, the internal electrodes _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~14B 3, external electrodes and a _{16A 1 ~16A 3, 16B 1 ~16B} 3.

  The dielectric body 10 opposes the main surfaces 10a (first main surface) and 10b (second main surface) facing each other and the side surfaces 10c (first side surface) and 10d (second side surface) facing each other. Side surfaces 10e and 10f. In the first embodiment, the side surface 10c or the side surface 10d is a mounting surface that faces the main surface of a circuit board (not shown).

The side surfaces 10c and 10d extend so as to connect the main surfaces 10a and 10b and the side surfaces 10e and 10f. The side surfaces 10e and 10f extend so as to connect the main surfaces 10a and 10b and the side surfaces 10c and 10d. Since dielectric body 10 is usually barrel-polished after firing, the ridge portion of dielectric body 10 that connects adjacent surfaces has a curved surface shape having a predetermined curvature. .

The dielectric body 10 can be formed of, for example, a dielectric ceramic material obtained by adding a rare earth element to barium titanate or strontium titanate. In the first embodiment, the length of the dielectric body 10 in the longitudinal direction can be set, for example, to about 2.0 mm, the width, for example, about 1.25 mm, and the thickness, for example, about 0.85 mm.

The dielectric body 10, as shown in FIG. 4, a dielectric layer A10~A15 exhibiting a rectangular internal electrode _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~ and 14B ₃ are formed by laminating. The actual surface mount capacitor array 1 is integrated to such an extent that the boundaries between the dielectric layers A10 to A15 cannot be visually recognized. That is, the internal electrodes _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~14B 3 are both disposed inside of the dielectric body 10.

On the dielectric layer A11 is three internal electrodes _12A 1 _{~12A 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A11 (side 10e, 10f opposite direction). The internal electrodes 12A _{1 to} 12A ₃ have a predetermined distance from each other on the dielectric layer A11. In each of the internal electrodes 12A _{1 to} 12A ₃ , lead-out portions 12a _{1 to} 12a ₃ are integrally formed at the central portion of the short side on the main surface 10a side. Each lead portion _12a 1 _{~12a 3} has a rectangular shape, respectively, one end is exposed to the main surface 10a.

On the dielectric layer A12 is three internal electrodes _12B 1 _{~12B 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A12 (side 10e, 10f opposite direction). The internal electrodes 12B _{1 to} 12B ₃ have a predetermined distance from each other on the dielectric layer A12. Each internal electrode _12B 1 _{~12B 3,} deriving portion _12b 1 _{~12b 3} in a central portion of the short side of the principal surface 10b side is integrally formed, respectively. Each lead portion _12b 1 _{~12b 3} has a rectangular shape, respectively, one end is exposed to the main surface 10b.

On the dielectric layer A13 is three internal electrodes _14A 1 to 14A ₃ exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A13 (side 10e, 10f opposite direction). The internal electrodes 14A _{1 to} 14A ₃ have a predetermined distance from each other on the dielectric layer A13. Each internal electrode _14A 1 to 14A _3, deriving section _14a 1 to 14A ₃ in the central portion of the short side of the principal surface 10a side is integrally formed, respectively. Each lead portion _14a 1 to 14A ₃ has a rectangular shape, respectively, one end is exposed to the main surface 10a.

On the dielectric layer A14 is three internal electrodes _14B 1 _{~14B 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A14 (side 10e, 10f opposite direction). The internal electrodes 14B _{1 to} 14B ₃ have a predetermined distance from each other on the dielectric layer A14. Each internal electrode _14B 1 _{~14B 3,} deriving portion _14b 1 _{~14b 3} in the central portion of the short side of the principal surface 10b side is integrally formed, respectively. Each lead portion _14b 1 _{~14b 3} has a rectangular shape, respectively, one end is exposed to the main surface 10b.

The internal electrodes 12A ₁ , 12B ₁ , 14A ₁ , 14B ₁ are alternately stacked via the dielectric layers A11 to A13, and overlap each other when viewed from the stacking direction. The internal electrodes 12A ₂ , 12B ₂ , 14A ₂ , 14B ₂ are alternately stacked via the dielectric layers A11 to A13, and overlap each other when viewed from the stacking direction. The internal electrodes 12A ₃ , 12B ₃ , 14A ₃ , 14B ₃ are alternately stacked via the dielectric layers A11 to A13, and overlap each other when viewed from the stacking direction.

The facing area of the internal electrodes 12A ₁ , 12B ₁ , 14A ₁ , 14B ₁ and the interval between the internal electrodes 12A ₁ , 12B ₁ , 14A ₁ , 14B ₁ when viewed from the stacking direction (that is, the dielectric layers A11 to 11) A thickness of A13) defines a part of the capacitance of the surface-mounted capacitor array 1. The facing area of the internal electrodes 12A ₂ , 12B ₂ , 14A ₂ , 14B ₂ and the distance between the internal electrodes 12A ₂ , 12B ₂ , 14A ₂ , 14B ₂ when viewed from the stacking direction (that is, the dielectric layers A11 to A11) A thickness of A13) defines a part of the capacitance of the surface-mounted capacitor array 1. The facing area of the internal electrodes 12A ₃ , 12B ₃ , 14A ₃ , 14B ₃ and the interval between the internal electrodes 12A ₃ , 12B ₃ , 14A ₃ , 14B ₃ when viewed from the stacking direction (that is, the dielectric layers A11 to 11) A thickness of A13) defines a part of the capacitance of the surface-mounted capacitor array 1.

Internal electrodes _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~14B 3 , for example made of a conductive material such as Ag or Ni. The internal electrodes 12A _{1 to} 12A ₃ , 12B _{1 to} 12B ₃ , 14A _{1 to} 14A ₃ , and 14B _{1 to} 14B ₃ are configured as a sintered body of a conductive paste containing the conductive material.

1 to 3, the external electrode 16A ₁ (first external electrode) is formed so as to cover the main surface 10a of the dielectric element body 10 and wrap around the side surfaces 10c and 10d adjacent to the main surface 10a. ing. That is, the external electrodes 16A ₁ includes a main surface 10a, are arranged side 10c, on the main surface 10a side of the portion of the 10d.

The external electrode 16A ₁ has a baked electrode layer 18A ₁ , a resin electrode layer 20A ₁ , a first plating layer 22A ₁ and a second plating layer 24A ₁ . The baked electrode layer 18A ₁ , the resin electrode layer 20A ₁ , the first plating layer 22A _1, and the second plating layer 24A ₁ are arranged in this order from the dielectric body 10 toward the outside.

Sintered electrode layer 18A ₁ is a belt-like shape, the side surface 10c adjacent to the main surface 10a covers the major surface 10a of the dielectric body 10, as around to 10d, are formed on the dielectric body 10 ing. That is, the sintered electrode layer 18A ₁ includes a main surface 10a, and the main surface 10a side of the region of the side faces 10c, are arranged on the principal surface 10a side of the region of the side surface 10d.

Sintered electrode layer 18A ₁ is an end of the lead portion _12a 1, 14a ₁ which is exposed to the main surface 10a physically and electrically connected. Therefore, the sintered electrode layer 18A ₁ is electrically connected to the internal electrodes 12A ₁ via a lead portion 12a _1, and is connected the internal electrodes 14A ₁ and electrically via a lead portion 14a _1.

Resin electrode layer 20A ₁ is to cover the entire surface of the sintered electrode layers 18A _1, is formed on the baked electrode layer 18A ₁ and on the dielectric element 10. Specifically, the resin electrode layer 20A ₁ includes a wide portion 201A _1, 202A _1, and a narrow portion 203A _1.

Wide portion 201A ₁ is arranged in the region of the main surface 10a toward one side 10c side of the region and the side surface 10c of the main surface 10a, and covers a part of the surface of the sintered electrode layers 18A _1. Wide portion 202A ₁ is arranged in the region of the main surface 10a toward one side 10d side of the region and the side surface 10d of the main surface 10a, and covers a part of the surface of the sintered electrode layers 18A _1. Narrow portion 203A ₁ is disposed substantially at the center of the main surface 10a of the side surface 10c, 10d opposite direction, and covers a part of the surface of the sintered electrode layers 18A _1. That is, the wide part 201A ₁ , the narrow part 203A ₁ and the wide part 202A ₁ are arranged in this order in the extending direction of the resin electrode layer 20A ₁ (opposite direction of the side surfaces 10c and 10d).

Narrow portion 203A ₁ is particularly, as shown in FIGS. 1 and 2, is narrower than the width of the width of the wide portion 201A _1, 202A _1. That is, the resin electrode layer 20A ₁ is in a state of constricted at the narrow portion 203A _1.

Narrow portion 203A _1, especially as shown in FIG. 3, the side surface 10c, substantially at the center of the major surface 10a in the opposing direction of the 10d, has a recess. That is, the surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is changed in the extending direction of the resin electrode layer 20A ₁ (side 10c, 10d opposite direction).

More specifically, the narrow portion 203A _1, provided is a step of surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is higher than the side closer to the side surface 10c in the side away from the side surface 10c together they are, and step is provided that the surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is higher than the side closer to the side surface 10d at the side away from the side 10d. These steps are the narrow portion 203A _1, becomes thicker in side away from the side surface 10c, it becomes thicker in the side away from the side surface 10d, by a thin between these thick portions, it is configured ing. In the first embodiment, it is substantially identical to the wide portion 201A ₁ thickness and the wide portion 202A ₁ thickness.

First plating layer 22A ₁ is formed so as to cover the resin electrode layer 20A _1. Second plating layer 24A ₁ is formed so as to cover the first plated layer 22A _1. Therefore, the external electrodes 16A ₁ has the shape of the outer shape equivalent to the outer shape of the resin electrode layer 20A ₁ as a whole.

Since the configuration of the external electrodes 16A ₂ and 16A _{3 is the same as} the configuration of the external electrode 16A ₁ , the description thereof is omitted.

The external electrode 16B ₁ (second external electrode) is formed so as to cover the main surface 10b of the dielectric element body 10 and wrap around the side surfaces 10c and 10d adjacent to the main surface 10b. That is, the external electrodes 16B ₁ includes a main surface 10b, are arranged side 10c, on the main surface 10b side of the portion of the 10d.

The external electrode 16B ₁ has a baked electrode layer 18B ₁ , a resin electrode layer 20B ₁ , a first plating layer 22B ₁ and a second plating layer 24B ₁ . The baked electrode layer 18B ₁ , the resin electrode layer 20B ₁ , the first plating layer 22B ₁ and the second plating layer 24B ₁ are arranged in this order from the dielectric element body 10 toward the outside.

Sintered electrode layer 18B ₁ is a belt-like shape, the side surface 10c adjacent to the main surface 10b covers the main surface 10b of the dielectric body 10, as around to 10d, are formed on the dielectric body 10 ing. That is, the sintered electrode layer 18B ₁ includes a main surface 10b, and the main surface 10b side of the region of the side faces 10c, are arranged on the principal surface 10b side of the region of the side surface 10d.

The baked electrode layer 18B ₁ is physically and electrically connected to the end portions of the lead-out portions 12b ₁ and 14b ₁ exposed on the main surface 10b. Therefore, the sintered electrode layer 18B ₁ the derived portions 12b are electrically connected to the internal electrodes 12B ₁ through ₁ are connected internal electrodes 14B ₁ and the electrically via a lead portion 14b _1.

Resin electrode layer 20B ₁ so as to cover the entire surface of the sintered electrode layers 18B _1, is formed on the baked electrode layer 18B ₁ and on the dielectric element 10. Specifically, the resin electrode layer 20B ₁ has wide portions 201B ₁ and 202B ₁ and a narrow portion 202B ₁ .

The wide portion 201B ₁ is arranged in the region of the main surface 10b toward one side 10c side of the region and the side surface 10c of the main surface 10b, and covers a part of the surface of the sintered electrode layers 18B _1. The wide portion 202B ₁ is arranged in the region of the main surface 10b toward one side 10d side of the region and the side surface 10d of the main surface 10b, and covers a part of the surface of the sintered electrode layers 18B _1. The narrow portion 203B ₁ is disposed substantially at the center of the main surface 10b at the side surfaces 10c, 10d facing direction, and covers a part of the surface of the sintered electrode layers 18B _1. That is, the wide part 201B ₁ , the narrow part 203B ₁ and the wide part 202B ₁ are arranged in this order in the extending direction of the resin electrode layer 20B ₁ (opposite direction of the side surfaces 10c and 10d).

The narrow portion 203B _1, like the narrow portion 203A ₁ of the resin electrode layer 20A _1, is smaller than the width of the wide portions 201B _1, 202B ₁ width. That is, the resin electrode layer 20B ₁ is in a state of constricted at the narrow portion 203B _1.

The narrow portion 203B _1, especially as shown in FIG. 3, the side surface 10c, substantially at the center of the main surface 10b in the opposing direction of the 10d, has a recess. That is, the surface height of the narrow portion 203B ₁ in the direction perpendicular to the main surface 10b is changed in the extending direction of the resin electrode layer 20B ₁ (side 10c, 10d opposite direction).

More specifically, the narrow portion 203B _1, provided is a step of surface height of the narrow portion 203B ₁ in the direction perpendicular to the main surface 10b is higher than the side closer to the side surface 10c in the side away from the side surface 10c together they are, and step is provided that the surface height of the narrow portion 203B ₁ in the direction perpendicular to the main surface 10b is higher than the side closer to the side surface 10d at the side away from the side 10d. These steps are the narrow portion 203B _1, becomes thicker in side away from the side surface 10c, it becomes thicker in the side away from the side surface 10d, by a thin between these thick portions, it is configured ing.

First plating layer 22B ₁ is formed to cover the resin electrode layer 20B _1. Second plating layer 24B ₁ is formed to cover the first plated layer 22B _1. Therefore, the external electrodes 16B ₁ has the shape of the outer shape equivalent to the outer shape of the resin electrode layer 20B ₁ as a whole.

Since the configuration of the external electrodes 16B ₂ and 16B _{3 is the same as} the configuration of the external electrode 16B ₁ , the description thereof is omitted.

[1.2] Manufacturing Method of Surface Mount Electronic Component Array Subsequently, with reference to FIG. 1 and FIGS. 5 to 8, the surface mount electronic component array (surface mount capacitor array 1) according to the first embodiment. The manufacturing method will be described.

First, a dielectric material is prepared by mixing a dielectric material, which is a main component of the dielectric body 10, and rare earth oxide, magnesium oxide, manganese oxide, and the like, which are subcomponents, at a predetermined ratio. The dielectric material as the main component is not particularly limited as long as it is a known ceramic dielectric material mainly contained in the dielectric layer of the multilayer ceramic capacitor. For example, titanium oxide such as BaTiO ₃ , CaTiO ₃ and SrTiO ₃ is used. Things. The main dielectric material is used alone or in combination of two or more.

  Moreover, while mixing a co-material, an organic binder, a dispersing agent, an organic solvent, etc. with nickel powder (metal powder), it disperse | distributes with a ball mill or a roll mill etc., and is made into paste form, and becomes the electroconductivity used as internal electrode 18A-18D. Adjust the paste.

  Subsequently, a dielectric slurry is applied on a support such as a PET film by a coating method such as a doctor blade method, and dried at about 60 ° C. to 100 ° C. for about 1 second to 10 seconds, whereby the dielectric layer A10 A dielectric green sheet to be A15 is formed.

Subsequently, a conductive paste is applied onto each dielectric green sheet by screen printing and dried at about 80 ° C. to 120 ° C. for about 1 minute to 5 minutes, whereby internal electrodes 12A _{1 to} 12A ₃ , 12B _{1 to} 12B. ₃ , a plurality of conductive coatings to be 14A _{1 to} 14A ₃ and 14B _{1 to} 14B ₃ are formed. Then, a plurality of dielectric green sheets each having three conductive coating films are stacked and fired at a temperature of 1100 ° C. to 1300 ° C. for about 2 hours, for example. Thereby, the dielectric body 10 as a sintered body is obtained (see FIG. 5).

Subsequently, a conductive paste mainly composed of Cu, and connects the lead portion 14a ₁ of the lead portion 12a ₁ and the internal electrodes 14A ₁ of the internal electrodes 12A _1, deriving section 12a ₂ and the internal electrode 14A of the internal electrode 12A ₂ connect ₂ of the derivation portion 14a _2, so as to connect the outlet portion 14a ₃ of the lead portion 12a ₃ and the internal electrodes 14A ₃ of the internal electrodes 12A _3, the side surface adjacent to the main surface 10a and the main surface 10a 10c, Apply to 10d respectively. Further, a paste mainly composed of Cu, and connects the lead portion 14b ₁ of the lead portion 12b ₁ and the internal electrode 14B ₁ of the internal electrodes 12B _1, the internal electrodes 12B ₂ for deriving portion 12b ₂ and the internal electrode 14B ₂ connects the outlet portion 14b _2, so as to connect the outlet portion 14b ₃ of the lead portion 12b ₃ and the internal electrode 14B ₃ of the internal electrode 12B _3, side 10c adjacent to the main surface 10b and the main surface 10b, and 10d Apply each. Then, these conductive pastes are baked, for example, at a temperature of about 600 ° C. to 800 ° C. for about 20 minutes to 40 minutes, thereby forming the baked electrode layers 18A _{1 to} 18A ₃ and 18B _{1 to} 18B ₃ (FIG. 6). reference). The thickness of the baking electrode layers 18A _{1 to} 18A ₃ and 18B _{1 to} 18B ₃ can be set to, for example, about ₃₀ μm to 40 μm.

Subsequently, as shown in FIG. 7, a resin electrode paste in which metal particles are contained as a conductive material in a thermosetting resin is applied so as to cover a part of the surfaces of the baked electrode layers 18 </ b> A _{1 to} 18 </ b> A _3. For example, by drying the resin electrode paste at a temperature of about 80 ° C. to 160 ° C. for about 10 minutes to 30 minutes, the conductive coating films 211A _{1 to} 211A ₃ are formed. The thickness of the conductive coating films 211A _{1 to} 211A ₃ can be set to, for example, about 10 μm to 100 μm.

Specifically, Shirubeden'nurimaku 211A _1, the portion that flank 10c of the sintered electrode layers 18A _1, and, the side surface 10c of the sintered electrode layers 18A _1, from substantially the center of the principal surface 10a in the opposing direction of 10d The portion near the side surface 10c is covered. Shirubeden'nurimaku 211A _2, the portion located on the side surface 10c of the sintered electrode layers 18A _2, and the portion from substantially the center of the side surface 10c side of the main surface 10a side 10c of the sintered electrode layers 18A _2, in the opposing direction of 10d Covering. Shirubeden'nurimaku 211A ₃ are portions that flank 10c of the sintered electrode layers 18A _3, and, the side surface 10c, the portion from substantially the center of the side surface 10c side of the main surface 10a in the opposing direction of the 10d of the sintered electrode layers 18A ₃ Covering. These conductive coating 211A ₁ ~211A ₃ is a side 10c, a portion positioned substantially at the center of the principal surface 10a in the opposing direction of 10d (tapered) is becomes thinner it becomes narrower with increasing distance from the side surface 10c Yes.

Subsequently, as shown in FIG. 8, a resin electrode paste in which metal particles are contained as a conductive material in a thermosetting resin is applied so as to cover a part of the surfaces of the baked electrode layers 18 </ b> A _{1 to} 18 </ b> A _3. For example, by drying the resin electrode paste at a temperature of about 80 ° C. to 160 ° C. for about 10 to 30 minutes, the conductive coating films 212A _{1 to} 212A ₃ are formed. The thicknesses of the conductive coating films 212A _{1 to} 212A ₃ can be set to about 10 μm to 100 μm, for example.

Specifically, Shirubeden'nurimaku 212A _1, the portion that flank 10d of the sintered electrode layers 18A _1, and, the side surface 10c of the sintered electrode layers 18A _1, from substantially the center of the principal surface 10a in the opposing direction of 10d It covers the portion closer to the side surface 10d. Shirubeden'nurimaku 212A _2, the portion located on the side face 10d of the sintered electrode layers 18A _2, and the portion from substantially the center of the side surface 10d side of the main surface 10a side 10c of the sintered electrode layers 18A _2, in the opposing direction of 10d Covering. Shirubeden'nurimaku 212A ₃ are portions that flank 10d of the sintered electrode layers 18A _3, and, the side surface 10c, the portion from substantially the center of the side surface 10d side of the principal surface 10a in the opposing direction of the 10d of the sintered electrode layers 18A ₃ Covering. These conductive coating 212A ₁ to 212 a ₃ is a side 10c, a portion positioned substantially at the center of the principal surface 10a in the opposing direction of 10d (tapered) is becomes thinner it becomes narrower with increasing distance from the side surface 10d Yes.

Here, it is connected to the tapered and the conductive coating 212A ₁ of taper of Shirubeden'nurimaku 211A _1, and connected to the tapered and the conductive coating 212A ₂ of taper of Shirubeden'nurimaku 211A _2, conductive It is connected to the tapered and the conductive coating 212A ₃ of taper of the coating film 211A _3. Therefore, composed narrow portion 203A ₁ is in the portion where the tapered of tapered and the conductive coating 212A ₁ of Shirubeden'nurimaku 211A ₁ are connected, the Shirubeden'nurimaku 211A ₂ tapered in a conductive coating 212A ₂ previously width in the portion where detail and are connected narrow section 203A ₂ is configured, constructed the narrow portion 203A ₃ in tapered and tapered and the portion are connected conductive coating 212A ₃ of Shirubeden'nurimaku 211A ₃ The

A conductive coating film is also formed on the main surface 10b side by the same method as these conductive coating films 211A ₁ , 212A ₁ , 211A ₂ , 212A ₂ , 211A ₃ , 212A ₃ . Then, the conductive film formed on each of the main surfaces 10a and 10b is heated and cured at a temperature of about 180 ° C. to 220 ° C. for about 30 minutes to 120 minutes, for example, so that the resin electrode layer is formed on the main surface 10a side. Are formed, and three resin electrode layers are formed on the main surface 10b side.

  Here, in 1st Embodiment, Ag which is a noble metal is used as a material of the metal particle contained in the resin electrode paste. Although it does not restrict | limit especially as a thermosetting resin contained in a resin electrode paste, For example, a phenol resin, an acrylic resin, a silicon resin, an epoxy resin, a polyimide etc. can be used. In addition, the temperature at the time of thermosetting is appropriately adjusted according to the thermosetting resin to be used.

  The content of all metal particles in the resin electrode paste is preferably 60% by mass to 95% by mass based on the total solid content of the resin electrode paste. When the content is less than 60% by mass, the conductivity inside the resin electrode layer tends to be insufficient as compared with the case where the content is in the above range. When the content exceeds 95% by mass, the amount of the thermosetting resin is insufficient as compared with the case where the content is within the above range, and thus the adhesion between the baked electrode layer and the resin electrode layer tends to decrease. It is in.

  The resin electrode paste further contains a solvent as necessary. As the solvent, any known solvent can be used without particular limitation as long as it can dissolve or disperse the thermosetting resin. Specific examples of the solvent include methyl carbitol, ethyl carbitol, butyl carbitol, butyl carbitol acetate, cellosolve, butyl cellosolve, butyl cellosolve acetate, and terpineol.

Subsequently, by plating the surface of each resin electrode layer with Ni, first plating layers containing Ni as a main component (including the first plating layers 22A ₁ and 22B ₁ ) are formed. The thickness of each plating layer can be, for example, about 1 μm.

  When the first plating layer is plated on the surface of the resin electrode layer, the surface of the resin electrode layer is preferably barrel-polished in advance. By barrel polishing, the metal particles exposed on the surface of the resin electrode layer are extended to increase the area of the metal particles exposed on the surface of the resin electrode layer, and the bonding between the resin electrode layer and the first plating layer is performed. This is because the strength increases.

Subsequently, by plating the surface of each first plating layer with Sn or Sn alloy, second plating layers containing Sn or Sn alloy as a main component (including second plating layers 24A ₁ and 24B ₁ ), respectively. Form. The thickness of each plating layer can be about 1 μm to 10 μm, for example.

[1.3] Operation In the first embodiment as described above, the external electrode 16A ₁ covers the entire surface of the baked electrode layer 18A ₁ and is formed over the main surface 10a and the side surfaces 10c and 10d. has a _1, a recessed portion is formed in the narrow portion 203A _1. That is, the width in the narrow portion 203A _1, provided with a step which is configured by the surface height of the resin electrode layer 20A ₁ in a direction perpendicular to the main surface 10a is changed in the extending direction of the resin electrode layer 20A ₁ Yes. Therefore, up to when mounting the surface mount capacitor array 1 to the circuit board side 10c or side 10d as the mounting surface, even if solder has creeps up the surface of the external electrodes 16A _1, creeping of the solder by the step (recess) Will be suppressed. As a result, the solder can be prevented from creeping up an excess of the surface of the external electrodes 16A _1, it is possible to reduce the possibility of cracks occurring in the dielectric body 10.

In the first embodiment, the resin electrode layer 20A ₁ is includes a wide portion 201A _1, 202A ₁ and the narrow portion 203A _1, the wide portion 201A _1, the narrow portion 203A ₁ and the wide portion 202A ₁ , the extending direction of the resin electrode layer 20A ₁ are arranged in this order in the (side 10c, the opposing direction of 10d). That is, the width of the resin electrode layer 20A ₁ (external electrode 16A ₁ ) changes in the extending direction. Therefore, when implementing surface-mount capacitor array 1 to the circuit board side 10c or side 10d as the mounting surface, even if solder has creeps up the surface of the external electrodes 16A _1, with respect to the wide portion 201A _1, 202A ₁ the width the width of the narrow portion 203A ₁ Te is narrow (narrow portion 203A ₁ is constricted in the resin electrode layer 20A _1), so that the creeping of the solder is suppressed by the narrow portion 203A _1. As a result, the solder can be more prevented from creeping up an excess of the surface of the external electrodes 16A _1, it is possible to further reduce the risk of cracks occurring in the dielectric body 10.

In the first embodiment, the resin electrode layer 20A ₁ is formed on the baked electrode layer 18A ₁ so as to cover the entire surface of the sintered electrode layers 18A _1. Here, the resin electrode layer 20A ₁ is easily deformed as compared with the sintered electrode layer 18A _1. Therefore, after mounting the surface-mounted capacitor array 1 on the circuit board, external force is applied to the circuit board, or the surface-mounted capacitor array 1 itself expands and contracts due to heat generated when the surface-mounted capacitor array 1 operates. even or, and is capable of absorbing stress applied to the dielectric body 10 with the resin electrode layer 20A _1.

In the first embodiment, the resin electrode layer 20A ₁ is, by being formed on the baked electrode layer 18A ₁ so as to cover the entire surface of the sintered electrode layers 18A _1, first plating layer 22A ₁ is baked not formed on the electrode layer 18A _1. That is, in forming the first plating layer 22A _1, the entire surface of the sintered electrode layers 18A ₁ is covered by the resin electrode layer 20A _1, inside the dielectric body 10 through the baked electrode layer 18A _1, etc. The plating solution is difficult to penetrate. As a result, the deterioration of the characteristics of the surface mount capacitor array 1 due to the penetration of the plating solution into the dielectric body 10 can be sufficiently suppressed.

In the first embodiment, the narrow portion 203A _1, are positioned at substantially the center of the main surface 10a of the side surface 10c, 10d opposite direction. Therefore, when implementing surface-mount capacitor array 1 to the circuit board, even either side 10c or side 10d as the mounting surface, by equivalent is wicking effect of preventing the solder narrow portion 203A ₁ and the step (recess) Will be demonstrated.

[2] Second Embodiment [2.1] Configuration of Surface Mount Electronic Component Array Next, regarding the configuration of the surface mount electronic component array according to the second embodiment, the surface mount electronic component according to the first embodiment will be described. Description will be made with reference to FIGS. 9 to 10, focusing on differences from the configuration of the array. In the following description, the surface-mounted capacitor array 2 is described as an example of the surface-mounted electronic component array.

Narrow portion 203A _1, especially as shown in FIG. 10, the side surface 10c, substantially at the center of the major surface 10a in the opposing direction of the 10d, has a recess. That is, the surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is changed in the extending direction of the resin electrode layer 20A ₁ (side 10c, 10d opposite direction).

More specifically, the narrow portion 203A _1, provided is a step of surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is higher than the side closer to the side surface 10c in the side away from the side surface 10c together they are, and step is provided that the surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is higher than the side closer to the side surface 10d at the side away from the side 10d. These steps are the narrow portion 203A _1, becomes thicker in side away from the side surface 10c, it becomes thicker in the side away from the side surface 10d, by a thin between these thick portions, it is configured ing.

Portion of the side surface 10c side of the concave portion of the narrow portion 203A _1, and the wide portion 201A _1, the portion of the side surface 10d side of the recess out of the narrow portion 203A _1, and than the thickness of the wide portion 202A ₁ It is thick. That is, the resin electrode layer 20A ₁ at the side surface 10c side of the concave portion of the narrow portion 203A ₁ as a whole is larger than the thickness of the resin electrode layer 20A ₁ at the side surface 10d side of the recess of the narrow portion 203A ₁ Yes.

Since the configuration of the external electrodes 16A ₂ , 16A ₃ , 16B _{1 to} 16B _{3 is the same as} the configuration of the external electrode 16A ₁ , the description thereof is omitted.

[2.2] Method for Manufacturing Surface Mount Electronic Component Array Subsequently, the method for manufacturing the surface mount electronic component array (surface mount capacitor array 2) according to the second embodiment will be described. A description will be given with reference to FIGS. 11 to 12 focusing on differences from the manufacturing method of the mold electronic component array. In the second embodiment, since the process to form a baked electrode layer _{18A 1 ~18A 3, 18B 1 ~18B} 3 is the same as the first embodiment, description thereof will be omitted.

The baked electrode layer _{18A 1 ~18A 3, 18B 1 ~18B} 3 after the formation step, as shown in FIG. 11, the metal particles in the thermosetting resin is a resin electrode paste which is contained as a conductive material, baking a part of the surface of the electrode layer _18A 1 _{~18A 3} was coated so as to cover each of the resin electrode paste by drying by heating to form a Shirubeden'nurimaku 211A ₁ ~211A _3. The thickness of the conductive coating films 211A _{1 to} 211A ₃ can be set to, for example, about 20 μm to 100 μm.

Specifically, Shirubeden'nurimaku 211A _1, the portion that flank 10c of the sintered electrode layers 18A _1, and, the side surface 10c of the sintered electrode layers 18A _1, from substantially the center of the principal surface 10a in the opposing direction of 10d The portion near the side surface 10c is covered. Shirubeden'nurimaku 211A _2, the portion located on the side surface 10c of the sintered electrode layers 18A _2, and the portion from substantially the center of the side surface 10c side of the main surface 10a side 10c of the sintered electrode layers 18A _2, in the opposing direction of 10d Covering. Shirubeden'nurimaku 211A ₃ are portions that flank 10c of the sintered electrode layers 18A _3, and, the side surface 10c, the portion from substantially the center of the side surface 10c side of the main surface 10a in the opposing direction of the 10d of the sintered electrode layers 18A ₃ Covering.

Subsequently, as shown in FIG. 12, a resin electrode paste containing metal particles as a conductive material in a thermosetting resin is applied so as to cover a part of the surface of each of the baking electrode layers 18 </ b> A _{1 to} 18 </ b> A _3. and, the resin electrode paste by drying by heating to form a Shirubeden'nurimaku 212A ₁ to 212 a _3. The thickness of the conductive coating films 212A _{1 to} 212A ₃ can be set to, for example, about 10 μm to 80 μm.

Specifically, Shirubeden'nurimaku 212A _1, the portion that flank 10d of the sintered electrode layers 18A _1, and, the side surface 10c of the sintered electrode layers 18A _1, from substantially the center of the principal surface 10a in the opposing direction of 10d It covers the portion closer to the side surface 10d. Shirubeden'nurimaku 212A _2, the portion located on the side face 10d of the sintered electrode layers 18A _2, and the portion from substantially the center of the side surface 10d side of the main surface 10a side 10c of the sintered electrode layers 18A _2, in the opposing direction of 10d Covering. Shirubeden'nurimaku 212A ₃ are portions that flank 10d of the sintered electrode layers 18A _3, and, the side surface 10c, the portion from substantially the center of the side surface 10d side of the principal surface 10a in the opposing direction of the 10d of the sintered electrode layers 18A ₃ Covering.

[2.3] Operation In the surface mount electronic component array (surface mount capacitor array 2) according to the second embodiment as described above, the surface mount electronic component array (surface mount type) according to the first embodiment. The same effect as the capacitor array 1) is obtained.

In the second embodiment, the narrow portion 203A _1, becomes thicker in side away from the side surface 10c, it becomes thicker in the side away from the side 10d, the thin-walled between these thick portions Accordingly, the step of the narrow portion 203A ₁ is constructed. Then, the resin electrode layer 20A ₁ at the side surface 10c side of the concave portion of the narrow portion 203A ₁ is as a whole is larger than the thickness of the resin electrode layer 20A ₁ at the side surface 10d side of the recess of the narrow portion 203A ₁ Yes. In this way, so that the steep step is configured at the boundary where the thickness of the portion located on the main surface 10a side of the resin electrode layer 20A ₁ is changed. As a result, it is possible to further prevent the solder rises excessively crawl surfaces of the external electrodes 16A _1.

  Here, in order to surely exhibit such an effect of preventing the solder from creeping up in the surface-mount type electronic component array according to the second embodiment, the surface-mount type according to the second embodiment using the side surface 10d as a mounting surface. It is necessary to mount the electronic component array on the circuit board. For this reason, the surface-mount type electronic component array according to the second embodiment has a directionality in mounting. As a result, when the surface-mount type electronic component array requires identification of directionality, for example, an LC filter array, it is useful because it is not necessary to add a marker (marker).

[3] Third Embodiment [3.1] Configuration of Surface Mount Type Electronic Component Array Next, regarding the configuration of the surface mount type electronic component array according to the third embodiment, the surface mount type electronic component according to the first embodiment. Description will be made with reference to FIGS. 13 to 15 focusing on differences from the configuration of the array. In the following description, the surface mount type capacitor array 5 is described as an example of the surface mount type electronic component array.

Narrow portion 203A ₁ is particularly, as shown in FIGS. 13 and 14, is narrower than the width of the width of the wide portion 201A _1, 202A _1. That is, the resin electrode layer 20A ₁ is in a state of constricted at the narrow portion 203A _1.

Narrow portion 203A ₁ is thinner than the thickness of the wide portion 201A _1, 202A _1. Therefore, the resin electrode layer 20A ₁ a side 10e, when viewed from the opposing direction of 10f, the width is recessed than the narrow portion 203A ₁ is wide portions 201A _1, 202A _1, the wide portion 201A _1, 202A ₁ and narrow part 203A ₁ is formed into a recess in the resin electrode layer 20A ₁ together. That is, the surface height of the resin electrode layer 20A ₁ in a direction perpendicular to the main surface 10a is changed in the extending direction of the resin electrode layer 20A ₁ (side 10c, 10d opposite direction).

More specifically, the boundary between the wide portion 202A ₁ and the narrow portion 203A _1, the surface height of the resin electrode layer 20A ₁ in a direction perpendicular to the main surface 10a is from the side closer to the side surface 10c in the side away from the side surface 10c is provided with a level difference is also increased, the boundary between the wide portion 201A ₁ and the narrow portion 203A _1, the surface height of the resin electrode layer 20A ₁ in a direction perpendicular to the main surface 10a is farther from the side surface 10d On the side, a step is provided which is higher than the side close to the side surface 10d. That is, these steps are provided in the vicinity of the narrow portion 203A _1. Further, these steps are caused by the fact that the narrow portion 203A ₁ is thinner than the wide portions 201A ₁ and 202A ₁ like the concave portion.

Since the configuration of the external electrodes 16A ₂ , 16A ₃ , 16B _{1 to} 16B _{3 is the same as} the configuration of the external electrode 16A ₁ , the description thereof is omitted.

[3.2] Manufacturing Method of Surface Mount Electronic Component Array Subsequently, regarding the manufacturing method of the surface mount electronic component array (surface mount capacitor array 3) according to the third embodiment, the surface mounting according to the first embodiment. Description will be made with reference to FIGS. 16 to 18 focusing on differences from the manufacturing method of the mold electronic component array. In the third embodiment, since the process to form a baked electrode layer _{18A 1 ~18A 3, 18B 1 ~18B} 3 is the same as the first embodiment, description thereof will be omitted.

The baked electrode layer _{18A 1 ~18A 3, 18B 1 ~18B} 3 after the formation step, as shown in FIG. 16, the metal particles in the thermosetting resin is a resin electrode paste which is contained as a conductive material, baking the entire surface of the electrode layer _18A 1 _{~18A 3} was applied so as to cover each of the resin electrode paste by drying by heating to form a Shirubeden'nurimaku 211A ₁ ~211A _3. The thicknesses of the conductive coating films 211A _{1 to} 211A ₃ can be set to, for example, about 10 μm to 50 μm.

Subsequently, as shown in FIG. 17, a resin electrode paste containing metal particles as a conductive material in a thermosetting resin is applied so as to cover a part of the surfaces of the conductive coating films 211 </ b> A _{1 to} 211 </ b> A _3. and, the resin electrode paste by drying by heating to form a Shirubeden'nurimaku 212A ₁ to 212 a _3. The thickness of the conductive coating films 212A _{1 to} 212A ₃ can be set to, for example, about 10 μm to 50 μm.

Specifically, Shirubeden'nurimaku 212A _1, the portion that flank 10c of Shirubeden'nurimaku 211A _1, and the portion of the side surface 10c toward a portion positioned on the main surface 10a of Shirubeden'nurimaku 211A ₁ Covering. Shirubeden'nurimaku 212A ₂ covers a portion located on the side surface 10c of the Shirubeden'nurimaku 211A _2, and the a portion located on the main surface 10a portion of the side surface 10c closer of Shirubeden'nurimaku 211A _2. Shirubeden'nurimaku 212A ₃ covers a portion located on the side surface 10c of the Shirubeden'nurimaku 211A _3, and the a portion located on the main surface 10a portion of the side surface 10c closer of Shirubeden'nurimaku 211A _3.

Subsequently, as shown in FIG. 18, a resin electrode paste containing metal particles as a conductive material in a thermosetting resin is applied so as to cover a part of the surfaces of the conductive coating films 211 </ b> A _{1 to} 211 </ b> A _3. Then, the conductive film 213A _{1 to} 213A ₃ is formed by drying the resin electrode paste by heating. The thickness of the conductive coating films 213A _{1 to} 213A ₃ can be set to about 10 μm to 50 μm, for example.

Specifically, Shirubeden'nurimaku 213A _1, the portion that flank 10d of Shirubeden'nurimaku 211A _1, and, the portion of the side face 10d closer to a portion located on the main surface 10a of Shirubeden'nurimaku 211A ₁ Covering. Shirubeden'nurimaku 213A ₂ covers a portion located on the side face 10d of Shirubeden'nurimaku 211A _2, and the a portion located on the main surface 10a portion of the side surface 10d closer of Shirubeden'nurimaku 211A _2. Shirubeden'nurimaku 213A ₃ covers a portion located on the side face 10d of the Shirubeden'nurimaku 211A _3, and the a portion located on the main surface 10a portion of the side surface 10d closer of Shirubeden'nurimaku 211A _3.

[3.3] Operation In the surface mount electronic component array (surface mount capacitor array 3) according to the third embodiment as described above, the surface mount electronic component array (surface mount type) according to the first embodiment. The same effect as the capacitor array 1) is obtained.

[4] Fourth Embodiment [4.1] Configuration of Surface Mount Electronic Component Array Next, regarding the configuration of the surface mount electronic component array according to the fourth embodiment, the surface mount electronic component according to the first embodiment. Description will be made with reference to FIGS. 19 to 20 focusing on differences from the configuration of the array. In the following description, the surface-mounted capacitor array 4 is described as an example of the surface-mounted electronic component array.

Narrow portion 203A _1, as shown in FIGS. 19 and 20, the side surface 10c, substantially at the center of the major surface 10a in the opposing direction of the 10d, and has a convex portion. That is, the surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is changed in the extending direction of the resin electrode layer 20A ₁ (side 10c, 10d opposite direction).

More specifically, the narrow portion 203A _1, the width surface height of the narrow portion 203A ₁ in a direction perpendicular to the main surface 10a is directed substantially in the center of the principal surface 10a from the side surface 10c side 10c, in the opposing direction of 10d As the height increases, the height decreases from the approximate center of the main surface 10a in the opposing direction of the side surfaces 10c and 10d toward the side surface 10d, thereby providing a step. These steps are formed by being thick at the approximate center of the main surface 10a in the opposing direction of the side surfaces 10c and 10d and by being thin at both sides of the thick portion. In the fourth embodiment are substantially the same and the wide portion 201A ₁ thickness and the wide portion 202A ₁ thickness.

[4.2] Manufacturing Method of Surface Mount Electronic Component Array Subsequently, regarding the manufacturing method of the surface mount electronic component array (surface mount capacitor array 3) according to the fourth embodiment, the surface mounting according to the first embodiment. A description will be given with reference to FIG. 21 focusing on differences from the manufacturing method of the mold electronic component array. In the fourth embodiment, since the process to form a Shirubeden'nurimaku _{211A 1 ~211A 3, 212A 1 ~212A} 3 is the same as the first embodiment, description thereof will be omitted.

In Shirubeden'nurimaku _{211A 1 ~211A 3, 212A 1 ~212A} 3 after the formation step, as shown in FIG. 21, the metal particles in the thermosetting resin is a resin electrode paste which is contained as a conductive material, conductive The coating film 211A _{1 and} the coating film 212A ₁ are coated (dropped) with a dispenser (quantitative discharge device) or the like so as to cover the detail of the coating film 211A ₁ , and the resin electrode paste is dried by heating. to form a 213A _1. The same applies to the conductive coating films 213A ₂ and 213A ₃ . The thickness of the conductive coating films 213A _{1 to} 213A ₃ can be set to, for example, about 50 μm to 150 μm.

[4.3] Operation In the surface mount electronic component array (surface mount capacitor array 4) according to the fourth embodiment as described above, the surface mount electronic component array (surface mount type) according to the first embodiment. The same effect as the capacitor array 1) is obtained.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in the first to fourth embodiments, the present invention is applied to the surface-mounted capacitor arrays 1 to 3, but is not limited to this, and various surface-mounted electronic component arrays (for example, surface-mounted varistor arrays, surface-mounted Type filter array).

In the first to fourth embodiments, the three external electrodes 16A _{1 to} 16A ₃ are arranged along the opposing direction of the side surfaces 10e and 10f on the main surface 10a side, and the side surfaces 10e and 10f are on the main surface 10b side. The surface mount type capacitor arrays 1 to 3 in which the _three external electrodes 16B _{1 to} 16B ₃ are arranged along the opposing direction of each of the external electrodes have been described, but two or more external electrodes are arranged on the main surfaces 10a and 10b side. The present invention can be applied to any surface-mounted electronic component array. Therefore, the number of external electrodes arranged on the main surface 10a side may be different from the number of external electrodes arranged on the main surface 10b side.

In the first to fourth embodiments, the baking electrode layers 18A _{1 to} 18A ₃ are formed so as to cover the main surface 10a of the dielectric element body 10 and wrap around the side surfaces 10c and 10d adjacent to the main surface 10a. The baking electrode layers 18B _{1 to} 18B ₃ cover the main surface 10b of the dielectric body 10 and are formed so as to wrap around the side surfaces 10c and 10d adjacent to the main surface 10b. _{1 to} 18A ₃ , 18B _{1 to} 18B ₃ are physically and electrically connected to the corresponding internal electrodes 12A _{1 to} 12A ₃ , 12B _{1 to} 12B ₃ , 14A _{1 to} 14A ₃ , and 14B _{1 to} 14B ₃ It is not limited to this. Specifically, the baked electrode layers 18A _{1 to} 18A ₃ may be formed only on the main surface 10a, or may be formed so as to wrap around the main surface 10a and the side surface 10c adjacent to the main surface 10a. The main surface 10a and the side surface 10d adjacent to the main surface 10a may be formed. The same applies to the baked electrode layer _18B 1 _{~18B 3.}

In the first to fourth embodiments, the external electrodes 16A _{1 to} 16A ₃ are formed so as to cover the main surface 10a of the dielectric body 10 and wrap around the side surfaces 10c and 10d adjacent to the main surface 10a. The external electrodes 16B _{1 to} 16B ₃ are formed so as to cover the main surface 10b of the dielectric body 10 and wrap around the side surfaces 10c and 10d adjacent to the main surface 10b. However, the present invention is not limited to this. Specifically, the external electrodes 16A _{1 to} 16A ₃ may be formed so as to wrap around the main surface 10a and the side surface 10c adjacent to the main surface 10a, and on the main surface 10a and the side surface 10d adjacent to the main surface 10a. You may form so that it may wrap around. The same applies to the external electrodes _16B 1 _{~16B 3.} In the first to third embodiments, for example, when the external electrodes 16A _{1 to} 16A ₃ are formed so as to go around the main surface 10a and the side surface 10d adjacent to the main surface 10a, the concave portion of the narrow portion is formed. As a whole, the resin electrode layer on the side surface 10c side is made thicker than the thickness of the resin electrode layer on the side surface 10d side than the concave portion of the narrow portion.

  Moreover, in 1st-4th embodiment, although the narrow part was located in the approximate center of main surface 10a, 10b in the opposing direction of side surface 10c, 10d, it does not need to be located in the approximate center. In addition, since the level | step difference is integrally formed in the wide part and the narrow part, when the narrow part is not located in the approximate center of main surface 10a, 10b in the opposing direction of side surface 10c, 10d, Naturally, the step is not positioned at the approximate center of the main surfaces 10a and 10b in the opposing direction of the side surfaces 10c and 10d.

  In addition, the resin electrode layer has a width that changes in the extending direction (opposite direction of the side surfaces 10c and 10d) when viewed from the main surfaces 10a and 10b, and in the vicinity of the narrow portion. The height of the surface in the direction orthogonal to the main surfaces 10a and 10b may be provided with a step formed by changing in the extending direction (opposite direction of the side surfaces 10c and 10d). There is no particular limitation.

In the first embodiment, the conductive coating films 211A _{1 to} 211A ₃ are formed by applying and drying a resin electrode paste, and then the conductive coating films 212A _{1 to} 212A are applied and dried. ₃ was formed, but the formation method of the conductive coating film is not limited to this. For example, the portion located on the side surface 10c of the sintered electrode layers _18A 1 _{~18A 3,} and a side 10c of the sintered electrode layers _18A 1 _{~18A 3,} 10d from substantially the center of the principal surface 10a in the opposing direction of the side surface 10c side of the after applying the resin electrode paste so as to cover the portion respectively, the portion located on the side face 10d of the sintered electrode layers _18A 1 _{~18A 3,} and a side 10c, 10d opposing direction of the sintered electrode layers _18A 1 _{~18A 3} each coating a resin electrode paste so as to cover the portion from substantially the center of the side surface 10d side of the major surface 10a in, followed by drying by heating these resins electrode paste simultaneously, Shirubeden'nurimaku 211A ₁ ~211A ₃ and the conductive it may be form a coating film 212A ₁ to 212 a ₃ at the same timing. The same applies to the second to fourth embodiments.

In the third embodiment, the conductive coating film 211A ₁ , the conductive coating film 212A ₁ and the conductive coating film 213A ₁ are formed in this order, but the conductive coating film 211A ₁ , the conductive coating film 212A ₁ and the conductive coating film 213A ₁ are formed. The order of formation is not limited to this, and any order may be selected from the six possible orders.

FIG. 1 is a perspective view showing a surface-mount electronic component array according to the first embodiment. FIG. 2 is a side view showing the surface mount electronic component array according to the first embodiment. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is an exploded perspective view of the element body constituting the surface mount electronic component array according to the first embodiment. FIG. 5 is a diagram for explaining a manufacturing process of the surface-mount electronic component array according to the first embodiment. FIG. 6 is a diagram showing a step subsequent to FIG. FIG. 7 is a view showing a step subsequent to FIG. FIG. 8 is a diagram showing a step subsequent to FIG. FIG. 9 is a perspective view showing a surface-mounted electronic component array according to the second embodiment. 10 is a cross-sectional view taken along line XX of FIG. FIG. 11 is a diagram for explaining a manufacturing process of the surface mount electronic component array according to the second embodiment. FIG. 12 is a diagram showing a step subsequent to FIG. FIG. 13 is a perspective view showing a surface mount electronic component array according to the third embodiment. FIG. 14 is a side view showing a surface mount electronic component array according to the third embodiment. 15 is a cross-sectional view taken along line XV-XV in FIG. FIG. 16 is a diagram for explaining a manufacturing process of the surface mount electronic component array according to the third embodiment. FIG. 17 is a diagram showing a step subsequent to FIG. FIG. 18 is a diagram showing a step subsequent to FIG. FIG. 19 is a perspective view showing a surface mount electronic component array according to the fourth embodiment. FIG. 20 is a cross-sectional view showing a surface mount electronic component array according to the fourth embodiment. FIG. 21 is a diagram for explaining a manufacturing process of the surface mount electronic component array according to the fourth embodiment.

Explanation of symbols

1-4 ... surface mount capacitor array, 10 ... dielectric element, 10a, 10b ... main surface, 10C～10f ... _{aspect, 16A 1 ~16A 3, 16B 1} ~16B 3 ... outer _electrode, 18A 1 _{~18A 3} , 18B _{1 to} 18B ₃ ... baked electrode layer, 20A ₁ , 20B ₁ ... resin electrode layer, 201A ₁ , 202A ₁ , 201B ₁ , 202B ₁ ... wide part, 203A ₁ , 203B ₁ ... narrow part, 211A _{1 to} 211A ₃ , 212A _{1 to} 212A ₃ , 213A _{1 to} 213A ₃ ... Conductive coating, 22A ₁ , 22B ₁ ... First plating layer, 24A ₁ , 24B ₁ .

Claims (18)

A surface mount electronic component array comprising an element body and a first external electrode disposed on the element body,
The element body has a first main surface and a side surface adjacent to the first main surface;
The first external electrode is
A first baking electrode layer containing a metal as a main component and formed on the first main surface;
A first resin electrode layer containing a conductive material and covering the entire surface of the first baked electrode layer and formed over the first main surface and the side surface;
A first plating layer containing a metal as a main component and formed to cover the first resin electrode layer;
The portion of the first resin electrode layer located on the first main surface side includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion,
The 1-1 wide portion, the first narrow portion, and the 1-2 wide portion are arranged in this order in the extending direction of the first resin electrode layer,
In the vicinity of the first narrow portion of the first resin electrode layer, a surface height in a direction perpendicular to the first main surface of a portion of the first resin electrode layer located on the first main surface side is provided. A surface-mount type electronic component array, wherein a first step is formed on the side farther from the side than the side closer to the side.   In the vicinity of the first narrow portion, a portion of the first resin electrode layer located on the first main surface side is thick on the side far from the side surface and thin on the side near the side surface. The surface mount type electronic component array according to claim 1, wherein the first step is configured. A second external electrode disposed on the element body;
The element body further includes a second main surface adjacent to the side surface,
The second external electrode is
A second baking electrode layer containing a metal as a main component and formed on the second main surface;
A second resin electrode layer containing a conductive material and covering the entire surface of the second baked electrode layer and formed over the second main surface and the side surface;
Having a metal as a main component and a second plating layer formed to cover the second resin electrode layer;
The portion of the second resin electrode layer located on the second main surface side includes a 2-1 wide portion, a 2-2 wide portion, and a second narrow portion,
The 2-1 wide part, the second narrow part, and the 2-2 wide part are arranged in this order in the extending direction of the second resin electrode layer,
In the vicinity of the second narrow portion, the surface height in the direction perpendicular to the second main surface of the portion of the second resin electrode layer located on the second main surface side is on the side far from the side surface. The surface-mount type electronic component array according to claim 1, wherein a second step formed by being higher than a side close to the side surface is provided.   In the vicinity of the second narrow portion, the portion of the second resin electrode layer located on the second main surface side is thin on the side close to the side surface and thick on the side far from the side surface. The surface-mount type electronic component array according to claim 3, wherein the second step is configured. A surface mount electronic component array comprising an element body and a first external electrode disposed on the element body,
The element body includes a first main surface and a pair of first side surfaces and second side surfaces that are adjacent to the first main surface and face each other.
The first external electrode is
A first baking electrode layer containing a metal as a main component and formed on the first main surface;
A first resin electrode layer containing a conductive material and covering the entire surface of the first baked electrode layer and formed over the first side surface, the first main surface and the second side surface;
A first plating layer containing a metal as a main component and formed to cover the first resin electrode layer;
The portion of the first resin electrode layer located on the first main surface side includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion,
The 1-1 wide portion, the first narrow portion, and the 1-2 wide portion are arranged in this order in the extending direction of the first resin electrode layer,
In the vicinity of the first narrow portion, the surface height of the first resin electrode layer in the direction orthogonal to the first main surface is changed in the extending direction of the first resin electrode layer. A surface-mount type electronic component array, wherein a first step is provided.   In the vicinity of the first narrow portion, the thickness of the portion of the first resin electrode layer located on the first main surface side changes in the extending direction of the first resin electrode layer, thereby 6. The surface mount electronic component array according to claim 5, wherein one step is formed.   7. The surface according to claim 5, wherein the first narrow portion is located substantially at the center of the first main surface in a direction in which the first side surface and the second side surface are opposed to each other. Mounted electronic component array. A second external electrode disposed on the element body;
The element body further includes a second main surface that is adjacent to the first side surface and the second side surface and faces the first main surface,
The second external electrode is
A second baking electrode layer containing a metal as a main component and formed on the second main surface;
A second resin electrode layer containing a conductive material and covering the entire surface of the second baking electrode layer and formed over the first side surface, the second main surface and the second side surface;
Having a metal as a main component and a second plating layer formed to cover the second resin electrode layer;
The portion of the second resin electrode layer located on the second main surface side includes a 2-1 wide portion, a 2-2 wide portion, and a second narrow portion,
The 2-1 wide part, the second narrow part, and the 2-2 wide part are arranged in this order in the extending direction of the second resin electrode layer,
In the vicinity of the second narrow portion, the surface height of the second resin electrode layer in the direction orthogonal to the second main surface is changed in the extending direction of the second resin electrode layer. The surface-mount type electronic component array according to any one of claims 5 to 7, wherein a second step is provided.   In the vicinity of the second narrow portion, the thickness of the portion of the second resin electrode layer located on the second main surface side changes in the extending direction of the second resin electrode layer, thereby The surface-mount type electronic component array according to claim 8, wherein two steps are formed.   10. The surface according to claim 8, wherein the second narrow portion is located substantially at the center of the second main surface in a direction in which the first side surface and the second side surface are opposed to each other. Mounted electronic component array. An element body preparing step of preparing an element body having a first main surface and a side surface adjacent to the first main surface;
A first external electrode forming step of forming a first external electrode on the element body,
The first external electrode forming step includes
A first step 1-1 of forming a first baked electrode layer by applying and baking a conductive paste containing a metal as a main component on the first main surface;
A conductive resin paste containing a conductive material and a thermosetting resin material covers the entire surface of the first baked electrode layer, is applied over the first main surface and the side surface, and is cured by heating to form a first resin. A 1-2 step of forming an electrode layer;
And 1st-3 step of forming the first plating layer by performing metal plating so as to cover the first resin electrode layer,
In the step 1-2,
The portion of the first resin electrode layer located on the first main surface side includes a 1-1 wide portion, a 1-2 wide portion, and a first narrow portion,
The 1-1 wide portion, the first narrow portion, and the 1-2 wide portion are arranged in this order in the extending direction of the first resin electrode layer,
In the vicinity of the first narrow portion, the surface height in the direction orthogonal to the first main surface of the portion of the first resin electrode layer located on the first main surface side is on the side far from the side surface. A method for manufacturing a surface-mount type electronic component array, wherein the first resin electrode layer is formed such that a first step formed by being higher than a side closer to a side surface is located. The step 1-2 is
A 1-1 coating film forming step of forming a 1-1 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 1-2 coating film forming step of forming a 1-2 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 1-1 coating has a taper that becomes narrower and thinner as it gets away from the side surface,
The 1-2 coating film has a taper that becomes narrower and thinner as it approaches the side surface,
The taper of the 1-1 paint film and the tape of the 1-2 paint film are in contact with each other, and the taper of the 1-1 paint film and the 1-2 paint film are in contact with each other. 12. The method of manufacturing a surface-mount type electronic component array according to claim 11, wherein the first narrow portion and the first step are constituted by the tapered portion. The step 1-2 is
A 1-1 coating film forming step of forming a 1-1 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 1-2 coating film forming step of forming a 1-2 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 1-1 coating has a taper that becomes narrower and thinner as it gets away from the side surface,
The 1-2 coating film is narrower and narrower as it approaches the side surface, and the 1-1 coating film has a different film thickness from the first coating film.
The taper of the 1-1 paint film and the tape of the 1-2 paint film are in contact with each other, and the taper of the 1-1 paint film and the 1-2 paint film are in contact with each other. 12. The method of manufacturing a surface-mount type electronic component array according to claim 11, wherein the first narrow portion and the first step are constituted by the tapered portion. The step 1-2 is
A 1-1 coating film forming step of forming a 1-1 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 1-2 coating film forming step of forming a 1-2 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 1-3 coating film forming step of forming a 1-3 coating film on the first main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 1-1 coating film extends in a direction away from the side surface on the first main surface,
The 1-2 coating film and the 1-3 coating film are both wider than the 1-1 coating film, and are arranged so as to be separated from each other in the extending direction of the 1-1 coating film. And overlapped with the 1-1 coating so as to protrude from the 1-1 coating in the width direction of the 1-1 coating,
The first narrow coating portion is constituted by a portion located between the 1-2 coating film and the 1-3 coating film among the 1-1 coating film, and the 1-1 coating film, The said 1st level | step difference is comprised by the boundary part with the said 1-2 coating film, and the boundary part of the said 1-1 coating film and the said 1-3 coating film, It is characterized by the above-mentioned. A method of manufacturing the described surface mount electronic component array. A second external electrode forming step of forming a second external electrode on the element body;
The element body further includes a second main surface adjacent to the side surface,
The second external electrode forming step includes
2-1 step of forming a second baked electrode layer by applying and baking a conductive paste containing a metal as a main component on the second main surface;
A second resin is formed by applying a conductive resin paste containing a conductive material and a thermosetting resin material to cover the entire surface of the second baked electrode layer and to coat the second main surface and the side surface and to cure by heating. A step 2-2 for forming an electrode layer;
A second step of forming a second plating layer by performing metal plating so as to cover the second resin electrode layer,
In the step 2-2,
The portion of the second resin electrode layer located on the second main surface side includes a 2-1 wide portion, a 2-2 wide portion, and a second narrow portion,
The 2-1 wide portion, the second narrow portion, and the 2-2 wide portion are arranged in this order in the extending direction of the second resin electrode layer,
In the vicinity of the second narrow portion, the surface height in the direction perpendicular to the second main surface of the portion of the second resin electrode layer located on the second main surface side is on the side far from the side surface. The second resin electrode layer is formed such that a second step formed by being higher than a side close to a side surface is located. 15. A method for manufacturing a surface-mounted electronic component array. The step 2-2 includes
A 2-1 coating film forming step of forming a 2-1 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 2-2 coating film forming step of forming a 2-2 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 2-1 coating film has a taper that becomes narrower and thinner as it gets away from the side surface,
The 2-2 coating film has a taper that becomes narrower and thinner as it approaches the side surface,
The said detail of the said 2-1 coating film and the said detail of the said 2-2 coating film are contacting, The said detail of the said 2-1 coating film, and the said 2-2 coating film 16. The method for manufacturing a surface-mount type electronic component array according to claim 15, wherein the second narrow portion and the second step are constituted by the tapered portion. The step 2-2 includes
A 2-1 coating film forming step of forming a 2-1 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 2-2 coating film forming step of forming a 2-2 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 2-1 coating film has a taper that becomes narrower and thinner as it gets away from the side surface,
The 2-2 coating film is narrower and narrower as it approaches the side surface, and the film thickness is different from that of the 2-1 coating film and has a thin detail.
The said detail of the said 2-1 coating film and the said detail of the said 2-2 coating film are contacting, The said detail of the said 2-1 coating film, and the said 2-2 coating film 16. The method for manufacturing a surface-mount type electronic component array according to claim 15, wherein the second narrow portion and the second step are constituted by the tapered portion. The step 2-2 includes
A 2-1 coating film forming step of forming a 2-1 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 2-2 coating film forming step of forming a 2-2 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. When,
A 2-3 coating film forming step of forming a 2-3 coating film on the second main surface by applying a conductive resin paste containing a conductive material and a thermosetting resin material and drying by heating. Including
The 2-1 coating film extends in a direction away from the side surface on the second main surface,
The 2-2 coating film and the 2-3 coating film are both wider than the 2-1 coating film, and are arranged so as to be separated from each other in the extending direction of the 2-1 coating film. And overlaps with the 1-1 coating so as to protrude from the 2-1 coating in the width direction of the 2-1 coating,
Of the 2-1 coating film, the second narrow portion is constituted by a portion located between the 2-2 coating film and the 2-3 coating film, and the 2-1 coating film The said 2nd level | step difference is comprised by the boundary part of the said 2-2 coating film, and the boundary part of the said 2-1 coating film and the said 2-3 coating film, It is characterized by the above-mentioned. A method of manufacturing the described surface mount electronic component array.

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