JP4853482B2 - Surface mount electronic component and surface mount electronic component array - Google Patents

Description

  The present invention relates to a surface mount electronic component and a surface mount electronic component array.

  2. Description of the Related Art Conventionally, there has been known a surface mount capacitor including an element body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked, and a pair of first and second external electrodes disposed on the element body. (For example, refer to Patent Document 1 below). The element body has a rectangular parallelepiped shape, a pair of first and second side surfaces facing each other, a pair of third and fourth side surfaces facing each other, and a pair of fifth and sixth surfaces facing each other. It has the side. The third and fourth side surfaces are adjacent to the first and second side surfaces and the fifth and sixth side surfaces, respectively. The fifth and sixth side surfaces are the first and second side surfaces and the third side surface. And the fourth side surface are adjacent to each other.

The first and second external electrodes each have a baked electrode layer, a resin electrode layer, a Ni plating layer, and a Sn plating layer. The baked electrode layer of the first external electrode is formed on the element body so as to cover the first side surface of the element body and wrap around the third to sixth side surfaces adjacent to the first side surface. The resin electrode layer, the Ni plating layer, and the Sn plating layer of the first external electrode are formed in this order on the baking electrode layer of the first external electrode. The baked electrode layer of the second external electrode is formed on the element body so as to cover the second side surface of the element body and wrap around the third to sixth side surfaces adjacent to the second side surface. The resin electrode layer, Ni plating layer, and Sn plating layer of the second external electrode are formed in this order on the baking electrode layer of the second external electrode.
Japanese Patent Application Laid-Open No. 11-162771

  The resin electrode layer is easily deformed as compared with the baked electrode layer. For this reason, even if an external force is applied to the circuit board after the surface-mounted capacitor is mounted on the circuit board, or the surface-mounted capacitor itself expands and contracts due to the heat generated during the operation of the surface-mounted capacitor, The stress acting on the body can be absorbed by the resin electrode layer.

  By the way, after forming the resin electrode layer so as to cover the baked electrode layer on the baked electrode layer, before the plating layer is further formed on the resin electrode layer, barrel polishing of the surface of the resin electrode layer is usually performed. Is called. By barrel polishing, the metal particles exposed on the surface of the resin electrode layer are extended to increase the area of the metal particles exposed on the surface of the resin electrode layer, and the bonding strength between the resin electrode layer and the plating layer is increased. This is because it becomes larger.

  However, during barrel polishing, the resin portion of the resin electrode layer is easily scraped, and in particular, the portion of the resin electrode layer that is disposed on the ridge portion that connects the side surfaces of the element body tends to become thin. . Therefore, the portion that wraps around the third to sixth side surfaces of the baked electrode layer of the first external electrode and the third to sixth side surfaces of the baked electrode layer of the second external electrode. In some cases, the stress acting on the element body from the portion cannot be absorbed by the resin electrode layer, and there is a high possibility that cracks (cracks) may occur in the element body from these portions.

  Accordingly, an object of the present invention is to provide a surface-mounted electronic component and a surface-mounted electronic component array in which cracks are unlikely to occur in the element body by relaxing stress on the element body.

  A surface-mount electronic component according to the present invention includes an element body having a first main surface, a side surface adjacent to the first main surface, and a first ridge portion connecting the first main surface and the side surface; A first external electrode disposed on the first external electrode, the first external electrode containing a metal as a main component and a first baking electrode layer formed on the first main surface so as not to cover the first ridge. A first resin electrode layer containing a conductive material, covering the first baked electrode layer and formed over the first main surface, the first ridge, and the side surface; and containing a metal as a main component and the first resin And a first plating layer formed so as to cover the electrode layer.

  In the surface-mounted electronic component according to the present invention, the first baked electrode layer constituting the first external electrode is formed on the first main surface so as not to reach the first ridge. That is, the 1st baking electrode layer is not formed in the side surface and 1st ridge part which adjoin the 1st main surface. Therefore, even if the portion disposed on the first ridge portion of the first resin electrode layer is thinned by barrel polishing, the stress acting on the element body from the first baking electrode layer cannot be absorbed by the first resin electrode layer. Therefore, it is possible to relieve stress on the element body. As a result, cracks are less likely to occur in the element body. In addition, since an element | base_body is normally barrel-polished after baking, a 1st ridge part may exhibit not only a linear form but the curved surface form which has a curvature of a predetermined | prescribed magnitude | size.

  Preferably, when viewed from the first main surface side, the first baked electrode layer has a rounded shape as a whole. When corners are present in the first baked electrode layer, stress tends to concentrate on the corners. On the other hand, when viewed from the first main surface side, if the first baking electrode layer has a rounded shape as a whole, the occurrence of such stress concentration is suppressed. As a result, the stress acting on the element body can be further relaxed.

  Preferably, the battery further includes a second external electrode disposed on the element body, and the element body further includes a second main surface adjacent to the side surface, and a second ridge portion connecting the second main surface and the side surface. The second external electrode contains a metal as a main component, a second baked electrode layer formed on the second main surface so as not to cover the second ridge, and a conductive material, A second resin electrode layer that covers the second baking electrode layer and is formed over the second main surface, the second ridge, and the side surface; and a second resin electrode layer that contains the metal as a main component and covers the second resin electrode layer 2 plating layers. In this way, even if the portion of the second resin electrode layer disposed on the second ridge is thinned by barrel polishing, the stress applied to the element body from the second baking electrode layer is reduced to the second resin electrode layer. This makes it difficult to cause a situation where it cannot be absorbed, so that stress on the element body can be relaxed. As a result, cracks are less likely to occur in the element body. In addition, since the element body is usually barrel-polished after firing, the second ridge portion may exhibit not only a straight shape but also a curved surface shape having a predetermined curvature.

  More preferably, when it sees from the 2nd main surface side, the 2nd baking electrode layer is exhibiting the rounded shape as a whole. When corners are present in the second baked electrode layer, stress tends to concentrate on the corners. On the other hand, when viewed from the second main surface side, if the second baking electrode layer has a rounded shape as a whole, the occurrence of such stress concentration is suppressed. As a result, the stress acting on the element body can be further relaxed.

  On the other hand, the surface-mount electronic component array according to the present invention includes a first main surface, a side surface adjacent to the first main surface, and an element body having a first ridge portion connecting the first main surface and the side surface, And at least two first external electrodes arranged on the element body and arranged along the first ridge when viewed from the side, and each of the at least two first external electrodes is made mainly of metal. A first baked electrode layer formed on the first main surface so as not to cover the first ridge, and a conductive material, and as a component, covers the first baked electrode layer and covers the first main surface. And a first resin electrode layer formed over the first ridge and side surfaces, and a first plating layer that contains metal as a main component and is formed so as to cover the first resin electrode layer. .

  In the surface mount type electronic component array according to the present invention, each first baking electrode layer constituting each first external electrode is formed on the first main surface so as not to reach the first ridge. That is, each 1st baking electrode layer is not formed in the side surface and 1st ridge part which adjoin the 1st main surface. Therefore, even if the portion disposed at the first ridge portion of each first resin electrode layer becomes thin by barrel polishing, the stress acting on the element body from each first baking electrode layer is applied to each first resin electrode layer. This makes it difficult to cause a situation where it cannot be absorbed, so that stress on the element body can be relaxed. As a result, cracks are less likely to occur in the element body. In addition, since an element | base_body is normally barrel-polished after baking, a 1st ridge part may exhibit not only a linear form but the curved surface form which has a curvature of a predetermined | prescribed magnitude | size.

  Preferably, when viewed from the first main surface side, at least two first baked electrode layers all have a rounded shape as a whole. When corners are present in the first baked electrode layer, stress tends to concentrate on the corners. On the other hand, when viewed from the first main surface side, if the first baking electrode layer has a rounded shape as a whole, the occurrence of such stress concentration is suppressed. As a result, the stress acting on the element body can be further relaxed.

  Preferably, the element body further includes a second main surface adjacent to the side surface, and a second ridge portion that connects the second main surface and the side surface, and is disposed on the element body and viewed from the side surface. And at least two second external electrodes arranged along the second ridge, and each of the at least two second external electrodes contains a metal as a main component and does not cover the second ridge. The second baked electrode layer formed on the second main surface and the second baked electrode layer are formed over the second main surface, the second ridge, and the side surface while containing the conductive material and covering the second baked electrode layer. A resin electrode layer; and a second plating layer formed to cover the second resin electrode layer while containing a metal as a main component. In this way, even if the portion disposed at the second ridge portion of each second resin electrode layer becomes thin by barrel polishing, the stress acting on the element body from each second baking electrode layer is applied to each second electrode layer. Since it is difficult for the resin electrode layer to absorb, the stress on the element body can be relaxed. As a result, cracks are less likely to occur in the element body. In addition, since the element body is usually barrel-polished after firing, the second ridge portion may exhibit not only a straight shape but also a curved surface shape having a predetermined curvature.

  More preferably, when viewed from the second main surface side, at least two second baked electrode layers all have a rounded shape as a whole. When corners are present in the second baked electrode layer, stress tends to concentrate on the corners. On the other hand, when viewed from the second main surface side, if the second baking electrode layer has a rounded shape as a whole, the occurrence of such stress concentration is suppressed. As a result, the stress acting on the element body can be further relaxed.

  According to the present invention, it is possible to provide a surface-mounted electronic component and a surface-mounted electronic component array in which cracks are unlikely to occur in the element body by relaxing stress on the element body.

  Preferred embodiments of the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

(First embodiment)
The surface-mount type electronic component according to the first embodiment will be described with reference to FIGS. In the following description, the surface-mounted capacitor 1 is described as an example of the surface-mounted electronic component.

  The surface mount capacitor 1 includes a rectangular parallelepiped dielectric body (element body) 10, internal electrodes 12A, 12B, 14A, and 14B, external electrodes 16A (first external electrodes), 16B (second external electrodes), Is provided.

  The dielectric body 10 includes main surfaces 10a (first main surface) and 10b (second main surface) facing each other, side surfaces 10c (side surfaces) and 10d facing each other, and side surfaces 10e and 10f facing each other. Have. In the first embodiment, the side surface 10c or the side surface 10d is a mounting surface that faces the main surface of a circuit board (not shown).

  The side surfaces 10c and 10d extend so as to connect the main surfaces 10a and 10b and the side surfaces 10e and 10f. The side surfaces 10e and 10f extend so as to connect the main surfaces 10a and 10b and the side surfaces 10c and 10d. Main surface 10a and side surfaces 10c to 10f adjacent to main surface 10a are connected by ridges E1 to E4, respectively. Main surface 10b and side surfaces 10c to 10f adjacent to main surface 10b are connected by ridges E5 to E8, respectively. In addition, since the dielectric body 10 is usually barrel-polished after firing, the ridges E1 to E8 have a curved surface shape having a predetermined curvature in the first embodiment.

  The dielectric body 10 can be formed of, for example, a dielectric ceramic material obtained by adding a rare earth element to barium titanate or strontium titanate. In the first embodiment, the length of the dielectric body 10 in the longitudinal direction can be set, for example, to about 1.0 mm, the width, for example, about 0.5 mm, and the thickness, for example, about 0.5 mm.

  As shown in FIG. 4, the dielectric body 10 is configured by laminating rectangular dielectric layers A10 to A15 and internal electrodes 12A, 12B, 14A, and 14B. The actual surface mount capacitor 1 is integrated to such an extent that the boundaries between the dielectric layers A10 to A15 cannot be visually recognized. Therefore, all of the internal electrodes 12A, 12B, 14A, and 14B are disposed inside the dielectric body 10.

  The internal electrodes 12A, 12B, 14A, 14B are alternately stacked via the dielectric layers A11 to A13, and overlap each other when viewed from the stacking direction. Surface mounting depends on the facing area of the internal electrodes 12A, 12B, 14A, and 14B when viewed from the stacking direction and the interval between the internal electrodes 12A, 12B, 14A, and 14B (that is, the thickness of the dielectric layers A11 to A13). The capacitance of the type capacitor 1 is defined.

  Each internal electrode 12A, 14A extends in the opposing direction of the main surfaces 10a, 10b. In each of the internal electrodes 12A and 14A, lead-out portions 12a and 14a are integrally formed at the central portion of the short side on the main surface 10a side. Each derivation | leading-out part 12a, 14a is exhibiting the rectangular shape, respectively, The one end is exposed to the main surface 10a. On the other hand, the short side of each internal electrode 12A, 14A on the main surface 10b side is not exposed to the main surface 10b.

  Each internal electrode 12B, 14B extends in the opposing direction of the main surfaces 10a, 10b. In each of the internal electrodes 12B and 14B, lead-out portions 12b and 14b are integrally formed at the central portion of the short side on the main surface 10b side. Each derivation | leading-out part 12b, 14b is exhibiting the rectangular shape, respectively, The one end is exposed to the main surface 10b. On the other hand, the short side of each internal electrode 12B, 14B on the main surface 10a side is not exposed to the main surface 10a.

  The internal electrodes 12A, 12B, 14A, 14B are made of a conductive material such as Ag or Ni, for example. The internal electrodes 12A, 12B, 14A, and 14B are configured as a sintered body of a conductive paste containing the conductive material.

  The external electrode 16A is formed so as to cover the main surface 10a of the dielectric body 10 and wrap around the side surfaces 10c to 10f adjacent to the main surface 10a. That is, the external electrode 16A is disposed in a portion near the main surface 10a among the main surface 10a and the side surfaces 10c to 10f.

  As shown in FIG. 2, the external electrode 16A includes a baked electrode layer 18A, a resin electrode layer 20A, a first plating layer 22A, and a second plating layer 24A. The baked electrode layer 18A, the resin electrode layer 20A, the first plating layer 22A, and the second plating layer 24A are disposed outward from the dielectric element body 10 in this order.

  As shown in FIGS. 1 to 3, the baked electrode layer 18 </ b> A is formed on the main surface 10 a of the dielectric body 10 so as not to cover the ridges E <b> 1 to E <b> 4. That is, the baking electrode layer 18A is disposed only on the main surface 10a, which is a region surrounded by the ridges E1 to E4, and is not disposed on the side surfaces 10c to 10f. As shown in FIGS. 1 and 3, the baking electrode layer 18 </ b> A has a circular shape when viewed from the main surface 10 a side in the first embodiment.

  The baked electrode layer 18A is physically and electrically connected to the ends of the lead-out portions 12a and 14a exposed on the main surface 10a. For this reason, the baked electrode layer 18A is electrically connected to the internal electrode 12A via the lead-out portion 12a, and is electrically connected to the internal electrode 14A via the lead-out portion 14a.

  The resin electrode layer 20A is formed on the baking electrode layer 18A and the dielectric element body 10 so as to cover the entire surface of the baking electrode layer 18A. Specifically, the resin electrode layer 20A is formed so as to cover the surface of the baking electrode layer 18A and the main surface 10a and to wrap around the side surfaces 10c to 10f adjacent to the main surface 10a. The first plating layer 22A is formed so as to cover the resin electrode layer 20A. The second plating layer 24A is formed so as to cover the first plating layer 22A.

  The external electrode 16B is formed so as to cover the main surface 10b of the dielectric element body 10 and wrap around the side surfaces 10c to 10f adjacent to the main surface 10b. That is, the external electrode 16B is disposed in a portion near the main surface 10b among the main surface 10b and the side surfaces 10c to 10f.

  As shown in FIG. 2, the external electrode 16B includes a baked electrode layer 18B, a resin electrode layer 20B, a first plating layer 22B, and a second plating layer 24B. The baked electrode layer 18B, the resin electrode layer 20B, the first plating layer 22B, and the second plating layer 24B are arranged outward from the dielectric element body 10 in this order.

  As shown in FIGS. 1 to 3, the baked electrode layer 18 </ b> B is formed on the main surface 10 b of the dielectric element body 10 so as not to reach the ridges E <b> 5 to E <b> 8. That is, the baking electrode layer 18B is disposed only on the main surface 10b, which is a region surrounded by the ridges E5 to E8, and is not disposed on the side surfaces 10c to 10f. As shown in FIGS. 1 and 3, the baking electrode layer 18 </ b> B has a circular shape when viewed from the main surface 10 b side in the first embodiment.

  The baked electrode layer 18B is physically and electrically connected to the end portions of the lead-out portions 12b and 14b exposed on the main surface 10b. Therefore, the baked electrode layer 18B is electrically connected to the internal electrode 12B via the lead-out portion 12b, and is electrically connected to the internal electrode 14B via the lead-out portion 14b.

  The resin electrode layer 20B is formed on the baking electrode layer 18B and the dielectric element body 10 so as to cover the entire surface of the baking electrode layer 18B. Specifically, the resin electrode layer 20B covers the surface of the baked electrode layer 18B and the main surface 10b, and is formed so as to go around the side surfaces 10c to 10f adjacent to the main surface 10b. The first plating layer 22B is formed so as to cover the resin electrode layer 20B. The second plating layer 24B is formed so as to cover the first plating layer 22B.

  Here, the baked electrode layers 18A and 18B are mainly formed of a metal such as Cu. Specifically, the baking electrode layers 18A and 18B are formed by applying and baking a conductive paste containing Cu powder on the main surfaces 10a and 10b, respectively. The thickness of the baked electrode layers 18A and 18B can be set to about 30 μm to 40 μm, for example.

  The resin electrode layers 20A and 20B are formed by curing a resin electrode layer forming composition in which metal particles are contained as a conductive material in a thermosetting resin. The thickness of the resin electrode layers 20A and 20B can be set to about 130 μm, for example.

In the present embodiment, Ag, which is a noble metal, is used as the material for the metal particles. Although it does not restrict | limit especially as a thermosetting resin, For example, a phenol resin, an acrylic resin, a silicon resin, an epoxy resin, a polyimide etc. can be used.

  The content of all metal particles in the resin electrode layer forming composition is preferably 60% by mass to 95% by mass based on the total solid content of the resin electrode layer forming composition. When the content is less than 60% by mass, the conductivity inside the resin electrode layers 20A and 20B tends to be insufficient as compared with the case where the content is within the above range. When the content exceeds 95% by mass, the amount of the thermosetting resin is insufficient as compared with the case where the content is within the above range, so that the baking electrode layers 18A and 18B and the resin electrode layers 20A and 20B There exists a tendency for adhesiveness to fall.

  The resin electrode layer forming composition further contains a solvent as necessary. As the solvent, any known solvent can be used without particular limitation as long as it can dissolve or disperse the thermosetting resin. Specific examples of the solvent include methyl carbitol, ethyl carbitol, butyl carbitol, butyl carbitol acetate, cellosolve, butyl cellosolve, butyl cellosolve acetate, and terpineol.

  The resin electrode layers 20A and 20B are formed by applying the resin electrode layer forming composition onto the baked electrode layers 18A and 18B, followed by drying and thermosetting. Here, the temperature at the time of thermosetting is appropriately adjusted according to the curable resin to be used.

  The first plating layers 22A and 22B contain Ni as a main component. The first plating layers 22A and 22B are formed by plating the surfaces of the resin electrode layers 20A and 20B with Ni. The thickness of the first plating layers 22A and 22B can be set to, for example, about 1 μm.

  When the first plating layers 22A and 22B are plated on the surfaces of the resin electrode layers 20A and 20B, the surfaces of the resin electrode layers 20A and 20B are preferably barrel-polished in advance. By barrel polishing, the metal particles exposed on the surfaces of the resin electrode layers 20A and 20B are extended to increase the area of the metal particles exposed on the surfaces of the resin electrode layers 20A and 20B. This is because the bonding strength between 20B and the first plating layers 22A and 22B is increased.

  The second plating layers 24A and 24B contain Sn or Sn alloy as a main component. The second plating layers 24A and 24B are formed by plating the surfaces of the first plating layers 22A and 22B with Sn or an Sn alloy. The thickness of the second plating layers 24A and 24B can be, for example, about 1 μm to 10 μm.

  In the first embodiment as described above, the baking electrode layer 18A is formed on the main surface 10a so as not to cover the ridges E1 to E4, and the baking electrode layer 18B is not mainly applied to the ridges E5 to E8. It is formed on the surface 10b. Therefore, even if the part arrange | positioned by ridge E1-E4 among resin electrode layer 20A and the part arrange | positioned by ridge E5-E8 among resin electrode layers 20B became thin by barrel polishing, a baking electrode Since it is difficult for the resin electrode layers 20A and 20B to absorb the stress acting on the dielectric body 10 from the layers 18A and 18B, the stress on the dielectric body 10 can be relaxed. ing. As a result, cracks are less likely to occur in the dielectric body 10.

  In the first embodiment, the baking electrode layer 18A has a circular shape when viewed from the main surface 10a side, and the baking electrode layer 18B has a circular shape when viewed from the main surface 10b side. In the case where corners are present in the baked electrode layers 18A and 18B, stress tends to concentrate on the corners. On the other hand, when the baked electrode layers 18A and 18B have a round shape as a whole such as a circular shape, the occurrence of such stress concentration is suppressed. As a result, the stress acting on the dielectric body 10 can be further relaxed.

(Second Embodiment)
Next, the surface-mount electronic component array according to the second embodiment will be described with reference to FIGS. 5 to 7, focusing on the differences from the surface-mount capacitor 1 according to the first embodiment. In the following description, the surface-mounted capacitor array 2 is described as an example of the surface-mounted electronic component array.

The surface-mounted capacitor array 2 includes a rectangular parallelepiped dielectric element (element body) 10, internal electrodes 12A _{1 to} 12A ₃ , 12B _{1 to} 12B ₃ , 14A _{1 to} 14A ₃ , 14B _{1 to} 14B ₃ , an external Electrodes 16A _{1 to} 16A ₃ (first external electrodes) and 16B _{1 to} 16B ₃ (second external electrodes) are provided. In the second embodiment, the length of the dielectric body 10 in the longitudinal direction can be set, for example, to about 2.0 mm, the width, for example, about 1.25 mm, and the thickness, for example, about 0.85 mm.

The dielectric body 10, as shown in FIG. 7, a dielectric layer A10~A15 exhibiting a rectangular internal electrode _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~ and 14B ₃ are formed by laminating. The actual surface mount capacitor array 2 is integrated to such an extent that the boundaries between the dielectric layers A10 to A15 cannot be visually recognized. Therefore, the internal electrodes _{12A 1 ~12A 3, 12B 1 ~12B} 3, 14A 1 ~14A 3, 14B 1 ~14B 3 are both disposed inside of the dielectric body 10.

On the dielectric layer A11 is three internal electrodes _12A 1 _{~12A 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A11 (side 10e, 10f opposite direction). The internal electrodes 12A _{1 to} 12A ₃ have a predetermined distance from each other on the dielectric layer A11. In each of the internal electrodes 12A _{1 to} 12A ₃ , lead-out portions 12a _{1 to} 12a ₃ are integrally formed at the central portion of the short side on the main surface 10a side. Each lead portion _12a 1 _{~12a 3} has a rectangular shape, respectively, one end is exposed to the main surface 10a.

On the dielectric layer A12 is three internal electrodes _12B 1 _{~12B 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A12 (side 10e, 10f opposite direction). The internal electrodes 12B _{1 to} 12B ₃ have a predetermined distance from each other on the dielectric layer A12. Each internal electrode _12B 1 _{~12B 3,} deriving portion _12b 1 _{~12b 3} in the central portion of the short side of the principal surface 10b side is integrally formed, respectively. Each lead portion _12b 1 _{~12b 3} has a rectangular shape, respectively, one end is exposed to the main surface 10b.

On the dielectric layer A13 is three internal electrodes _14A 1 to 14A ₃ exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A13 (side 10e, 10f opposite direction). The internal electrodes 14A _{1 to} 14A ₃ have a predetermined distance from each other on the dielectric layer A13. Each internal electrode _14A 1 to 14A _3, deriving section _14a 1 to 14A ₃ in the central portion of the short side of the principal surface 10a side is integrally formed, respectively. Each lead portion _14a 1 to 14A ₃ has a rectangular shape, respectively, one end is exposed to the main surface 10a.

On the dielectric layer A14 is three internal electrodes _14B 1 _{~14B 3} exhibits a rectangular shape are juxtaposed in the longitudinal direction of the dielectric layer A14 (side 10e, 10f opposite direction). The internal electrodes 14B _{1 to} 14B ₃ have a predetermined distance from each other on the dielectric layer A14. Each internal electrode _14B 1 _{~14B 3,} deriving portion _14b 1 _{~14b 3} in the central portion of the short side of the principal surface 10b side is integrally formed, respectively. Each lead portion _14b 1 _{~14b 3} has a rectangular shape, respectively, one end is exposed to the main surface 10b.

External electrodes 16A ₁ is a side 10c adjacent to the main surface 10a covers the major surface 10a of the dielectric body 10 is formed so as to wrap around the 10d. That is, the external electrodes 16A ₁ is the major surface 10a and side surface 10c, is disposed on the main surface 10a side of the portion of the 10d.

The external electrode 16A ₁ has a baked electrode layer 18A ₁ , a resin electrode layer, a first plating layer, and a second plating layer (resin electrode layer, first electrode), as in the surface-mounted capacitor 1 according to the first embodiment. The first plating layer and the second plating layer are not shown). The baked electrode layer 18A ₁ , the resin electrode layer, the first plating layer, and the second plating layer are disposed outward from the dielectric element body 10 in this order.

As shown in FIGS. 5 and 6, the baked electrode layer 18 </ b> A ₁ is formed on the main surface 10 a of the dielectric body 10 so as not to reach the ridges E <b> 1 to E <b> 4. That is, the sintered electrode layer 18A ₁ is disposed only on the main surface 10a is an area surrounded by the ridge E1 to E4, it is not flanked 10C～10f. As shown in FIGS. 5 and 6, the baked electrode layer 18 </ b> A ₁ has an elliptical shape as viewed from the main surface 10 a side in the second embodiment.

Sintered electrode layer 18A ₁ is an end of the lead portion _12a 1, 14a ₁ which is exposed to the main surface 10a physically and electrically connected. Therefore, the sintered electrode layer 18A ₁ is electrically connected to the internal electrodes 12A ₁ via a lead portion 12a _1, and is connected the internal electrodes 14A ₁ and electrically via a lead portion 14a _1.

The external electrodes 16A _{2 to} 16A ₃ and 16B _{1 to} 16B ₃ are respectively baked electrode layers 18A _{2 to} 18A ₃ , 18B _{1 to} 18B ₃ , a resin electrode layer, a first plating layer, and a second plating, like the external electrode 16A _1. Has a layer. Sintered electrode layers _18A 2 _{~18A 3} is disposed only on the main surface 10a is an area surrounded by the ridge E1 to E4, it is not flanked 10C～10f. The baked electrode layers 18B _{1 to} 18B ₃ are disposed only on the main surface 10b, which is a region surrounded by the ridges E5 to E8, and are not disposed on the side surfaces 10c to 10f.

As shown in FIGS. 5 and 6, the baked electrode layers 18 </ b> A _{2 to} 18 </ b> A ₃ have an elliptical shape as viewed from the main surface 10 a side in the second embodiment. As shown in FIGS. 5 and 6, the baked electrode layers 18 </ b> B _{1 to} 18 </ b> B ₃ have an elliptical shape when viewed from the main surface 10 b side in the second embodiment.

Sintered electrode layers 18A ₂ is deriving section _12a 2, the ends of 14a ₂ physically and electrically connected to exposed to the main surface 10a, the sintered electrode layer 18A ₃ is exposed to the main surface 10a Are connected physically and electrically to the ends of the lead-out portions 12a ₃ and 14a ₃ . Sintered electrode layer 18B ₁ the derived portions _12b 1 which is exposed to the main surface 10b, is connected 14b ₁ end physically and electrically, the sintered electrode layer 18B ₂ is exposed to the main surface 10b The baked electrode layer 18B ₃ is physically and electrically connected to the end portions of the lead portions 12b ₂ and 14b _{2 and} the end portions of the lead portions 12b ₃ and 14b ₁ exposed on the main surface 10b. It is physically and electrically connected.

  The surface mount capacitor array 2 according to the second embodiment as described above has the same effects as the surface mount capacitor 1 according to the first embodiment.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in the first embodiment, the present invention is applied to the surface mount capacitor 1. However, the present invention is not limited to this, and various surface mount electronic components (for example, surface mount varistors, surface mount transformers, surface mount LC composites). It can be applied to (parts). In the second embodiment, the present invention is applied to the surface mount capacitor array 2. However, the present invention is not limited to this, and various surface mount electronic component arrays (for example, surface mount varistor arrays, surface mount filter arrays) are used. It can be applied to.

Further, in the surface-mounted capacitor 1 according to the first embodiment, the baked electrode layers 18A and 18B have a circular shape when viewed from the main surfaces 10a and 10b, respectively, and the surface-mounted capacitor according to the second embodiment In the type capacitor array 2, the baking electrode layers 18 </ b> A _{1 to} 18 </ b> A ₃ and 18 </ b> B _{1 to} 18 </ b> B ₃ have an elliptical shape when viewed from the main surfaces 10 a and 10 b, respectively, but are not limited thereto. That is, the major surface 10a of the dielectric body 10 so as not to ridge E1 to E8, be formed on 10b, baked electrode layer 18A, 18B and baked electrode layer _18A 1 _{~18A 3, 18B} 1 _{~18B 3} can have various shapes.

Specifically, the sintered electrode layer 18A, and 18B and the baked electrode layer _{18A 1 ~18A 3, 18B 1 ~18B} 3, for example, or a polygonal shape such as triangular or quadrangular shape, a circular shape, an elliptical shape, a racetrack shape It can be. However, when there are corners in the baked electrode layer, stress tends to concentrate on the corners, so that the baked electrode layer as a whole has a rounded shape when viewed from the main surfaces 10a and 10b. This is preferable because the occurrence of stress concentration is suppressed.

As the “rounded shape”, specifically, a circular shape such as a baked electrode layer 18A of the surface-mounted capacitor 1 shown in FIG. 3, or a baked electrode of the surface-mounted capacitor array 2 shown in FIG. other ellipse shapes such as layer 18A ₁ ～18A _3, the shape and the four corners, such as baked electrode layer 18A of the surface mount capacitors 3 shown in FIG. 8 is chamfered so as to have a predetermined radius of curvature, FIG. 9 A racetrack shape such as a baked electrode layer 18A of the surface mount capacitor 4 shown in FIG. Note that the racetrack shape has first and second arc portions and first and second straight portions, and the opening of the first arc portion and the opening of the second arc portion face each other. The first arc portion and the second arc portion are arranged on one end, and one end of the first arc portion and one end of the second arc portion on the one end side are connected by the first straight portion, and the first arc portion The other end of a part and the other end of a 2nd circular arc part say the shape connected by the 2nd linear part.

In the second embodiment, three external electrodes 16A _{1 to} 16A ₃ are arranged along the opposing direction of the side surfaces 10e and 10f on the main surface 10a side, and the opposing direction of the side surfaces 10e and 10f on the main surface 10b side. The surface mount type capacitor array 2 in which the _three external electrodes 16B _{1 to} 16B ₃ are arranged along the surface has been described. However, the surface mount type capacitor in which two or more external electrodes are arranged on the main surfaces 10a and 10b side, respectively. The present invention is applicable to any array. Therefore, the number of external electrodes arranged on the main surface 10a side may be different from the number of external electrodes arranged on the main surface 10b side.

FIG. 1 is a perspective view showing a surface mount electronic component according to the first embodiment. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 3 is a side perspective view of the surface mount electronic component according to the first embodiment. FIG. 4 is an exploded perspective view of the dielectric body constituting the surface mount electronic component according to the first embodiment. FIG. 5 is a perspective view showing a surface mount electronic component array according to the second embodiment. FIG. 6 is a side perspective view of the surface-mounted electronic component array according to the second embodiment. FIG. 7 is an exploded perspective view of a dielectric body constituting the surface mount electronic component array according to the second embodiment. FIG. 8 is a side perspective view showing another example (first example) of the surface-mount type electronic component according to the first embodiment. FIG. 9 is a side perspective view illustrating another example (second example) of the surface mount electronic component according to the first embodiment.

Explanation of symbols

1 ... surface mount capacitors, 2 ... surface mount capacitor array, 10 ... dielectric element, 10a, 10b ... main surface, 10C～10f ... _{side, 16A, 16B, 16A 1 ~16A} 3, 16B 1 ~16B 3 ... external _{electrode, 18A, 18B, 18A 1 ~18A} 3, 18B 1 ~18B 3 ... baked electrode layer, 20A, 20B ... resin electrode layer, 22A, 22B ... first plating layer, 24A, 24B ... second plating layer, E1 to E8 ... ridges.

Claims (8)

An element body having a first main surface, a side surface adjacent to the first main surface, and a first ridge portion connecting the first main surface and the side surface;
A first external electrode disposed on the element body,
The first ridge portion has a curved surface shape,
The first external electrode is
A first baked electrode layer formed on the first main surface so as not to cover the first ridge while containing a metal as a main component;
A first resin electrode layer containing a conductive material and covering the first baking electrode layer and formed over the first main surface, the first ridge, and the side surface;
A surface-mounting electronic component comprising: a metal as a main component; and a first plating layer formed so as to cover the first resin electrode layer.   2. The surface-mount type electronic component according to claim 1, wherein when viewed from the first main surface side, the first baked electrode layer has a rounded shape as a whole. A second external electrode disposed on the element body;
The element body further includes a second main surface adjacent to the side surface, and a second ridge portion connecting the second main surface and the side surface,
The second ridge portion has a curved surface shape,
The second external electrode is
A second baking electrode layer containing a metal as a main component and formed on the second main surface so as not to cover the second ridge,
A second resin electrode layer containing a conductive material and covering the second baking electrode layer and formed over the second main surface, the second ridge, and the side surface;
The surface-mount type electronic component according to claim 1, further comprising: a second plating layer that contains a metal as a main component and covers the second resin electrode layer.   4. The surface-mount type electronic component according to claim 3, wherein when viewed from the second main surface side, the second baked electrode layer has a rounded shape as a whole. 5. An element body having a first main surface, a side surface adjacent to the first main surface, and a first ridge portion connecting the first main surface and the side surface;
Comprising at least two first external electrodes arranged on the element body and arranged along the first ridge when viewed from the side surface;
The first ridge portion has a curved surface shape,
The at least two first external electrodes are respectively
A first baked electrode layer formed on the first main surface so as not to cover the first ridge while containing a metal as a main component;
A first resin electrode layer containing a conductive material and covering the first baking electrode layer and formed over the first main surface, the first ridge, and the side surface;
A surface-mount type electronic component array comprising: a metal as a main component; and a first plating layer formed to cover the first resin electrode layer.   6. The surface mount according to claim 5, wherein when viewed from the first main surface side, the at least two first baked electrode layers have a rounded shape as a whole. Type electronic component array. The element body further includes a second main surface adjacent to the side surface, and a second ridge portion connecting the second main surface and the side surface,
And further comprising at least two second external electrodes arranged on the element body and arranged along the second ridge when viewed from the side surface,
The second ridge portion has a curved surface shape,
The at least two second external electrodes are respectively
A second baking electrode layer containing a metal as a main component and formed on the second main surface so as not to cover the second ridge,
A second resin electrode layer containing a conductive material and covering the second baking electrode layer and formed over the second main surface, the second ridge, and the side surface;
7. The surface-mount type electronic component array according to claim 5, further comprising: a second plating layer that contains a metal as a main component and covers the second resin electrode layer. 8.   8. The surface mount according to claim 7, wherein when viewed from the second main surface side, the at least two second baked electrode layers all have a rounded shape as a whole. Type electronic component array.

Images