JP2009231728A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the frequency of the occurrence of product defects and to improve a yield, in a method of manufacturing a semiconductor device for separating element regions by a groove provided on a semiconductor substrate. <P>SOLUTION: In the method of manufacturing the semiconductor device, a layered structure 26 is formed for which a first oxide film 22, a first nitride film 23, a second oxide film 24 and a second nitride film 25 are laminated in the order from the bottom on a silicon substrate 21, and the sidewall 28a of a nitride film is formed on the layered structure 26. Then, the layered structure 26 and the sidewall 28 are turned to a mask and the groove 21a is formed on the silicon substrate 21. Then, the sidewall 28a and the second nitride film 25 are removed, and an embedded layer 30 is formed on the silicon substrate 21. Then, the first nitride film 23 is used as a stopper, the embedded layer 30 is planarized, and an element isolation structure is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which element regions are separated by a groove provided in a semiconductor substrate.

  2. Description of the Related Art In recent years, STI (Shallow Trench Isolation) structures in which adjacent element regions are separated by a groove provided in a semiconductor substrate have been widely used in semiconductor devices. Conventionally, a semiconductor device having this STI structure has been manufactured, for example, as shown in FIGS. Here, FIG. 1 and FIG. 2 are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art in the order of steps.

  First, as shown in FIG. 1A, a silicon oxide (SiO) film 2 is formed on a silicon (semiconductor) substrate 1 by a thermal oxidation method, followed by silicon nitride by a CVD (Chemical Vapor Deposition) method. The (SiN) film 3 is formed.

  Next, as shown in FIG. 1B, the silicon nitride film 3 is patterned to form a silicon nitride film pattern 3a having an opening 3b. Subsequently, using the silicon nitride film pattern 3 a as a mask, the silicon oxide film 2 and the silicon substrate 1 are etched to form element isolation grooves 1 a in the silicon substrate 1. The flat portion below the silicon nitride film pattern 3a becomes the element region 1b. Next, the silicon substrate 1 is thermally oxidized to form a silicon oxide film 2a on the surface of the element isolation trench 1a. In this way, the structure shown in FIG. 1B is completed.

  Next, as shown in FIG. 1C, a buried layer 4 made of silicon oxide is formed above the silicon substrate 1 by a plasma CVD method.

  Thereafter, as shown in FIG. 1D, the surface of the buried layer 4 is planarized by a CMP (Chemical Mechanical Polishing) method to separate the buried layer 4. At this time, the end 4a of the buried layer 4 is formed above the side wall of the element isolation trench 1a.

  Next, as shown in FIG. 2A, after the silicon substrate 1 is annealed, the silicon nitride film pattern 3a is removed with a chemical solution containing phosphoric acid.

  Subsequently, as shown in FIG. 2B, the thermal oxide film 2 exposed on the element region 1b is removed by wet etching using a chemical solution containing hydrofluoric acid to expose the silicon substrate 1 in the element region 1b. . At this time, the film thickness of the buried layer 4 also decreases.

  Next, steps required until a structure shown in FIG. First, a well forming silicon oxide film (not shown) is formed on the surface of the element region 1b by thermal oxidation. Subsequently, impurities are ion-implanted using a well-forming silicon oxide film as a through film to form a well 5 in the element region 1b. Next, the well-forming silicon oxide film is removed by wet etching using a chemical solution containing hydrofluoric acid. At this time, the buried layer 4 is also etched to reduce the film thickness. Thereafter, a gate insulating film 10 made of silicon oxide is formed on the element region 1b by a thermal oxidation method.

  When the thickness of the gate insulating film 10 is made different between the high-voltage and low-voltage MOS transistors, the following 15th to 17th steps are further performed. First, a partial etching resist pattern (not shown) is formed on a region where the thick gate insulating film 10 is to be formed. Subsequently, the gate insulating film 10 in a region not covered with the partial etching resist pattern is removed with a chemical solution containing hydrofluoric acid. Then, after removing the resist pattern, the entire upper surface of the silicon substrate 1 is thermally oxidized to grow the gate insulating film 10. With the above steps, formation of the gate insulating film 10 is completed.

  Thereafter, a polysilicon film 6 is formed on the entire upper surface of the silicon substrate 1. As described above, the structure shown in FIG. 2C is completed.

  Next, in order to form the structure shown in FIG. 2D, a resist pattern (not shown) is formed on the polysilicon film 6, and the polysilicon film 6 is dry-etched using the resist pattern as a mask to form the gate electrode 6a. Form. Thereafter, the sidewall 8a is formed, and ion implantation is performed using the sidewall 8a and the gate electrode 6a as a mask to form the source / drain regions 9. In this way, the semiconductor device as shown in FIG.

In addition, there are the following Patent Documents 1 to 5 that disclose a method of forming an STI structure.
JP-A-9-181158 JP 2001-332613 A JP 2003-273207 A JP 2004-39734 A JP 2004-356484 A

  However, the above-described manufacturing method has a problem in that the defective product occurrence rate is high and the yield is not stable.

  Therefore, an object of the method for manufacturing a semiconductor device in which element regions are separated by grooves provided in a semiconductor substrate is to suppress the occurrence of product defects and improve yield.

  The object is to form a layered structure composed of a first oxide film, a first nitride film, a second oxide film and a second nitride film on a semiconductor substrate, and to form a sidewall on the layered structure, Grooves are formed in the semiconductor substrate using the layered structure and sidewalls as a mask, the sidewalls are removed, a buried layer is formed on the semiconductor substrate, the buried layer is planarized, and at least one of the layered structures is formed. This is achieved by a method for manufacturing a semiconductor device, wherein the portion is removed.

  According to the manufacturing method of the semiconductor device described above, the groove is formed using the layered structure and the sidewall as a mask. Then, after removing the sidewall, a buried layer is formed. As a result, a structure in which the end portion of the buried layer protrudes to the element region side is obtained. Further, the buried layer can be formed of a material by a uniform manufacturing method, that is, a material having a uniform etching rate with respect to hydrofluoric acid. Thereby, it is possible to prevent the occurrence of a depot (a concave portion) or a step at the end portion of the buried layer, and the generation of a residue of the gate electrode material can be prevented. For this reason, it can prevent that the residue of a gate electrode material short-circuits between wiring, and a defective product generate | occur | produces.

  Furthermore, in the above viewpoint, it is preferable that the planarization is performed based on the height of the first nitride film. That is, in the planarization, the first nitride film is used as a stopper film. In this case, the upper surface of the first nitride film constituting a part of the layered structure is covered with the second oxide film until planarization is performed. Therefore, the height of the first nitride film is kept uniform, and the buried layer can be formed in a uniform shape (height) on the semiconductor substrate. For this reason, generation | occurrence | production of the inferior goods by the variation in the shape of an embedding layer can be suppressed.

  Prior to the description of the embodiments of the present invention, considerations made by the inventors will be described.

(Investigation of cause of defects in conventional technology)
The inventor of the present application conducted an experiment reproducing the manufacturing process shown in FIGS. 1 and 2, and observed a cross section of the sample extracted in the middle with a scanning electron microscope. The observation results are shown in FIG. FIG. 3 is a schematic diagram showing a result of observing a cross section of the semiconductor substrate during the semiconductor device manufacturing method according to the prior art. 3A shows a cross section immediately after the element isolation trench 1a is formed by dry etching using the silicon nitride film pattern 3a as a mask, and FIG. 3B shows a state immediately after the buried layer 4 is formed by the CVD method. A cross section is shown. FIG. 3C shows a cross section immediately after the buried layer 4 is planarized by the CMP method, and FIG. 3D shows a cross section immediately after the silicon nitride pattern 3a is removed by wet etching with phosphoric acid. Show. FIG. 3E shows a cross section immediately after removing the silicon oxide film 2 exposed on the element region 1b by etching with hydrofluoric acid, and FIG. 3F shows immediately after removing the gate insulating film 10 by partial etching. The cross section of is shown. FIG. 3G shows a cross section immediately after the polysilicon film 6 is formed by the CVD method.

  When the surface of the element isolation trench 1a is thermally oxidized, the thermal oxide film 2a is formed so that the side wall of the element isolation trench 1a slightly enters under the opening 3b of the silicon nitride film pattern 3a. When the silicon nitride film pattern 3a and the silicon oxide film 2 are removed after the buried layer 4 made of silicon oxide is buried in the groove and planarized, the portion surrounded by the broken line A in FIG. A concave portion called a depot is formed. Thereafter, as shown in a portion surrounded by a broken line B in FIG. 3F, this depot grows greatly by repeating the wet etching with a chemical solution containing hydrofluoric acid a plurality of times. Then, as shown in a portion surrounded by a broken line C in FIG. 3G, conductive polysilicon is buried in the depot portion of the buried layer 4 by the step of forming the polysilicon film 6.

  The inventor of the present application further observed the surface of the semiconductor device manufactured in the manufacturing process shown in FIGS. 1 and 2 with a scanning electron microscope. The observation results are shown in FIGS. FIG. 4 is a schematic view showing a result of observing the surface of a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device from above, and FIG. 5 is an enlarged view of a part of the sample shown in FIG. It is a schematic diagram showing a result observed from obliquely upward.

  In FIG. 4, the part denoted by reference numeral 1 b is an element region, and the part denoted by reference numeral 4 is a buried layer. A portion denoted by reference numeral 6a is a gate electrode, and a transistor is formed at a portion where the gate electrode intersects the element region (a portion surrounded by a broken line Tr1 or a broken line Tr2). As shown in FIG. 4, it became clear that innumerable polysilicon residues 6 b were attached to the vicinity of the boundary between the element region 1 a and the buried layer 4.

  Further, as shown in FIG. 5, it has been clarified that the polysilicon residue 6 b is formed so as to continue along the boundary between the element region 1 b and the buried layer 4.

  The inventor of the present application extended the over-etching time of the polysilicon film 6 for gate electrode in order to prevent the generation of the residue 6b of silicon, but could not prevent the generation of the residue 6b. Therefore, it is considered that the generation of the residue 6b is not due to insufficient etching time.

  Based on the above examination results, the inventor of the present application considers that one of the causes of defective products in the conventional method for manufacturing a semiconductor device is the polysilicon film embedded in the depot portion of the embedded layer 4. FIG. 6 is a schematic diagram showing the cause of defective products in the depot generated in the conventional manufacturing process. That is, as shown in FIG. 6A, when the polysilicon film 6 for the gate electrode is formed on the buried layer 4 where the depot is generated by the conventional manufacturing method, the depot portion (broken line portion D) has a conductive property. A polysilicon film 6 is embedded. Then, the polysilicon film 6 buried in the depot portion cannot be completely removed by dry etching in the formation process of the gate electrode 6a and becomes a residue 6b. And since this residue 6b short-circuits adjacent wiring, it is thought that a defect generate | occur | produces.

(Manufacturing method of semiconductor device according to second study)
7 and 8 are cross-sectional views showing a method of manufacturing a semiconductor device according to a second study conducted by the inventors of the present application in the order of steps. FIG. 9 is a schematic diagram showing the cause of the generation of etching residues in the semiconductor device manufacturing method according to the second study conducted by the present inventors. FIG. 10 is a schematic diagram showing the shape of the sidewall formed when the sidewall insulating film is formed by the thermal CVD method and by the plasma CVD method.

  The inventor of the present application has studied a method of manufacturing a semiconductor device in which the end of the buried layer is formed so as to protrude toward the element region in order to prevent the occurrence of depots.

  Hereinafter, a method for manufacturing a semiconductor device, which has been secondly studied by the inventors of the present application, will be described with reference to FIGS.

First, steps required until a structure shown in FIG. First, a silicon oxide film 2 is formed on a silicon substrate 1 by a thermal oxidation method. Subsequently, a silicon nitride film (not shown) is formed on the silicon oxide film 2. Next, the silicon nitride film is patterned to form a silicon nitride film pattern 3a having an opening 3b. Next, a sidewall silicon oxide film (not shown) is formed on the entire upper surface of the silicon substrate 1 by a thermal CVD method using SiH ₄ and N ₂ O. The reason for forming the side wall silicon oxide film by the thermal CVD method will be described later. Next, the sidewall silicon oxide film is etched back to form a sidewall 12 made of silicon oxide on the side of the silicon nitride film pattern 3a. The structure shown in FIG. 7A is formed by the above process.

  Next, as shown in FIG. 7B, the silicon oxide film 2 and the silicon substrate 1 are etched using the silicon nitride film pattern 3a and the sidewalls 12 as a mask to form element isolation grooves 1a. Subsequently, a silicon oxide film 2a is formed on the surface of the element isolation trench 1a by a thermal oxidation method.

  Next, as shown in FIG. 7C, a buried layer 4 is formed on the entire upper surface of the silicon substrate 1 by high density plasma CVD (HDPCVD). At this time, the sidewall 12 is integrated with the buried layer 4 as shown by the broken line portion, and the end 4a of the buried layer 4 is projected to the element region 1b side.

  Next, as shown in FIG. 7D, the upper surface of the silicon substrate 1 is polished and planarized by the CMP method, and the buried layer 4 is separated.

  Next, as shown in FIG. 8A, the silicon nitride film pattern 3 is removed by etching using a chemical solution containing phosphoric acid.

  Thereafter, as shown in FIG. 8B, the silicon oxide film 2 exposed above the element region 1b is removed with a chemical solution containing hydrofluoric acid. In this step, the buried layer 4 is also etched to reduce the film thickness.

  Next, steps required until a structure shown in FIG. First, the silicon substrate 21 having the structure shown in FIG. 8B is thermally oxidized to form a well forming silicon film (not shown) on the element region 1b. Subsequently, the well 5 is formed by performing ion implantation using the well forming silicon oxide film as the through film. Then, after the well-forming silicon oxide film is removed with a chemical solution containing hydrofluoric acid, a gate insulating film 10 made of silicon oxide is formed in the element region 1b by a thermal oxidation method. Thereafter, a polysilicon film 6 is formed on the entire upper surface of the silicon substrate 1 to complete the structure shown in FIG.

  Next, as shown in FIG. 8D, a resist pattern (not shown) is formed on the polysilicon film 6, and the polysilicon film 6 is dry-etched using the resist pattern as a mask to form a gate electrode 6a. . Thereafter, sidewalls and source / drain regions are formed by the same method as in the prior art, and the manufacturing of the semiconductor device in the second study is completed.

  The inventor of the present application tried the method for manufacturing the semiconductor device according to the second study described above, but the residue of the polysilicon film 6 remains in the vicinity of the boundary between the element region 1b and the buried layer 4 even in the semiconductor device by this manufacturing method. I have.

  This is presumably because a level difference occurred because the etching rate of the buried layer 4 was different between the part where the buried layer 4 was the sidewall 12 and the other part, and the polysilicon film remained in this level difference part. In other words, in the method of manufacturing a semiconductor device according to the second study, the sidewall 12 is made a part of the buried layer 4 so that the end of the buried layer 4 is projected to the element region 1b side. . Thereby, it is possible to suppress the occurrence of a depot above the side wall 4a of the element isolation trench 1a.

  However, the etching rate for hydrofluoric acid is about 3.6 times higher in the silicon oxide film formed by the plasma CVD method than in the silicon oxide film formed by the thermal CVD method. For this reason, as shown in FIG. 9A, during the wet etching with the chemical solution containing hydrofluoric acid, the buried layer 4 is formed by the plasma CVD method rather than the portion of the sidewall 12 formed by thermal CVD. The part is etched quickly. For this reason, it is thought that a level | step difference generate | occur | produces in a boundary part (dashed line E part).

  Thereafter, as shown in FIG. 9B, the conductive polysilicon film 6 is buried in the stepped portion. As shown in FIG. 9C, it is considered that the polysilicon film 6 in the stepped portion is not completely removed by dry etching when forming the gate electrode 6a, and becomes a residue 6b (part indicated by a broken line F). It is done. And it is thought that the residue 6b short-circuits the gate electrodes 6a to generate defective products.

  In the semiconductor device manufacturing method according to the second study, the sidewall oxide film is formed by the thermal CVD method in order to form a large sidewall. That is, when a silicon oxide film is formed on the silicon nitride film pattern 3a by a thermal CVD method, a relatively flat surface is formed as shown by a broken line G portion in FIG. By etching this back, a large sidewall 12 can be formed on the side of the silicon nitride film pattern 3 as shown in FIG. On the other hand, when the silicon oxide film is formed by the plasma CVD method, as shown by a broken line H portion in FIG. When this is etched back, a small sidewall 12 is formed as shown in FIG. For this reason, it is more preferable to form the buried layer 4 and the sidewalls 12 by different methods.

  Based on the above examination, the inventors of the present application have come up with an embodiment of the present invention described below.

(Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. 11 to 14 are cross-sectional views showing the method of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps.

  First, steps required until a structure shown in FIG. First, the surface of the silicon substrate 21 is thermally oxidized in an oxidizing atmosphere to form a first oxide film 22 made of silicon oxide having a thickness of about 10 nm. Further, a first nitride film 23 made of silicon nitride is formed thereon with a thickness of about 150 nm by CVD. Next, the first nitride film 23 is thermally oxidized to form a second oxide film 24 made of silicon oxide with a thickness of about 10 nm. The second oxide film 24 can be formed by a CVD method other than the thermal oxidation method. Then, a second nitride film 25 made of silicon nitride is formed on the second oxide film 24 to a thickness of about 10 to 100 nm by CVD. The structure shown in FIG. 11A is completed through the above steps.

  Next, as shown in FIG. 11B, a photoresist pattern (not shown) is formed on the second nitride film 25, and this is used as a mask to form the second nitride film 25, the second nitride film 25, and the second nitride film 25. The layered structure 26 is formed by etching the oxide film 24, the first nitride film 23, and the first oxide film 22. Thereafter, the photoresist pattern is removed to complete the structure shown in FIG.

  Next, as shown in FIG. 11C, a third oxide film 27 made of silicon oxide is formed to a thickness of about 10 nm on the surfaces of the semiconductor substrate 21 and the layered structure 26 by thermal oxidation or CVD. Next, a silicon nitride film 28 having a thickness of about 50 to 300 nm is formed on the entire upper surface of the semiconductor substrate 21 by a thermal CVD method.

  Next, as shown in FIG. 11D, the silicon nitride film 28 formed on the entire upper surface of the semiconductor substrate 21 is etched back to form side walls 28 a on the side of the layered structure 26. At this time, part of the third oxide film 27 is also removed at the same time. On the other hand, since the second oxide film 24 is covered with the second nitride film 25, it remains without being removed.

  Next, as shown in FIG. 12A, the semiconductor substrate 21 is etched using the layered structure 26 and the sidewalls 28a as masks to form element isolation grooves 21a having a depth of about 400 nm. A flat portion under the layered structure 26 and the side wall 28a becomes an element region 21b.

  Next, steps required until the structure shown in FIG. First, the sidewall 28a and the second nitride film 25 are removed by wet etching with a chemical solution containing phosphoric acid. At this time, since the first nitride film 23 is covered with the first oxide film 22, the second oxide film 23, and the third oxide film 27, the first nitride film 23 is not etched when the sidewall 28a is removed. Remain. If silicon oxide is attached to the surface of silicon nitride, the sidewall 28a and the second nitride film 25 cannot be removed cleanly by wet etching using phosphoric acid. For this reason, it is preferable to pre-process the entire upper surface of the silicon substrate 21 with a chemical solution containing hydrofluoric acid as pre-processing. The second nitride film 25 prevents the second oxide film 24 from being removed by the pretreatment using hydrofluoric acid.

  Next, in order to recover the damage received by the element isolation trench 21a by dry etching, the inside of the element isolation trench 21a is thermally oxidized to form a thermal oxide film 29 made of silicon oxide with a thickness of about 10 nm. As described above, the structure shown in FIG. 12B is completed.

  Next, as shown in FIG. 12C, a buried layer 30 made of silicon oxide is formed on the entire upper surface of the semiconductor substrate 21 to a thickness of about 500 to 1000 nm by HDPCVD (High Density Plasma CVD) method. Then, the element isolation trench 21a is completely embedded.

  Next, as shown in FIG. 12D, the buried layer 30 is separated and planarized by polishing by the CMP method. At this time, the first nitride film 23 serves as a stopper for polishing by the CMP method. In this manner, the buried layer 30 is obtained in which the end portion 30a projects toward the element region 21b and the etching rate with respect to hydrofluoric acid is uniform. During the planarization by this CMP method, the second oxide film 24 made of silicon oxide is also removed, and the first nitride film 23 is exposed. Further, since the first nitride film 23 is covered with the second oxide film 24 until CMP polishing is performed, the first nitride film 23 is kept in a uniform thickness. Since the first nitride film 23 serves as a CMP polishing stopper for the buried layer 30, the shape (thickness) of the buried layer 30 can also be planarized with a uniform shape (height) on the silicon substrate 1.

  Next, as shown in FIG. 13A, wet etching is performed with a chemical solution containing hydrofluoric acid to remove silicon oxide remaining on the first nitride film 23. This is because it is necessary to clean the surface of the first nitride film 23 in order to reliably remove the first nitride film 23 in the next step. Subsequently, wet etching is performed with a chemical solution containing phosphoric acid to remove the first nitride film 23. Thereafter, wet etching is performed with a chemical solution containing hydrofluoric acid to remove the first oxide film 22. The buried layer 30 is also etched by wet etching using hydrofluoric acid to reduce the film thickness. However, since the buried layer 30 has the end 30a projecting toward the element region 1b and the etching rate with respect to hydrofluoric acid is uniformly formed, almost no depots or steps are generated. The structure shown in FIG. 13A is completed through the above steps.

  Next, as shown in FIG. 13B, a well oxide film 31 made of silicon oxide is formed on the element region 1b by thermal oxidation. Thereafter, using the well oxide film 31 as a through film, p-type impurities are ion-implanted into the semiconductor substrate 21 to form a p-type well 32 in the element region 1b.

  Next, steps required until a structure shown in FIG. First, the well oxide film 31 is removed by etching using a chemical solution containing hydrofluoric acid. Even in this step, the buried layer 30 is etched, but since the end 30a protrudes to the element region 21b side and the etching rate is uniform, no depot or step is generated in the buried layer 30. Next, the exposed surface of the element region 1b is thermally oxidized to form a gate insulating film 33 made of silicon oxide to a thickness of about 2 to 20 nm.

  When the thickness of the gate insulating film 33 is made different between the high-voltage and low-voltage MOS transistors, first, a partial etching resist pattern (not shown) is formed on the region where the thick gate insulating film 33 is formed. Z). Next, the gate insulating film 33 in a region not covered with the partial etching resist pattern is removed with a chemical solution containing hydrofluoric acid. Thereafter, after removing the partial etching resist pattern, the entire upper surface of the silicon substrate 1 is thermally oxidized to grow a gate insulating film 33. Thus, a thick gate insulating film 33 is formed in a region that is not partially etched, and a thin gate insulating film 33 is formed in a region that is partially etched.

  Thereafter, a polysilicon film 34 for a gate electrode is formed on the gate insulating film 33 and the element isolation film 30 to a thickness of about 180 nm. The polysilicon film 34 may be formed using, for example, a low pressure CVD method using silane or the like as a reaction gas. As described above, the structure shown in FIG. 13C is completed.

  Next, as shown in FIG. 13D, a resist pattern 36 is formed on the polysilicon film 34, and the polysilicon film 34 is dry-etched using the resist pattern 36 as a mask to form a gate electrode 34a. Since no depot or step is generated in the buried layer 30, the gate electrode 34a can be formed without forming a polysilicon residue by dry etching. Thereafter, the resist pattern 36 is removed.

  Next, as shown in FIG. 14A, n-type impurities are ion-implanted into the semiconductor substrate 21 to form source / drain extensions 37 on the side of the gate electrode 34a. In order to prevent the concentration distribution of the source / drain extension 37 from diffusing in the subsequent thermal process, the semiconductor substrate 21 is annealed at this point to diffuse the source / drain extension 37 to some extent in advance. You may keep it.

  Subsequently, a sidewall insulating film 38 made of silicon oxide is formed on the entire upper surface of the semiconductor substrate 21 by a CVD method.

  Next, as shown in FIG. 14B, the sidewall insulating film 38 is etched back, leaving the sidewall insulating film 38 as a sidewall 38a beside the gate electrode 34a. Thereafter, n-type impurities are ion-implanted into the semiconductor substrate 21 to form source / drain regions 39 on the side of the gate electrode 34a. As described above, the structure shown in FIG. 14B is completed, and the semiconductor device (transistor) 40 is completed.

  As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, a groove is formed by dry etching using the layer structure 26 and the side wall 28a made of silicon nitride as a mask, and then the side wall 28a is formed. After the removal, the buried layer 30 is formed. Thereafter, the buried layer 30 is planarized. As a result, the upper end 30a of the buried layer 30 protrudes toward the element region 21b, and the etching rate of the buried layer 30 with respect to hydrofluoric acid can be made uniform. Therefore, even when the treatment is performed with a chemical solution containing hydrofluoric acid, depots and steps are hardly generated in the buried layer 30. For this reason, in the step of dry etching the polysilicon film 34 to form the gate electrode 34a, no residue of the polysilicon film is generated on the buried layer 30, and generation of defective products can be suppressed.

  Further, since the upper surface of the first nitride film 23 constituting a part of the layered structure 26 is covered with the second oxide film 24, the first nitride film 23 that functions as a stopper film in the planarization process of the buried layer 30 is formed. The height can be kept uniform. As a result, the flattened buried layer 30 can have a uniform shape (thickness) on the semiconductor substrate 21, and generation of defective products due to variations in the shape (height) of the buried layer 30 can be suppressed. .

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

  (Supplementary Note 1) A layered structure including a first oxide film, a first nitride film, a second oxide film, and a second nitride film is formed on a semiconductor substrate, and a sidewall is formed on the layered structure. Grooves are formed in the semiconductor substrate using the layered structure and sidewalls as a mask, the sidewalls are removed, a buried layer is formed on the semiconductor substrate, the buried layer is planarized, and at least one of the layered structures is formed. A method for manufacturing a semiconductor device, comprising removing a portion.

  (Additional remark 2) The said planarization is performed on the basis of the height of a said 1st nitride film, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 3) The said sidewall is a nitride film, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.

  (Additional remark 4) Before forming the said side wall, the 3rd oxide film which coat | covers the said layered structure is further formed, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 3 characterized by the above-mentioned .

  (Supplementary note 5) The method of manufacturing a semiconductor device according to supplementary note 4, wherein the first nitride film is surrounded by the first oxide film, the second oxide film, and the third oxide film. .

  (Supplementary note 6) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein the second nitride film is also removed when the sidewall is removed.

  (Additional remark 7) The said planarization is performed using the said 1st nitride film as a stopper, The manufacturing method of the semiconductor device of Additional remark 6 characterized by the above-mentioned.

  (Supplementary note 8) By the planarization, the buried layer is separated, and an upper end portion thereof is formed in a portion protruding from the groove, and the buried layer is formed by the end portion and the other portion. 8. The method of manufacturing a semiconductor device according to any one of appendices 1 to 7, wherein etching rates for acids are equal.

  (Appendix 9) The semiconductor according to appendix 7 or 8, wherein the layered structure is removed by removing the first nitride film by wet etching and then removing the first oxide film by wet etching. Device manufacturing method.

FIG. 1A to FIG. 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art in the order of steps (No. 1). 2A to 2D are cross-sectional views showing a method for manufacturing a semiconductor device according to the prior art in the order of steps (No. 2). FIG. 3 is a schematic diagram showing a result of observing a cross section of a semiconductor substrate in the middle of a method for manufacturing a semiconductor device according to the prior art. FIG. 4 is a schematic diagram showing a result of observing the surface of a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device from above. FIG. 5 is a schematic diagram illustrating a result of further enlarging a part of the sample illustrated in FIG. 4 and observing the sample from an obliquely upward direction. 6 (a) and 6 (b) are schematic diagrams showing the cause of defective products due to depots generated in the conventional manufacturing process. FIG. 7: is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd examination which this inventor performed in order of a process (the 1). FIG. 8: is sectional drawing which shows the manufacturing method of the semiconductor device based on the 2nd examination which this inventor performed in order of a process (the 2). FIG. 9 is a schematic diagram showing the cause of the generation of etching residues in the semiconductor device manufacturing method according to the second study conducted by the present inventors. FIG. 10 is a schematic diagram showing the shape of the sidewall formed when the sidewall insulating film is formed by the thermal CVD method and by the plasma CVD method. 11A to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps (No. 1). 12A to 12D are cross-sectional views showing the method of manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps (No. 2). FIGS. 13A to 13D are sectional views showing the semiconductor device manufacturing method according to the embodiment of the present invention in the order of steps (No. 3). 14 (a) and 14 (b) are cross-sectional views showing the method of manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps (No. 4).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon (semiconductor) substrate, 1a ... Element isolation groove, 1b ... Element area | region, 2, 2a ... Silicon oxide film, 3 ... Silicon nitride film, 3a ... Silicon nitride film pattern, 3b ... Opening, 4 ... Embedded layer, 4a ... end, 5 ... well, 6 ... polysilicon film, 6a ... gate electrode, 6b ... residue (polysilicon), 8a ... sidewall, 9 ... source / drain region, 10 ... gate insulating film, 11 ... resist pattern , 12 ... sidewalls, 21 ... silicon substrate (Si substrate), 21a ... element isolation trench, 21b ... element region, 22 ... first oxide film, 23 ... first nitride film, 24 ... second oxide film, 25 ... second nitride film, 26 ... layered structure, 27 ... third oxide film, 28 ... silicon nitride film, 28a ... sidewall, 29 ... thermal oxide film, 30 ... buried layer, 31 ... oxide film for well, 32 ... , 33 ... gate insulating film, 34 ... polysilicon film, 34a ... gate electrode, 36 ... resist pattern, 37 ... source / drain extension, 38 ... side wall insulating film, 38a ... side wall, 39 ... source / drain Region, 40... Semiconductor device, Tr ₁ , Tr ₂ ... Transistor.

Claims (5)

Forming a layered structure including a first oxide film, a first nitride film, a second oxide film, and a second nitride film on a semiconductor substrate;
Forming a sidewall in the layered structure;
Forming a groove in the semiconductor substrate using the layered structure and sidewalls as a mask;
Removing the sidewall,
Forming a buried layer on the semiconductor substrate;
Planarizing the buried layer;
A method for manufacturing a semiconductor device, wherein at least a part of the layered structure is removed. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization is performed based on a height of the first nitride film. The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall is a nitride film.   4. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a third oxide film covering the layered structure before forming the sidewall. 5.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first nitride film is surrounded by the first oxide film, the second oxide film, and the third oxide film.

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