JP2009231641A - Thin film transistor and active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a channel protective layer type thin film transistor of high mobility, high reliability and high productivity; and to provide an active matrix display device. <P>SOLUTION: The thin film transistor includes: a gate electrode provided on an insulating layer; a microcrystal silicon layer provided on the gate electrode through a gate insulating film; a channel protective layer provided on the microcrystal silicon layer; an adhesiveness-improving layer provided between the microcrystal silicon layer and the channel protective layer and composed of an amorphous material; and a source electrode and a drain electrode provided on at least one of the microcrystal silicon layer and the adhesiveness-improving layer and separated from each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor and an active matrix display device.

Thin film transistors (TFTs) are widely used in liquid crystal display devices, organic EL display devices, and the like.
Amorphous silicon TFTs that use amorphous silicon as the active layer of the TFT are required to improve mobility and stabilize the threshold. On the other hand, the development of TFTs using microcrystalline silicon as the active layer is energetic. Has been done. That is, by making the amorphous silicon portion of the gate interface microcrystallized, mobility can be improved and threshold fluctuation can be suppressed.

  On the other hand, as one of the TFT structures, there is a TFT having a channel protective layer made of, for example, silicon nitride for protecting a semiconductor layer in which a channel is formed. Since this channel protective layer type TFT can reduce the damage of the semiconductor layer on the back channel side as compared with the back channel cut type TFT having no channel protective layer, it can exhibit high performance and high reliability.

In the case of a TFT having a structure in which the above-described microcrystalline silicon and a channel protective layer are combined, the adhesion between the channel protective layer and the microcrystalline silicon provided on the microcrystalline silicon is low, and the channel protective layer is peeled off, yield (production) Performance), performance, and reliability.
Further, when patterning the channel protective layer, the etchant permeates into the interface with the lower insulating film from the grain boundary of the microcrystalline silicon exposed after the channel protective layer is etched, and the microcrystalline silicon is peeled off or the microcrystalline silicon is peeled off. And the etchant soaked through the interface between the channel protective layer and the microcrystalline silicon through the grain boundary, damages the gate insulating film under the microcrystalline silicon, or exposes the microcrystal exposed after etching the channel protective layer. Silicon may oxidize from the grain boundaries, causing contact failures and adversely affecting yield (productivity), performance, and reliability.

On the other hand, Patent Document 1 discloses a TFT in which an amorphous silicon layer is provided on microcrystalline silicon in a back channel cut type TFT that does not use a channel protective layer. However, since this TFT does not have a channel protective layer, the surface of the semiconductor layer is damaged, and there is room for improvement in terms of performance and reliability.
JP 2005-344845 A

  The present invention provides a channel protection layer thin film transistor and an active matrix display device with high mobility, high reliability, and high productivity.

  According to one embodiment of the present invention, a gate electrode provided over an insulating layer, a microcrystalline silicon layer provided over the gate electrode with a gate insulating film interposed therebetween, and an upper surface of the microcrystalline silicon layer. A channel protective layer provided on the surface, an adhesion improving layer made of an amorphous material provided between the microcrystalline silicon layer and the channel protective layer, and the microcrystalline silicon layer and the adhesion improving layer. There is provided a thin film transistor comprising a source electrode and a drain electrode provided on at least one of the electrodes and spaced apart from each other.

  According to another aspect of the present invention, a plurality of thin film transistors according to any one of claims 1 to 5 arranged in a matrix, and gate lines connected to respective gate electrodes of the thin film transistors, A signal line connected to one of each source electrode and each drain electrode of the thin film transistor, a pixel electrode connected to either one of the source electrode and each drain electrode of the thin film transistor, An active matrix display device comprising an optical element that generates at least one of a change in optical characteristics and light emission by an electrical signal applied to a pixel electrode is provided.

  According to the present invention, a channel protection layer type thin film transistor and an active matrix type display device having high mobility, high reliability, and high productivity are provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the present specification and the following drawings, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and the detailed description will be omitted as appropriate.
(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the structure of a thin film transistor according to the first embodiment of the invention.
As shown in FIG. 1, the thin film transistor 10 according to the first embodiment of the present invention includes a gate electrode 110, a gate insulating film 120, A microcrystalline silicon layer 140, an amorphous adhesion improving layer 150, and a channel protective layer 160 are provided.
In addition, the semiconductor device further includes a source electrode 181 and a drain electrode 180 which are provided so as to cover the microcrystalline silicon layer 140 and the channel protective layer 160. A contact layer 170 is provided between the microcrystalline silicon layer 140 (including part of the channel protective layer 160), the source electrode 181 and the drain electrode.

That is, the thin film transistor 10 includes a gate electrode 110 provided over a surface insulating substrate 105, a microcrystalline silicon layer 140 provided over the gate electrode 110 with a gate insulating film 120 interposed therebetween, and a microcrystalline silicon. A channel protective layer 160 provided over the layer 140; and an adhesion improving layer 150 made of amorphous, provided between the microcrystalline silicon layer 140 and the channel protective layer 160; the microcrystalline silicon layer 140; A source electrode 181 and a drain electrode 180 are provided separately from each other on at least one of the property improving layers 150. Between at least one of the microcrystalline silicon layer 140 and the adhesion improving layer 150 and the source electrode 181 and between at least one of the microcrystalline silicon layer 140 and the adhesion improving layer 150 and the drain electrode 180. And a contact layer 170 provided on the substrate.
Note that in the above, the source electrode 181 and the drain electrode 180 may be interchanged.

  For the substrate 105, for example, a translucent glass substrate is used. However, the present invention is not limited to this, and for example, an insulating layer provided on a non-transparent substrate such as silicon or stainless steel may be used. That is, the substrate 105 only needs to be surface insulating.

  For the gate electrode 110, for example, a refractory metal such as MoW, Ta, or W can be used, or an Al alloy mainly composed of Al with hillock countermeasures or Cu having a lower resistance can be used. good. However, the present invention is not limited to this, and various conductive materials can be used.

For the gate insulating film 120, for example, silicon oxide (SiO _x ) can be used. However, the present invention is not limited to this, and silicon nitride (SiN _x ), silicon oxynitride, or the like can be used, and a stacked film of these films may be used. However, the present invention is not limited to this.

The microcrystalline silicon layer 140 is formed by, for example, CVD (Chemical Vapor Deposition). Then, in the microcrystalline silicon layer 140, for example, or lattice image is observed by a transmission electron microscope, in Raman spectroscopic analysis, Raman shift is changed from 480 cm ^-1 derived from amorphous silicon to 500~520cm ^-1.
Note that the thickness of the microcrystalline silicon layer 140 may be approximately 30 nm in order to ensure electrical characteristics. Specifically, in order to improve reliability, only the interface layer may be microcrystalline silicon. The layer thickness of the microcrystalline silicon layer 140 can be about 10 nm to 60 nm.

  For the channel protective layer 160, silicon nitride having high resistance to mobile ions is used. However, the present invention is not limited to this, and silicon oxide, silicon oxynitride, or the like can be used.

For the contact layer 170, for example, an n ⁺ silicon layer containing a large amount of P or As (for example, at several atm%) can be used.

  For the source electrode 181 and the drain electrode 180, for example, various conductive materials such as a laminated film of Mo / Al / Mo and Ti / Al / Ti can be used.

In order to improve the durability of the thin film transistor 10, a passivation film made of an insulator such as SiN _x is often formed so as to cover the entire structure illustrated in FIG. It is omitted.

The adhesion improving layer 150 can be formed using an amorphous material that improves the adhesion between the channel protective layer 160 and the microcrystalline silicon layer 140.
In order to ensure conductivity in a region of the microcrystalline silicon layer 140 up to the interface with the channel protective layer 160 or conductivity between the microcrystalline silicon layer 140 and the contact layer 170, the adhesion improving layer 150 includes: An amorphous semiconductor material can be used.
In the thin film transistor 10 illustrated in FIG. 1, non-doped amorphous silicon is used as the adhesion improving layer 150. However, the present invention is not limited to this. For the adhesion improving layer 150, for example, silicon carbide (SiC), a Ge-based amorphous semiconductor, or an amorphous insulator such as silicon oxide is used. it can.

  This improves the adhesion between the channel protective layer 160 and the microcrystalline silicon layer 140, prevents the channel protective layer 160 from being peeled off, and improves the yield (productivity), performance, and reliability. In addition, penetration of the etchant into the microcrystalline silicon layer 140 during patterning of the channel protective layer 160 can be prevented, damage to the gate insulating film 120 and peeling of the microcrystalline layer can be prevented, and the microcrystalline silicon layer 140 can be separated. Contact failure due to oxidation from the grain boundary can be prevented, and yield (productivity), performance, and reliability are improved.

  As described above, the thin film transistor 10 according to this embodiment can provide a channel protective layer type thin film transistor with high mobility, high reliability, and high productivity.

  Note that, as described later, in the case where the light-transmitting substrate 105 is used and the channel protective layer 160 is formed in a self-aligned manner with respect to the gate electrode 110 by a backside exposure method, the microcrystalline silicon layer 140 serving as an active layer is formed. And the total layer thickness of the adhesion improving layer 150 provided thereon is preferably 100 nm or less. In addition, as described above, considering that the thickness of the microcrystalline silicon layer 140 is 25 nm to 60 nm, the thickness of the adhesion improving layer 150 is preferably 10 nm to 75 nm, and more preferably 10 to 50 nm.

Further, as illustrated in FIG. 1, generally, the outer shape of the channel protective layer 160 when viewed from the substrate vertical direction is smaller than the outer shape of the microcrystalline silicon layer 140. In the thin film transistor 10 according to the present embodiment, the adhesion improving layer 150 may be provided between the channel protective layer 160 and the microcrystalline silicon layer 140. Therefore, as illustrated in FIG. The planar shape when viewed from the substrate vertical direction can be substantially the same as the planar shape when the channel protective layer 160 is viewed from the substrate vertical direction.
However, the present invention is not limited to this, and the planar shape of the adhesion improving layer 150 when viewed from the substrate vertical direction may be larger than the planar shape of the channel protective layer 160 when viewed from the substrate vertical direction.

(First comparative example)
FIG. 2 is a schematic cross-sectional view illustrating the structure of the thin film transistor of the first comparative example.
As shown in FIG. 2, the thin film transistor 90 of the first comparative example is not provided with an adhesion improving layer with respect to the thin film transistor 10 according to the present embodiment. That is, it is a channel protective layer type thin film transistor including the microcrystalline silicon layer 140 and the channel protective layer 160. The channel protective layer 160 is made of silicon nitride.
In this case, the adhesiveness between the channel protective layer 160 and the microcrystalline silicon layer 140 is low, and the channel protective layer 160 is peeled off, which adversely affects yield, performance, and reliability.

  Microcrystalline silicon has lower adhesion to other surfaces (in this case, the channel protective layer 160) than amorphous silicon. This is because, in the case of microcrystalline silicon, stress acts on the crystal grain boundary during crystal growth, and the shape of the microscopic irregularities existing on other surfaces and the crystal grain boundary of microcrystalline silicon It is considered that mismatching occurs without matching, and as a result, adhesion to other surfaces is assumed to be reduced. In particular, in the case of microcrystalline silicon containing hydrogen, dangling bonds are terminated with hydrogen. Furthermore, when the channel protective layer is a relatively low temperature silicon nitride film formed by plasma CVD or the like, a large amount of hydrogen is contained in the film surface in the same manner as amorphous silicon, and dangling bonds at the interface are terminated with hydrogen. As a result, the effect of improving the adhesiveness due to chemical affinity cannot be expected, and the adhesiveness is particularly reduced. For this reason, in the case of this comparative example, the channel protective layer 160 is easily peeled off.

Further, in the case of this comparative example, the etchant when patterning the channel protective layer 160 damages the gate insulating film 120 through the grain boundary of the microcrystalline silicon layer 140, and further, after the channel protective layer 160 is etched. The exposed microcrystalline silicon layer 140 is oxidized from the grain boundary to cause a contact failure, which adversely affects yield, performance, and reliability.
For example, when a wet etching method mainly using dilute hydrofluoric acid is used to etch the channel protective layer 160, the amorphous silicon serves as an etching stopper in a thin film transistor using amorphous silicon as an active layer, and the above problem occurs. do not do. However, when the microcrystalline silicon layer 140 is used as the active layer as in the thin film transistor 90 of this comparative example, the gate insulating film 120 is damaged due to the penetration of the etchant from the crystal grain boundary, and the gate-source. The short circuit between the drains occurs or the exposed microcrystalline silicon layer peels off, resulting in a decrease in yield.

  On the other hand, since the thin film transistor 10 according to the present embodiment uses the adhesion improving layer 150 made of amorphous material, the microscopic irregularities existing on the other surface and the adhesion improving layer made of amorphous material The interfaces of these are highly coincident and no mismatch is considered to occur. This improves adhesion and prevents the etchant from penetrating into the microcrystalline silicon layer 140 when patterning the channel protective layer 160, so that the gate insulating film 120 is damaged or the microcrystalline silicon layer 140 becomes grainy. Contact failure due to oxidation from the field can be prevented, and productivity, performance and reliability are improved.

(Second comparative example)
FIG. 3 is a schematic cross-sectional view illustrating the structure of the thin film transistor of the second comparative example.
As shown in FIG. 3, the thin film transistor 91 of the second comparative example is not provided with a channel protective layer as compared with the thin film transistor 10 according to this embodiment illustrated in FIG. 1. That is, the thin film transistor is a back channel cut thin film transistor including the microcrystalline silicon layer 140. An amorphous silicon layer 145 is provided on the microcrystalline silicon layer 140.

  In the thin film transistor 91 of this comparative example, in order to reduce the influence of damage to the amorphous silicon layer 145 due to the formation process of the contact layer 170, the source electrode 181 and the drain electrode 180, the layer thickness of the amorphous silicon layer 145 is, for example, The thickness is set to 100 nm, which is thicker than 50 nm, which is the thickness of the adhesion improving layer 150 in the thin film transistor 10 according to this embodiment.

  In Patent Document 1, a thin film transistor having a structure similar to that of the thin film transistor 91 of the second comparative example illustrated in FIG. 3 is disclosed. Then, the contact layer 170 and the amorphous silicon layer 145 are joined, and the amorphous silicon layer 145 and the microcrystalline silicon layer 140 are joined, thereby reducing band gap mismatch and leakage current due to tunneling conduction through defects. Is going to decrease.

  However, since the thin film transistor of Patent Document 1 and the thin film transistor 91 of this comparative example do not have a channel protective layer, the surface of the semiconductor layer on the back channel side (in this case, the amorphous silicon layer 145) is not formed during the manufacturing process. Performance and reliability are low, such as damage and leakage due to back channel interface states and characteristic variations.

  On the other hand, the thin film transistor 10 according to the present embodiment includes the channel protective layer 160, and the adhesion improving layer 150 improves the adhesion of the channel protective layer 160 to the microcrystalline silicon layer 140. Thus, a channel protective layer type thin film transistor with high mobility, high reliability, and high productivity can be provided.

(Second Embodiment)
FIG. 4 is a schematic cross-sectional view illustrating the structure of a thin film transistor according to the second embodiment of the invention.
As shown in FIG. 4, in the thin film transistor 20 according to the second embodiment of the present invention, the shape of the adhesion improving layer 150 is different from that of the thin film transistor 10 illustrated in FIG.

That is, in the thin film transistor 10 illustrated in FIG. 1, the planar shape of the adhesion improving layer 150 when viewed from the substrate vertical direction is substantially the same as the planar shape of the channel protective layer 160 when viewed from the substrate vertical direction. However, in the thin film transistor 20 illustrated in FIG. 4, the planar shape of the adhesion improving layer 150 when viewed from the substrate vertical direction is substantially the same as the planar shape of the microcrystalline silicon layer 140 when viewed from the substrate vertical direction. It is said that it is the same. Except for the shape of the adhesion improving layer 150, it can be the same as that of the thin film transistor 10, and thus description thereof is omitted.
The thin film transistor 20 having such a structure can also provide a channel protective layer type thin film transistor having high mobility, high reliability, and high productivity.

FIG. 5 is a schematic cross-sectional view illustrating the structure of another thin film transistor according to the second embodiment of the invention.
As shown in FIG. 5, in another thin film transistor 21 according to the second embodiment of the present invention, the structure of the gate insulating film 120 is different from the thin film transistor 20 illustrated in FIG.
That is, in the thin film transistor 20 illustrated in FIG. 4, the gate insulating film 120 is a single layer film made of silicon oxide. However, in the thin film transistor 21 illustrated in FIG. 5, the gate insulating film 120 is the lower gate insulating film ( For example, it has a stacked structure in which a silicon oxide film) 121 and an upper gate insulating film (for example, silicon nitride film) 130 are stacked. Except for the gate insulating film 120, the structure can be the same as that of the thin film transistor 20, and thus the description thereof is omitted.
The thin film transistor 21 having such a structure can also provide a channel protective layer type thin film transistor having high mobility, high reliability, and high productivity.
In addition, since the thin film transistor 21 has a stacked structure of the gate insulating film 120, the gate insulating film 120 has more stable electric characteristics than the thin film transistor 20 or the thin film transistor 10 with a single layer, and has high performance and high reliability. Can be provided.

  Note that, as in the thin film transistors 20 and 21 illustrated in FIGS. 4 and 5, the planar shape of the adhesion improving layer 150 when viewed from the substrate vertical direction is as viewed from the substrate vertical direction of the microcrystalline silicon layer 140. When the shape is substantially the same as the planar shape, the shape processing of the adhesion improving layer 150 and the microcrystalline silicon layer 140 can be performed at the same time, which is advantageous in that the productivity is further improved.

(Third embodiment)
The third embodiment is an active matrix display device using the above thin film transistor. Hereinafter, as an example, an active matrix liquid crystal display device using the thin film transistor 21 illustrated in FIG. 5 will be described.

FIG. 6 is a schematic view illustrating the configuration structure of the main part of an active matrix display device according to the third embodiment of the invention.
That is, FIG. 6A is a schematic plan view illustrating the configuration of one pixel, which is a main part of the active matrix display device 30 according to the third embodiment of the invention, and FIG. ) Is a cross-sectional view taken along line AA of FIG. FIG. 6B is an enlarged view of FIG. 6A.
As shown in FIG. 6, the active matrix display device 30 according to the third embodiment of the present invention includes the above-described thin film transistors 21 arranged in a matrix, and FIG. 6 shows one of the elements. The part is illustrated.
The active matrix display device 30 is connected to the scanning line 210 connected to the gate electrode 110 of the thin film transistor 21, the signal line 220 connected to the source electrode 181 of the thin film transistor 21, and the drain electrode 180 of the thin film transistor 21. A pixel electrode 190 and an optical element (in this case, a liquid crystal layer) whose optical characteristics are changed by an electric signal applied to the pixel electrode 190 are provided.

Note that the liquid crystal layer is provided between the pixel electrode 190 and a counter electrode (not shown) provided to face the pixel electrode 190.
In the above description, the source electrode 181 and the drain electrode 180 may be interchanged.
In addition, the active matrix display device 30 illustrated in FIG. 6 further includes an auxiliary capacitance line 230 and an auxiliary capacitance electrode 240 that are provided in parallel to the scanning line 210.

  In the above, the optical element is not limited to the liquid crystal layer, and may be one that emits light by an electrical signal, such as an organic EL layer. That is, the optical element changes at least one of optical characteristics and emits light according to an electrical signal.

FIG. 7 is a circuit diagram illustrating an equivalent circuit of an active matrix display device according to the third embodiment of the invention.
As shown in FIG. 7, in one element of the active matrix display device 30 according to the third embodiment of the present invention, the liquid crystal layer 301 serving as the optical element 300 includes the pixel electrode 190 and the counter electrode 310. It is an electric load that is sandwiched, and is connected in parallel with the auxiliary capacitance Cs formed by the auxiliary capacitance electrode 240. These are connected to the signal line 220 through the thin film transistor 21, and the gate electrode 110 of the thin film transistor 21 is sequentially turned on / off by the scanning line 210, and a desired charge is written in the liquid crystal layer 301. 30 displays.

(Example)
As an example of the active matrix display device 30 according to this embodiment, a manufacturing method thereof will be described.
FIG. 8 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the main part of the active matrix display device according to the example of the invention.
FIG. 9 is a schematic cross-sectional view in order of the processes following FIG.
In these drawings, the left side exemplifies the region of the thin film transistor portion, and the right side exemplifies the region of the scanning line pad portion 212.

As shown in FIG. 8A, first, after forming a SiO ₂ film as the base layer 106 on the glass substrate 105, a MoW film serving as the scanning line 210 and the gate electrode 110 was formed, The gate electrode 110 and the scanning line pad portion 212 were formed by patterning.

Next, as shown in FIG. 8B, a SiOx film (lower gate insulating film 121) and a SiNx film (upper gate insulating film 130) to be the gate insulating film 120 are formed by plasma CVD, and The microcrystalline silicon film 141 that becomes the microcrystalline silicon layer 140 is continuously formed with a thickness of 30 nm by using the plasma CVD method without breaking the vacuum, and then the amorphous silicon film 151 that becomes the adhesion improving layer 150. Was formed with a thickness of 20 nm, and a SiN film 161 to be the channel protective layer 160 was formed with a thickness of 200 nm.
As in this embodiment, by continuously forming the SiOx film (the lower gate insulating film 121) to the SiN film 161 without breaking the vacuum, it is possible to avoid mixing impurities.
In the above, the microcrystalline silicon film 141 is formed using a mixed gas of silane and hydrogen. At this time, the flow rate ratio between silane and hydrogen is, as an example of the conditions for forming the microcrystalline silicon film 141, hydrogen = 100 in proportion to silane = 2, and the input RF power density is 0.6 W / cm ² . . The deposition rate is about 0.2 nm / s.
On the other hand, in the amorphous silicon film 151, the flow rate ratio between silane and hydrogen was set to hydrogen = 100 with respect to silane = 15, and the input RF power density was set to 0.12 W / cm ² . The film formation rate is 1 nm / s.

Next, as shown in FIG. 8C, photolithography using a backside exposure method by forming a resist on the front surface 102 of the substrate 105 and irradiating ultraviolet rays from the back surface 101 of the substrate 105, and dilute fluorine. The SiN film 161 was processed by wet etching mainly including an acid, and the channel protective layer 160 was formed in a self-aligned manner with respect to the gate electrode 110.
At this time, in order to use ultraviolet irradiation from the back surface 101, the total film thickness of the microcrystalline silicon film 141 and the amorphous silicon film 151 is desirably 100 nm or less in view of productivity.
In addition, when a positive potential is applied to the gate electrode 110, a region where a channel is formed is about 30 nm at most. Therefore, the thickness of the microcrystalline silicon film 141 having a low deposition rate is set to 250 to 60 nm. Is preferred. The thickness of the amorphous silicon film 151 is preferably 10 to 75 nm, and more preferably 10 to 50 nm.

Next, as shown in FIG. 8D, an n ⁺ silicon film 171 to be the contact layer 170 was formed on the entire surface.
Note that the amorphous silicon film 151 prevents the microcrystalline silicon film 141 from being exposed to the air and oxidizing the grain boundaries after the channel protective layer 160 is patterned and before the n ⁺ silicon film 171 is formed.

Next, as shown in FIG. 9A, the n ⁺ silicon film 171, the amorphous silicon film 151, and the microcrystalline silicon film 141 are patterned into a predetermined shape to form the contact layer 170, the adhesion improving layer 150, and the microscopic silicon film 141. A crystalline silicon layer 140 was formed.

  Next, as shown in FIG. 9B, a transparent electrode film made of ITO (Indium-Tin-Oxide) is sputtered to 40 nm on the entire surface, and then patterned into a predetermined shape to form a pixel electrode 190. did.

  Next, as illustrated in FIG. 9C, an insulating film (a lower gate insulating film 121 and an upper gate insulating film 130 on the scanning line pad portion 212 is used as a connection pad with the peripheral circuit of the scanning line 210. ) Was removed.

  Then, as shown in FIG. 9D, the signal line 220, the source electrode 181 and the drain electrode 180 are formed by sputtering with 50 nm thick Mo, 300 nm thick Al, and 50 nm thick Mo. Then, the signal line 220, the source electrode 181, the drain electrode 180, and the conductive part 213 of the scanning line pad part 212 were formed by patterning into a predetermined shape.

  After that, as a protective film, SiN is formed to a thickness of 200 nm by plasma CVD, the protective film on the electrode extraction pad and the pixel electrode is removed, and then combined with the counter substrate having the counter electrode, Liquid crystal was sealed in, and an optical element such as a polarizing plate, a peripheral circuit, and a backlight were incorporated to produce an active matrix display device 30 illustrated in FIG.

  The thin film transistor 21 of the active matrix display device 30 manufactured in this manner has a lower probability of point defects than the thin film transistor 90 illustrated in FIG. This is because the defective characteristics of the thin film transistor due to insufficient adhesion between the microcrystalline silicon layer 140 and the channel protective layer 160 is reduced, and the point defects due to short-circuiting of the auxiliary capacitance electrode 240 are reduced. It is considered that the attack on the insulating film for the auxiliary capacitance electrode 240 due to the penetration of the etchant when the SiN film as the channel protective layer 160 is etched is considered to be reduced.

  In addition, it was found that the thin film transistor 21 manufactured in this manner has a higher electric field mobility of the thin film transistor than the thin film transistor 90 illustrated in FIG. Although the cause of this is not clear, when a thin active layer is used, it is considered that not only the interface with the gate electrode 110 but also the state of the back gate interface affects the electrical characteristics of the thin film transistor. It is presumed that the interface state between the adhesion improving layer 150 and the channel protective layer 160 (this example) is better than the interface with the channel protective layer 160 (for example, the first comparative example). Is done.

The example in which the thin film transistor of the present embodiment is applied to an active matrix liquid crystal display device has been described above. However, the present invention is not limited to this, and may be applied to, for example, an active matrix organic EL (Electro Luminescence) display device. it can.
FIG. 10 is a circuit diagram illustrating an equivalent circuit of another active matrix display device according to the third embodiment of the invention.
FIG. 10A is an example of an equivalent circuit of an active matrix organic EL display device, and FIG. 10B is an example of an equivalent circuit of another active matrix organic EL display device.
As shown in FIG. 10A, the active matrix organic EL display device 60 according to the present embodiment is connected to the first transistor Tr <b> 1 for pixel selection and the power supply line 320 and drives the organic EL 302. Transistor DTr. The thin film transistor according to the above embodiment can be used for the first transistor Tr1 and the pixel driving transistor DTr.
As shown in FIG. 10B, another active matrix organic EL display device 61 according to this embodiment includes first to fourth transistors for pixel selection Tr1 to Tr4 and transistors for pixel driving. A DTr is provided. The gate of the second transistor Tr2 is connected to the _nth scanning line 210n, and the gates of the first transistor Tr1 and the fourth transistor Tr4 are connected to the (n-1) th scanning line 210n _-1 . . The thin film transistor according to the above embodiment can be used for the first to fourth transistors Tr1 to Tr4 and the pixel driving transistor DTr.
Since these active matrix type organic EL display devices 60 and 61 use the thin film transistor according to the embodiment of the present invention, by using the channel protective layer type thin film transistor having high mobility, high reliability, and high productivity. An active matrix display device with high display performance, high reliability, and high productivity can be provided.
In particular, since a positive potential is applied to the gate of DTr or Tr3 during most of the driving time, high reliability is required as a TFT.

In each of the above embodiments, the material of the gate electrode 110, the material of the signal line 220, and the like can be changed as appropriate. The gate insulating film 120 in contact with the microcrystalline silicon layer 140 may be SiO ₂ , and very thin (5 nm or less) amorphous silicon is inserted between the gate insulating film 120 and the microcrystalline silicon layer 140. May be.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with regard to the specific configuration of each element constituting the thin film transistor and the active matrix display device, those skilled in the art can implement the present invention in the same manner by selecting appropriately from a known range, and the same effect can be obtained. As long as it is within the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.
In addition, all thin film transistors and active matrix display devices that can be implemented by those skilled in the art based on the above-described thin film transistors and active matrix display devices as embodiments of the present invention are also included in the gist of the present invention. As long as it is included, it belongs to the scope of the present invention.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a schematic cross-sectional view illustrating the structure of a thin film transistor according to a first embodiment of the invention. It is a typical sectional view which illustrates the structure of the thin film transistor of the 1st comparative example. It is a typical sectional view which illustrates the structure of the thin film transistor of the 2nd comparative example. FIG. 6 is a schematic cross-sectional view illustrating the structure of a thin film transistor according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the structure of another thin film transistor according to the second embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of the active matrix display device which concerns on the 3rd Embodiment of this invention. 10 is a circuit diagram illustrating an equivalent circuit of an active matrix display device according to a third embodiment of the invention; FIG. FIG. 6 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the main part of the active matrix display device according to the example of the invention. FIG. 9 is a schematic cross-sectional view in order of the steps, following FIG. 8. 10 is a circuit diagram illustrating an equivalent circuit of another active matrix display device according to the third embodiment of the invention; FIG.

Explanation of symbols

10, 20, 21, 90, 91 Thin film transistor 30, 60, 61 Active matrix display device 101 Back surface 102 Surface 105 Substrate 106 Underlayer 110 Gate electrode 120 Gate insulating film 121 Lower gate insulating film 130 Upper gate insulating film 140 Microcrystal Silicon layer 141 Amorphous silicon film 145, 151 Amorphous silicon film 150 Adhesion improving layer 160 Channel protective layer 161 SiN film 170 Contact layer 171 n ⁺ Silicon film 180 Drain electrode 181 Source electrode 190 Pixel electrode 210, 210 _n , 210 _{n− 1} scanning line 212 scanning line pad part 213 conductive part 220 signal line 230 auxiliary capacity line 240 auxiliary capacity electrode 300 optical element 301 liquid crystal layer 302 organic EL layer 310 counter electrode 320 power line

Claims (6)

A gate electrode provided on the insulating layer;
A microcrystalline silicon layer provided over the gate electrode via a gate insulating film;
A channel protective layer provided on the microcrystalline silicon layer;
An adhesion improving layer made of an amorphous material provided between the microcrystalline silicon layer and the channel protective layer;
A source electrode and a drain electrode provided on at least one of the microcrystalline silicon layer and the adhesion improving layer and spaced apart from each other;
A thin film transistor comprising:   2. The thin film transistor according to claim 1, wherein the adhesion improving layer is made of amorphous silicon.   The thin film transistor according to claim 1 or 2, wherein the adhesion improving layer has a thickness of 10 nm to 50 nm.   The thin film transistor according to claim 1, wherein the planar shape of the adhesion improving layer is substantially the same as the planar shape of the microcrystalline silicon layer.   The thin film transistor according to claim 1, wherein the channel protective layer is made of silicon nitride. A plurality of thin film transistors according to any one of claims 1 to 5, arranged in a matrix,
A gate line connected to each gate electrode of the thin film transistor;
A signal line connected to one of each source electrode and each drain electrode of the thin film transistor;
A pixel electrode connected to one of the source electrode and the drain electrode of the thin film transistor;
An optical element that generates at least one of a change in optical characteristics and light emission by an electrical signal applied to the pixel electrode;
An active matrix display device comprising:

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