JP2009224667A - Field effect transistor, semiconductor device, control circuit, control method therefor, and insulated gate bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor, and the like, for reducing the influence of a pattern impedance of signal wiring, and for reducing outbreak voltage of a gate in a simple configuration. <P>SOLUTION: The field effect transistor includes a switching part 112 disposed between a gate 115 and a source 113 for short-circuiting the gate 115 and the source 113 based on a clamp signal 116. The switching part 112 is a PNP type transistor with an emitter and the gate 115 connected and a collector and the source 113 connected. The clamp signal 116 is input into the base of the PNP type transistor. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a field effect transistor, a semiconductor device, a control circuit, a control method thereof, and an insulated gate bipolar transistor.

  In a power supply circuit used in a half-bridge circuit, a full-bridge circuit, or a three-phase bridge circuit, one of the two field-effect transistors (FETs) is turned on in one arm portion. In some cases, the voltage between the drain and the source of the other field-effect transistor turned off rapidly increases.

  In addition, when the voltage between the drain and source of the field effect transistor that is turned off increases rapidly, the parasitic capacitance that the field effect transistor itself has between the drain and gate and between the gate and source is reduced. Due to the influence, the gate voltage of the field effect transistor may rise temporarily, and the field effect transistor may be turned on.

  When a field effect transistor to be turned off is turned on, a field effect transistor connected to the high voltage side (high side) and a field effect transistor connected to the low voltage side (low side) Both are turned on. Thus, when both the field effect transistor connected to the high voltage side and the field effect transistor connected to the low voltage side are turned on, there is a concern that an overcurrent may flow and the circuit system may be damaged in some cases. Arise.

  FIG. 9 is a diagram sequentially illustrating the operation of a conventional control circuit using field effect transistors. In FIG. 9, the field effect transistor 811 on the high voltage side (high side) is controlled by a gate signal transmitted from the gate driver 813 via the resistor 814. Further, the field effect transistor 821 on the low voltage side (low side) is controlled by a gate signal transmitted from the gate driver 823 via the resistor 824.

  FIG. 8 is a sequence diagram showing gate signals of the conventional control circuit shown in FIG. In the sequence diagram of the gate signal shown in FIG. 8, the period T1 is the operation of FIG. 9A, the period T2 is the operation of FIG. 9B, the period T3 is the operation of FIG. 9C, and the period T4 is Each corresponds to the operation of FIG.

  Here, in the period T1, the field-effect transistor 811 is turned on and the field-effect transistor 821 is turned off. As a result, a current 831 flows through the choke coil 830. In the period T2, the field effect transistor 811 is turned off and the field effect transistor 821 is turned off. For this reason, a current 832 flows through the choke coil 830.

  In the period T3, the field-effect transistor 811 is turned off and the field-effect transistor 821 is turned on. For this reason, a current 833 flows through the choke coil 830. In the period T4, the field-effect transistor 811 is turned off and the field-effect transistor 821 is turned off. For this reason, a current 834 flows through the choke coil 830.

  In FIG. 8, when a gate signal 704 having a rectangular shape is applied from the gate driver 813 to the field effect transistor 811, the voltage between the gate and the source of the field effect transistor 811 becomes a solid voltage signal 702. . When a rectangular gate signal 705 is supplied from the gate driver 823 to the field effect transistor 821, the voltage between the gate and the source of the field effect transistor 821 becomes a solid line voltage signal 703.

  Here, in the period T1, the sudden voltage 701 is such that both the low-voltage side field-effect transistor 821 and the high-voltage-side field effect transistor 811 are off, and the parasitic diode of the low-voltage side field-effect transistor 821. When the high-voltage side field-effect transistor 811 is turned on while a current flows from the source to the drain through the gate, the low-voltage-side field effect transistor 821 is turned off between the gate and the source. This voltage is temporarily generated due to parasitic capacitance or the like. When the sudden voltage 701 is generated, not only energy loss occurs but also there is a concern that an element failure due to an unexpected overcurrent occurs.

  In addition, when the current flowing through the choke coil 830 is opposite to the currents 831, 832, 833, and 834 shown in FIG. 9, the sudden voltage 701 is generated in the field effect transistor 811 on the high voltage side. That is, in this case, the signal waveform shown in FIG. 8 is switched between the high voltage side (high side) and the low voltage side (low side).

  Therefore, the sudden voltage 701 is such that the low-voltage side field-effect transistor 821 and the high-voltage side field-effect transistor 811 are both off, and the source-to-drain voltage is applied through the parasitic diode of the high-voltage side field-effect transistor 811. When the low-voltage side field-effect transistor 821 is turned on while a current is flowing in the direction, a parasitic capacitance or the like is generated between the gate and the source of the high-voltage-side field effect transistor 811 that is turned off. Will occur.

  In order to cope with the above problems, various driving methods shown in FIG. 7 have been proposed. FIG. 7 is a control circuit diagram illustrating a conventional method for dealing with the sudden voltage 701. FIG. 7A is a control circuit diagram for driving the gate drivers 613 and 623 using a drive power supply between a plus 10 volt voltage and a minus 5 volt voltage.

  FIG. 7B is a control circuit diagram in which capacitors 615 and 625 are added between the gate and the source. FIG. 7C is a control circuit diagram using gate drivers 616 and 626 with a clamping function. Detailed descriptions of the various control circuits shown in FIG. 7 are omitted.

Such a control circuit is disclosed in, for example, Patent Document 1 below.
JP 2002-112544 A JP 2000-217349 A

  In the conventional control circuit, there is a tendency that the impedance of the wiring pattern increases due to a long signal wiring line with the switching unit, and the switching characteristics of the field effect transistor deteriorate.

  The present invention has been made in view of the above-described problems, and provides a field-effect transistor or the like that can reduce the influence of pattern impedance of a signal wiring and reduce the sudden voltage of a gate with a simple configuration. Objective.

  The field effect transistor according to the present invention includes a switching unit that short-circuits between the gate and the source based on a clamp signal between the gate and the source.

  In the field effect transistor according to the present invention, the switching unit is preferably a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and a clamp signal is applied to a base of the PNP transistor. It is input.

  According to another aspect of the present invention, there is provided a semiconductor device including: a field effect transistor; and a switching unit that short-circuits between the gate and the source of the field effect transistor based on a clamp signal.

  In the semiconductor device according to the present invention, preferably, the switching unit is a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and a clamp signal is input to a base of the PNP transistor. It is characterized by that.

  A control circuit according to the present invention is a control circuit including the above-described field effect transistor, the first field effect transistor having a drain connected to the high voltage side, and a source connected to the low voltage side. A second field effect transistor, the source of the first field effect transistor is connected to the drain of the second field effect transistor, and the first field effect transistor and the second field effect transistor Are turned off and a current flows from the source to the drain through the parasitic diode of the second field effect transistor, and the second field effect transistor is turned on when the first field effect transistor is turned on. The switching portion of the second field effect transistor is connected to the second field effect transistor so as to mitigate the sudden voltage generated at the transistor gate. Based on the clamp signal input to the register, the gate and source of the second field effect transistor are short-circuited, or both the first field effect transistor and the second field effect transistor are turned off. When the second field effect transistor is turned on while a current is flowing from the source to the drain through the parasitic diode of the first field effect transistor, the gate of the first field effect transistor is In order to mitigate the sudden voltage that occurs, the switching unit of the first field effect transistor has a gate and a source of the first field effect transistor based on a clamp signal input to the first field effect transistor. It is characterized by short-circuiting between.

  In the control circuit according to the present invention, preferably, the switching unit is a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and the clamp signal is a gate of a corresponding field effect transistor. The gate signal is input to the base of a PNP transistor.

  Another control circuit according to the present invention is a control circuit including the above-described semiconductor device, and includes a first semiconductor device connected to the high voltage side and a second semiconductor device connected to the low voltage side. The first semiconductor device includes a first field effect transistor whose drain is connected to the high voltage side, and the second semiconductor device is a second field effect transistor whose source is connected to the low voltage side The source of the first field effect transistor is connected to the drain of the second field effect transistor, and the first field effect transistor and the second field effect transistor are both turned off and the second field effect transistor is When a current flows from the source to the drain through the parasitic diode of the field effect transistor and the first field effect transistor is turned on, the second field effect transistor In order to mitigate the sudden voltage generated at the gate of the second semiconductor device, the switching unit of the second semiconductor device is connected to the gate and source of the second field effect transistor based on the clamp signal input to the second semiconductor device. The first field effect transistor and the second field effect transistor are both turned off and current flows from the source to the drain through the parasitic diode of the first field effect transistor. When the second field effect transistor is turned on in a state where the first semiconductor device is switched, the switching unit of the first semiconductor device is configured to reduce the sudden voltage generated at the gate of the first field effect transistor. The gate and source of the first field effect transistor are short-circuited based on a clamp signal input to the device.

  In another control circuit according to the present invention, preferably, the switching unit is a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and the clamp signal is a corresponding field effect transistor. The gate signal to the gate of the PNP transistor is a signal input to the base of the PNP transistor.

  The field effect transistor control method according to the present invention includes a switching unit that short-circuits between the gate and the source based on a clamp signal between the gate and the source. Has a step of short-circuiting the gate and the source based on the clamp signal so as to alleviate the sudden voltage generated in the gate.

  In the field effect transistor control method according to the present invention, the switching unit is preferably a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and the switching unit is generated in the gate. A step of short-circuiting the gate and the source based on a clamp signal input to the base of the PNP transistor from the gate signal input line to the gate so as to alleviate the sudden voltage is characterized.

  According to another aspect of the present invention, there is provided a semiconductor device control method in which a semiconductor device includes a field effect transistor and a switching unit that short-circuits between the gate and the source of the field effect transistor based on a clamp signal. And the switching unit includes a step of short-circuiting the gate and the source based on the clamp signal so as to alleviate the sudden voltage generated in the gate.

  In the method of controlling a semiconductor device according to the present invention, preferably, the switching unit is a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and the clamp signal is a gate signal to the gate. The switching unit includes a step of short-circuiting the gate and the source based on the clamp signal so as to relieve the sudden voltage generated in the gate, which is input to the base of the PNP transistor from the input line.

  A control method of a control circuit according to the present invention is a control method of a control circuit including the above-described field effect transistor, wherein the control circuit includes a first field effect transistor whose drain is connected to the high voltage side. And a second field effect transistor whose source is connected to the low voltage side, the source of the first field effect transistor is connected to the drain of the second field effect transistor, and the first field effect The first field-effect transistor is turned on while both the first transistor and the second field-effect transistor are turned off and current flows from the source to the drain through the parasitic diode of the second field-effect transistor. In such a case, the switch of the second field effect transistor is set so as to reduce the sudden voltage generated at the gate of the second field effect transistor. Or a short circuit between the gate and the source of the second field effect transistor based on the clamp signal input to the second field effect transistor, or the first field effect The second field effect transistor is turned on while both the first transistor and the second field effect transistor are turned off and current flows from the source to the drain through the parasitic diode of the first field effect transistor. In this case, the switching portion of the first field effect transistor is based on the clamp signal input to the first field effect transistor so as to alleviate the sudden voltage generated at the gate of the first field effect transistor. And a step of short-circuiting between the gate and the source of the first field effect transistor.

  Another control circuit control method according to the present invention is a control circuit control method comprising the above-described semiconductor device, wherein the control circuit is connected to the first semiconductor device connected to the high voltage side and to the low voltage side. The first semiconductor device includes a first field effect transistor having a drain connected to the high voltage side, and the second semiconductor device includes a source on the low voltage side. A first field-effect transistor connected to a drain of the second field-effect transistor, the first field-effect transistor and the second field-effect transistor; The first field effect transistor was turned on while both the transistors were off and current was flowing from the source to the drain through the parasitic diode of the second field effect transistor. The switching portion of the second semiconductor device is based on the clamp signal of the second semiconductor device so as to alleviate the sudden voltage generated at the gate of the second field effect transistor. A step of short-circuiting between the gate and the source of the transistor, or the first field-effect transistor and the second field-effect transistor are both turned off and through the parasitic diode of the first field-effect transistor When the second field effect transistor is turned on while a current is flowing from the source to the drain, the first semiconductor is designed to reduce the sudden voltage generated at the gate of the first field effect transistor. The switching section of the device shorts between the gate and source of the first field effect transistor based on the clamp signal of the first semiconductor device. It characterized by having a step.

  In the control method of another control circuit according to the present invention, preferably, the switching unit is a PNP transistor in which an emitter and a gate are connected and a collector and a source are connected, and a clamp signal is supplied to the switching unit. The gate signal to the gate of the corresponding field effect transistor is a signal input to the base of each PNP transistor.

  In addition, the insulated gate bipolar transistor according to the present invention is characterized in that a switching unit is provided between the gate and the emitter to short-circuit the gate and the emitter based on a clamp signal.

  In the insulated gate bipolar transistor according to the present invention, the switching unit is preferably a PNP transistor, the emitter of the PNP transistor and the gate of the insulated gate bipolar transistor are connected, and the collector and insulated gate of the PNP transistor are connected. The emitter of the bipolar transistor is connected.

  In the semiconductor device according to the present invention, preferably, the field effect transistor is an insulated gate bipolar transistor, the source is an emitter of the insulated gate bipolar transistor, and the drain is a collector of the insulated gate bipolar transistor. Features.

  It is possible to provide a field effect transistor or the like that can reduce the influence of the pattern impedance of the signal wiring and reduce the sudden voltage of the gate with a simple configuration.

  The field effect transistor exemplified in this embodiment is a one-chip field effect transistor that is integrally provided with a switching unit having a gate clamp function. Further, the semiconductor device exemplified in this embodiment includes a switching portion having a gate clamp function in the vicinity of the field effect transistor between the gate and the source of the field effect transistor. In addition, this semiconductor device is a hybrid IC in which a field effect transistor and a switching unit are one-packaged and are provided close to each other.

  Therefore, in the semiconductor device and the like exemplified in this embodiment, the distance between the field effect transistor and the switching unit can be shortened. In addition, the field effect transistor and the semiconductor device exemplified in this embodiment can realize operation processing with reduced delay due to the influence of the wiring pattern impedance.

  In the field effect transistor and the semiconductor device exemplified in this embodiment, the switching unit can short-circuit the gate and the source of the field effect transistor at a desired timing. Therefore, an unexpected or undesired temporary increase in gate voltage (hereinafter referred to as a sudden voltage) caused by a parasitic capacitance of a field effect transistor is alleviated, and a temporary increase in gate voltage (hereinafter referred to as a sudden voltage). ) Can be reduced.

  Further, in the field effect transistor and the semiconductor device exemplified in this embodiment, when the switching unit is configured by a PNP transistor, the clamp signal for operating the switching unit is shared with the gate signal of the field effect transistor. can do. For this reason, it is not necessary to separately provide a circuit for generating a clamp signal, and the configuration of the control circuit can be simplified. For this reason, the control circuit can be reduced in size and weight, and an inexpensive control circuit can be realized.

  Therefore, each embodiment will be described in detail below based on the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating an N-channel field effect transistor of this embodiment. As shown in FIG. 1A, the N-channel field effect transistor 111 integrally includes a switching unit 112 that can short-circuit between the gate 115 and the source 113. The switching unit 112 can short-circuit between the gate 115 and the source 113 in the N-channel field effect transistor 111 element by the clamp signal 116.

  In addition, the clamp signal 116 is a gate signal that is input to the gate 115 due to a parasitic capacitance between the drain 114 and the gate 115 and a parasitic capacitance between the gate 115 and the source 113. The voltage is applied so as to mitigate sudden voltage generated between the source 115 and the source 113.

  That is, the sudden voltage generated between the gate 115 and the source 113 is reduced and alleviated by the switching unit 112 performing a short-circuit operation between the gate 115 and the source 113 based on the clamp signal 116. As a result, the N-channel field effect transistor 111 can suppress destruction and damage due to overcurrent of the control circuit including the N-channel field effect transistor 111.

  Since the N-channel field effect transistor 111 can short-circuit between the gate 115 and the source 113 on one chip, characteristic deterioration due to the influence of impedance due to the wiring pattern can be reduced. The switching unit 112 can use an FET, a transistor, a photocoupler, or the like. In addition, since FETs, transistors, photocouplers, and the like are a combination of a p-type semiconductor and an n-type semiconductor, they can be made into one chip.

  FIG. 1B is a diagram illustrating a semiconductor device 157 provided with the switching unit 152 in the vicinity of the N-channel field effect transistor 151. This semiconductor device 157 is typically a semiconductor device 157 in which an N-channel field effect transistor 151 and a switching unit 152 are integrally sealed in one package.

  As shown in FIG. 1B, the semiconductor device 157 includes an N-channel field effect transistor 151 and a switching unit 152 capable of short-circuiting between the gate 155 and the source 153 close to each other and sealed in one package. Prepare. Further, the switching unit 152 short-circuits between the gate 155 and the source 153 by the clamp signal 156.

  The clamp signal 156 is generated by the gate 155 regardless of whether the off signal is input to the gate 155 due to the parasitic capacitance between the drain 154 and the gate 155 and the parasitic capacitance between the gate 155 and the source 153. It is applied so as to mitigate sudden voltage generated between the source 153 and the like.

  That is, the sudden voltage generated between the gate 155 and the source 153 or the like is reduced and alleviated by the switching unit 152 performing a short-circuit operation between the gate 155 and the source 153 based on the clamp signal 156. As a result, the semiconductor device 157 can suppress destruction or damage due to overcurrent or the like of the control circuit including the semiconductor device 157.

  Next, the control circuit 200 using the semiconductor device 157 will be described with reference to FIG. FIG. 2 is a diagram illustrating a control circuit using the semiconductor device 157. In the following description, the same parts as those in FIG. 1B will be described with corresponding reference numerals. In addition, even when the field effect transistor 111 shown in FIG. 1A is used, the description is omitted here because the circuit configuration and operation processing are the same. In addition, for convenience of explanation, each signal passing through each signal line is described with reference to the symbol of the signal line.

  As illustrated in FIG. 2, the control circuit 200 includes a semiconductor device 1571 and a semiconductor device 1572. Further, both the semiconductor device 1571 and the semiconductor device 1572 have the same configuration as the semiconductor device 157 illustrated in FIG. The semiconductor device 1571 and the semiconductor device 1572 are sequentially connected from the high voltage side, the semiconductor device 1571 is connected to the high voltage side (high side), and the semiconductor device 1572 is connected to the low voltage side (low side).

  The semiconductor device 1571 of the control circuit 200 includes an N-channel field effect transistor 1511. The drain 1541 of the N-channel field effect transistor 1511 is connected to the high voltage side (Vdd). In addition, the semiconductor device 1571 includes a switching unit 1521 that can short-circuit between the gate 1551 and the source 1531 of the N-channel field effect transistor 1511.

  In addition, the control circuit 200 includes a gate driver 213 that applies a gate signal 1581 to the gate 1551 of the N-channel field effect transistor 1511 via the resistor 214. The gate driver 213 is driven at plus 10 volts with the potential of the source 1531 being 0 volts. In addition, the control circuit 200 includes a signal generation circuit 215 that generates a clamp signal 1561 that is applied to the switching unit 1521 and serves as a trigger for short-circuiting between the gate 1551 and the source 1531.

  In addition, the semiconductor device 1572 of the control circuit 200 includes an N-channel field effect transistor 1512. The source 1532 of the N-channel field effect transistor 1512 is connected to the low voltage side (Vss). The drain 1542 of the N-channel field effect transistor 1512 is connected to the source 1531 of the N-channel field effect transistor 1511. In addition, the semiconductor device 1572 includes a switching unit 1522 that can short-circuit between the gate 1552 and the source 1532 of the N-channel field effect transistor 1512.

  The control circuit 200 also includes a gate driver 223 that applies a gate signal 1582 to the gate 1552 of the N-channel field effect transistor 1512 via the resistor 224. The gate driver 223 is driven at plus 10 volts with the potential of the source 1532 being 0 volts. In addition, the control circuit 200 includes a signal generation circuit 225 that generates a clamp signal 1562 that is applied to the switching unit 1522 and serves as a trigger for short-circuiting between the gate 1552 and the source 1532.

  The control circuit 200 is a control circuit that controls the current to flow through the choke coil 230 by controlling on / off of the N-channel field effect transistor 1511 and the N-channel field effect transistor 1512, respectively. Since the relationship between the switch operation processing of the control circuit 200 and the current flowing through the choke coil 230 overlaps with the content already described with reference to FIG. 9 and the like, the description thereof is omitted here.

  Further, the signal generation circuit 225 of the control circuit 200 generates the clamp signal 1562 at the timing when the sudden voltage 701 shown in FIG. 8 is generated. When the clamp signal 1562 is input, the switching unit 1522 performs a short-circuit operation. By the short-circuit operation of the switching unit 1522, the gate 1552 and the source 1532 of the N-channel field effect transistor 1512 are short-circuited.

  Further, when the gate 1552 and the source 1532 of the N-channel field effect transistor 1512 are short-circuited, the sudden voltage 701 shown in FIG. 8 is relaxed and reduced. Therefore, the control circuit 200 can suppress overcurrent caused by the sudden voltage 701 and reduce the risk of element destruction and circuit damage.

  The signal generation circuit 225 preferably outputs a clamp signal 1562 when a predetermined period elapses in correspondence with the timing at which the sudden voltage 701 is generated after the high-voltage gate signal 1581 is turned on. When the gate signal 1581 is turned on, it corresponds to the output of the rectangular gate signal 704 shown in FIG.

  For this reason, the signal generation circuit 225 measures in advance a predetermined period after the output of the gate signal 1581 from the gate driver 213, that is, after the output of the rectangular gate signal 704 until the sudden voltage 701 is generated, or by simulation or the like It may be calculated in advance and stored in a storage unit (not shown). In addition, the signal generation circuit 225 includes a calculation unit that calculates in real time a predetermined period after the output of the gate signal 1581 from the gate driver 213, that is, after the output of the rectangular gate signal 704 until the sudden voltage 701 is generated. Also good.

  Then, after the gate signal 1581 is output from the gate driver 213, that is, after the output of the rectangular gate signal 704, the signal generation circuit 225 passes a predetermined period read from the storage unit or a predetermined period calculated by the calculation unit. It is preferable to output the clamp signal 1562 at the timing to be performed. As a result, the control circuit 200 can relax the sudden voltage 701 accurately and efficiently without delay.

  Further, the signal generation circuit 225 measures in advance a predetermined period until the sudden voltage 701 is generated after the gate signal 1582 from the gate driver 223 is turned off, or calculates in advance by simulation or the like and stores it in a storage unit (not shown). You may keep it. In addition, the signal generation circuit 225 includes a calculation unit that calculates in real time a predetermined period after the gate signal 1582 from the gate driver 223 is turned off, that is, after the rectangular gate signal 705 is turned off until the sudden voltage 701 is generated. May be.

  Then, after the gate signal 1582 from the gate driver 223 is turned off, the signal generation circuit 225 outputs the clamp signal 1562 at a timing when a predetermined period read from the storage unit or a predetermined period calculated by the calculation unit elapses. It is preferable. As a result, the control circuit 200 can relax the sudden voltage 701 accurately and efficiently without delay.

  Note that the signal generation circuit 225 preferably detects the off signal of the gate signal 1582 from the gate driver 223 because the off detection wiring distance of the gate signal 1582 can be shortened.

  In addition, the control circuit 200 may include a sudden voltage detection unit (not shown) in the gate 1552. The signal generation circuit 225 may output the clamp signal 1562 in real time when the sudden voltage detection unit detects the sudden voltage generated in the gate 1552 in real time. As a result, even when the sudden voltage 701 occurs at a random or unpredictable timing, the control circuit 200 can quickly mitigate the sudden voltage 701 in real time and minimize the influence of the overcurrent caused by the sudden voltage 701. A reduced power supply control circuit or the like can be realized.

  Further, the signal generation circuit 215 of the control circuit 200 generates the clamp signal 1561 at the timing when the sudden voltage is generated. When the clamp signal 1561 is input, the switching unit 1521 performs a short-circuit operation. By the short-circuit operation of the switching unit 1521, the gate 1551 and the source 1531 of the N-channel field effect transistor 1511 are short-circuited.

  Further, when the gate 1551 and the source 1531 of the N-channel field effect transistor 1511 are short-circuited, the sudden voltage generated at the gate 1551 is relaxed and reduced. Therefore, the control circuit 200 can suppress overcurrent caused by the sudden voltage generated at the gate 1551 and reduce the risk of element destruction and circuit damage.

  The signal generation circuit 215 preferably outputs a clamp signal 1561 when a predetermined period elapses in correspondence with the timing at which the sudden voltage occurs after the low-voltage gate signal 1582 is turned on. When the gate signal 1582 is turned on, it corresponds to the output of the rectangular gate signal 705 shown in FIG.

  For this reason, the signal generation circuit 215 measures in advance a predetermined period after the output of the gate signal 1582 from the gate driver 223, that is, after the output of the rectangular gate signal 705 until the sudden voltage occurs, or in advance by simulation or the like. It may be calculated and stored in a storage unit (not shown).

  In addition, the signal generation circuit 215 includes a calculation unit that calculates in real time a predetermined period after the output of the gate signal 1582 from the gate driver 223, that is, after the output of the rectangular gate signal 705, until the sudden voltage occurs. Also good.

  Then, the signal generation circuit 215 outputs the clamp signal 1561 at a timing when a predetermined period read from the storage unit or a predetermined period calculated by the calculation unit elapses after the gate signal 1582 is output from the gate driver 223. It is preferable. As a result, the control circuit 200 can relax the sudden voltage accurately and efficiently without delay.

  The signal generation circuit 215 preferably outputs a clamp signal 1561 when a predetermined period elapses in correspondence with the timing at which the sudden voltage occurs after the high-voltage side gate signal 1551 is turned off. When the high-voltage side gate signal is turned off, this corresponds to the output of the rectangular low-voltage side gate signal 705 shown in FIG.

  Therefore, the signal generation circuit 215 measures in advance a predetermined period until the sudden voltage is generated after the gate signal 1581 is turned off from the gate driver 213, or calculates in advance by simulation or the like, and stores it in a storage unit (not shown). You may remember it. In addition, the signal generation circuit 215 includes an arithmetic unit that calculates in real time a predetermined period after the gate signal 1581 from the gate driver 213 is turned off, that is, after the rectangular gate signal 704 is turned off until a sudden voltage is generated. Also good.

  Further, the signal generation circuit 215 outputs the clamp signal 1561 at a timing when a predetermined period read from the storage unit or a predetermined period calculated by the calculation unit passes after the gate signal 1581 from the gate driver 213 is turned off. Is preferred. The signal generation circuit 215 preferably detects the off signal of the gate signal 1581 from the gate driver 213 because the off detection wiring distance of the gate signal 1581 can be shortened.

  In addition, the control circuit 200 may include a sudden voltage detection unit (not shown) in the gate 1551. The signal generation circuit 215 may output the clamp signal 1561 in real time when the sudden voltage detection unit detects the sudden voltage generated in the gate 1551 in real time. As a result, the control circuit 200 can quickly relieve the sudden voltage in real time and reduce the influence of overcurrent due to the sudden voltage as much as possible even when the sudden voltage occurs at random or unpredictable timing. Can be realized.

  Next, a typical example of a specific configuration of the N-channel field effect transistor 111 illustrated in FIG. 1A will be described with reference to FIG. FIG. 3 is a diagram showing a typical example of a specific structure of the N-channel field effect transistor 111.

  As shown in FIG. 3, the one-chip N-channel field effect transistor 311 includes a PNP transistor 312 between the gate 315 and the source 313 of the vertical MOSFET. The PNP transistor 312 corresponds to the switching unit 112 shown in FIG.

  The clamp signal 316 shown in FIG. 1A is input to the clamp 316. Further, the drain 314 corresponds to the drain 114 shown in FIG.

  As illustrated in FIG. 3, the one-chip N-channel field effect transistor 311 (corresponding to the N-channel field effect transistor 111) is configured by appropriately stacking a p-type semiconductor and an n-type semiconductor on an n-type substrate. The In addition, the one-chip N-channel field effect transistor 311 has a structure in which a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor are sequentially provided in the lateral direction after the p-type semiconductor portion of the source 313, so that the PNP transistor 312 is provided. Is provided.

  The p-type semiconductor layer provided opposite to the p-type semiconductor provided continuously with the p-type semiconductor layer of the source 313 around the n-type semiconductor of the PNP transistor 312 has an attached electrode 315e of the gate 315. Provided.

  For this reason, in the one-chip N-channel field effect transistor 311, the p-type semiconductor provided with the p-type semiconductor layer of the source 313 and the attached electrode 315 e of the gate 315 when the clamp signal 116 is input to the clamp 316. A p-channel is formed and electrically connected to the layer. Thereby, the one-chip N-channel field effect transistor 311 can release the sudden voltage of the gate 315 to the source 313 without delay.

  Note that the one-chip N-channel field effect transistor 311 illustrated in FIG. 3 illustrates a typical configuration of the N-channel field effect transistor 111. Therefore, the structure of the N-channel field effect transistor 111 is not limited to the structure shown in FIG. 3, and the structure can be designed by appropriately combining a p-type semiconductor, an n-type semiconductor, an insulating film, and an electrode.

  FIG. 4 is a diagram showing a typical example of a specific structure of the switching element corresponding to FIG. 1A using an insulated gate bipolar transistor.

  As shown in FIG. 4, the insulated gate bipolar transistor 411 includes a PNP transistor 412 between the gate 415 and the emitter 413 of the vertical IGBT. The PNP transistor 412 corresponds to the switching unit 112 shown in FIG.

  The clamp signal 416 shown in FIG. 1A is input to the clamp 416. The collector 414 corresponds to the drain 114 shown in FIG.

  As illustrated in FIG. 4, the insulated gate bipolar transistor 411 is configured by appropriately stacking a p-type semiconductor and an n-type semiconductor on an n-type substrate. In addition, the insulated gate bipolar transistor 411 has a configuration in which a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor are sequentially provided in the lateral direction after the p-type semiconductor portion of the emitter 413, so that the PNP corresponding to the switching portion 112 is provided. A type transistor 412 is provided.

  The p-type semiconductor layer provided in the opposite direction of the p-type semiconductor provided continuously with the p-type semiconductor layer of the emitter 413 around the n-type semiconductor of the PNP transistor 412 has an attached electrode 415e of the gate 415. Provided.

  For this reason, the insulated gate bipolar transistor 411 receives the clamp signal 116 to the clamp 416, and thus the p-type semiconductor layer of the emitter 413 and the p-type semiconductor layer provided with the attached electrode 415e of the gate 415, A p-channel is formed between and electrically connected. As a result, the insulated gate bipolar transistor 411 can release the sudden voltage of the gate 415 to the emitter 413 without delay.

  Note that the insulated gate bipolar transistor 411 illustrated in FIG. 4 exemplifies one of typical configurations of the present invention. Therefore, the structure of the insulated gate bipolar transistor 411 is not limited to the structure shown in FIG. 4, and the structure can be designed by appropriately combining a p-type semiconductor, an n-type semiconductor, an insulating film, and an electrode.

(Second embodiment)
FIG. 5 is a diagram illustrating a semiconductor device 457 in which the switching unit 152 of the semiconductor device 157 shown in FIG.

  As shown in FIG. 5, the semiconductor device 457 includes a PNP transistor 452 and an N-channel field effect transistor 451 that are close to each other. The semiconductor device 457 is typically a semiconductor device 457 provided by sealing an N-channel field effect transistor 451 and a PNP transistor 452 in one package.

  Further, the PNP transistor 452 of the semiconductor device 457 can short-circuit between the gate 455 and the source 453 of the N-channel field effect transistor 451. The PNP transistor 452 shorts between the gate 455 and the source 453 by the clamp signal 456.

  The clamp signal 456 is output from the gate 455 even though an OFF signal is input to the gate 455 due to a parasitic capacitance between the drain 454 and the gate 455 and a parasitic capacitance between the gate 455 and the source 453. It is applied at such a timing as to mitigate sudden voltage generated between the source 453 and the like.

  The sudden voltage generated between the gate 455 and the source 453 or the like is reduced and alleviated by causing the PNP transistor 452 to short-circuit between the gate 455 and the source 453 based on the clamp signal 456. As a result, the N-channel field effect transistor 451 can suppress destruction or damage of the control circuit including the N-channel field effect transistor 451 due to overcurrent or the like. Further, the semiconductor device 457 can be applied to flexible circuit design, such as being easy to add to an existing circuit.

  Further, the semiconductor device 457 can share the clamp signal 456 and the gate signal input to the gate 455. Next, the control circuit 500 sharing the clamp signal 456 and the gate signal input to the gate 455 will be described with reference to FIG. FIG. 6 is a diagram illustrating a control circuit 500 that shares a clamp signal and a gate signal.

  As illustrated in FIG. 6, the control circuit 500 includes a semiconductor device 5571 and a semiconductor device 5572. Further, the semiconductor device 5571 and the semiconductor device 5572 included in the control circuit 500 each have the same configuration as the semiconductor device 457.

  The semiconductor device 5571 and the semiconductor device 5572 are connected in order from the high voltage side, and the semiconductor device 5571 becomes the high voltage side (high side) and the semiconductor device 5572 becomes the low voltage side (low side).

  Further, the semiconductor device 5571 of the control circuit 500 includes an N-channel field effect transistor 5511. The drain 5541 of the N-channel field effect transistor 5511 is connected to the high voltage side (Vdd). In addition, the semiconductor device 5571 includes a PNP transistor 5521 that can short-circuit between the gate 5551 and the source 5531 of the N-channel field effect transistor 5511.

  The control circuit 500 further includes a gate driver 513 that applies a gate signal 5581 to the gate 5551 of the N-channel field effect transistor 5511 via the resistor 514. The gate driver 513 is driven at plus 10 volts with the potential of the source 5531 being 0 volts. Further, the control circuit 500 does not need to include a separate signal generation circuit that generates the clamp signal 5561 that serves as a trigger for short-circuiting the gate 5551 and the source 5531 to be provided to the PNP transistor 5521.

  The clamp signal 5561 is input from the gate signal 5581 output from the gate driver 513 through the resistor 515. That is, the control circuit 500 can share the clamp signal 5561 and the gate signal 5551 with the same signal 5581 from the gate driver 513.

  In addition, the semiconductor device 5572 of the control circuit 500 includes an N-channel field effect transistor 5512. The source 5532 of the N-channel field effect transistor 5512 is connected to the low voltage side (Vss). Further, the drain 5542 of the N-channel field effect transistor 5512 is connected to the source 5531 of the N-channel field effect transistor 5511. The semiconductor device 5572 further includes a PNP transistor 5522 that can short-circuit between the gate 5552 and the source 5532 of the N-channel field effect transistor 5512.

  In addition, the control circuit 500 includes a gate driver 523 that applies a gate signal 5582 to the gate 5552 of the N-channel field effect transistor 5512 via the resistor 524. The gate driver 523 is driven at plus 10 volts with the potential of the source 5532 set to 0 volts. In addition, the control circuit 500 does not need to include a separate signal generation circuit that generates the clamp signal 5562 that serves as a trigger for short-circuiting the gate 5552 and the source 5532, which is provided to the PNP transistor 5522.

  The clamp signal 5562 is input from the gate signal 5582 output from the gate driver 523 through the resistor 525. That is, the control circuit 500 can share the clamp signal 5562 and the gate signal 5552 with the same signal 5582 from the gate driver 523. As described above, the control circuit 500 can share the clamp signal with each gate signal in each semiconductor device on both the high voltage side and the low voltage side, and therefore requires a circuit for separately generating the clamp signal. And a simple circuit configuration.

  The control circuit 500 controls the N-channel field effect transistor 5511 and the N-channel field effect transistor 5512 to be turned on and off so that a current flows through the choke coil 530 as appropriate. Since the relationship between the switch operation processing of the control circuit 500 and the current flowing through the choke coil 530 overlaps with the content already described with reference to FIG. 9 and the like, description thereof is omitted here. Further, since the principle that the sudden voltage is generated overlaps with the content already described with reference to FIG. 8 and the like, the description will be continued with appropriate reference to FIG. 8 and FIG.

  In addition, the control circuit 500 generates only a gate signal for turning on and off the field effect transistor 5512. When the gate driver 523 outputs a gate signal 5582 for turning off the N-channel field effect transistor 5512 to the gate 5552, the clamp signal is input to the base 5562 of the PNP transistor 5522 via the resistor 525. That is, in the control circuit 500, the gate signal 5552 to the N-channel field effect transistor 5512 and the clamp signal 5562 to the PNP transistor 5522 are input almost simultaneously.

  In addition, when the clamp signal 5562 is input, the PNP transistor 5522 performs a short-circuit operation only when the voltage of the gate 5552 becomes higher than the voltage of the gate signal 5582. By the short-circuit operation of the PNP transistor 5522, the gate 5552 and the source 5532 of the N-channel field effect transistor 5512 are short-circuited.

  In addition, when the gate 5552 and the source 5532 of the N-channel field effect transistor 5512 are short-circuited, the sudden voltage 701 illustrated in FIG. 8 is relaxed and reduced. Therefore, the control circuit 500 can suppress overcurrent caused by the sudden voltage 701 and reduce the risk of element destruction and circuit damage.

  In addition, when the current flowing through the choke coil 530 is in the opposite direction as described above, the voltage of the gate 5551 is higher than the voltage of the gate signal 5581 of the semiconductor device 5571 on the high voltage side at the timing when the sudden voltage is generated on the high voltage side. The PNP transistor 5521 performs a short circuit operation. By the short-circuit operation of the PNP transistor 5521, the gate 5551 and the source 5531 of the N-channel field effect transistor 5511 are short-circuited.

  In addition, when the gate 5551 and the source 5531 of the N-channel field effect transistor 5511 are short-circuited, the sudden voltage generated in the gate 5551 is relaxed and reduced. Therefore, the control circuit 500 can suppress overcurrent and the like due to the sudden voltage generated in the gate 5551, and can reduce the risk of element destruction and circuit damage.

  In the present embodiment, a control circuit using mainly a field effect transistor as a semiconductor switching element is exemplified. However, the semiconductor switching element is not limited to a field effect transistor, and an insulated gate bipolar transistor (IGBT) can be used.

  Further, the semiconductor switching element is not limited to the field effect transistor having the structure illustrated in the embodiment, and an FET having another structure, another transistor, and a semiconductor device such as a photocoupler or a photomoss switch may be used. Good. Use of a photo moss switch is preferable because insulation between elements in the circuit is further improved.

  In addition, when an insulated gate bipolar transistor is used, an ON operation with less resistance can be performed depending on conditions. In the insulated gate bipolar transistor, the output of the n-type MOS field effect transistor is used as the input of the PNP-type bipolar transistor. Further, a p + collector may be provided on the drain side of the vertical n-type MOS field effect transistor. The insulated gate bipolar transistor may be a so-called planar type or a trench type.

  In addition, the control circuit and the like exemplified in this embodiment can have a simple circuit configuration without separately requiring a power supply circuit for driving gates with plus and minus voltages. Further, the control circuit and the like exemplified in this embodiment can have a flexible circuit configuration using a so-called bootstrap system. Further, in the control circuit and the like exemplified in the present embodiment, the switching characteristics of the FET are not deteriorated, and the failure due to the pattern impedance or the pattern inductance can be eliminated.

  In addition, the field-effect transistor, the semiconductor device, the control circuit, and the like exemplified in this embodiment can be used by appropriately changing the structure, operation, and processing within an obvious range. For example, the control circuit or the like according to the present invention is not limited to the bridge circuit or the like exemplified in the embodiment, and the voltage applied to the field effect transistor, the insulated gate bipolar transistor, or the like may change unexpectedly. The present invention may be applied to other control circuits. The control circuit according to the present invention can be applied to a power supply circuit used in a half bridge circuit, a full bridge circuit, a three-phase bridge circuit, or the like.

It is a figure which illustrates the N channel field effect type transistor of this embodiment. It is a figure which illustrates the control circuit using a semiconductor device. It is a figure which shows the typical example of the N channel field effect transistor structure of this invention. It is a figure which shows the typical structure of the insulated gate bipolar transistor of this invention. It is the figure which comprised the switching part of the semiconductor device with the PNP type transistor. It is a control circuit diagram which shares a clamp signal and a gate signal. It is a figure which illustrates the conventional coping method to a sudden current. It is a sequence diagram which shows the gate signal of the conventional control circuit. It is a figure which shows the operation | movement of the conventional control circuit sequentially.

Explanation of symbols

111... Field effect transistor, 112.. Switching part, 113.. Source, 114 .. Drain, 115... Gate, 116... Clamp signal, 151. 153 .. Source, 154... Drain, 155... Gate, 156 .. Clamp signal, 157 .. Semiconductor device, 200... Control circuit, 213... Gate driver, 214. Circuit 223 gate driver 224 resistance signal generation circuit 230 choke coil 311 one-chip N-channel field effect transistor 312 PNP transistor 313 source 314 ... Drain, 315 ... Gate, 315e ... Attached electrode, 316 ... 411 .. Insulated gate bipolar transistor 412.. PNP type transistor 413 .. Emitter 414 .. Collector 415 .. Gate 415 e .. Attached electrode 416 .. Clamp 451. Effect type transistor 452... PNP type transistor 453... Source 454... Drain 455.

Claims (18)

A field-effect transistor comprising a switching unit that short-circuits between the gate and the source based on a clamp signal between the gate and the source. The field effect transistor according to claim 1,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The field effect transistor, wherein the clamp signal is input to a base of the PNP transistor. A semiconductor device comprising: a field effect transistor; and a switching unit that short-circuits between the gate and the source of the field effect transistor based on a clamp signal. The semiconductor device according to claim 3.
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The semiconductor device, wherein the clamp signal is input to a base of the PNP transistor. In a control circuit comprising the field effect transistor according to claim 1 or 2,
A first field effect transistor having a drain connected to the high voltage side, and a second field effect transistor having a source connected to the low voltage side,
A source of the first field effect transistor is connected to a drain of the second field effect transistor;
In a state where the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the second field effect transistor, When the first field effect transistor is turned on,
The switching unit of the second field effect transistor is based on the clamp signal input to the second field effect transistor so as to alleviate the sudden voltage generated at the gate of the second field effect transistor. Short-circuiting between the gate and the source of the second field effect transistor,
Alternatively, the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the first field effect transistor. When the second field effect transistor is turned on,
The switching unit of the first field effect transistor is based on the clamp signal input to the first field effect transistor so as to alleviate the sudden voltage generated at the gate of the first field effect transistor. Then, a short circuit is provided between the gate and the source of the first field effect transistor. The control circuit according to claim 5,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The control circuit, wherein the clamp signal is a signal for inputting a gate signal to the gate of the corresponding field effect transistor to a base of the PNP transistor. In a control circuit comprising the semiconductor device according to claim 3 or 4,
The first semiconductor device connected to the high voltage side and the second semiconductor device connected to the low voltage side,
The first semiconductor device includes the first field effect transistor having a drain connected to a high voltage side,
The second semiconductor device includes the second field effect transistor having a source connected to a low voltage side,
A source of the first field effect transistor is connected to a drain of the second field effect transistor;
In a state where the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the second field effect transistor, When the first field effect transistor is turned on,
Based on the clamp signal input to the second semiconductor device, the switching unit of the second semiconductor device is configured to reduce the sudden voltage generated at the gate of the second field effect transistor. Short-circuiting between the gate and the source of a second field effect transistor;
Alternatively, the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the first field effect transistor. When the second field effect transistor is turned on,
Based on the clamp signal input to the first semiconductor device, the switching unit of the first semiconductor device is configured to reduce the sudden voltage generated at the gate of the first field effect transistor. A short circuit between the gate and the source of one field effect transistor. The control circuit according to claim 7,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The control circuit, wherein the clamp signal is a signal for inputting a gate signal to the gate of the corresponding field effect transistor to a base of the PNP transistor. In a method for controlling a field effect transistor,
The field effect transistor includes a switching unit that short-circuits between the gate and the source based on a clamp signal between the gate and the source,
The switching unit includes a step of short-circuiting the gate and the source based on the clamp signal so as to alleviate the sudden voltage generated in the gate. The method of controlling a field effect transistor according to claim 9,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
Based on the clamp signal input from the gate signal input line to the gate to the base of the PNP transistor, the switching unit relaxes the sudden voltage generated at the gate. A method for controlling a field-effect transistor, comprising the step of: In a method for controlling a semiconductor device,
The semiconductor device includes a field-effect transistor and a switching unit that short-circuits between the gate and the source of the field-effect transistor based on a clamp signal,
The switching method includes: a step of short-circuiting the gate and the source based on the clamp signal so as to alleviate the sudden voltage generated at the gate. The method for controlling a semiconductor device according to claim 11,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The clamp signal is input to the base of the PNP transistor from the gate signal input line to the gate,
The switching method includes: a step of short-circuiting the gate and the source based on the clamp signal so as to alleviate the sudden voltage generated at the gate. In the control method of a control circuit provided with the field effect transistor according to claim 1 or 2,
The control circuit includes the first field effect transistor whose drain is connected to the high voltage side, and the second field effect transistor whose source is connected to the low voltage side,
A source of the first field effect transistor is connected to a drain of the second field effect transistor;
In a state where the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the second field effect transistor, When the first field effect transistor is turned on,
The switching unit of the second field effect transistor is based on the clamp signal input to the second field effect transistor so as to alleviate the sudden voltage generated at the gate of the second field effect transistor. And short-circuiting between the gate and the source of the second field effect transistor,
Alternatively, the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the first field effect transistor. When the second field effect transistor is turned on,
The switching unit of the first field effect transistor is based on the clamp signal input to the first field effect transistor so as to alleviate the sudden voltage generated at the gate of the first field effect transistor. And a step of short-circuiting between the gate and the source of the first field-effect transistor. In the control method of a control circuit provided with the semiconductor device according to claim 3 or 4,
The control circuit includes the first semiconductor device connected to the high voltage side and the second semiconductor device connected to the low voltage side,
The first semiconductor device includes the first field effect transistor having a drain connected to a high voltage side,
The second semiconductor device includes the second field effect transistor having a source connected to a low voltage side,
A source of the first field effect transistor is connected to a drain of the second field effect transistor;
In a state where the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the second field effect transistor, When the first field effect transistor is turned on,
Based on the clamp signal of the second semiconductor device, the switching unit of the second semiconductor device causes the switching portion of the second semiconductor device to relax the sudden voltage generated at the gate of the second field effect transistor. Short-circuiting between the gate and the source of an effect transistor,
Alternatively, the first field effect transistor and the second field effect transistor are both turned off and a current flows from the source to the drain through the parasitic diode of the first field effect transistor. When the second field effect transistor is turned on,
Based on the clamp signal of the first semiconductor device, the switching unit of the first semiconductor device is configured to reduce the sudden voltage generated at the gate of the first field effect transistor. A control circuit control method, comprising: short-circuiting between the gate and the source of an effect transistor. In the control method of the control circuit according to claim 13 or 14,
The switching unit is a PNP transistor in which an emitter and the gate are connected, and a collector and the source are connected,
The control method of a control circuit, wherein the clamp signal is a signal for inputting a gate signal to the gate of the field effect transistor corresponding to the switching unit to a base of the PNP transistor. An insulated gate bipolar transistor, comprising: a switching portion that short-circuits between the gate and the emitter based on a clamp signal between the gate and the emitter. The insulated gate bipolar transistor according to claim 16, wherein
The switching unit is a PNP transistor, and an emitter of the PNP transistor and the gate of the insulated gate bipolar transistor are connected, and a collector of the PNP transistor and the emitter of the insulated gate bipolar transistor are connected. An insulated gate bipolar transistor, characterized in that: The semiconductor device according to claim 3 or claim 4,
The field effect transistor is an insulated gate bipolar transistor,
The semiconductor device, wherein the source is an emitter of the insulated gate bipolar transistor, and the drain is a collector of the insulated gate bipolar transistor.

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