JP2009224546A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a semiconductor device high in productivity; and a manufacturing method of the semiconductor device. <P>SOLUTION: This semiconductor device 1a includes: a support substrate 10; a plurality of wires 12 selectively arranged on a principal surface of the support substrate 10; electrode terminals 12a extended from the wires 12 to an end of the support substrate 10; semiconductor elements 20a and 20b mounted on the support substrate 10; at least one semiconductor element 21 controlling the semiconductor elements 20a and 20b; and a wire support base material 30 with a plurality of conductive patterns 40 selectively arranged thereon. The semiconductor elements 20a and 20b and the semiconductor element 21, or the semiconductor elements 20a and 20b or the semiconductor element 21 and the wires 12 are electrically connected to one another through one or more conductive patterns 40. According to such a semiconductor device 1a, productivity is improved as a semiconductor device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a multichip module type semiconductor device in which a plurality of semiconductor elements are mounted, and a method for manufacturing such a semiconductor device.

Multi-chip modules are one of the elemental technologies that make small TVs and mobile phones smaller and lighter.
The multi-chip module is characterized in that a plurality of semiconductor elements are enclosed in one package and each semiconductor element is connected by wiring to improve system performance.

Among them, a multi-chip power device in which power semiconductor elements and control ICs are two-dimensionally arranged on the same support substrate and these elements are wired with bonding wires has attracted attention (for example, see Patent Document 1). ).
JP 2003-218309 A

However, in the device disclosed in the preceding example, a plurality of bonding wires are used between a plurality of elements or between elements and wirings.
Such bonding wire formation requires a lot of time, and there is a problem that the productivity of the device is not improved.

  The present invention has been made in view of such a point, and an object thereof is to provide a highly productive semiconductor device (multichip power device) and a method for manufacturing the semiconductor device.

  In order to solve the above problems, according to one embodiment of the present invention, a support substrate, a plurality of first wirings selectively disposed on a main surface of the support substrate, and the first wiring to the support substrate. A terminal extending to an end; at least one first semiconductor element mounted on the support substrate; at least one second semiconductor element controlling the first semiconductor element; and a plurality of second semiconductor elements A wiring support substrate on which the wirings are selectively arranged, and the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first A semiconductor device is provided in which one wiring is electrically connected through at least one second wiring.

  In one embodiment of the present invention, a support substrate, a plurality of first wirings selectively disposed on a main surface of the support substrate, and the first wiring extend to an end of the support substrate. Selectively selecting a terminal, at least one first semiconductor element mounted on the support substrate, at least one second semiconductor element for controlling the first semiconductor element, and a plurality of second wirings; At least one of the first semiconductor element and the first wiring, the wiring support base disposed, and a solder layer that penetrates the wiring support base and is electrically connected to the second wiring. A semiconductor device is provided which is electrically connected through the second wiring and the solder layer.

  Furthermore, in one embodiment of the present invention, the support substrate, a plurality of first wirings selectively disposed on the main surface of the support substrate, and the first wiring are extended to the end of the support substrate. Selectively selecting a terminal, at least one first semiconductor element mounted on the support substrate, at least one second semiconductor element for controlling the first semiconductor element, and a plurality of second wirings; A wiring support base disposed; and a solder layer that penetrates the wiring support base and is electrically connected to the second wiring. The first semiconductor element and the second semiconductor element, or Provided is a semiconductor device, wherein the first semiconductor element or the second semiconductor element and the first wiring are electrically connected through at least one of the second wiring and the solder layer. Is done.

  In order to manufacture the semiconductor device described above, according to one embodiment of the present invention, a plurality of first wirings are connected to a main surface of a continuous support substrate, and the first wiring is electrically connected to the end of the support substrate unit. A step of selectively disposing terminals extending to the at least one terminal; at least one first semiconductor element on the main surface of the support substrate; and at least one second semiconductor element for controlling the first semiconductor element. A mounting step, a step of disposing a solder material on a part of the first wiring, the electrode of the first semiconductor element, and the electrode of the second semiconductor element, and a plurality of second wirings. A step of placing the selectively arranged wiring support base on the first wiring, the first semiconductor element, and the second semiconductor element via the solder material; and a reflow process. The solder material is melted, and the first semiconductor element and the front Electrically connecting a second semiconductor element or the first semiconductor element or the second semiconductor element and the first wiring through the second wiring; and the first wiring; Sealing the first semiconductor element, the second semiconductor element, the second wiring, and the wiring support base with a resin, and dividing the support substrate, the wiring support base, and the resin; There is provided a method for manufacturing a semiconductor device comprising the steps of:

  In one embodiment of the present invention, a plurality of first wirings and terminals extending to the end of the support substrate unit are selectively disposed on the main surface of the continuous support substrate and connected to the first wiring. A step of mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element on a main surface of the support substrate; and a plurality of second semiconductor elements A wiring support base on which wiring and a plurality of solder balls electrically connected to the second wiring are selectively disposed are disposed on the first wiring and the first semiconductor element via the solder balls. A step of placing, a step of melting the solder ball by a reflow process, and electrically connecting the first semiconductor element and the first wiring through the second wiring and a solder layer; First wiring, the first semiconductor element, the first A step of sealing the semiconductor element, the second wiring, the solder layer, and the wiring support base material with a resin, and a step of dividing the support substrate, the wiring support base material, and the resin. A method for manufacturing a semiconductor device is provided.

  In one embodiment of the present invention, a plurality of first wirings and terminals extending to the end of the support substrate unit are selectively disposed on the main surface of the continuous support substrate and connected to the first wiring. And mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element on the first main surface of the wiring support base material via an adhesive member And a step of selectively disposing a plurality of second wirings on a second main surface opposite to the first main surface on which the first semiconductor element and the second semiconductor element are mounted. Forming a through hole that penetrates the second wiring, the wiring support base joined to the second wiring, the adhesive member joined to the joined wiring support base, and The main surface of the support substrate on which the first wiring is disposed is arranged on the first surface. The step of placing the wiring support base so that the semiconductor element and the second semiconductor element face each other, the step of supplying the solder material into the through-hole, and the reflow process, the solder material And the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring are electrically connected through the second wiring. Connecting the first wiring, the first semiconductor element, the second semiconductor element, the second wiring, and the wiring support base with a resin, and the support substrate And a step of dividing the wiring support base and the resin.

  According to the present invention, a highly productive semiconductor device and a method for manufacturing the semiconductor device can be realized. Furthermore, it is possible to realize a semiconductor device having a reduced thickness and size and a method for manufacturing the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a main part view of the semiconductor device according to the first embodiment. Here, FIG. (A) shows the upper surface of the semiconductor device 1a according to the first embodiment, and FIG. (B) shows the semiconductor device 1a at the ab position in FIG. (A). A cross section is shown.

  As shown in the figure, the semiconductor device 1a uses a rectangular support substrate 10 as a base. Then, at a predetermined position of the support substrate 10, at least one cavity 10a is formed in a substantially parallel shape, and, for example, lead-free solder (tin (Sn) -silver (Ag)) is contained in each cavity 10a. The semiconductor elements 20a, 20b, and 21 are mounted via the (solder) layer 11.

  Here, a so-called printed wiring board (circuit board) in which electrodes, wiring, and resin layers are laminated in a multilayer structure is applied to the support substrate 10. And as the said resin, organic-material insulating resin, such as glass-epoxy resin, glass-bismaleimide triazine, or a polyimide, is mentioned.

Moreover, such a support substrate 10, instead of the printed wiring board, for example, alumina (Al ₂ O _3), aluminum nitride (AlN), silicon oxide (SiO _2), magnesium oxide (MgO), calcium oxide You may use the ceramic wiring board which has (CaO) or a mixture of these as a main component.

Further, when the semiconductor device 1a is manufactured by a wafer process, a silicon wiring board having a base material of a silicon (Si) wafer as a base material may be used as a support substrate.
Alternatively, an insulating film-covered metal wiring board may be used as a support substrate (described later). Further, a metal frame obtained by etching a metal plate may be used directly (described later).

Further, as shown in FIG. (B), a metal heat radiating plate (heat spreader) 10h may be fixed below the support substrate 10 as necessary.
In addition, for example, vertical power semiconductor elements are applied to the semiconductor elements (first semiconductor elements) 20a and 20b. Specifically, a main electrode (for example, a source electrode) and a control electrode (gate electrode) are disposed on one main surface (upper surface side), and another main electrode (for example, a lower electrode side) is disposed on the other main surface (lower surface side). This corresponds to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) element provided with a drain electrode.

Alternatively, an IGBT (Insulated Gate Bipolar Transistor) element may be used as an element instead of the power MOSFET.
The semiconductor element (second semiconductor element) 21 located between the semiconductor elements 20a and 20b is a control IC chip, and the semiconductor element 21 is ON / OFF of at least one of the semiconductor elements 20a and 20b. Control.

  The number of semiconductor elements mounted on the semiconductor device 1a is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 1a, wiring (wiring) incorporated in the main circuit, signal circuit, power supply circuit, etc. on the main surface (upper surface side) of the support substrate 10 on which the semiconductor elements 20a, 20b, and 21 are not mounted. A plurality of patterns) 12 are selectively arranged. These wirings 12 are composed of, for example, copper (Cu) as a main component. Further, a wiring support substrate (base film) 30 processed into a predetermined shape is disposed above the semiconductor elements 20a and 20b and the wiring 12.

  Here, the wiring support substrate 30 is made of a resin including at least one of a polyimide resin (PI), a liquid crystal polymer resin (LCP), an epoxy resin (EP), a polyethylene terephthalate resin (PET), and a polyphenylene ether resin (PPE). It is configured. Moreover, thickness is 10-50 micrometers.

  Further, in the semiconductor device 1a, a plurality of wirings each including a conductive pattern (conductor connector) 40 constituting a wiring pattern is selectively disposed on the wiring support base 30. Yes. These conductive patterns 40 are composed of, for example, copper as a main component, and are fixed onto the wiring support base 30 via an adhesive member composed of an epoxy resin or a silicon resin.

  With the arrangement of the conductive patterns 40, the electrodes provided in the semiconductor elements 20a, 20b, and 21 and the wirings 12 corresponding to the respective elements are electrically connected through the conductive patterns 40. Yes. Alternatively, electrodes between elements provided in each of the semiconductor elements 20 a, 20 b, and 21 are electrically connected through the conductive pattern 40.

Note that a solder layer 13 made of lead-free solder is applied as an adhesive member for ensuring the electrical connection.
Further, in the semiconductor device 1a, electrode terminals 12a are extended from the respective wirings 12, and further, input / output terminals 50 (material is copper) are extended from these electrode terminals 12a to the end of the support substrate 10. Has been issued.

  Then, the semiconductor elements 20a, 20b, 21, the wiring 12, the wiring support base material 30, the conductive pattern 40, and the like mounted on the support substrate 10 are completely made of the epoxy resin 60 formed by the transfer molding method. It is sealed.

In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 1a.
In addition to the transfer molding method, such a resin 60 may be formed by any one of a potting method, a dipping method, a casting method, and a fluidized immersion method. Further, the resin 60 may be impregnated with an inorganic filler composed of alumina or silicon oxide.

With such a configuration, the semiconductor device 1a can function as a multi-chip power device with a compact shape and low cost.
Next, in order to better understand the structure of the semiconductor device 1a shown in FIG. 1, the structure of the semiconductor device 1a will be described with reference to an enlarged view of the cross section of the semiconductor device 1a.

In all the drawings shown below, the same members as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
FIG. 2 is a schematic cross-sectional view of an essential part of the semiconductor device according to the first embodiment. In FIG. 2, the resin 60, the input / output terminal 50, and the like are not particularly displayed, and an enlarged view of the characteristic form of the semiconductor device 1a is shown.

As described above, in the semiconductor device 1a, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. In the support substrate 10, conductive pads 14 are selectively disposed. For example, in the semiconductor device 1a, the main surfaces of the conductive pads 14a and 14b constitute the bottom surfaces of the cavities 10a.

  Such conductive pads 14a and 14b are electrically connected to wirings, vias, and the like (not shown) disposed in the support substrate 10, and further, electrical connection with the input / output terminals 50 and the like is ensured through the wirings and the like. Yes.

Then, semiconductor elements 20a and 21 are mounted on the conductive pads 14a and 14b via the solder layer 11.
Accordingly, in the semiconductor element 20 a, the drain electrode on the lower surface side and the conductive pad 14 a are electrically connected via the solder layer 11.

  Also, in the semiconductor element 21 that is an IC chip for control, when electrodes are disposed on the upper and lower main surfaces, the electrode on the lower surface side and the conductive pad 14b are connected via the solder layer 11. Electrically connected. However, in the semiconductor element 21, in the case where electrodes are not provided on both main surfaces, the conductive pads 14b are not necessarily provided.

  Further, the conductive pads 14a and 14b are arranged in the support substrate 10 so that the area of the main surface is as large as possible. In order to suppress the influence (interference) of noise between the semiconductor elements 20a and 21, the conductive pads 14a and 14b are separated from each other, and the distance d is set to 0.2 to 3 mm or more.

  A plurality of wirings 12 are selectively arranged on the upper surface of the support substrate 10 on which the semiconductor elements 20a and 21 are not mounted. A wiring support base 30 processed into a predetermined shape is disposed on the wiring 12.

  Furthermore, in the semiconductor device 1 a, the conductive pattern 40 is disposed on the wiring support base 30. With the arrangement of the conductive pattern 40, the electrode pads 20 ap and 21 p disposed on the upper surfaces of the semiconductor elements 20 a and 21 and the wiring 12 are electrically connected through the conductive pattern 40.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
In the semiconductor device 1a, the depth of the cavity 10a is adjusted so that the upper surfaces of the electrode pads 20ap and 21p and the upper surface of the wiring 12 have substantially the same height.

Next, the structure of the wiring support base material 30 and the conductive pattern 40 disposed on the main surface thereof will be described.
FIG. 3 is a main part view of the conductive pattern selectively disposed on the wiring support base. Here, FIG. 3 shows a state of the wiring support base 30 and the conductive pattern 40 when the semiconductor device 1a shown in FIG. 1A is viewed from above.

  As shown in the drawing, a conductive pattern 40 is selectively placed and supported on an interconnect support base 30 processed into a predetermined shape via an adhesive member (not shown). Here, the conductive pattern 40 has a thickness and a line width of 5 mm or less.

Further, a through hole 30 a is provided in the central portion of the wiring support base 30. The semiconductor element 21 shown in FIGS. 1 and 2 is located below the through hole 30a.
Each conductive pattern 40 includes an extended portion (finger portion) 40 a extending from the main surface of the wiring support base 30 at both ends thereof. And the electrode pad and wiring which are to-be-joined bodies are located below the said extension part 40a (back direction of a figure).

  With such a structure, after the wiring support base material 30 on which the conductive pattern 40 is disposed is placed on the electrode pads 20ap, 21p or the wiring 12, the semiconductor element 20a, The electrodes provided on 20b and 21 and the wiring 12 corresponding to each element, or the electrodes between the elements provided on the respective semiconductor elements 20a, 20b and 21 are collectively connected through the conductive pattern 40. Can be electrically connected (described later).

Next, a method for manufacturing the semiconductor device 1a will be described with reference to FIGS.
FIG. 4 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
First, a substrate in which the above-described support substrate 10 is continuous vertically and horizontally is prepared. At this stage, the wiring 12 and the input / output terminals 50 are already selectively disposed in the units of the respective support substrates 10. Such selective arrangement is performed, for example, by plating or selective etching. In addition, at least one cavity 10a is formed on the main surface of the support substrate 10 on which the wiring 12 is not disposed, if necessary.

However, the number of continuous support substrates 10 may be adjusted as necessary according to the capacity of a mold installed in a resin sealing device described later.
FIG. 5 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.

  Next, a paste-like solder material made of lead-free solder is placed in the cavity 10a by a dispensing method (not shown). Alternatively, a sheet-like solder material may be disposed in the cavity 10a instead of the paste-like solder material.

  Subsequently, the semiconductor elements 20a, 20b, and 21 are placed on the solder material. Further, a paste-like solder material is disposed by a dispensing method (not shown) on the joint portion of the wiring 12 and the electrode pads 20ap, 20bp, 21p of the semiconductor elements 20a, 20b, 21.

  Alternatively, a solder material may be disposed in the cavity 10a, and the semiconductor elements 20a, 20b, and 21 may be bonded to the support substrate 10 by performing a reflow process immediately after placing the semiconductor elements 20a, 20b, and 21. In this embodiment, the reflow process at this stage is not performed.

  Further, if necessary, before placing the semiconductor elements 20a, 20b, 21 on the solder material, the solder material is arranged on the electrode pads 20ap, 20bp, 21p of the semiconductor elements 20a, 20b, 21 in advance. May be.

FIG. 6 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, the wiring support base material 30 in which a plurality of conductive patterns 40 are selectively disposed is placed on the wiring 12 and the semiconductor elements 20a, 20b, and 21 via the solder material. Here, the wiring support base material 30 is placed in the direction in which the conductive pattern 40 is exposed on the wiring support base material 30. Further, the wiring support base material 30 at this stage is in a state of being continuous in the horizontal direction so as to correspond to the support substrate 10 continuous in the vertical and horizontal directions. At this stage, the end of the conductor connector 40 contacts the wiring 12 and the electrodes of the semiconductor elements 20a, 20b, and 21 via the solder material.

In addition, in the wiring support base material 30, you may mount the wiring support base material 30 separated into pieces instead of continuing in the horizontal direction.
Then, in the heating furnace, the support substrate 10 or the like is subjected to a reflow process at 260 ° C. for 10 seconds, for example, to melt and permeate the solder material. By this processing, the electrode between the elements arranged in the semiconductor elements 20 a and 20 b and the semiconductor element 21, or the electrode arranged in the semiconductor elements 20 a, 20 b and 21 and the wiring 12 are electrically connected through the conductive pattern 40. Connected.

  That is, instead of bonding bonding wires one by one as in wire bonding, the semiconductor elements 20a, 20b and the semiconductor element 21 or the semiconductor elements 20a, 20b, 21 and the wiring are collectively performed by a reflow process. 12 are electrically connected to each other through the conductive pattern 40.

FIG. 7 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Subsequently, a continuous support substrate 10 or the like is placed in a mold (not shown) provided in the resin sealing device, and the wiring 12, semiconductor elements 20a, 20b, and 21 arranged on the support substrate 10 are supported. The base material 30 and the conductive pattern 40 are sealed with the resin 60.

  The resin sealing is performed by any one of a transfer molding method, a potting method, a dipping method, a casting method, and a fluidized immersion method, as well as a compression molding mold or a printing molding method.

  And after sealing with the said resin 60, the continuous support substrate 10, the wiring support base material 30, and the resin 60 are divided | segmented along the dicing line DL, and are separated into pieces. As a result, an individualized multichip module (semiconductor device 1a) as shown in FIG. 1 is formed.

  As described above, according to the first embodiment, the electrodes between the elements disposed in the semiconductor elements 20a and 20b and the semiconductor element 21 or the semiconductor elements are collectively formed by the plurality of conductive patterns 40. Since the electrodes disposed in 20a, 20b, and 21 and the wiring 12 can be electrically connected, the productivity of a semiconductor device as a multichip power device can be significantly improved.

  Subsequently, a semiconductor device obtained by modifying the configuration of the semiconductor device 1a according to the present embodiment will be described. In addition, in drawing shown below, the same code | symbol is attached | subjected to the member same as the member shown to FIGS. 1-7, and the detail of the description is abbreviate | omitted.

<Variation 1 of the first embodiment>
First, FIG. 8 shows a semiconductor device 1b in which, after the above-described singulation is completed, another rod-shaped input / output terminal is joined to each input / output terminal 50.

  FIG. 8 is a main part view of a semiconductor device according to a modification of the first embodiment. Here, in FIG. 1A, a top view of the semiconductor device 1b to which a plurality of rod-like input / output terminals 51 are mounted is shown, and in FIG. A cross-sectional view of the position between b is shown.

  As shown, rod-like input / output terminals 51 are fixed and extended from the respective input / output terminals 50. Such an input / output terminal 51 is obtained by dividing the support substrate 10, the wiring support base material 30, and the resin 60 described above along the dicing line DL, and sandwiching the solder layer 52 between the end portions of the support substrate 10 with an adhesive member. Disguise. The clamping is performed by soldering (reflow process).

  Here, the input / output terminal 51 is provided with a clip part 51a that is split into two branches at one end thereof. The clip portion 51a is sandwiched between the input / output terminal 50 and the wiring 12 disposed on the main surface of the support substrate 10 via the plating layer 12g and the solder layer 52.

  Thus, the clip-shaped input / output terminal 51 is fixed to the support substrate 10 by fitting the clip portion 51a to the end of the support substrate 10 and soldering the clip portion 51a, the input / output terminal 50, and the wiring 12 through the plating layer 12g. Firmly supported at the end.

  Furthermore, the solder layer 52 is not only disposed in the gap between the plating layer 12g and the clip part 51a, but also from the end of the clip part 51a to the input / output terminal 50 and a part of the wiring 12, It is formed to cover. By forming such a solder layer 52, the mechanical strength in the sandwiched state is further increased.

  The plating layer 12g is composed mainly of nickel (Ni), tin (Sn), nickel (Ni), and gold (Au) from the lower layer. The plating layer 12g may be formed on the surface of the clip portion 51a in addition to being formed on the main surface of the wiring 12.

Subsequently, a semiconductor device obtained by modifying the configuration of the semiconductor device 1a according to the present embodiment will be described.
<Modification 2 of the first embodiment>
Next, a semiconductor device 1c in which the support substrate 10 is replaced with the above-described insulating film-covered metal wiring board will be described.

FIG. 9 is a schematic cross-sectional view of a relevant part of a semiconductor device according to another modification of the first embodiment.
As shown in the drawing, in the semiconductor device 1 c, the insulating film-covered metal wiring board 73 described above is used instead of the support substrate 10. The insulating film-covered metal wiring board 73 includes a core substrate 70, a resin layer 71 disposed above and below the core substrate 70, and an insulating film 72.

Here, the core substrate 70 has a thickness of 100 μm to 1 mm, and its material is mainly copper, aluminum, or an alloy thereof.
On the core substrate 70, a resin layer 71 made of the same material as that of the support substrate 10 and having wiring, vias and the like laminated therein is selectively disposed.

  In addition, the semiconductor element 20 a is mounted via the solder layer 11 on the main surface of the core substrate 70 on which the resin layer 71 is not selectively disposed. Further, the resin layer 71 is provided with a cavity 10a, and the semiconductor element 21 is mounted in the cavity 10a via an adhesive member (not shown).

The insulating film 72 disposed under the core substrate 70 is made of the ceramic or resin.
According to such a configuration of the semiconductor device 1 c, heat generated from the semiconductor elements 20 a and 21 can be reliably radiated to the core substrate 70 through the solder layer 11 or the resin layer 71.

  The insulating film-covered metal wiring board 73 described above may be a metal core substrate in which both ends of the core substrate 70 are covered with a resin or the like, or a metal base substrate in which the insulating film 72 is not disposed in the lowermost layer.

<Modification 3 of the first embodiment>
Next, a semiconductor device in which the support substrate 10 is replaced with the above-described metal frame will be described. Here, the configuration of the semiconductor device formed above the metal frame is omitted, and the configuration of the metal frame will be described in detail.

FIG. 10 is a main part diagram for explaining the configuration of the lead frame.
As shown in the figure, the lead frame 15 has a rectangular outer frame and has a pattern corresponding to the wiring 12 shown in FIG.

  Then, the semiconductor elements 20a and 20b described above are mounted, for example, on the element mounting regions 15a and 15b surrounded by a rectangular shape via an adhesive member (not shown). Moreover, in the semiconductor element 21, it adhere | attaches on the element mounting area | region 15c via an adhesive member (not shown).

  Further, the wiring support base material 30 provided with a plurality of conductive patterns 40 is placed above the semiconductor elements 20a, 20b, and 21, and is provided on the semiconductor elements 20a, 20b, and 21 by soldering. The electrode and the wiring 12 corresponding to each element are electrically connected through the conductive pattern 40. Alternatively, the electrodes between the elements provided in the respective semiconductor elements 20 a, 20 b, and 21 are electrically connected through the conductive pattern 40.

Thus, in the above-described semiconductor devices 1 a and 1 b, the support substrate 10 can be used as the lead frame 15.
For example, such a lead frame 15 is produced by etching a metal plate made of copper.

  Next, a semiconductor device obtained by modifying the semiconductor devices 1a and 1b according to the first embodiment will be described. Note that, in all the drawings shown below, the same members shown in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

<Second Embodiment>
FIG. 11 is a main part view of a semiconductor device according to the second embodiment. Here, FIG. (A) shows the upper surface of the semiconductor device 2 according to the second embodiment, and FIG. (B) shows the semiconductor device 2 at the ab position in FIG. (A). A cross section is shown.

  As shown in the figure, the semiconductor device 2 uses a rectangular support substrate 10 as a base. A heat radiating plate 10h may be fixed below the support substrate 10 as required, as shown in FIG.

  On the main surface (upper surface side) of the support substrate 10, a plurality of wirings 12 are selectively arranged. The back surfaces (drain electrodes) of the semiconductor elements 20a and 20b are mounted on the wiring 12 via an adhesive member (not shown). In FIG. 2A, the semiconductor elements 20a and 20b are located below the wiring support base 31 described later, and the external shapes of the elements are indicated by dotted lines.

  A semiconductor element 21 is mounted on the center of the support substrate 10 via an adhesive member (not shown) made of epoxy resin or silicon resin. The semiconductor element 21 is electrically connected to the wiring 12 selectively disposed on the central main surface of the support substrate 10 through a gold bonding wire 22.

In the semiconductor device 2, a wiring support base 31 processed into a predetermined shape is disposed above the semiconductor elements 20 a and 20 b and the wiring 12.
Furthermore, a plurality of conductive metal films 41a and 41b constituting a wiring pattern are selectively disposed on the wiring support base 31 via the adhesive member. One end of the solder layers 42a, 42b, 43a, 43b formed by the reflow process penetrates into the conductive metal films 41a, 41b and the wiring support base 31, and the conductive metal films 41a The solder layers 42a and 42b are in a conductive state. Further, the conductive metal film 41b and the solder layers 43a and 43b are in a conductive state.

  The other ends of the solder layers 42 a and 43 a are in a state of being bonded to the wiring 12 on the support substrate 10. Furthermore, the other ends of the solder layers 42b and 43b are joined to the electrodes of the semiconductor elements 20a and 20b.

  Due to the arrangement of the conductive metal films 41a and 41b and the solder layers 42a, 42b, 43a and 43b, the electrodes provided on the semiconductor elements 20a, 20b and 21 and the wirings 12 corresponding to the respective elements are electrically connected. Connected. Alternatively, the electrodes between the elements provided in the respective semiconductor elements 20a, 20b, and 21 are electrically connected.

  Further, the number of semiconductor elements mounted on the semiconductor device 2 is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 2, the electrode terminals 12 a are extended from the wiring 12 at the end in the longitudinal direction of the support substrate 10, and a plurality of input / output terminals 50 are connected to the electrode terminals 12 a. This extends to the end of the support substrate 10.

  The semiconductor elements 20 a, 20 b, 21, the wiring 12, the wiring support base 31, the conductive metal films 41 a, 41 b and the like mounted on the support substrate 10 are sealed with a resin 60. In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 2.

With such a configuration, the semiconductor device 2 can function as a multi-chip power device with a compact shape and low cost.
Next, in order to understand the structure of the semiconductor device 2 shown in FIG. 11 in more detail, the structure of the semiconductor device 2 will be described using a schematic diagram in which the characteristic structure of the semiconductor device 2 is enlarged.

FIG. 12 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the second embodiment. In FIG. 12, the resin 60, the input / output terminal 50, and the like are not displayed.
As described above, in the semiconductor device 2, the support substrate 10 is used as a base, and the heat radiating plate 10 h is fixed below the support substrate 10.

  A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10. Then, the back side of the semiconductor element 20 a is mounted on a part of the wiring 12 via the solder layer 11.

  The semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). The electrode pad 21p disposed on the main surface of the semiconductor element 21 and the wiring 12 are electrically connected through the bonding wire 22.

  A wiring support base 31 processed into a predetermined shape is disposed above the semiconductor element 20a. Further, a plurality of conductive metal films 41 a are selectively disposed on the wiring support base 31. Solder layers 42a and 42b are disposed on the main surface opposite to the main surface of the wiring support base 31 on which the conductive metal film 41a is disposed.

  And in the said wiring support base material 31, one end of solder layer 42a, 42b formed by the reflow process has penetrated through through-hole 42ah, 42bh. Therefore, the conductive metal film 41a and the solder layers 42a and 42b are in a conductive state. The other ends of the solder layers 42a and 42b are in a state of being joined to the wiring 12 or the electrode pad 20ap of the semiconductor element 20a.

  With the arrangement of the conductive metal film 41a and the solder layers 42a and 42b, the electrode pad 20ap provided in the semiconductor element 20a and the corresponding wiring 12 are electrically connected. Alternatively, although not shown in the figure, the electrode of the semiconductor element 20a and the electrode of the semiconductor element 21 are electrically connected through a conductive metal film.

In the semiconductor device 2, the conductive metal films 41 a and 41 b and the main surface of the support substrate 10 are in a substantially parallel state by adjusting the heights of the respective solder layers 42 a and 42 b.
Next, a method for manufacturing the semiconductor device 2 will be described with reference to FIGS.

FIG. 13 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
First, a substrate in which the above-described support substrate 10 is continuous vertically and horizontally is prepared. At this stage, the wiring 12 and the input / output terminals 50 are already selectively disposed in the units of the respective support substrates 10. Such selective arrangement is performed, for example, by plating or selective etching.

However, the number of continuous support substrates 10 may be adjusted as necessary according to the capacity of a mold installed in a resin sealing device described later.
In the continuous support substrate 10, a plurality of through holes 10 b into which positioning pins (to be described later) are fitted are formed at predetermined locations.

FIG. 14 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, a paste-like solder material is disposed on the wiring 12 on which the semiconductor elements 20a and 20b are mounted (not shown). Further, an adhesive member is disposed on the support substrate 10 on which the semiconductor element 21 is mounted by a dispensing method (not shown). Then, the semiconductor elements 20a, 20b, and 21 are placed on these solder material and adhesive member.

  Thereafter, in the semiconductor element 21, the electrode pad 21 p disposed on the main surface of the semiconductor element 21 and the wiring 12 positioned around the semiconductor element 21 are electrically connected through a gold bonding wire 22.

  The semiconductor elements 20a and 20b may be subjected to a reflow process immediately after being placed on the wiring 12, and the semiconductor elements 20a and 20b may be joined to the wiring 12, but in this embodiment, this stage Do not perform the reflow process.

  Next, the wiring support base material 31 on which the conductive metal film 41b and the like described above are formed is placed above the semiconductor elements 20a and 20b and the wiring 12. In the wiring support base 31, the conductive metal film 41 b and the like are formed in advance by the method shown in FIGS.

  FIG. 15 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device. Here, FIG. (A) shows the structure on the upper surface side of the wiring support base material 31, and FIG. (B) shows the cross-sectional structure at the position ab in FIG. (A). Yes.

First, a plurality of conductive metal films 41a and 41b are selectively disposed at predetermined positions on the upper surface of the continuous wiring support base 31 via an adhesive member (not shown).
Further, a through hole 31a is formed in a predetermined portion where the conductive metal films 41a and 41b are not disposed. The significance of forming such a through hole 31a is to allow the semiconductor element 21 to be exposed from the wiring support base 31 as shown in FIG.

In addition, through holes 31b through which positioning pins (described later) are fitted are periodically formed at predetermined locations on the wiring support base 31.
Further, a plurality of through holes 42ah, 42bh, 43ah, 43bh penetrating between the main surfaces are selectively formed in the wiring support base 31. The through hole is formed by, for example, drill cutting, laser beam processing, punching, or the like.

Such a set of the conductive metal films 41a and 41b and the through holes 31a and 31b constitutes the same pattern on the continuous wiring support base 31, and the patterns are periodically arranged.
FIG. 16 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device. Here, FIG. (A) shows the structure on the lower surface side of the wiring support base material 31, and FIG. (B) shows the cross-sectional structure at the position ab in FIG. (A). Yes.

  Next, a paste-like solder material is supplied and filled in the through holes 42ah, 42bh, 43ah, and 43bh described above in a slightly excessive manner. Then, solder balls 42ab, 42bb, 43ab, 43bb are formed on the lower surface side of the wiring support base 31 by heat treatment and cooling. The solder balls 42ab, 42bb, 43ab, 43bb are electrically connected to the conductive metal films 41a, 41b through the solder layers filled in the through holes 42ah, 42bh, 43ah, 43bh.

  In addition, in the height of the solder balls 42ab and 42bb from the lower surface of the wiring support base 31 and the height of the solder balls 43ab and 43bb from the lower surface of the wiring support base 31, the supply amount of the solder material and the through hole diameter Etc. are adjusted so that an appropriate level difference is generated.

By such a method, the conductive metal film 41b, the solder balls 42ab, 42bb, 43ab, 43bb and the like are previously formed on the wiring support base 31.
FIG. 17 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.

  Next, the support jig 80 is prepared. The support jig 80 is a jig that supports the continuous support substrate 10, the wiring support base material 31, and the like. The support jig 80 is provided with positioning pins 80a for fixing the positions of the support substrate 10 or the wiring support base material 31 in a continuous state when the support jig 80 is placed on the support jig 80. ing.

  Then, above the support jig 80, the support substrate 10 on which elements and the like are arranged, and the wiring support base material 31 on which solder balls and the like are formed are arranged, and their alignment is performed. That is, when the support substrate 10 and the wiring support base material 31 are lowered and placed from above the support jig 80, the pin 80a has the through hole 10b of the support substrate 10 and the through hole 31b of the wiring support base material 31. The support substrate 10 and the wiring support base material 31 are aligned so as to directly penetrate.

At this stage, as described above, the solder material 11a located under the semiconductor elements 20a and 20b is in a paste state.
18 and 19 are principal part views for explaining one process of the manufacturing process of the semiconductor device.

  Next, as shown in FIG. 18, the support substrate 10 on which elements and the like are arranged, and the wiring support base material 31 on which solder balls and the like are formed are lowered in this order on the support jig 80, and then on the support jig 80. Place them.

  Here, in the wiring support base 31, the main surface on which the solder balls 42 ab, 42 bb, 43 ab, and 43 bb are formed is placed so as to face the support substrate 10. At this stage, the tips of the solder balls 42ab, 42bb, 43ab, 43bb come into contact with the wiring 12 and the electrodes of the semiconductor elements 20a, 20b, 21.

  Note that the wiring 12 on the support substrate 10 and the electrode pads 20ap and 20bp of the semiconductor elements 20a and 20b have different heights. However, as described above, the steps are different in the solder balls 42ab, 42bb, 43ab and 43bb. Therefore, the height and the level difference cancel each other, and the conductive metal films 41a and 41b and the main surface of the support substrate 10 are substantially parallel to each other.

  FIG. 19 shows a top view of the state after the placement. As shown in the figure, a band-shaped wiring support base 31 in which conductive metal films 41a and 41b, solder balls 42ab, 42bb, 43ab, and 43bb are periodically formed is disposed on the support substrate 10 in the lateral direction. ing.

FIG. 20 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, in the heating furnace, the support substrate 10 and the like are subjected to a reflow process at 260 ° C. for 10 seconds, for example, to melt the solder balls 42ab, 42bb, 43ab, 43bb, and the solder material 11a. By this processing, the solder balls 42ab, 42bb, 43ab, 43bb form the solder layers 42a, 42b, 43a, 43b, and the electrode pads 20ap, 20bp disposed on the semiconductor elements 20a, 20b and the wiring 12 are electrically connected. Are electrically connected through the conductive metal films 41a and 41b and the solder layers 42a, 42b, 43a and 43b.

  That is, the operation of bonding metal wires one by one as in wire bonding is not performed, and the semiconductor elements 20a and 20b and the wiring 12 are connected to the conductive metal films 41a and 41b and the solder layer 42a by a batch reflow process. , 42b, 43a, 43b.

  In the reflow process, since the support substrate 10 and the wiring support base 31 are fixed by the positioning pins 80a, the molten solder material is applied to portions other than the wiring 12 and the electrode pads 20ap and 20bp. There is no flow.

  Further, the wiring 12 on the support substrate 10 and the electrode pads 20ap and 20bp of the semiconductor elements 20a and 20b have different heights, but the solder layers 42a, 42b, 43a and 43b also have steps. Therefore, the height and the step cancel each other, and the conductive metal films 41a and 41b and the main surface of the support substrate 10 are in a substantially parallel state.

  The solder material 11a melts together during the reflow process. Then, after curing, the solder layer 11 is formed. As a result, the back surfaces of the semiconductor elements 20 a and 20 b and the wiring 12 are joined via the solder layer 11.

  Thereafter, the support jig 80 is removed, and as shown in FIG. 7, the support substrate 10 that has completed the above mounting is placed in a mold (not shown) provided in the resin sealing device. To do. Further, the wiring 12, the semiconductor elements 20 a, 20 b, 21, the wiring support base 30, the conductive metal films 41 a, 41 b and the like disposed on the support substrate 10 are sealed with the resin 60.

  After sealing with the resin 60, the continuous support substrate 10, the wiring support base material 30, and the resin 60 are divided along the dicing line DL and separated into individual pieces. As a result, an individualized multichip module (semiconductor device 2) as shown in FIG. 11 is formed.

  As described above, according to the second embodiment, the plurality of conductive metal films 41a and 41b and the solder layers 42a, 42b, 43a, and 43b are collectively disposed on the semiconductor elements 20a and 20b. The electrodes between the elements and the semiconductor element 21 or the electrodes disposed in the semiconductor elements 20a, 20b, and 21 and the wiring 12 can be electrically connected. As a result, the productivity of the semiconductor device can be significantly improved.

Note that the separated semiconductor device 2 may be provided with a rod-like input / output terminal 51 shown in FIG. 8 as necessary.
<Third Embodiment>
FIG. 21 is a main part view of a semiconductor device according to the third embodiment. Here, FIG. (A) shows the upper surface of the semiconductor device 3 according to the third embodiment, and FIG. (B) shows the state of the semiconductor device 3 at the ab position in FIG. (A). A cross section is shown.

  As shown in the figure, the semiconductor device 3 uses a rectangular support substrate 10 as a base. A heat radiating plate 10h may be fixed below the support substrate 10 as required, as shown in FIG.

  On the main surface (upper surface side) of the support substrate 10, a plurality of wirings 12 are selectively arranged. Further, a plurality of cavities 10a are selectively formed in the support substrate 10 where the wiring 12 is not disposed.

  In addition, the back surfaces of the semiconductor elements 20a, 20b, and 21 are mounted in the cavity 10a via adhesive members (not shown). These elements are located below the wiring support base 32 to be described later, and the outer shapes of the elements are indicated by dotted lines.

In the semiconductor device 3, the wiring support base material 32 processed into a predetermined shape is disposed above the semiconductor elements 20 a, 20 b, 21 and the wiring 12.
Further, a plurality of conductive metal films 41a, 41b, and 46 constituting the wiring are selectively disposed on the wiring support base 32. The conductive metal films 41a, 41b, 46 and the wiring support base 32 are penetrated by solder layers 44a, 44b, 45a, 45b, 47a, 47b formed by reflow processing.

  Due to the penetration, the conductive metal film 41a and the solder layers 44a and 44b are in a conductive state. The conductive metal film 41b and the solder layers 45a and 45b are in a conductive state. Further, the conductive metal film 46 and the solder layers 47a and 47b are in a conductive state.

  Further, the solder layers 44 a, 45 a, 47 a are in a state of being bonded to the wiring 12 on the support substrate 10. Further, the solder layers 44b and 45b are joined to the electrodes of the semiconductor elements 20a and 20b. Furthermore, the solder layer 47 b is in a state of being bonded to the electrode of the semiconductor element 21.

  Accordingly, the electrodes provided on the semiconductor elements 20a, 20b, and 21 and the wiring corresponding to the respective elements are arranged by the arrangement of the conductive metal films 41a, 41b, and 46 and the solder layers 44a, 44b, 45a, 45b, 47a, and 47b. 12 are electrically connected. Alternatively, the electrodes between the elements provided in the respective semiconductor elements 20a, 20b, and 21 are electrically connected.

  Further, the number of semiconductor elements mounted on the semiconductor device 3 is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 3, the electrode terminal 12 a extends from the wiring 12 at the end portion in the longitudinal direction of the support substrate 10, and a plurality of input / output terminals 50 are connected to these electrode terminals 12 a. This extends to the end of the support substrate 10.

  The semiconductor elements 20 a, 20 b, 21, the wiring 12, the wiring support base material 32, the conductive metal films 41 a, 41 b, 46 and the like mounted on the support substrate 10 are sealed with a resin 60. In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 3.

With such a configuration, the semiconductor device 3 can function as a multi-chip power device with a compact shape and a low price.
Next, in order to understand the structure of the semiconductor device 3 shown in FIG. 21 more deeply, the structure of the semiconductor device 3 will be described using a schematic diagram in which the characteristic structure of the semiconductor device 3 is enlarged.

FIG. 22 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the third embodiment. In FIG. 22, the resin 60, the input / output terminal 50, and the like are not displayed.
As described above, in the semiconductor device 3, the support substrate 10 is used as a base, and the heat radiating plate 10 h is fixed below the support substrate 10.

  A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10. A plurality of cavities 10a are formed in the support substrate 10 where the wiring 12 is not disposed.

  Conductive pads 14a and 14b are disposed inside the support substrate 10 and form the bottom surface of the cavity 10a. Then, semiconductor elements 20a and 21 are mounted on the conductive pads 14a and 14b via the solder layer 11.

  In addition, a wiring support base 32 processed into a predetermined shape is disposed above the semiconductor elements 20 a and 21 and the wiring 12. A plurality of conductive metal films 41 a and 46 are selectively disposed on the upper surface of the wiring support base 32. Further, an adhesive member 33 made of epoxy resin or silicon resin is disposed on the lower surface of the wiring support base 32. Due to the arrangement of the adhesive member 33, the upper surfaces of the semiconductor elements 20 a and 21 are fixed to the lower surface of the wiring support base 32.

  Then, through holes 44ah and 44bh are provided in the conductive metal film 41a, the wiring support base material 32 positioned below and the adhesive member 33, and solder layers 44a and 44b are provided in the through holes 44ah and 44bh. Is filled. Therefore, the electrode pad 20ap of the semiconductor element 20a and the wiring 12 are in an electrically connected state through the conductive metal film 41a and the solder layers 44a and 44b.

  Further, through holes 47ah and 47bh are provided in the conductive metal film 46, the wiring support base material 32 located below and the adhesive member 33, and the solder layers 47a and 47b are provided in the through holes 47ah and 47bh. Filled. Therefore, the electrode pad 21p of the semiconductor element 21 and the wiring 12 are in an electrically connected state through the conductive metal film 46 and the solder layers 47a and 47b.

  With the arrangement of the conductive metal films 41a and 46 and the solder layers 44a, 44b, 47a and 47b, the electrode pads 20ap and 21p provided on the semiconductor elements 20a and 21 and the corresponding wiring 12 are electrically connected. Has been. Alternatively, although not shown in the drawing, the electrode pad 20ap of the semiconductor element 20a and the electrode pad 21p of the semiconductor element 21 are electrically connected through a conductive metal film.

Next, a method for manufacturing the semiconductor device 3 will be described.
First, a substrate in which the support substrate 10 described in the first embodiment is continuous is prepared (see FIG. 4). At this stage, the wiring 12 and the input / output terminals 50 are selectively disposed on the main surface of the unit of each support substrate 10. In addition, at least one cavity 10a is formed on the main surface of the support substrate 10 on which the wiring 12 is not disposed, if necessary.

However, the number of continuous support substrates 10 may be adjusted as necessary according to the capacity of a mold installed in a resin sealing device described later.
Then, after the paste-like solder material is disposed in the cavity 10a, the semiconductor device 3 is subsequently manufactured by the manufacturing method shown in FIGS.

  FIG. 23 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device. Here, FIG. (A) shows the structure on the upper surface side of the wiring support base material 32, and FIG. (B) shows the cross-sectional structure at the position ab in FIG. (A). Yes.

First, a plurality of conductive metal films 41a, 41b, and 46 are selectively disposed at predetermined locations on the upper surface of the continuous wiring support base 32 via an adhesive member (not shown).
A continuous adhesive member 33 is attached to the lower surface of the wiring support base 32. The adhesive member 33 is made of a low elastic material in addition to being sticky. Therefore, the adhesive member 33 exhibits tackiness and is easily deformed when pressed.

  Further, in the conductive metal films 41a, 41b, 46, the wiring support base material 32 joined to the conductive metal films 41a, 41b, 46 and the adhesive member 33, through holes 44ah penetrating between the main surfaces are provided. A plurality of 44bh, 45ah, 45bh, 47ah, 47bh are selectively formed. The through hole is formed by, for example, drill cutting, laser beam processing, punching, or the like. Further, in the wiring support base material 32 and the adhesive member 33, a through hole 32b for fitting a positioning pin (described later) is formed around the periphery.

Such a set of the conductive metal films 41a, 41b, and 46 and the through holes 32b form the same pattern on the continuous wiring support base 32, and the patterns are periodically arranged.
The semiconductor elements 20a, 20b, and 21 are fixed and arranged on the lower surface of the adhesive member 33 at positions below the through holes 44bh, 45bh, and 47bh. For example, the upper surfaces of the semiconductor elements 20a and 20b are bonded so that the electrodes (source electrodes and control electrodes) disposed on the upper surfaces of the semiconductor elements 20a and 20b are exposed at the bottoms of the through holes 44bh and 45bh. Affixed to the member 33 in advance. In addition, the main surface of the semiconductor element 21 is attached to the adhesive member 33 so that the electrode disposed on the main surface of the semiconductor element 21 is exposed at the bottom of the through hole 47bh.

FIG. 24 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, the support jig 80 is prepared. Further, the support jig 80 is provided with positioning pins 80a for fixing the positions of the support substrate 10 or the wiring support base material 32 in a continuous state when the support jig 80 is placed on the support jig 80. Yes.

  Then, the support substrate 10 on which the wirings 12 and the like are formed and the wiring support base material 32 on which the elements are mounted are arranged above the support jig 80, and their alignment is performed. That is, when the support substrate 10 and the wiring support base material 32 are lowered and placed from above the support jig 80, the through holes 10b of the support substrate 10 and the through holes 32b of the wiring support base material 32 are formed on the pins 80a. The support substrate 10 and the wiring support base material 32 are aligned so as to directly penetrate.

At this stage, as described above, the solder material 11a disposed in the cavity 10a is in a paste state.
25 and 26 are principal part views for explaining one process of the manufacturing process of the semiconductor device.

  Next, as shown in FIG. 25, the support substrate 10 on which the wirings 12 and the like are arranged, and the wiring support base material 32 on which the elements and the like are arranged are lowered on the support jig 80 in order, Place them. Here, in the wiring support base material 32, the main surface on which the element is arranged is placed so as to face the main surface of the support substrate 10 on which the wiring 12 is arranged.

With such mounting, the semiconductor elements 20a, 20b, and 21 are accommodated in the cavity 10a.
FIG. 26 shows a top view of the state after the placement. As shown in the figure, a band-shaped wiring support base material 32 in which conductive metal films 41 a, 41 b, 46 and the like are periodically formed is disposed on the support substrate 10 in the lateral direction.

FIG. 27 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, a pressing jig 81 is placed on the wiring support base material 32 via the conductive metal films 41a, 41b, and 46. Due to the load of the jig 81, the adhesive member 33 disposed under the wiring support base material 32 is deformed because it is a low-elasticity material, and forms a state where it wraps around the semiconductor elements 20a, 20b, and 21 and the periphery of the wiring 12. . In order to promote the wraparound of the adhesive member 33, the support substrate 10 and the like may be heated as necessary.

  In the jig 81, a plurality of through holes 81a are selectively formed so as to correspond to the positions of the through holes 44ah, 44bh, 45ah, 45bh, 47ah, 47bh. That is, the jig 81 also has a function as a mask material.

  Then, an appropriate amount of solder material is filled into the respective through holes 44ah, 44bh, 45ah, 45bh, 47ah, 47bh from these through holes 81a by, for example, dipping method, printing method or the like (not shown).

FIG. 28 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, in the heating furnace, the support substrate 10 or the like is subjected to a reflow process at 260 ° C. for 10 seconds, for example, and placed on the solder pads filled in the through holes and the conductive pads 14a and 14b. The solder material 11a is melted. By this processing, the solder material filled in the through holes forms solder layers 44a, 44b, 45a, 45b, 47a, 47b, and electrode pads 20ap, 20bp, 21p disposed on the semiconductor elements 20a, 20b, 21. And the wiring 12 are electrically connected through the conductive metal films 41a, 41b, 46 and the solder layers 44a, 44b, 45a, 45b, 47a, 47b.

  That is, the operation of bonding metal wires one by one as in wire bonding is not performed, and the semiconductor elements 20a, 20b, and 21 and the wiring 12 are connected to the conductive metal films 41a, 41b, and 46 by batch reflow processing. In addition, the solder layers 44a, 44b, 45a, 45b, 47a, 47b are electrically connected.

  The solder material 11a melts together during the reflow process. Then, after curing, the solder layer 11 is formed. As a result, the back surfaces of the semiconductor elements 20a, 20b, and 21 and the conductive pads 14a and 14b are joined via the solder layer 11.

  After that, the support jig 80 and the jig 81 are removed, and the support substrate in which the above-described mounting is completed in a mold (not shown) provided in the resin sealing device as shown in FIG. 10 is installed. Further, the wiring 12, the semiconductor elements 20 a, 20 b, 21, the wiring support base 32, the conductive metal films 41 a, 41 b, 46, etc. arranged on the support substrate 10 are sealed with the resin 60.

  After sealing with the resin 60, the continuous support substrate 10, the wiring support base material 32, and the resin 60 are divided along the dicing line DL and separated into pieces. Thereby, an individualized multichip module (semiconductor device 3) as shown in FIG. 21 is formed.

  As described above, according to the third embodiment, the plurality of conductive metal films 41a, 41b, 46 and the solder layers 44a, 44b, 45a, 45b, 47a, 47b are collectively collected into the semiconductor elements 20a, The electrodes between the elements arranged in 20b and the semiconductor element 21 or the electrodes arranged in the semiconductor elements 20a, 20b and 21 and the wiring 12 can be electrically connected. As a result, the productivity of the semiconductor device can be significantly improved.

Note that the separated semiconductor device 3 may be provided with a rod-like input / output terminal 51 shown in FIG. 8 as necessary.
Next, a modification according to the third embodiment will be described.

  In the third embodiment, the cavity 10a is formed in the support substrate 10, but a method for manufacturing a semiconductor device using the support substrate 10 in which the cavity 10a is not formed is shown in FIGS. Will be described.

<Modification of Third Embodiment>
FIG. 29 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
First, the support jig 80 is prepared. As described above, the support jig 80 includes the pins 80a.

Then, the support substrate 10 on which the wirings 12 and the like are formed and the wiring support base material 32 on which the elements are mounted are arranged above the support jig 80, and their alignment is performed.
As shown in the figure, the cavity 10 a described above is not formed in the support substrate 10.

At this stage, as described above, the solder material 11a disposed on the wiring 12 is in a paste state.
FIG. 30 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.

  Next, the support substrate 10 on which the wirings 12 and the like are arranged, and the wiring support base material 32 on which the elements and the like are formed are lowered on the support jig 80 and placed on the support jig 80. With such placement, the back surfaces of the semiconductor elements 20a and 20b come into contact with the solder material 11a.

  However, the semiconductor element 21 is in a state separated from the main surface of the support substrate 10. Further, the lower ends of the through holes 45ah and 47ah are separated from the wiring 12 positioned below the through holes 45ah and 47ah.

FIG. 31 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, a pressing jig 82 is placed on the wiring support base material 32 via the conductive metal films 41a, 41b, and 46. The jig 82 is provided with a bending structure at a predetermined portion. Then, the semiconductor element 21 is bonded to the main surface of the support substrate 10 through an adhesive member (not shown) by a load applied by the jig 82 having the bent structure. Further, the lower ends of the through holes 45ah and 47ah are in contact with the wiring 12 located below the through holes 45ah and 47ah. Further, the conductive metal films 41b and 46 are partially bent by the load applied by the jig 82, and the conductive metal films 41b and 46 have a bent structure.

  Further, the adhesive member 33 disposed under the wiring support base material 32 is deformed because it is a low-elasticity material, and forms a state in which the semiconductor elements 20 a, 20 b, 21 and the periphery of the wiring 12 are wrapped around. In order to promote the wraparound of the adhesive member 33, the support substrate 10 and the like may be heated as necessary.

  In the jig 82, a plurality of through holes 82a are selectively formed so as to correspond to the positions of the through holes 44ah, 44bh, 45ah, 45bh, 47ah, 47bh. That is, the jig 82 also has a function as a mask material.

  Then, an appropriate amount of solder material is filled into the respective through holes 44ah, 44bh, 45ah, 45bh, 47ah, 47bh from these through holes 82a by, for example, dipping method, printing method or the like (not shown).

FIG. 32 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, in the heating furnace, the support substrate 10 or the like is subjected to a reflow process at 260 ° C. for 10 seconds, for example, and placed on the solder pads filled in the through holes and the conductive pads 14a and 14b. The solder material 11a is melted. By this processing, the solder material filled in the through holes forms solder layers 44a, 44b, 45a, 45b, 47a, 47b, and electrode pads 20ap, 20bp, 21p disposed on the semiconductor elements 20a, 20b, 21. And the wiring 12 are electrically connected through the conductive metal films 41a, 41b, 46 and the solder layers 44a, 44b, 45a, 45b, 47a, 47b.

  The solder material 11a melts together during the reflow process. Then, after curing, the solder layer 11 is formed. As a result, the back surfaces of the semiconductor elements 20a, 20b, and 21 and the conductive pads 14a and 14b are joined via the solder layer 11.

  Thereafter, the support jig 80 and the jig 82 are removed, and as shown in FIG. 7, the above-described mounting is completed in a mold (not shown) provided in the resin sealing device. 10 is installed. Further, the wiring 12, the semiconductor elements 20 a, 20 b, 21, the wiring support base 32, the conductive metal films 41 a, 41 b, 46, etc. arranged on the support substrate 10 are sealed with the resin 60.

After sealing with the resin 60, the support substrate 10, the wiring support base material 32, and the resin 60 are divided along the dicing line DL and separated into pieces.
As described above, according to the modification according to the third embodiment, the plurality of conductive metal films 41a, 41b, 46 and the solder layers 44a, 44b, 45a, 45b, 47a, 47b are collectively collected. The electrode between the elements arranged in the semiconductor elements 20a and 20b and the semiconductor element 21 or the electrode arranged in the semiconductor elements 20a, 20b and 21 and the wiring 12 can be electrically connected. As a result, the productivity of the semiconductor device can be significantly improved.

Note that the separated semiconductor device may be provided with a rod-like input / output terminal 51 shown in FIG. 8 if necessary.
As described above, according to the first to third embodiments, the productivity of a semiconductor device as a multi-chip power device can be remarkably improved.

  For example, in the conventional wire bonding method using aluminum wiring, it takes about 1 second to bond one aluminum wiring. Therefore, it takes about 20 seconds to complete the wire bonding in one multichip module on which about 20 bonding wires are mounted.

Thus, when M multichip modules are manufactured, a time of about 20 × M seconds is spent for wire bonding.
However, according to the present embodiment, wire bonding of all M multichip modules can be completed in 10 seconds of reflow processing.

Therefore, according to the present embodiment, the time required for conventional wire bonding can be shortened to about 10 × 20 × M (10 / (20 × M)).
In the semiconductor device shown in the first to third embodiments, the wiring support bases 30, 31, 32 on which the conductive pattern 40 and the conductive metal films 41a, 41b, 46 are selectively arranged are provided in the semiconductor device. It is built in. Thereby, the semiconductor device can be reduced in thickness and size.

  Further, the first to third embodiments described above are not necessarily independent embodiments. One embodiment among the first to third embodiments may be combined with another embodiment.

  Further, the combination of the semiconductor elements (first semiconductor elements) 20a and 20b and the semiconductor element (second semiconductor element) 21 is not limited to the power semiconductor element and the control IC chip described above.

  For example, the first semiconductor element may be a semiconductor memory, and the second semiconductor element may be a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or a semiconductor memory. Good. Further, both the first semiconductor element and the second semiconductor element may be analog IC chips.

1 is a main part view of a semiconductor device according to a first embodiment; It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 1st Embodiment. It is a principal part figure of the electroconductive pattern selectively arrange | positioned on the wiring support base material. FIG. 6 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 1); FIG. 7 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 2); FIG. 9 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 3); FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 4); It is a principal part figure of the semiconductor device which concerns on the modification of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on another modification of 1st Embodiment. It is a principal part figure for demonstrating the structure of a lead frame. It is a principal part figure of the semiconductor device which concerns on 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 5); FIG. 6 is a main part view for explaining one process of manufacturing the semiconductor device (part 6); FIG. 7 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 7); FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 8); FIG. 9 is a main part view for explaining one step of the manufacturing process of the semiconductor device (No. 9). FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 10); FIG. 11 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 11); FIG. 12 is a main part diagram for explaining one process of manufacturing the semiconductor device (part 12); It is a principal part figure of the semiconductor device which concerns on 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment. It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 13). FIG. 14 is a main part diagram for explaining one process of manufacturing the semiconductor device (part 14); FIG. 15 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 15); It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 16). FIG. 17 is a main part view for explaining one process of manufacturing the semiconductor device (part 17); It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 18). It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 19). It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 20). FIG. 21 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 21); It is a principal part figure explaining 1 process of the manufacturing process of a semiconductor device (the 22).

Explanation of symbols

1a, 1b, 1c, 2, 3 Semiconductor device 10 Support substrate 10a Cavity 10b Through hole 10h Heat sink 11, 13, 42a, 42b, 43a, 43b, 44a, 44b, 45a, 45b, 47a, 47b, 52 Solder layer 11a Solder material 12 Wiring 12a Electrode terminal 12g Plating layer 14a, 14b Conductive pad 15 Lead frame 15a, 15b, 15c Device mounting area 20a, 20b, 21 Semiconductor element 20ap, 20bp, 21p Electrode pad 22 Bonding wire 30, 31, 32 Wiring support Substrate 30a, 31a, 31b, 32b Through hole 33 Adhesive member 40 Conductive pattern 40a Extension part 41a, 41b, 46 Conductive metal film 42ab, 42bb, 43ab, 43bb Solder ball 42ah, 42bh, 43ah, 43bh, 44ah, 4 4bh, 45ah, 45bh, 47ah, 47bh Through hole 50, 51 Input / output terminal 51a Clip part 60 Resin 70 Core substrate 71 Resin layer 72 Insulating film 73 Insulating film coated metal wiring board 80 Support jig 81, 82 Jig 80a Pin 81a, 82a Through hole DL Dicing line

Claims (32)

A support substrate;
A plurality of first wirings selectively disposed on the main surface of the support substrate;
A terminal extending from the first wiring to the end of the support substrate;
At least one first semiconductor element mounted on the support substrate;
At least one second semiconductor element for controlling the first semiconductor element;
A wiring support substrate on which a plurality of second wirings are selectively arranged;
And the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring are at least one second wiring. A semiconductor device characterized by being electrically connected through.   2. The semiconductor device according to claim 1, wherein the support substrate is any one of a printed wiring board, a ceramic wiring board, a silicon wiring board, an insulating film-covered metal wiring board, and a lead frame.   3. The semiconductor according to claim 2, wherein a plurality of cavities are formed in the support substrate, and at least one of the first semiconductor element and the second semiconductor element is mounted in the cavity. apparatus.   The cavity mounted so that the height of the first wiring and the electrode pad disposed in the main surface of the first semiconductor element or the second semiconductor element mounted in the cavity is the same height. 4. The semiconductor device according to claim 3, wherein the depth of the semiconductor device is adjusted.   The semiconductor device according to claim 1, wherein the second wiring is a conductive pattern fixed to a main surface of the wiring support base.   A plurality of electrode terminals that are electrically connected to the first wiring are extended to end portions of the main surface of the support substrate, and rod-like input / output terminals are electrically connected to the respective electrode terminals. The semiconductor device according to claim 1. A support substrate;
A plurality of first wirings selectively disposed on the main surface of the support substrate;
A terminal extending from the first wiring to the end of the support substrate;
At least one first semiconductor element mounted on the support substrate;
At least one second semiconductor element for controlling the first semiconductor element;
A wiring support substrate on which a plurality of second wirings are selectively arranged;
A solder layer penetrating the wiring support base material and conducting to the second wiring;
The semiconductor device is characterized in that the first semiconductor element and the first wiring are electrically connected through at least one of the second wiring and the solder layer.   8. The semiconductor device according to claim 7, wherein the support substrate is any one of a printed wiring board, a ceramic wiring board, a silicon wiring board, and an insulating film-covered metal wiring board.   8. The semiconductor device according to claim 7, wherein the electrode of the second semiconductor element and the first wiring are electrically connected by a wire.   8. The semiconductor device according to claim 7, wherein the second wiring is a metal film formed on a main surface of the wiring support base.   The solder layer is disposed on a second main surface opposite to the first main surface of the wiring support base on which the second wiring is disposed, and one end of the solder layer is disposed on the wiring support base. The semiconductor device according to claim 7, wherein the semiconductor device is electrically connected to the second wiring through the material.   8. The semiconductor device according to claim 7, wherein the other end of the solder layer is bonded to the first wiring or the electrode of the first semiconductor element.   By adjusting the height of the solder layer bonded to the first wiring and the height of the solder layer bonded to the electrode of the first semiconductor element, the second wiring and the support substrate The semiconductor device according to claim 7, wherein the main surface is in a parallel state.   A plurality of electrode terminals that are electrically connected to the first wiring are extended to end portions of the main surface of the support substrate, and rod-like input / output terminals are electrically connected to the respective electrode terminals. The semiconductor device according to claim 7. A support substrate;
A plurality of first wirings selectively disposed on the main surface of the support substrate;
A terminal extending from the first wiring to the end of the support substrate;
At least one first semiconductor element mounted on the support substrate;
At least one second semiconductor element for controlling the first semiconductor element;
A wiring support substrate on which a plurality of second wirings are selectively arranged;
A solder layer penetrating the wiring support base material and conducting to the second wiring;
And the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring are at least one second wiring. The semiconductor device is electrically connected through the solder layer.   16. The semiconductor device according to claim 15, wherein the support substrate is any one of a printed wiring board, a ceramic wiring board, a silicon wiring board, and an insulating film-covered metal wiring board.   16. The semiconductor device according to claim 15, wherein the second wiring is a metal film formed on a main surface of the wiring support base.   16. The semiconductor according to claim 15, wherein a plurality of cavities are formed in the support substrate, and at least one of the first semiconductor element and the second semiconductor element is mounted in the cavity. apparatus.   16. The semiconductor device according to claim 15, wherein the main surface of the first semiconductor element or the second semiconductor element is fixed to the main surface of the wiring support base via an adhesive member.   A plurality of electrode terminals that are electrically connected to the first wiring are extended to end portions of the main surface of the support substrate, and rod-like input / output terminals are electrically connected to the respective electrode terminals. The semiconductor device according to claim 15. A step of selectively disposing a plurality of first wirings on the main surface of the continuous support substrate, and terminals extending to the end of the support substrate unit, which are electrically connected to the first wiring;
Mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element on a main surface of the support substrate;
Disposing a solder material on a part of the first wiring, the electrode of the first semiconductor element, and the electrode of the second semiconductor element;
A wiring support base on which a plurality of second wirings are selectively arranged is placed on the first wiring, the first semiconductor element, and the second semiconductor element via the solder material. And a process of
The solder material is melted by a reflow process, and the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring, Electrically connecting through the second wiring;
Sealing the first wiring, the first semiconductor element, the second semiconductor element, the second wiring, and the wiring support base with a resin;
Dividing the support substrate, the wiring support base material and the resin;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 21, wherein at least one cavity is formed in the support substrate, and the first semiconductor element or the second semiconductor element is mounted in the cavity.   22. The method of manufacturing a semiconductor device according to claim 21, wherein after the division, an input / output terminal is electrically connected to the terminal that conducts to the first wiring. A step of selectively disposing a plurality of first wirings on the main surface of the continuous support substrate, and terminals extending to the end of the support substrate unit, which are electrically connected to the first wiring;
Mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element on a main surface of the support substrate;
A wiring support substrate on which a plurality of second wirings and a plurality of solder balls that are electrically connected to the second wirings are selectively disposed, on the first wiring and the first semiconductor element, A step of placing via solder balls;
A step of melting the solder ball by a reflow process and electrically connecting the first semiconductor element and the first wiring through the second wiring and the solder layer;
Sealing the first wiring, the first semiconductor element, the second semiconductor element, the second wiring, the solder layer, and the wiring support base with a resin;
Dividing the support substrate, the wiring support base material and the resin;
A method for manufacturing a semiconductor device, comprising:   The height difference between the first solder ball located on the first wiring and the second solder ball located on the first semiconductor element is provided. 25. A method of manufacturing a semiconductor device according to 24.   25. The electrode of the second semiconductor element and the first wiring are electrically connected by a wire after the second semiconductor element is mounted on the support substrate. A method for manufacturing a semiconductor device.   On the support jig, the continuous support substrate and the wiring support base material are placed, and the support substrate and the through hole formed in the wiring support base material are provided on the pins erected on the support jig. 25. The method of manufacturing a semiconductor device according to claim 24, wherein reflow processing is performed in a state in which the semiconductor device is penetrated.   25. The method of manufacturing a semiconductor device according to claim 24, wherein after the division, an input / output terminal is electrically connected to the terminal conducted to the first wiring. A step of selectively disposing a plurality of first wirings on the main surface of the continuous support substrate, and terminals extending to the end of the support substrate unit, which are electrically connected to the first wiring;
Mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element on the first main surface of the wiring support base via an adhesive member;
A step of selectively disposing a plurality of second wirings on a second main surface opposite to the first main surface on which the first semiconductor element and the second semiconductor element are mounted;
Forming the second wiring, the wiring support substrate bonded to the second wiring, and a through hole penetrating the adhesive member bonded to the bonded wiring support substrate;
Placing the wiring support base so that the first semiconductor element and the second semiconductor element face the main surface of the support substrate on which the first wiring is disposed;
Supplying the solder material into the through hole;
The solder material is melted by a reflow process, and the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring, Electrically connecting through the second wiring;
Sealing the first wiring, the first semiconductor element, the second semiconductor element, the second wiring, and the wiring support base with a resin;
Dividing the support substrate, the wiring support base material and the resin;
A method for manufacturing a semiconductor device, comprising:   30. The at least one cavity is formed in the support substrate, and the first semiconductor element or the second semiconductor element is accommodated in the cavity by placing the wiring support base. The manufacturing method of the semiconductor device of description.   After placing the wiring support base, a load is applied to the wiring support base with a jig having a bending structure, and a part of the second wiring fixed to the main surface of the wiring support base 30. The method of manufacturing a semiconductor device according to claim 29, wherein:   30. The method of manufacturing a semiconductor device according to claim 29, wherein after the division, an input / output terminal is electrically connected to the terminal conducted to the first wiring.

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