JP2007266435A - Semiconductor device and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor package which enable reduction in manufacturing costs. <P>SOLUTION: The semiconductor device 2 includes a board, and a plurality of element portions which are formed on the board and operate as horizontal power devices electrically insulated from each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor package, and more particularly to a semiconductor device and a semiconductor package called a power device to which a high voltage and a large current are applied, such as those for power distribution and automobiles.

Conventionally, a power device for high withstand voltage and high power is known as one of the uses of a semiconductor device. Currently, a device using silicon (Si) is mainly used as such a power device. In order to further improve the performance of the power device, a so-called wide band gap semiconductor (for example, silicon carbide (SiC)) is used. ) Has been proposed (see, for example, Non-Patent Document 1).
Hisashi Kawai, “Expectations for SiC devices from the perspective of automotive electronics”, FED Review, New Functional Device Research and Development Association, Vol. 1 2002

  In a power device using conventional Si, a high output could not be obtained if a horizontal structure was used. For this reason, power devices using Si have a vertical structure.

  However, compared to the vertical structure, in the horizontal structure, the resistance component of the substrate does not affect the current flow path so much, so that there is an advantage of adopting the horizontal structure from the viewpoint of realizing a low-loss device. In the vertical structure, an electrode is disposed on the lower surface of the substrate. Therefore, the vertical structure device has a more complicated mounting structure than the horizontal structure device in which all the electrodes are arranged on one surface of the substrate. Since such a complicated mounting structure leads to an increase in manufacturing cost, there is an advantage in adopting the horizontal structure also in this respect.

  Here, when the above-described wide band gap semiconductor is used as a substrate, it is expected that a sufficient output as a power device can be obtained even if a lateral structure is adopted. However, when the horizontal structure is adopted as the structure of the power device using the wide band gap semiconductor as the substrate, there are the following problems.

  That is, in order to connect the chip to an external circuit, a wire bond technique is widely used. In the wire bond technique, the wire and the electrode on the chip surface are basically connected by a point. And the wiring for collecting an electric current is needed for the electrode (connection area | region) connected with such a wire. Since the power device described above needs to control a relatively large current, so-called electromigration is a problem in the wiring. In order to prevent the occurrence of electromigration, it is necessary to increase the cross-sectional area of the wiring to some extent in order to keep the current density flowing in the wiring below a predetermined value. Here, since there is a limit to securing the cross-sectional area by increasing the thickness of the wiring, the width of the wiring is often widened. However, when the wiring width is increased in this way, there is a problem that the chip size increases as a result. In the lateral structure in which the source and the drain are formed on one surface of the substrate, the influence of the increase in the wiring width as described above (the influence of increasing the chip size) becomes more remarkable.

  Further, as described above, as the chip size increases, the yield of chips deteriorates exponentially due to the occurrence of defects in the substrate and defects caused by the process. And, for wide band gap semiconductors such as SiC described above, since the substrate manufacturing technology and process technology are immature, the incidence of defects due to the substrate and process is higher than conventional Si. . Such a decrease in yield leads to an increase in chip manufacturing costs.

  In addition, in the conventional power device using Si, it is difficult to adopt the horizontal structure as described above, and therefore the vertical structure is the mainstream. Various mounting structures suitable for the vertical structure have been proposed. On the other hand, as for the mounting structure suitable for the horizontal structure, a mounting structure utilizing the feature has not been proposed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a semiconductor package capable of reducing manufacturing costs.

  A semiconductor device according to the present invention includes a semiconductor substrate and a plurality of element portions that are formed on the semiconductor substrate and act as horizontal power devices that are electrically insulated from each other.

  In this way, a large current can be shared and controlled by a plurality of element portions. Therefore, there is no need to flow a large current through one wiring or electrode as in the case where a single element portion is formed on a semiconductor substrate and a large current is controlled by the element portion. In order to prevent this, it is not necessary to increase the area of the wiring or electrode. Accordingly, since the area of the wiring and the electrode can be reduced when viewed in total, the semiconductor device can be miniaturized. As a result, it is possible to suppress a decrease in yield due to an increase in the area occupied by the semiconductor device.

  In the semiconductor device, an electrode portion for connecting the outside of the semiconductor device and the element portion may be formed in the element portion.

  In this case, current can be input / output directly from / to the outside from the electrode portions formed in the individual element portions. Therefore, in order to flow a large current to the set of electrode portions while suppressing the occurrence of electromigration as in the case where a set of electrode portions is formed on a semiconductor substrate on which a plurality of element portions are formed, the electrode portions There is no need to take measures such as increasing the area. For this reason, it is possible to reliably reduce the size of the semiconductor device.

  In the semiconductor device, the semiconductor substrate may be composed of a wide band gap semiconductor.

  In this case, if a substrate composed of a wide band gap semiconductor is used, a high output and low loss device can be realized by adopting a lateral structure as the structure of the power device. In such a horizontal power device, since the electrodes are concentrated on one surface of the semiconductor substrate, the area of the electrodes and wirings is increased in order to suppress the occurrence of electromigration as described above. The enlargement of the apparatus has been a problem. Therefore, the effect of downsizing the semiconductor device is particularly effective by applying the present invention.

  A semiconductor package according to the present invention includes the above semiconductor device, a heat dissipating body on which the semiconductor device is mounted, an external terminal, a plurality of wirings, and a base member. The external terminal is electrically connected to a plurality of element portions of the semiconductor device. The plurality of wirings electrically connect the external terminal and the plurality of element portions, respectively. The base member fixes the relative positions of the plurality of wires.

  In this way, current can be input / output to / from the outside reliably from the individual element portions in the semiconductor device according to the present invention via the plurality of wirings. In addition, since the element portion of the semiconductor device functions as a horizontal power device, an electrode is disposed only on one surface of the semiconductor substrate. Therefore, the semiconductor device can be effectively cooled by bringing the surface of the semiconductor substrate on which the electrode is not disposed into contact with the heat radiator. In addition, since the element portion and the external terminal are individually connected for each external terminal by a plurality of wirings, the output of each element portion is not collectively performed from one electrode portion on the semiconductor substrate, and the external device Can be reliably connected.

  In the semiconductor package, the base member may be a flexible tape-like member that holds a plurality of wirings.

  In this case, since a plurality of wirings are held in advance in the tape-like member, it is possible to easily perform an operation of connecting the element portion on the semiconductor substrate and the external terminal by the plurality of wirings held in the tape-like member. it can.

  As described above, according to the present invention, it is possible to reduce the manufacturing cost by enabling the miniaturization of the semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  FIG. 1 is a schematic plan view of a semiconductor package using a semiconductor device according to the present invention. 2 is a schematic cross-sectional view taken along line II-II in FIG. FIG. 3 is a schematic plan view of a semiconductor device used in the semiconductor package shown in FIG. 4 is a schematic cross-sectional view of the basic cell structure of the semiconductor device taken along line IV-IV in FIG. FIG. 5 is a schematic partial cross-sectional view of the semiconductor device taken along line VV in FIG. A semiconductor device and a semiconductor package according to the present invention will be described with reference to FIGS.

  1 to 3, a semiconductor package 1 according to the present invention includes four semiconductor devices 2 according to the present invention, a heat sink 8 as a heat radiating body on which the semiconductor device 2 is mounted, and external terminals 5 a to 5. 5c, a plurality of wirings 4 and a base member 6, and a connection wiring member 3 used for input / output of signals from each semiconductor device 2 and supply of power. On the surface of the heat sink 8, a plurality of (four in FIG. 1) semiconductor devices 2 each having an element portion acting as a horizontal power device are arranged at a predetermined distance from each other. Note that the number of semiconductor devices 2 mounted on the surface of the heat sink 8 is not limited to four, and may be one, two, or an arbitrary number of five or more. The semiconductor device 2 includes a plurality (four in FIG. 3) of element portions 11 as shown in FIG. In the semiconductor device 2, as will be described later, a plurality of element portions 11 are arranged with an insulating layer therebetween.

  Sheet-like insulators 7 a and 7 b are formed on the surface of the heat sink 8 so as to sandwich the semiconductor device 2. The insulators 7a and 7b are formed so as to extend in a direction along the direction in which the semiconductor devices 2 are arranged. External terminals 5a to 5c are arranged on the insulators 7a and 7b. Specifically, two external terminals 5a and 5b are disposed on the insulator 7a, and the external terminal 5c is disposed on the insulator 7b. The external terminals 5a to 5c are formed to extend in a direction along the extending direction of the insulators 7a and 7b. The external terminals 5 a to 5 c are electrically connected to the plurality of element portions 11 of the semiconductor device 2 through the connection wiring member 3. That is, the plurality of wires 4 of the connection wiring member 3 electrically connect the external terminals 5a to 5c and the electrode portions 12 (see FIG. 3) of the plurality of element portions 11 respectively.

  Here, the connection wiring member 3 includes a base member 6 made of a sheet-like flexible member and a plurality of wirings 4 formed on the base member 6. The base member 6 fixes the relative positions of the plurality of wirings 4. That is, a plurality of wirings 4 are fixed to the surface of the strip-shaped base member 6. For example, an FPC (Flexible Printed Circuit Board) may be used as the connection wiring member 3.

  In this way, it is possible to reliably input / output current and signals to / from the outside through the plurality of wirings 4 from the individual element portions 11 in the semiconductor device 2 according to the present invention. Further, since the element portion 11 of the semiconductor device 2 functions as a horizontal power device, the electrode portion 12 is disposed only on one surface of the semiconductor substrate constituting the semiconductor device 2. Therefore, the semiconductor device 2 can be effectively cooled by bringing the surface of the semiconductor substrate (the back surface of the semiconductor device 2) on the side where the electrode portion 12 is not placed into contact with the heat sink 8 as a heat radiator. . In addition, since the element portion 11 and the external terminals 5a to 5c can be individually connected to the external terminals 5a and 5c by the plurality of wirings 4, the output of each element portion 11 is collected from one electrode portion on the semiconductor device 2. Electrical connection between the semiconductor device 2 according to the present invention which is not performed and the outside of the semiconductor package 1 can be reliably performed.

  In the semiconductor package 1, the base member 6 may be a flexible tape-like member that holds the plurality of wirings 4 as described above. As a material constituting the base member 6, any material can be used as long as it is flexible and can hold the wiring 4.

  In this case, since the plurality of wirings 4 are held in a state where the relative positions are determined in advance on the base member 6 which is a flexible tape-like member, the electrode portion in the element portion 11 of the semiconductor device 2 is previously stored. The positions of the plurality of wirings 4 can be determined on the base member 6 so as to correspond to the arrangement of 12. Therefore, the operation of connecting the element portion 11 of the semiconductor device 2 and the external terminals 5a to 5c by the plurality of wirings 4 can be easily performed. In FIG. 1, the connection wiring members 3 are arranged so as to correspond to the individual semiconductor devices 2. However, if the positioning of the semiconductor device 2 is made accurate in advance, a plurality (for example, two or three) is provided. One connection wiring member 3 may be used for the semiconductor device 2. In this way, the number of manufacturing steps of the semiconductor package 1 can be further reduced.

Next, the configuration of the semiconductor device 2 according to the present invention will be described with reference to FIGS. As shown in FIG. 4, in the basic cell of the semiconductor device 2 using the wide band gap semiconductor, the p ⁻ layer 14 having a thickness T1 is formed on the surface of the substrate 13 made of SiC. The p ⁻ layer 14 is made of SiC having a conductivity type of p type, and is formed by epitaxial growth. An n layer 15 is formed on the p ⁻ layer 14. The n layer 15 is made of SiC of n type conductivity and is formed by epitaxial growth. A p layer 16 is formed on the n layer 15. The p layer 16 is made of SiC having a conductivity type of p type, and is formed by epitaxial growth.

In the basic cell structure shown in FIG. 4, recesses 40 are formed at both ends of the basic cell structure. The recess 40 is formed so as to reach the n layer 15 from the upper surface of the p layer 16. In the region sandwiched between the recesses 40, n ⁺ layers 19 and 21, which are regions where conductive impurities of n-type conductivity are diffused at intervals, are formed in portions adjacent to the recesses 40. Has been. The n ⁺ layers 19 and 21 are formed so as to reach the n layer 15 from the upper surface of the p layer 16. Between the n ⁺ layers 19 and 21, a p ⁺ layer 20, which is a region in which a p-type conductive impurity is diffused, is formed so as to reach the n layer 15 from the upper surface of the p layer 16. ing. In addition, the conductivity of the p-type conductivity is set so that the bottom of one recess 40 (right recess 40 in FIG. 4) reaches the p ^- layer 14 from the n layer 15 (that is, from the bottom of the recess 40). A p ⁺ layer 18, which is a region in which a conductive impurity is diffused, is formed.

An oxide film 17 as an insulating film is formed so as to cover the upper surface of p layer 16 from the inner periphery of recess 40 described above. In the oxide film 17, openings 22 are formed in portions located on the p ⁺ layers 18 and 20 and the n ⁺ layers 19 and 21, respectively. A nickel layer 25 (Ni layer 25) which is a conductor film is formed so as to fill the opening 22. A source electrode 26 is formed on the p ⁺ layer 18 and the n ⁺ layer 19 with a Ni layer 25 interposed. Source electrode 26 is electrically connected to p ⁺ layer 18 and n ⁺ layer 19 through Ni layer 25. A gate electrode 27 is formed on the p ⁺ layer 20 via the Ni layer 25. The gate electrode 27 is electrically connected to the p ⁺ layer 20 and the Ni layer 25. A drain electrode 28 is formed on the n ⁺ layer 21 with a Ni layer 25 interposed therebetween. The drain electrode 28 is electrically connected through the n ⁺ layer 21 and the Ni layer 25. In this manner, a basic cell of a Resurf (REduced SURface Field) SiC-JFET that functions as a horizontal power device is configured.

The distance L3 in the horizontal direction (direction along the surface of the substrate 13) between the n ⁺ layer 19 and the p ⁺ layer 20 can be 3 μm or more and 8 μm or less, for example, 5 μm. Further, the width L2 of the p ⁺ layer 20 can be 3 μm or more and 8 μm or less, for example, 5 μm. Further, the horizontal distance L1 between the p ⁺ layer 20 and the n ⁺ layer 21 can be set to 5 μm or more and 15 μm or less, for example, 9 μm. Further, the thickness T1 of the p ⁻ layer 14 may be 7 μm or more and 14 μm or less, for example, 10 μm. Further, the thickness T2 of the n layer 15 may be 0.2 μm or more and 0.6 μm or less, for example, 0.4 μm. Moreover, the thickness T3 of the p layer 16 can be 0.1 μm or more and 0.4 μm or less, for example, 0.2 μm. Further, the distance T4 between the bottom surface of the p ⁺ layer 20 and the upper surface of the p ⁻ layer 14 (that is, the thickness T4 of the n layer 15 under the p ⁺ layer 20) is 0.1 μm or more and 0.3 μm or less, for example, 0 .2 μm. The semiconductor device 2 shown in FIG. 3 has a rectangular planar shape as shown. The planar shape may be a rectangular shape as shown in FIG. 3 or a square shape. When the planar shape of the semiconductor device 2 is a square shape, the size may be, for example, 2 mm × 2 mm. In this case, the size of the planar shape of the element portion 11 may be, for example, 2 mm × 0.5 mm.

Further, as the substrate 13, a substrate having an n-type conductivity can be used. In this case, the concentration of the n-type conductive impurity in the substrate 13 can be 5E18 / cm ³ or more and 5E19 / cm ³ or less, for example, 1E19 / cm ³ . The concentration of the p-type conductive impurity in the p ⁻ layer 14 can be 5E15 / cm ³ or more and 5E16 / cm ³ or less, for example, 1E16 / cm ³ . In addition, the concentration of the n-type conductive impurity in the n layer 15 can be 5E16 / cm ³ or more and 5E17 / cm ³ or less, for example, 1E17 / cm ³ . In addition, the concentration of the n-type conductive impurities in the n ⁺ layers 19 and 21 can be 5E18 / cm ³ or more and 5E19 / cm ³ or less, for example, 1E19 / cm ³ . The concentration of the p-type conductive impurities in the p ⁺ layers 18 and 20 can be 5E18 / cm ³ or more and 5E19 / cm ³ or less, for example, 1E19 / cm ³ . The concentration of the p-type conductive impurity in the p layer 16 can be 5E16 / cm ³ or more and 5E17 / cm ³ or less, for example, 2E17 / cm ³ .

  Next, with reference to FIG. 5, a cross-sectional structure of the semiconductor device 2 taken along a line segment V-V across the two element portions 11 in FIG. 3 will be described. FIG. 5 also shows a separation structure between the element portions 11 which are blocks in which basic cells are gathered.

In FIG. 5, two adjacent element portions 11 separated by the recess 41 are shown. As shown in FIG. 5, in the semiconductor device 2, the p ⁻ layer 14 is formed on the surface of the substrate 13 made of SiC as described above. An n layer 15 is formed on the p ⁻ layer 14. A p layer 16 is formed on the n layer 15. Concave portions 41 that reach the n layer 15 from the upper surface of the p layer 16 are arranged at an interval. A region sandwiched by the recesses 41 is the element portion 11. That is, the adjacent element portions 11 are partitioned by the concave portions 41.

Since the adjacent element portions 11 have the same structure, the structure of one element portion 11 will be described below. The p ⁺ layer 18, the n ⁺ layer 19, the p ⁺ layer 20, the n ⁺ layer 21, and the p ⁺ layer 31 are formed at a distance from each other in the portion sandwiched between the recesses 41. . A p ⁺ layer 18 that reaches the p ⁻ layer 14 from the n layer 15 is formed at the bottom of the recess 41 adjacent to the p ⁺ layer 18. Further, a p ⁺ layer 32 that reaches the p ⁻ layer 14 from the n layer 15 is formed at the bottom of the recess 41 adjacent to the p ⁺ layer 31.

An oxide film 17 is formed so as to cover the upper surface of p layer 16 from the inner peripheral surface of recess 41. In the oxide film 17, an opening 22 is formed in a region located on the p ⁺ layer 18, the n ⁺ layer 19, the p ⁺ layer 20, the n ⁺ layer 21, and the p ⁺ layer 31. The opening 22 is filled with the Ni layer 25. On the p ⁺ layer 18 and ^{n +} layer 19, ^{the p +} layer 18 and ^{n +} layer 19 electrically connected to the source electrode 26 was through the Ni layer 25 is formed. As can be seen from FIG. 5, the source electrode 26 is formed so as to extend from the region on the n ⁺ layer 19 (the region on the upper surface of the p layer 16) to the bottom of the recess 41. p ⁺ a layer 20 on the, ^{p +} layer 20 and electrically connected to the gate electrode 27 through the Ni layer 25 is formed. On the n ⁺ layer 21 and the p ⁺ layer 31, a drain electrode 28 electrically connected to the n ⁺ layer 21 and the p ⁺ layer 31 through the Ni layer 25 is formed.

  To summarize the characteristic configuration of the semiconductor device 2 described above, the semiconductor device 2 includes a substrate 13 as a semiconductor substrate and a plurality of lateral power devices that are formed on the substrate 13 and electrically insulated from each other. And an element portion 11. In this way, a large current can be shared and controlled by the plurality of element portions 11. Therefore, unlike the case where one element portion is formed on the substrate 13 and a large current is controlled by the element portion, there is no need to flow a large current through one wiring portion or electrode portion in the one element portion. Therefore, it is not necessary to increase the area of the wiring part or the electrode part in order to prevent the occurrence of electromigration due to a large current in the wiring part. Therefore, the area of wiring and electrodes can be reduced when viewed in total. For this reason, size reduction of the semiconductor device 2 can be achieved. As a result, it is possible to suppress a decrease in yield due to an increase in the occupation area of the semiconductor device 2.

  In the semiconductor device 2, an electrode portion 12 for connecting the outside of the semiconductor device 2 and the element portion 11 may be formed in the element portion 11. In this case, current can be directly input / output from / to the outside via the connection wiring member 3 from the electrode portion 12 formed in each element portion 11. Therefore, in order to flow a large current to the set of electrode portions while suppressing the occurrence of electromigration as in the case where the set of electrode portions is formed on the substrate 13 on which the plurality of element portions 11 are formed, the electrodes There is no need to take measures such as increasing the area of the part. For this reason, the semiconductor device 2 can be reliably reduced in size.

  In the semiconductor device 2, the substrate 13 may be formed of a wide band gap semiconductor such as SiC. In this case, if the substrate 13 made of a wide band gap semiconductor is used, a high output and low loss device can be realized by adopting a lateral structure as the structure of the power device.

  Next, a method for manufacturing the semiconductor device 2 shown in FIGS. 3 to 5 will be described. 6 to 11 are schematic views for explaining a method of manufacturing the semiconductor device 2 shown in FIGS. 6 to 11 show a cross section of a basic cell of the element portion 11 constituting the semiconductor device 2.

First, as shown in FIG. 6, a step of preparing a substrate 13 made of SiC is performed. A p ⁻ layer 14, an n layer 15, and a p layer 16 are sequentially formed on the substrate 13 using an epitaxial growth method.

Next, a resist pattern is formed on the p layer 16 using a photolithography method. In the resist pattern, an opening is formed in a portion to be the recess 40 (see FIG. 4). Using this resist pattern as a mask, part of p layer 16 and n layer 15 is removed by reactive ion etching (RIE). In RIE, for example, SF ₆ -based gas can be used as an etching gas. As a result, a recess 40 (see FIG. 7) is formed. Thereafter, the resist pattern is removed. As a result, a structure as shown in FIG. 7 is obtained. Note that when forming the recess 40 serving as the groove, an element isolation groove (the recess 41 in FIG. 5) that separates the adjacent element portions 11 from each other is also formed at the same time.

Next, in a state where the substrate 13 on which the p ⁻ layer 14, the n layer 15, and the p layer 16 formed by the epitaxial growth method are heated to a predetermined temperature, the conductive impurities of n type and p type are removed. By injecting into predetermined regions of the p ⁻ layer 14, the n layer 15 and the p layer 16, p ⁺ layers 18 and 20 and n ⁺ layers 19 and 21 are formed as shown in FIG. The heating temperature of the substrate 13 can be set to 500 ° C., for example.

Next, as shown in FIG. 9, in order to recover the damaged portion of the crystal generated in the epitaxial growth layers such as the p ⁻ layer 14, the n layer 15, and the p layer 16 by the conductive impurity implantation step described above, An annealing step is performed. In this annealing step, for example, the heating temperature of the substrate 13 can be 1800 ° C. and the heating time can be 30 minutes.

  Next, as shown in FIG. 10, a step of forming an oxide film 17 so as to cover the surface of the epitaxial growth layer is performed. The oxide film 17 can be formed by any method, but may be formed by thermal oxidation, for example. As thermal oxidation conditions, for example, the heating temperature of the substrate 13 may be 1200 ° C., and dry oxygen may be used as the atmospheric gas. The thickness of the oxide film 17 can be 0.1 μm, for example.

  Next, a resist pattern is formed on the oxide film 17 by photolithography. Using this resist pattern (resist film having a pattern) as a mask, the oxide film 17 is partially removed to form an opening 22 (see FIG. 11) in the oxide film 17. Thereafter, the resist pattern is removed. The opening 22 is filled with a Ni layer 25 as a conductor film. The Ni layer 25 can be formed by any method, but is preferably formed, for example, by vapor deposition. For example, as a method of forming the Ni layer 25 only inside the opening 22, for example, the following method may be used. That is, a Ni layer is deposited on the entire surface before removing the resist pattern described above from the oxide film 17. Thereafter, the Ni layer formed on the resist pattern (that is, the Ni layer formed at a position other than the inside of the opening 22) is removed together with the resist pattern by removing the resist pattern, or the resist pattern is removed. Then, after depositing a Ni layer so as to cover from the inside of the opening 22 to the upper surface of the oxide film 17, a resist pattern is formed so as to cover the opening 22, and the resist pattern is used as a mask. A method of removing the Ni layer on the oxide film 17 may be used.

  Next, as shown in FIG. 11, a source electrode 26, a gate electrode 27, and a drain electrode 28 made of aluminum (Al) are formed on the Ni layer 25. As a method for forming these electrodes, for example, the following method may be used. First, an Al layer is formed by depositing Al so as to cover the Ni layer 25 and the oxide film 17. Thereafter, a resist pattern is formed on the Al layer by photolithography. Using this resist pattern as a mask, the Al layer is partially removed by etching. Then, the resist pattern is removed. In this way, the semiconductor device 2 is formed as shown in FIG.

  Using the semiconductor device 2 formed as described above, the semiconductor package shown in FIGS. 1 and 2 can be formed. Specifically, first, the heat sink 8 shown in FIGS. 1 and 2 is prepared. Insulators 7 a and 7 b and external terminals 5 a to 5 c are formed in advance on the surface of the heat sink 8. Then, the plurality of semiconductor devices 2 are fixed to the surface of the heat sink 8 between the external terminals 5a and 5b and the external terminal 5c. As a method of fixing the semiconductor device 2 to the surface of the heat sink 8, any fixing method can be adopted as long as the heat of the semiconductor device 2 can be transmitted to the heat sink 8. For example, the semiconductor device 2 may be fixed to the surface of the heat sink 8 by interposing an adhesive layer made of a heat resistant resin or an arbitrary material between the semiconductor device 2 and the surface of the heat sink 8. Since the semiconductor device 2 is directly fixed to the heat sink 8 in this way, heat from the semiconductor device 2 can be efficiently transmitted to the heat sink 8 by a conventional method. That is, the semiconductor package 1 excellent in heat dissipation can be realized.

  In addition, solder bumps 9 (see FIG. 2) are formed in advance on the electrode portions 12 (see FIG. 3) in the plurality of element portions 11 of the semiconductor device 2. Any material may be used as the material constituting the solder bump 9 as long as it is a conductive material, but it is preferable to use lead (Pb) -free solder. Then, the connection wiring member 3 is arranged so as to extend from the external terminals 5a and 5b to the external terminal 5c through the semiconductor device 2. In this state, for example, by locally heating the contact portion between the wiring 4 and the solder bump 9 of the connection wiring member 3 and the connection portion between the wiring 4 and the external terminals 5a to 5c, the wiring 4 and the solder bump 9 and the wiring 4 and the external terminals 5a to 5c are electrically connected to each other. In this way, the semiconductor package 1 shown in FIGS. 1 and 2 can be obtained. In this way, by using the connection wiring member 3 in which the plurality of wirings 4 are formed, the tact time is shortened compared to the case where the semiconductor device 2 and the external terminals 5a to 5c are connected using the wire bonding method as in the prior art. it can. That is, the manufacturing efficiency of the semiconductor package can be improved.

  12 is a schematic cross-sectional view showing a modification of the semiconductor package shown in FIGS. A modification of the semiconductor package according to the present invention will be described with reference to FIG.

  The semiconductor package 1 shown in FIG. 12 basically has the same configuration as that of the semiconductor package 1 shown in FIGS. 1 and 2, but the connection wiring member 3 having the shape and flexibility of the heat sink 8 (FIG. 2). The difference is that a substrate 42 on which wiring is formed is used instead of (see). Specifically, a recess 43 for disposing the semiconductor device 2 therein is formed on the surface of the heat sink 8. The semiconductor device 2 is fixed to the bottom of the recess 43. And the board | substrate 42 is being fixed to the heat sink 8 so that this recessed part 43 may be plugged up. On the substrate 42, wiring (not shown) and external terminals connected to the wiring are formed. The wiring formed on the surface of the substrate 42 is electrically connected to the electrode portion 12 (see FIG. 3) formed on the surface of the semiconductor device 2 via the solder bumps 9. As the substrate 42, a PCB (Printed Circuit Board), a ceramic substrate (for example, aluminum nitride (AlN), silicon nitride (SiN), etc.) with wiring formed on the surface, or the like can be used. Even with such a configuration, the same effects as those of the semiconductor package 1 shown in FIGS. 1 and 2 can be obtained.

  The semiconductor package shown in FIG. 12 can be manufactured by the following processes, for example. First, a substrate 42 on which wiring is formed is prepared. The semiconductor device 2 is fixed to the substrate 42 by connecting the wiring of the substrate 42 and the electrode portion of the semiconductor device 2 via the solder bumps 9. Thereafter, the heat sink 8 is connected to the back surface of the semiconductor device 2 (the surface opposite to the surface facing the substrate 42 in the semiconductor device 2). At this time, the substrate 42 and the heat sink 8 may be connected. As a connection method between the semiconductor device 2 and the heat sink 8, a method similar to the connection method in the semiconductor package 1 shown in FIGS. 1 and 2 can be basically used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The semiconductor device and the semiconductor package according to the present invention are particularly preferably applied to a semiconductor device and a semiconductor package constituting a horizontal power device.

It is a plane schematic diagram of the semiconductor package using the semiconductor device according to the present invention. It is a cross-sectional schematic diagram in line segment II-II of FIG. FIG. 2 is a schematic plan view of a semiconductor device used for the semiconductor package shown in FIG. 1. FIG. 4 is a schematic cross-sectional view of a basic cell structure of a semiconductor device taken along line IV-IV in FIG. 3. FIG. 4 is a partial cross-sectional schematic view of the semiconductor device taken along line VV in FIG. 3. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 6 is a schematic diagram for explaining a method of manufacturing the semiconductor device shown in FIGS. FIG. 3 is a schematic cross-sectional view showing a modification of the semiconductor package shown in FIGS. 1 and 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor package, 2 Semiconductor device, 3 Connection wiring member, 4 wiring, 5a-5c External terminal, 6 Base member, 7a, 7b Insulator, 8 Heat sink, 9 Solder bump, 11 Element part, 12 Electrode part, 13 Substrate, 14 p ⁻ layer, 15 n layer, 16 p layer, 17 oxide film, 18, 20, 31, 32 p ⁺ layer, 19, 21 n ⁺ layer, 22 opening, 25 nickel (Ni) layer, 26 source electrode, 27 gate electrode, 28 drain electrode, 40, 41 recess, 42 substrate on which wiring is formed, 43 recess.

Claims (5)

A semiconductor substrate;
A semiconductor device comprising: a plurality of element portions that are formed on the semiconductor substrate and act as horizontal power devices that are electrically insulated from each other.   The semiconductor device according to claim 1, wherein an electrode portion for connecting the outside of the semiconductor device and the element portion is formed in the element portion.   The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide band gap semiconductor. The semiconductor device according to any one of claims 1 to 3,
A radiator that mounts the semiconductor device;
An external terminal electrically connected to the plurality of element portions of the semiconductor device;
A plurality of wirings that electrically connect the external terminal and the plurality of element portions, respectively;
And a base member for fixing relative positions of the plurality of wirings.   The semiconductor package according to claim 4, wherein the base member is a flexible tape-like member that holds the plurality of wirings.

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