JP2009218391A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of achieving a high coupling ratio without increasing the film thickness of a floating gate electrode, having excellent data retention characteristics, and suitable for high integration. <P>SOLUTION: A first insulating film 6 projected from the surface of a substrate is formed in a part of the region of a semiconductor substrate 1. A gate oxide film 7 is formed on the exposed surface of the substrate, and a first gate electrode film 8 that is conductive is formed on the entire surface in such a manner as to cover the gate oxide film 7 and the upper surface and the side surface of the protrusion of the first insulating film 6. The first gate electrode film 8 that is formed at the upper part of the upper surface of the protrusion of at least the first insulating film 6 is selectively removed. Etching is performed to the first insulating film 6 within the range that the upper surface position of the first insulating film 6 is not lower than the bottom surface position of the first gate electrode film 8. A second insulating film 10 is formed on the entire surface at the film thickness within the range that a recess is not completely filled, and a second gate electrode film 11 that is conductive is formed on the entire surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOSFET structure in which two gate electrode films are stacked via an insulating film.

  7 is a sectional view of a part of a semiconductor device (nonvolatile semiconductor memory device) having a floating gate electrode and a control gate electrode according to a conventional manufacturing method (cut along a plane parallel to the extending direction in which the control gate electrode is formed). It is the schematic which shows a cross-sectional structure.

  A conventional semiconductor device 50 shown in FIG. 7 includes a gate oxide film (tunnel oxide film) 7 and a floating gate electrode (first gate electrode film) on a semiconductor substrate 1 having a trench structure filled with a first insulating film 6. 8, an ONO film 10 and a control gate electrode (second gate electrode film) 11. In FIG. 7, illustration of an interlayer insulating film and the like formed on the upper surface of the second gate electrode film 11 is omitted.

  The semiconductor device 50 having the structure as shown in FIG. 7 controls the voltage (gate voltage) applied to the control gate electrode 11 and the voltage applied between impurity diffusion layers (source / drain) not shown. Thus, the nonvolatile semiconductor memory device performs writing and erasing of information by taking in and releasing charges into the floating gate electrode 8.

  Here, as described above, when writing information into the semiconductor device 50, charges (hot electrons) are injected into the floating gate electrode 8. At this time, a positive voltage is applied to the control gate electrode 11 to raise the potential of the floating gate electrode 8 in order to draw electrons accelerated by the electric field between the source and drain into the floating gate electrode 8.

  The voltage induced in the floating gate electrode 8 is the ratio of the operating voltage applied to the control gate electrode 11 to the voltage induced in the floating gate electrode 8 when a voltage is applied to the control gate electrode 11 (hereinafter, “ It is determined depending on “coupling ratio”. That is, when the same operating voltage is applied to the control gate electrode 11, the induced voltage induced in the floating gate electrode 8 increases as the coupling ratio increases. Therefore, by increasing the coupling ratio, the operating voltage to be applied to the control gate electrode 11 necessary for injecting charges into the floating gate electrode 8 can be lowered.

  The coupling ratio is C2 / (C1 + C2), where C1 is the capacitance between the semiconductor substrate 1 and the floating gate electrode 8, and C2 is the capacitance between the floating gate electrode 8 and the control gate electrode 11. It is a value defined by. Increasing the coupling ratio can be realized by decreasing C1 or increasing C2.

  However, C1 depends on the film thickness of the gate oxide film 7. However, increasing the film thickness of the gate oxide film 7 in order to reduce C1 causes the inflow of charges to the floating gate electrode 8 and the floating gate electrode 8. This makes it difficult to escape the charge and deteriorates the write and erase characteristics. For this reason, it is practically difficult to reduce C1. Therefore, various methods for increasing the coupling ratio by increasing C2 have been developed. For example, as one of the methods, a method of increasing the thickness of the floating gate electrode 8 can be considered.

  FIG. 8 shows a schematic cross-sectional structure diagram when the thickness of the floating electrode 8 is increased. For convenience of explanation, FIG. 8 shows a cross-sectional structure taken along a plane orthogonal to the extending direction of the control gate electrode 11, unlike FIG. 7.

  In the semiconductor device 51 shown in FIG. 8, a plurality of impurity diffusion regions 31 (source / drain regions) are separated from each other on the semiconductor substrate 1, and a gate oxide film 7 is formed above the region sandwiched between both diffusion regions. A floating gate electrode 8, an ONO film 10, and a control gate electrode 11 are stacked in this order from the bottom. An interlayer insulating film 34 is formed so as to cover both gate electrodes and the impurity diffusion region 31, and a wiring 36 is formed on the interlayer insulating film 34. A contact plug 35 penetrating the interlayer insulating film 34 is formed in the upper region of the impurity diffusion region 31, and electrical connection between the wiring 36 and the impurity diffusion region 31 is ensured by the contact plug 35. Insulating films 32 and 33 are formed on the side walls of both gate electrodes.

  As shown in FIG. 8, when the film thickness of the floating gate electrode 8 is made sufficiently thick, the height position of the substrate surface of the semiconductor substrate 1 and the film formation surface of the control gate electrode 11 are greatly different. Therefore, as shown in FIG. 8, when forming the contact plug 35 for ensuring electrical connection between the wiring 36 and the impurity diffusion region 31, it is necessary to form a deep contact hole in the interlayer insulating film 34. Occurs.

  The contact hole is not shaped to extend in a direction completely perpendicular to the substrate surface, and is usually formed with a certain inclination. Therefore, in order to form a contact plug in contact with the impurity diffusion region 31 with a contact area within a range in which the contact resistance is sufficiently suppressed when making electrical connection with the impurity diffusion region 31, the wiring 36 is formed. It is necessary to increase the contact diameter at the upper position near to a certain extent.

  In this way, when the contact plug 35 has a large contact diameter at the upper position close to the wiring 36, if the floating gate electrode 8 is sufficiently thick, the contact plug 35, the floating gate electrode 8, and the contact plug 35 are formed. And the control gate electrode 11 are formed close to each other. For this reason, a short circuit is likely to occur between the contact plug 35 and the floating gate electrode 8 or between the contact plug 35 and the control gate electrode 11.

  On the other hand, if a gate electrode is formed in advance with a sufficient separation distance to avoid such a short circuit, it will go against the recent trend of small-scale and large-capacity nonvolatile semiconductor memory devices.

  Further, in the situation where each element is forced to be miniaturized in response to such a trend of small scale and large capacity, when forming a deep contact hole as described above, the surface of the semiconductor substrate 1 is temporarily assumed. If there are irregularities, the depth of focus required in the photolithography process becomes large, and there is a problem that processing becomes difficult in forming a pattern.

  Therefore, a method for increasing the coupling ratio without increasing the film thickness of the floating gate electrode 8 is required. Here, it is theoretically possible to increase C2 by reducing the thickness of the ONO film 10 between the floating gate electrode 8 and the control gate electrode 11, but the potential barrier of the ONO film 10 is lowered. Therefore, there is a problem that the charges accumulated in the floating gate electrode 8 easily escape to the control gate electrode 11 and the data retention characteristics deteriorate.

  Accordingly, a conventional method for increasing the coupling ratio by making the area where the floating gate electrode 8 and the control gate electrode 11 face each other larger than the area where the floating gate electrode 8 and the semiconductor substrate 1 face each other is disclosed. (For example, see Patent Documents 1 to 3).

JP 2004-119745 A JP-A-10-199998 Japanese Patent Laid-Open No. 6-252412

  In the method according to Patent Document 1, the first gate electrode film to be the floating gate electrode 8 is deposited, and then the surface is etched back into a V shape by performing anisotropic etching, and then the control gate electrode 11 is formed. In this method, the opposing area between the floating gate electrode 8 and the control gate electrode 11 is increased by depositing a two-gate electrode film.

  However, when manufacturing a semiconductor device using the method described in Patent Document 1, if the thickness of the first gate electrode film deposited before etching is thin, the central portion of the floating gate electrode 8, that is, the V-shaped valley There is a concern that the first gate electrode film located in the portion becomes too thin. Therefore, it is necessary to secure a certain thickness of the first gate electrode film. In this case, as described above, the height positions of the electrode surface of the control gate electrode 11 and the substrate surface of the semiconductor substrate 1 are greatly different, which causes the same problem as in FIG.

  In the method according to Patent Document 2, a spacer is formed on the side surface of the first gate electrode film to be the floating gate electrode 8, and a gate electrode film (hereinafter referred to as "first gate electrode film") is further formed on the step between the spacer and the first gate electrode film. 3 ”is formed and integrated with the first gate electrode film, thereby forming a recessed region in the floating gate electrode 8. Thereafter, a second gate electrode film to be the control gate electrode 11 is formed through the ONO film 10, so that the floating gate electrode 8 having a recessed area and the second gate electrode film through the ONO film 10 are formed. In this method, the control gate electrode 11 having a convex region formed by filling is made to face each other, and the facing area between the floating gate electrode 8 and the control gate electrode 11 is increased.

  However, when a semiconductor device is manufactured using the method described in Patent Document 2, the third gate electrode film is deposited in a predetermined shape after depositing the third gate electrode film on the step between the spacer and the first gate electrode film. It is necessary to perform etching. Since this etching process is performed using a photolithography process, it is necessary to form a spacer with a margin for alignment in advance, and it is necessary to use a large layout rule, which is in reverse with the recent trend of miniaturization. Will be.

  Moreover, the method by patent document 3 is as follows. First, after depositing a first gate electrode film to be the floating gate electrode 8 on the semiconductor substrate 1, a gate electrode film (hereinafter referred to as “third gate electrode film”) is further deposited through an etching stopper film. After patterning the first and third gate electrode films, an insulating film (element isolation insulating film) is formed in the gate electrode formation outside region, and etch back is performed on the third gate electrode film to form the insulating film side wall. The third gate electrode film is left in the shape of a sidewall, and the third stopper film is doped with phosphorus to cause dielectric breakdown of the etching stopper film interposed between the two gate electrode films. Thus, both the gate electrode films are integrated to form the floating gate electrode 8 having a recessed region, and then the control is performed via the ONO film 10. By forming the second gate electrode film to be the gate electrode 11, the floating gate electrode 8 having a recessed region and the recessed region are filled with the second gate electrode film through the ONO film 10. This is a method of increasing the facing area between the floating gate electrode 8 and the control gate electrode 11 by making the control gate electrode 11 having a convex region to face each other.

  However, when a semiconductor device is manufactured using the method described in Patent Document 3, when the step of electrically connecting the first gate electrode film and the third gate electrode film by performing dielectric breakdown on the etching stopper film is performed. As a result of applying a large stress to the gate oxide film 4 formed below the first gate electrode film, there is a concern that charges accumulated in the floating gate electrode 8 are likely to escape through the gate oxide film 4, There is a problem that data retention characteristics deteriorate.

  In view of the above-described problems, the present invention can realize a high coupling ratio without increasing the thickness of the floating gate electrode, and has excellent data retention characteristics and manufacture of a semiconductor device suitable for high integration. It aims to provide a method.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a MOSFET structure in which two gate electrode films are stacked with an insulating film interposed therebetween. A first step of forming a first insulating film protruding from the substrate surface in a partial region; a second step of forming a gate oxide film on the exposed surface of the semiconductor substrate after the completion of the first step; After the step, a conductive first gate electrode film is formed on the entire surface so as to cover the upper surface and side surfaces of the gate oxide film and the protruding portion of the first insulating film, thereby adjacent the first insulating film. A third step of forming a first recess having a bottom surface and an inner wall covered with the first gate electrode film therebetween, and at least above the upper surface of the protrusion of the first insulating film after the third step is completed Selectively removing the formed first gate electrode film After the completion of the fourth step and the fourth step, the first insulating film is etched within a range in which the top surface position of the first insulating film is not lower than the bottom surface position of the first gate electrode film. A fifth step of forming a second recess having a bottom surface of the first insulating film and an inner wall of the first gate electrode film; and after the fifth step, the first recess and the second recess are completely formed Forming a second insulating film on the entire surface with a film thickness within a range not filled, and then forming a conductive second gate electrode film on the entire surface, and after the sixth step, the second gate electrode And a seventh step of forming source / drain regions after patterning the film.

  According to the first feature of the method of manufacturing a semiconductor device according to the present invention, the third step forms the first recess whose bottom and inner walls are covered with the first gate electrode film, and the fifth step. A second recess having a bottom surface covered with the first insulating film and an inner wall covered with the first gate electrode film is formed. Then, since the second gate electrode film is formed through the second insulating film formed within a range that does not completely fill the first and second recesses, the second gate electrode film is It will have the convex part shape which protrudes below above a recessed part and a 2nd recessed part. Therefore, compared with the case where the second gate electrode film is formed on the flattened first gate electrode film, the area where both gate electrodes face each other can be increased. Thereby, since the area which both gate electrodes oppose can be enlarged rather than the area which the bottom face of a 1st gate electrode film | membrane and the board | substrate surface of a semiconductor substrate oppose, a coupling ratio can be enlarged.

  The positions where the first and second recesses are formed are determined by the position where the first insulating film is formed and the thickness of the first gate electrode film deposited in the third step. That is, if the first insulating film is previously aligned in the first step, the formation positions of the first recess and the second recess can be determined in a self-aligned manner according to the deposited film thickness of the first gate electrode film. it can. Therefore, the first and second recesses can be formed at predetermined positions of the first gate electrode film without considering the alignment accuracy, and can be applied to fine layout rules.

  In addition, since the first insulating film having the protruding shape is already formed in the previous stage of the third step, the bottom surface and the inner side can be obtained without increasing the thickness of the first gate electrode film in the third step. A first recess having a wall covered with the first gate electrode film may be formed. Furthermore, even if the thickness of the first gate electrode film is not increased, etching back is performed on the first insulating film in the fifth step, so that the bottom surface is the first insulating film and the inner wall is the first gate. A second recess made of an electrode film can be formed. That is, according to the method for manufacturing a semiconductor device according to the present invention, it is not necessary to form a first gate electrode film having a large film thickness in advance in order to increase the opposing area of both gate electrode films. For this reason, the height position of the film formation surface of the control gate electrode can be suppressed within a predetermined range from the substrate surface of the semiconductor substrate. Therefore, since the contact plug can be formed with a certain distance from the control gate electrode or the floating gate electrode, a problem that a short circuit occurs between them can be prevented.

  Further, in the method for manufacturing a semiconductor device according to the present invention, it is not necessary to perform a dielectric breakdown process on the insulating film in order to increase the facing area between both gate electrodes, and no stress is generated on the gate oxide film. Therefore, in the completed semiconductor device, the charge accumulated in the floating gate electrode formed by the first gate electrode film does not easily escape through the gate oxide film, and the semiconductor device has excellent data retention characteristics. Can be realized.

  In addition to the first feature described above, the method for manufacturing a semiconductor device according to the present invention is such that the film thickness of the first gate electrode film formed in the third step is formed at the end of the second step. The second feature is that it is smaller than the height of the protruding portion of the first insulating film and smaller than one half of the interval between two adjacent first insulating films.

  According to the second feature of the method of manufacturing a semiconductor device according to the present invention, the first recess can be reliably formed at the end of the third step.

  In addition to the first or second feature, the method of manufacturing a semiconductor device according to the present invention includes dry etching with respect to the first gate electrode film in a state where the non-removed region is masked in the fourth step. The third feature is that the process is a step of exposing the upper surface of the protruding portion of the first insulating film and separating the first gate electrode film into a plurality of parts.

  In addition to the first or second feature, the semiconductor device manufacturing method according to the present invention is planarized until the fourth step reaches a height position of the upper surface of the protruding portion of the first insulating film. The fourth feature is that the process is a step of exposing the upper surface of the protruding portion of the first insulating film and separating the first gate electrode film into a plurality of parts.

  According to the present invention, there is provided a method for manufacturing a semiconductor device capable of realizing a high coupling ratio without increasing the thickness of the floating gate electrode, having excellent data retention characteristics, and suitable for high integration. .

  In the following, an embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “method of the present invention” as appropriate) will be described with reference to FIGS. Note that the schematic configuration diagrams shown in the following drawings are merely schematically illustrated, and the dimensional ratio of the actual structure does not necessarily match the dimensional ratio of the drawings. Further, the same components as those in FIGS. 7 and 8 referred to in the background art will be described with the same reference numerals.

  FIG. 1 is a schematic sectional view of a semiconductor device manufactured by the method of the present invention. FIG. 1 relates to a semiconductor device (nonvolatile semiconductor memory device) having a floating gate electrode and a control gate electrode, as in FIG. 7, and is a cross-sectional view cut along a plane parallel to the extending direction in which the control gate electrode is formed. It is.

  A semiconductor device 20 shown in FIG. 1 is formed on a semiconductor substrate 1 in which a trench structure is formed so as to fill the trench, and an insulating film for element isolation protruding above the surface of the semiconductor substrate 1. 6 (hereinafter referred to as “first insulating film 6” as appropriate), gate oxide film 7, electrode film constituting floating gate electrode 8 (hereinafter referred to as “first gate electrode film 8” as appropriate), control gate electrode 11 , And an ONO film (corresponding to a second insulating film) interposed between the first gate electrode film 8 and the second gate electrode film 11. ) 10.

  The first gate electrode film 8 has an end protruding upward in a region between two adjacent first insulating films 6 and having a recess therebetween. Then, an ONO film 10 is formed so as to cover the first gate electrode film 8 having this recess, and thereby, a recess 15 whose bottom surface and inner wall are covered with the ONO film 10 is formed. The recess 15 is filled with the second gate electrode film 11.

  Further, the first gate electrode film 8 is separated from the adjacent first gate electrode film 8 across the protruding portion of the first insulating film 6 and the upper region of the upper surface thereof. In this region, the ONO film 10 is formed so as to cover the first insulating film 6 constituting the bottom surface and the first gate electrode film 8 constituting the inner side wall, whereby the bottom surface and the inner side wall are covered with the ONO film 10. A concave portion 16 is formed. The recess 16 is filled with the second gate electrode film 11. That is, the second gate electrode film 11 is formed in the recesses 15 and 16 so as to have a protruding portion protruding downward.

  With this configuration, the second gate electrode film 11 and the first gate electrode are interposed via the ONO film 10 in a region (including the inside of the recess 15) except for the region above the upper surface of the first insulating film 6. The film 8 faces in a direction parallel to the substrate surface of the semiconductor substrate 1, and further faces in a direction perpendicular to the substrate surface in the recess 15 and the recess 16. Thereby, the opposing area of the 1st gate electrode film 8 and the 2nd gate electrode film 11 becomes larger than the opposing area of the 1st gate electrode film 8 and the semiconductor substrate 1, and it can increase a coupling ratio. Therefore, a large coupling ratio can be easily ensured even if the elements are miniaturized.

  Hereinafter, the method of the present invention will be described with reference to FIGS. 2 and 3 schematically show process cross-sectional views when the semiconductor device 20 is manufactured using the method of the present invention, and FIGS. 2A to 2F and FIG. The drawings are divided into (a) to (e) (divided into two drawings for the sake of space). FIG. 4 is a flowchart showing the manufacturing process of the method of the present invention, and each step in the following sentence represents each step of the flowchart shown in FIG.

  First, as shown in FIG. 2A, a silicon oxide film 2 and a silicon nitride film 3 are deposited on the entire surface of the semiconductor substrate 1 (step # 1). At this time, the silicon oxide film 2 may be formed by a thermal oxidation method in a diffusion furnace, and the silicon nitride film 3 may be formed by a low pressure CVD (Chemical Vapor Deposition) method.

  Note that the total thickness of the silicon oxide film 2 and the silicon nitride film 3 deposited in step # 1 is such that the first insulating film 6 protrudes even after the film forming process of the gate oxide film 7 in the subsequent step # 6 is completed. 6a (see FIG. 2F), the gate oxide film 7 formed in step # 6 is sufficiently thicker than the film thickness.

  Next, as shown in FIG. 2B, a photoresist film 4 patterned by a photolithography method is formed in a predetermined region on the silicon nitride film 3 using an exposure apparatus such as a stepper scanner (step #). 2). In this step # 2, the photoresist film 4 is left on the region other than the region where the trench hole 5 is formed by etching the semiconductor substrate 1 in the next step # 3. Incidentally, even if an antireflection film made of an organic BARC (Bottom Anti-Reflective Coating) material or a polysilicon material is deposited on the silicon nitride film 3 in order to suppress reflection of light irradiated in the photolithography process. good. Even in this case, since the deposited antireflection film can be removed after the photoresist film 4 is peeled off and before the etching process for the semiconductor substrate 1 is started, the subsequent processes are not affected. .

  Next, as shown in FIG. 2C, the silicon nitride film 3 and the silicon oxide film 2 are etched by plasma etching using the photoresist film 4 formed in step # 2 as a mask, and then the photoresist film Using the silicon nitride film 3 remaining after peeling 4 as a mask, the semiconductor substrate 1 is etched to form trench holes 5 (step # 3).

  Next, a silicon oxide film (HDP film, hereinafter referred to as “first insulating film 6”) is deposited by a high density plasma CVD method to completely fill the trench hole 5 (step # 4). Thereafter, a polishing process is further performed using CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 3 around the trench hole 5 is exposed (see FIG. 2D).

  The processes according to steps # 1 to # 4 described above are the same as the manufacturing process performed using a known trench isolation method called a so-called STI (Shallow Trenchi Isolation) method. In addition, after the trench formation process which concerns on step # 3, before filling the 1st insulating film 6, you may have the process of growing an oxide film about 10-50 nm using a diffusion furnace. By performing such a process, the shape of the corner portion generated in the portion having a different height position by the etching process according to Step # 3 is rounded, and the electric field can be prevented from concentrating on the corner portion.

  Next, as shown in FIG. 2 (e), the silicon nitride film 3 is removed using a chemical solution such as phosphoric acid heated to a high temperature, and a silicon oxide film using a chemical solution such as hydrofluoric acid heated to a high temperature. By removing 2, the substrate surface of the semiconductor substrate 1 is exposed (step # 5). Thereby, the height positions of the upper surface of the first insulating film 6 and the substrate surface of the semiconductor substrate 1 are different, and the first insulating film 6 protrudes (protruding portion 6a).

  Next, as shown in FIG. 2F, the substrate surface of the semiconductor substrate 1 is oxidized by using a diffusion furnace, so that the silicon oxide film 7 (hereinafter referred to as “gate oxide film 7”) having a thickness of about 10 nm is described. ) Is grown (step # 6). The gate oxide film 7 takes in electrons from the impurity diffusion region with respect to the floating gate electrode 8 formed in a later process, or passes electrons when the electrons are extracted from the floating gate electrode 8 into the impurity diffusion region. To form a so-called tunnel oxide film.

  As described above, in step # 1, the total thickness of the silicon oxide film 2 and the silicon nitride film 3 is made sufficiently thicker than the thickness of the gate oxide film 7. For this reason, the height of the protruding portion 6a of the first insulating film 6 protruding after step # 5 is sufficiently higher than the thickness of the gate oxide film 7. Therefore, even after the gate oxide film 7 is formed in step # 6, the upper surface of the first insulating film 6 still protrudes and the protruding portion 6a is formed.

  After step # 5 (after exposing the substrate surface of the semiconductor substrate 1), a silicon oxide film having a thickness of about 20 nm is formed using a diffusion furnace before the gate oxide film 7 forming step according to step # 6. After the formation on the substrate surface of the semiconductor substrate 1, a step of removing the formed silicon oxide film may be further performed. This step is a method called a sacrificial oxidation method, and has the effect of improving the film quality of the gate oxide film 7 by forming the gate oxide film 7 after executing the step.

  Further, after the completion of step # 5, before the step of forming the gate oxide film 7 according to step # 6, a photomask process and ion implantation process for well region formation and surface concentration adjustment (not shown) may be performed.

  Next, as shown in FIG. 3A, a conductive material film made of polysilicon (hereinafter referred to as “first gate electrode film 8”) is formed to a thickness of, for example, about 10 nm by the CVD method. (Step # 7). As a result, the upper surface of the gate oxide film 7 and the upper surface and side surfaces of the protruding portion 6 a of the first insulating film 6 are covered with the first gate electrode film 8.

  Incidentally, the film thickness of the first gate electrode film 8 formed in this step # 7 is such that after the completion of this step # 7, the bottom surface and the inner wall between the two adjacent first insulating films 6 are the first gate electrode film. 8 is set within a range in which a recess 13 (corresponding to a first recess) is formed.

  FIG. 5 is an enlarged view of FIG. 3A and is a diagram for explaining the film thickness of the first gate electrode film 8 formed in Step # 7.

  As shown in FIG. 5, when the protrusion height of the protrusion 6a of the first insulating film 6 protruding at the end of step # 6 is k, the first gate electrode film has a film thickness larger than the protrusion height k. When depositing 8, the recess 13 is completely filled with the first gate electrode film 8, so that the recess 13 is not formed after step # 7 is completed. That is, the film thickness d of the first gate electrode film 8 formed in step # 7 needs to satisfy d <k.

  Further, assuming that the interval between the protruding portions 6a of the two adjacent first insulating films 6 protruding at the end of step # 6 is W, the value “2d” obtained by doubling the film thickness d is larger than the interval W. If it is larger, the recess 13 is completely filled with the first gate electrode film 8. Therefore, the film thickness d of the first gate electrode film 8 formed in Step # 7 needs to satisfy 2d <W, in other words, the film thickness d needs to satisfy d <W / 2.

  In summary, the thickness of the first gate electrode film 8 formed in step # 7 is smaller than the height of the protruding portion 6a of the first insulating film 6 protruding at the end of step # 6, and is adjacent to the first gate electrode film 8. By setting the value to be smaller than one half of the interval between the protruding portions 6a of the two first insulating films 6 to be performed, the bottom surface between the two adjacent first insulating films 6 after step # 7 is completed. And the recessed part 13 which makes the inner wall the 1st gate electrode film 8 can be formed.

  Next, as shown in FIG. 3B, the first gate electrode film 8 formed above the height position of the upper surface of the protruding portion 6a of the first insulating film 6 is selectively removed (step #). 8). Specifically, etching is performed in a state where a non-etched region is masked with a resist film patterned by photolithography. As another method, the entire surface may be flattened by CMP until reaching the height position of the upper surface of the protruding portion 6a of the first insulating film 6.

  By the completion of this step # 8, the upper surface of the first insulating film 6 is exposed. On the other hand, the recess 13 is still formed as shown in FIG. That is, by this step # 8, the first gate electrode film 8 having the recess 13 is separated into a plurality.

  Next, as shown in FIG. 3C, wet etching is performed on the first insulating film 6 using a chemical solution such as hydrofluoric acid, and the height position of the upper surface is retracted (step # 9). At this time, the etching amount is set so that at least the height position of the upper surface of the first insulating film 6 is higher than the bottom surface position of the first gate electrode film 8. This is because if the upper surface of the first insulating film 6 is positioned below the bottom surface position of the first gate electrode film 8, the first gate electrode film 8 is patterned in a later step to form the floating gate electrode. Since the patterning process becomes difficult when forming, the object is to avoid such a situation. In consideration of the variation in wet etching, the etching conditions are set such that the height position of the upper surface of the first insulating film 6 is higher than the position of the bottom surface of the first gate electrode film 8 even when the etching amount becomes maximum. Set.

  By this step # 9, a recess 14 (corresponding to a second recess) having the first insulating film 6 as a bottom surface and the first gate electrode film 8 as an inner wall is formed.

  Next, as shown in FIG. 3D, the ONO film 10 is formed on the entire surface with a film thickness that does not completely fill the recesses 13 and 14 (step # 10). In this step # 10, for example, after a silicon oxide film is grown on the first gate electrode film 8 using a diffusion furnace, a silicon nitride film and a silicon oxide film (HTO film) are sequentially formed by the CVD method. To do. By the ONO film 10 formed in this step # 10, electrons taken into the first gate electrode film 8 (floating gate electrode) are converted into a second gate electrode film 11 (control gate electrode) formed in a later process. ) Has an effect of preventing escape. Even after the end of Step # 10, the recesses 15 and 16 are still formed.

  Next, as shown in FIG. 3E, an electrode film made of polysilicon (hereinafter referred to as “second gate electrode film 11”) is deposited on the entire surface by the CVD method (step # 11). As a result, the recesses 15 and 16 formed at the end of step # 10 are completely filled. As a result, the second gate electrode film 11 has a protrusion protruding downward at the position where the recesses 15 and 16 are formed. Has a shape. Thereafter, the second gate electrode film 11 and the first gate electrode film 8 are simultaneously patterned to form a control gate electrode and a floating gate electrode.

  In step # 8, after selectively removing a part of the first gate electrode film 7, a photomask process and an etching process are performed before the ONO film 10 forming process according to step # 10. The floating gate electrode may be formed by patterning the first gate electrode film 7. In this case, after step # 11, the control gate electrode is formed by patterning only the second gate electrode film 11.

  After that, it conforms to a conventional method for manufacturing a nonvolatile semiconductor memory device. That is, impurity ion implantation is performed using these gate electrodes as a mask to form source / drain regions, and then an interlayer insulating film is deposited. Then, after forming a contact hole in a predetermined region on the source / drain region, a metal film such as tungsten (W) is filled in the contact hole, and a wiring layer for electrical connection with the source / drain region Form. If necessary, an interlayer insulating film forming step and a wiring layer forming step may be performed a plurality of times to form a multilayer wiring structure.

  If necessary, after forming a control gate electrode and source / drain regions, a high melting point metal such as cobalt (Co) or titanium (Ti) is deposited by a sputtering method, and then a lamp annealing apparatus or the like is used. Heat treatment (about 450 to 530 ° C. for Co, about 650 to 700 ° C. for Ti) to form a metal salicide layer on the surface of the control gate electrode and the source / drain regions, A step of performing phase transition of the salicide layer formed by removing unreacted refractory metal using a chemical solution such as hydrogen oxide and then performing heat treatment for about 30 seconds (both Co and Ti are about 650 to 700 ° C.). May be added. By doing so, the contact resistance between the wiring layer and the source / drain regions can be reduced.

  In place of the salicide, a step of depositing tungsten silicide may be performed after the deposition step of the second gate electrode film 11 according to step # 11.

  By going through the above-described steps # 1 to # 11, the device 20 of the present invention that can secure a large coupling ratio as shown in FIG. 1 can be manufactured.

  The formation position of the first insulating film 6 is determined by the mask position of the photoresist film 4 in Step # 2, the formation position of the first gate electrode film 8 is determined by the formation position of the first insulating film 6, and The formation positions of the recesses 15 and 16 are determined by the formation position of the first insulating film 6 and the deposited film thickness of the first gate electrode film 8. That is, if the alignment for forming the element isolation region is previously performed in step # 2, the formation positions of the recesses 15 and 16 are self-aligned according to the deposited film thickness of the first gate electrode film 8 in step # 7. Determined. Therefore, since the recesses 15 and 16 can be formed without considering the alignment accuracy, the invention can be applied to a fine layout rule.

  Furthermore, according to the method of the present invention, the recesses 15 and 16 are formed by performing the selective removal process for the first gate electrode film 8 according to Step # 8 and the etch-back process for the first insulating film 6 according to Step # 9. Since it can be formed, it is not necessary to form the first gate electrode film 8 having a sufficient thickness in advance. For this reason, the height position of the film formation surface of the second gate electrode film 11 can be suppressed within a predetermined range from the substrate surface of the semiconductor substrate 1. Therefore, since the contact plug can be formed with a certain distance from the control gate electrode or the floating gate electrode, a problem that a short circuit occurs between them can be prevented.

  In addition, since the dielectric breakdown process is not required for the insulating film in order to increase the facing area between both gate electrodes, no stress is generated on the gate oxide film 7. For this reason, the charge accumulated in the first gate electrode film (floating gate electrode) 8 under the written state does not easily escape through the gate oxide film 7, and the nonvolatile semiconductor has excellent data retention characteristics. A storage device can be realized.

  In the above embodiment, in step # 8, the first gate electrode film 8 whose height is higher than the upper surface of the protruding portion 6a of the first insulating film 6 is selectively removed, whereby the first gate electrode film 8 is removed. The upper surface and the upper surface of the protruding portion 6a are aligned. The present step # 8 is not limited to such a method, and may be any configuration that selectively removes at least the first gate electrode film 8 formed above the upper surface of the protruding portion 6a. That is, at the end of step # 8, for example, the configuration shown in FIG. 6A may be used instead of the configuration shown in FIG. In this case, it can be realized by performing etching while masking the non-etched region by photolithography. After the configuration of FIG. 6A, the semiconductor device having the configuration shown in FIG. 6B can be realized through the steps # 9 to # 11. In the case of FIG. 6B as well, the configuration having the recesses 15 and 16 whose bottom and inner walls are surrounded by the ONO film 10 can be realized as in FIG. By filling, the coupling ratio can be increased.

Schematic sectional view of a semiconductor device manufactured by the method of the present invention Part of a process cross-sectional view when manufacturing a semiconductor device based on the method of the present invention Another part of the process cross-sectional view when manufacturing a semiconductor device based on the method of the present invention The flowchart which shows the manufacturing process of this invention method in order Schematic cross-sectional view related to one process when manufacturing a semiconductor device based on the method of the present invention Another schematic cross-sectional view according to one process when manufacturing a semiconductor device based on the method of the present invention Schematic sectional view of a conventional nonvolatile semiconductor memory device Another schematic cross-sectional view of a conventional nonvolatile semiconductor memory device

Explanation of symbols

1: Semiconductor substrate 2: Silicon oxide film 3: Silicon nitride film 4: Photoresist film 5: Trench hole 6: First insulating film 6a: Projection of first insulating film 7: Gate oxide film 8: First gate electrode film (Floating gate electrode)
10: Second insulating film (ONO film)
11: Second gate electrode film (control gate electrode)
13, 14, 15, 16: Recess 20: Semiconductor device manufactured by the method of the present invention 31: Impurity diffusion region (source / drain region)
32: Side wall insulating film 33: Side wall insulating film 34: Interlayer insulating film 35: Contact plug 36: Wiring 50: Semiconductor device manufactured by a conventional method 51: Semiconductor device manufactured by a conventional method

Claims (4)

A method of manufacturing a semiconductor device having a MOSFET structure in which two gate electrode films are stacked via an insulating film,
A first step of forming a first insulating film protruding from the substrate surface in a partial region of the semiconductor substrate;
A second step of forming a gate oxide film on the exposed surface of the semiconductor substrate after completion of the first step;
After completion of the second step, a conductive first gate electrode film is formed on the entire surface so as to cover the upper surface and side surfaces of the gate oxide film and the protruding portion of the first insulating film, thereby adjacent the first step. A third step of forming a first recess whose bottom surface and inner wall are covered with the first gate electrode film between the insulating films;
A fourth step of selectively removing at least the first gate electrode film formed above the upper surface of the protrusion of the first insulating film after the third step;
After the fourth step, the first insulating film is etched so that the top surface position of the first insulating film is not lower than the bottom surface position of the first gate electrode film. A fifth step of forming an insulating film, a second recess having an inner wall made of the first gate electrode film;
After the fifth step, a second insulating film is formed on the entire surface with a thickness that does not completely fill the first recess and the second recess, and then a conductive second gate electrode film is formed on the entire surface. A sixth step of forming;
And a seventh step of forming source / drain regions after patterning the second gate electrode film after completion of the sixth step.   The film thickness of the first gate electrode film formed in the third step is smaller than the height of the protruding portion of the first insulating film formed at the end of the second step, and two adjacent the above-mentioned The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device manufacturing method is smaller than one half of the interval between the first insulating films.   In the fourth step, the first gate electrode film is dry-etched in a state where the non-removed region is masked to expose the upper surface of the protruding portion of the first insulating film, and the first gate The method for manufacturing a semiconductor device according to claim 1, wherein the method is a step of separating the electrode film into a plurality of parts.   In the fourth step, planarization is performed until the height of the upper surface of the protruding portion of the first insulating film is reached, thereby exposing the upper surface of the protruding portion of the first insulating film and the first gate. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a step of separating the electrode film into a plurality of parts.