JP2009206230A - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
JP2009206230A
JP2009206230A JP2008045551A JP2008045551A JP2009206230A JP 2009206230 A JP2009206230 A JP 2009206230A JP 2008045551 A JP2008045551 A JP 2008045551A JP 2008045551 A JP2008045551 A JP 2008045551A JP 2009206230 A JP2009206230 A JP 2009206230A
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package
substrate
solder ball
mounting substrate
package substrate
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Shigetoshi Ogawa
成敏 小川
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked semiconductor package capable of reducing the inductance components of a power route or a ground route and being easily and stably mounted on a mounting substrate. <P>SOLUTION: The stacked semiconductor package comprises: a first package substrate 11 arranged in the first layer from the side of the mounting substrate 16, loaded with a semiconductor element 13 and provided with a first solder ball group 14 to be bonded with the mounting substrate 16; and a second package substrate 12 arranged in the upper layer of the first package substrate 11, loaded with the semiconductor element 13, provided with a projection part 17 projected to the side of the mounting substrate 16 on the outer peripheral part, and provided with a second solder ball group 15 to be bonded with the mounting substrate 16 on the projection part 17. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体チップが実装された複数の半導体パッケージを３次元的に複数積層した積層型半導体パッケージに関するものである。   The present invention relates to a stacked semiconductor package in which a plurality of semiconductor packages on which semiconductor chips are mounted are three-dimensionally stacked.

近年、電子機器の高性能化がますます進んでおり、これに対応して、使用される電気回路の規模は益々増大してきている。そこで電気回路の高密度化を実現するために、半導体パッケージを３次元的に積層配置した積層型半導体パッケージが使用されるようになっている。   In recent years, the performance of electronic devices has been increasing, and the scale of electric circuits used has been increasing more and more accordingly. Therefore, in order to realize a high density electric circuit, a stacked semiconductor package in which semiconductor packages are three-dimensionally stacked is used.

３次元配置の積層型半導体パッケージの構造としては、ＰＯＰ（Package on Package）構造などが知られている。ＰＯＰ構造はパッケージとパッケージとを、はんだボールなどを介して上下に複数枚積層した構造となっており、一つのパッケージを実装するスペースにおいて複数のパッケージを実装することができる。この結果限られたスペースで高密度な実装を行なうことが可能となる。   As a structure of a three-dimensionally arranged stacked semiconductor package, a POP (Package on Package) structure or the like is known. The POP structure has a structure in which a plurality of packages are stacked one above the other through solder balls, and a plurality of packages can be mounted in a space for mounting one package. As a result, high-density mounting can be performed in a limited space.

半導体パッケージは、信号を伝達するためのシグナル線路と、電源およびグランド電位を供給するための電源経路およびグランド経路とを有している。電源経路およびグランド経路は、通常パッケージ内に形成した電極プレーンを用い、パッケージ外部からの電源電位およびグランド電位をチップ部品に供給する役割を果たしている。   The semiconductor package has a signal line for transmitting a signal, and a power supply path and a ground path for supplying a power supply and a ground potential. The power supply path and the ground path normally use an electrode plane formed in the package, and serve to supply a power supply potential and a ground potential from the outside of the package to the chip component.

この電源経路およびグランド経路はインダクタンス成分を持っており、このインダクタンス成分が増大したり変動が激しかったりする場合、半導体素子のスイッチング動作に伴うスイッチングノイズが大きくなり、信号伝送が行われるシグナル線路に影響を及ぼす。そして、シグナル線路における高速伝送の妨害になってしまう。   The power supply path and ground path have an inductance component. If the inductance component increases or the fluctuation is severe, the switching noise associated with the switching operation of the semiconductor element increases, affecting the signal line on which signal transmission is performed. Effect. And it will become the obstruction of the high-speed transmission in a signal line.

積層型半導体パッケージの場合、電源経路およびグランド経路は複数のパッケージ内の線路やパッケージ間を接続するはんだボールを介して形成されるため、経路におけるインダクタンス成分の変動が大きくなってしまう。この結果安定した信号品質を得られないという問題があった。   In the case of a stacked semiconductor package, since the power supply path and the ground path are formed via lines in a plurality of packages and solder balls connecting the packages, fluctuations in inductance components in the paths become large. As a result, there is a problem that stable signal quality cannot be obtained.

このような問題に対して、例えば特許文献１に示す構造のものが提案されている。図３はその断面図、図４は積層方向からみた透視図である。   For such a problem, for example, a structure shown in Patent Document 1 has been proposed. FIG. 3 is a sectional view thereof, and FIG. 4 is a perspective view seen from the stacking direction.

３１は第１層目のパッケージ、３２は第２層目のパッケージ、３３は前記３１および３２に実装されるチップ部品、３６は実装基板、３４は第１の半田ボール群、３５は第２の半田ボール群である。   31 is a first layer package, 32 is a second layer package, 33 is a chip component mounted on the 31 and 32, 36 is a mounting substrate, 34 is a first solder ball group, and 35 is a second package. A group of solder balls.

第１層目のパッケージ３１が実装基板３６に第１の半田ボール群３４を介して実装され、さらに第１層目のパッケージ３１に第２層目のパッケージ３２が積層されている。   A first layer package 31 is mounted on a mounting substrate 36 via a first solder ball group 34, and a second layer package 32 is stacked on the first layer package 31.

第２層目のパッケージ３２は一部が第２の半田ボール群３５を介して直接実装基板３６に接続されている。第２層目への電源経路およびグランド経路は第２の半田ボール群３５を介して形成される。第２の半田ボール群の半田ボールは大径であることから実装基板３６と第２層目のパッケージ３２を直接接続することができる。このため、複数の半田ボールやパッケージを介して電源経路およびグランド経路を形成した場合に比べ、接続点が少なくなるためインダクタンス成分の変動が少なくなる。   Part of the second layer package 32 is directly connected to the mounting substrate 36 via the second solder ball group 35. The power supply path and the ground path to the second layer are formed via the second solder ball group 35. Since the solder balls of the second solder ball group have a large diameter, the mounting substrate 36 and the second-layer package 32 can be directly connected. For this reason, compared with the case where the power supply path and the ground path are formed via a plurality of solder balls and packages, the number of connection points is reduced, and the fluctuation of the inductance component is reduced.

この結果、第２層目のパッケージにおける電源経路およびグランド経路のノイズが軽減され高品質な伝送特性をもつ積層型半導体パッケージを実現できる。
特開２００６−２９５１３６号公報 As a result, it is possible to realize a stacked semiconductor package having reduced noise in the power supply path and ground path in the second layer package and having high quality transmission characteristics.
JP 2006-295136 A

しかしながら、上記従来の構造の積層型半導体パッケージでは、第２層目への電源経路およびグランド経路として大径の半田ボールを用いているため、この半田ボールを多く配置することができない。電源経路およびグランド経路におけるインダクタンス成分は、並列接続により低減させることができるが、このような従来の構造では多くの電源経路およびグランド経路を確保することが困難であり、さらなるインダクタンス成分の低減を図りにくいという問題点があった。   However, since the stacked semiconductor package having the conventional structure uses large-diameter solder balls as the power supply path and the ground path to the second layer, many solder balls cannot be arranged. The inductance component in the power supply path and the ground path can be reduced by parallel connection. However, it is difficult to secure a large number of power supply paths and ground paths in such a conventional structure, and the inductance component is further reduced. There was a problem that it was difficult.

また、大きさの異なる半田ボールを用いることによって半田ボールの融解温度の差が生じて融解時間のずれが起こることに対し、従来技術では大径である第２の半田ボール群を低融点材料とすることによって対応している。しかし、異なる融解点の材料であること、および半田ボールの大きさが異なるから、融解時間のずれを調整する手間がかかり、実装基板への実装プロセスが煩雑になるという問題点があった。   In addition, the use of solder balls of different sizes causes a difference in melting temperature of the solder balls, resulting in a shift in melting time. In contrast, the second solder ball group having a large diameter in the prior art is used as a low melting point material. It corresponds by doing. However, since the materials have different melting points and the size of the solder balls is different, there is a problem that it takes time to adjust the difference in melting time, and the mounting process on the mounting board becomes complicated.

本発明はこれらの問題点を解決するために為されたもので、その目的は、電源経路またはグランド経路のインダクタンス成分を低減させると共に、容易で安定した実装基板への実装を可能とする積層型半導体パッケージを提供することにある。   The present invention has been made to solve these problems, and its purpose is to reduce the inductance component of the power supply path or the ground path and to enable easy and stable mounting on a mounting board. It is to provide a semiconductor package.

本発明の積層型半導体パッケージは、半導体素子が実装される複数枚のパッケージ基板が積層されており、実装基板に実装される積層型半導体パッケージにおいて、前記実装基板側から数えて第１層目に配置され、半導体素子を搭載するとともに、前記実装基板と接合するための第１の半田ボール群を有した第１パッケージ基板と、該第１パッケージ基板よりも上層に配置され、半導体素子を搭載するとともに外周部に前記実装基板側へ向けて突出する凸部を有し、該凸部に前記実装基板と接合するための第２の半田ボール群を有した第２パッケージ基板とを具備していることを特徴とする。   In the stacked semiconductor package of the present invention, a plurality of package substrates on which semiconductor elements are mounted are stacked, and in the stacked semiconductor package mounted on the mounting substrate, the first layer counted from the mounting substrate side. A first package substrate having a first solder ball group for bonding to the mounting substrate and a semiconductor device mounted thereon, and disposed in an upper layer than the first package substrate and mounting the semiconductor device And a second package substrate having a convex portion projecting toward the mounting substrate side on the outer peripheral portion and a second solder ball group for joining the mounting substrate to the convex portion. It is characterized by that.

また、好ましくは、前記第１および前記第２の半田ボール群は、同じ大きさおよび同じ材質の半田ボールで構成され、前記第２の半田ボール群の一部は、前記第２パッケージ基板に電源を供給するための経路を成しており、前記第２の半田ボール群の一部は、前記第２パッケージ基板にグランド電位を供給するための経路を成しており、前記第２パッケージ基板は、前記実装基板側に開口するキャビティ構造を有しており、該キャビティの周囲が前記凸部として用いられて前記第２の半田ボール群を有するとともに、前記キャビティ内に前記第１パッケージ基板が収容されていることを特徴とする。   Preferably, the first and second solder ball groups are composed of solder balls of the same size and the same material, and a part of the second solder ball group is supplied to the second package substrate. A part of the second solder ball group forms a path for supplying a ground potential to the second package substrate, and the second package substrate And a cavity structure that opens to the mounting substrate side, the periphery of the cavity is used as the convex portion to have the second solder ball group, and the first package substrate is accommodated in the cavity. It is characterized by being.

本発明の積層型半導体パッケージによれば、半導体素子が実装される複数枚のパッケージ基板が積層されており、実装基板に実装される積層型半導体パッケージにおいて、前記実装基板側から数えて第１層目に配置され、半導体素子を搭載するとともに、前記実装基板と接合するための第１の半田ボール群を有した第１パッケージ基板と、該第１パッケージ基板よりも上層に配置され、半導体素子を搭載するとともに外周部に前記実装基板側へ向けて突出する凸部を有し、該凸部に前記実装基板と接合するための第２の半田ボール群を有した第２パッケージ基板とを具備していることから、実装基板と第２パッケージ基板との間の接続は、複数のパッケージ基板およびそれらの間の接続のための半田ボールを複数回通過する場合に比べてインダクタンスの変化点が少なくなり、インダクタンス成分の変動が抑えられ、伝送特性に与える影響を低く抑えることができる。   According to the stacked semiconductor package of the present invention, a plurality of package substrates on which semiconductor elements are mounted are stacked, and in the stacked semiconductor package mounted on the mounting substrate, the first layer counted from the mounting substrate side. A first package substrate having a first solder ball group to be mounted on the mounting substrate and having a first solder ball group to be bonded to the mounting substrate; and disposed on an upper layer than the first package substrate. And a second package substrate having a convex portion projecting toward the mounting substrate side on the outer peripheral portion, and a second solder ball group for joining the mounting substrate to the convex portion. For this reason, the connection between the mounting substrate and the second package substrate is more difficult than the case where a plurality of package substrates and solder balls for connection between them are passed multiple times. Change point of inductance is reduced, variation in the inductance component is suppressed, it is possible to suppress the influence on the transmission characteristics.

また、第１および第２の半田ボール群は、同じ大きさおよび同じ材質の半田ボールで構成されている場合は、実装基板へ実装する際の半田ボールの融解の状態を揃えることができる。つまり、各所の半田ボールの融解のタイミングが揃うため、半田材や半田ボールの大きさの調整などによって融解のタイミングを揃える必要がなく、実装を容易にすることが可能となる。   When the first and second solder ball groups are composed of solder balls having the same size and the same material, the melting state of the solder balls when mounted on the mounting board can be made uniform. That is, since the melting timings of the solder balls in each place are aligned, it is not necessary to align the melting timing by adjusting the size of the solder material or the solder balls, and the mounting can be facilitated.

また、第２の半田ボール群の一部は、第２パッケージ基板に電源を供給するための経路またはグランド電位を供給するための経路を成している場合には、第２の半田ボール群は実装基板と第２パッケージ基板を直接接続しているため、電源経路またはグランド経路におけるインダクタンス成分の変動が少なくなり、安定した伝送特性を得ることができる。   In addition, when a part of the second solder ball group forms a path for supplying power to the second package substrate or a path for supplying a ground potential, the second solder ball group is Since the mounting substrate and the second package substrate are directly connected, fluctuations in the inductance component in the power supply path or the ground path are reduced, and stable transmission characteristics can be obtained.

以下に、添付の図面を参照して、本発明の実施の形態について説明する。図１はパッケージ基板を２枚積層した本発明の積層型半導体パッケージの断面図、図２は図１の積層型半導体パッケージを積層方向（上面側）から第２パッケージ基板１２を透視して見た透視図である。   Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a stacked semiconductor package of the present invention in which two package substrates are stacked. FIG. 2 is a perspective view of the stacked semiconductor package of FIG. 1 seen through the second package substrate 12 from the stacking direction (upper side). FIG.

図１，図２において、１１は第１パッケージ基板、１２は第２パッケージ基板、１３は半導体素子、１４は第１の半田ボール群、１５は第２の半田ボール群、１６は実装基板である。第１パッケージ基板１１および第２パッケージ基板１２にはそれぞれ半導体素子１３が実装されている。   1 and 2, 11 is a first package substrate, 12 is a second package substrate, 13 is a semiconductor element, 14 is a first solder ball group, 15 is a second solder ball group, and 16 is a mounting substrate. . A semiconductor element 13 is mounted on each of the first package substrate 11 and the second package substrate 12.

実装基板１６上に第１の半田ボール群１４を介して第１パッケージ基板１４が実装されており、さらに上層に半田ボール１９を介して第２パッケージ基板１２が実装されている。第２パッケージ基板１２は外周部に実装基板１６側へ向けて突出する凸部１７を有し、凸部１７の実装基板１６と対向する下面には第２の半田ボール群１５を介して直接実装基板１６に接続されている。   The first package substrate 14 is mounted on the mounting substrate 16 via the first solder ball group 14, and the second package substrate 12 is further mounted on the upper layer via the solder ball 19. The second package substrate 12 has a convex portion 17 projecting toward the mounting substrate 16 on the outer peripheral portion, and is directly mounted on the lower surface of the convex portion 17 facing the mounting substrate 16 via the second solder ball group 15. It is connected to the substrate 16.

第１パッケージ基板１１および第２パッケージ基板１２は、例えばセラミックグリーンシート積層法によって積層されて積層体とされる。積層体は、酸化アルミニウム質焼結体，窒化アルミニウム質焼結体，炭化珪素質焼結体，窒化珪素質焼結体，ムライト質焼結体またはガラスセラミックス等の無機絶縁材料から成る。あるいはポリイミド，エポキシ樹脂，フッ素樹脂，ポリノルボルネンまたはベンゾシクロブテン等の有機絶縁材料を積層して、あるいはセラミックス粉末等の無機絶縁物粉末をエポキシ系樹脂等の熱硬化性樹脂で結合して成る複合絶縁材料などの電気絶縁材料を積層して多層の有機樹脂基板とされる。   The first package substrate 11 and the second package substrate 12 are laminated by, for example, a ceramic green sheet lamination method to form a laminate. The laminate is made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Or a composite made by laminating organic insulating materials such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or bonding inorganic insulating powder such as ceramic powder with thermosetting resin such as epoxy resin A multilayer organic resin substrate is formed by laminating an electrical insulating material such as an insulating material.

基板の厚みや大きさは、使用する材料の特性に応じて、要求される仕様に対応する機械的強度や電気的特性、基板形成の容易さ等の条件を満たすように適宜設定される。   The thickness and size of the substrate are appropriately set according to the characteristics of the material used so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications, ease of substrate formation, and the like.

本発明の積層型半導体パッケージの一実施形態例においては、第２パッケージ基板１２が実装基板１６側に実装基板１６と対向するように開口するキャビティ１８構造を有している。そして、キャビティ１８部には第１パッケージ基板１１が収容される形状となっている。すなわち、第２パッケージ基板１２は、平面視において、第１パッケージ基板１１より一回り大きい面積を有している。また、第２パッケージ基板の周辺部が実装基板１６側に突出する凸部１７の役割を果たし、凸部１７において第２の半田ボール群１５を介して実装基板１６に直接接続されている。この第２の半田ボール群１５、第２パッケージ基板１２の凸部１７を通り、第２パッケージ基板に形成された配線導体を通る電流経路は、その一部が、第２パッケージ基板１２に実装されている半導体素子１３を駆動させるための電源電位およびグランド電位を供給する経路を形成する。   In one embodiment of the stacked semiconductor package of the present invention, the second package substrate 12 has a cavity 18 structure that opens on the mounting substrate 16 side so as to face the mounting substrate 16. The cavity 18 is configured to accommodate the first package substrate 11. That is, the second package substrate 12 has a larger area than the first package substrate 11 in plan view. Further, the peripheral portion of the second package substrate serves as a convex portion 17 protruding toward the mounting substrate 16, and the convex portion 17 is directly connected to the mounting substrate 16 via the second solder ball group 15. A part of the current path passing through the second solder ball group 15 and the projection 17 of the second package substrate 12 and passing through the wiring conductor formed on the second package substrate is mounted on the second package substrate 12. A path for supplying a power supply potential and a ground potential for driving the semiconductor element 13 is formed.

近年の半導体素子１３は、集積度が高くなり、半導体素子１３のスイッチング動作に伴って、電源経路またはグランド経路には大きく変動する電源電流またはグランド電流が流れる。この場合、電源経路またはグランド経路のインダクタンス成分がスイッチングノイズの原因となって半導体素子１３の動作に影響を与えるため、パッケージ基板１１，１２のインダクタンス成分およびインダクタンス成分の変動を低く抑えることが重要となっている。   In recent years, the degree of integration of the semiconductor element 13 is increased, and a power supply current or a ground current that varies greatly flows in the power supply path or the ground path in accordance with the switching operation of the semiconductor element 13. In this case, since the inductance component of the power supply path or the ground path causes switching noise and affects the operation of the semiconductor element 13, it is important to keep the inductance component and the variation of the inductance components of the package substrates 11 and 12 low. It has become.

本発明の一実施形態の構造によると、実装基板１６と第２パッケージ基板１２の間の接続は半田ボール１５を介して行なわれ、複数のパッケージ基板およびそれらの間の接続のための半田ボールを複数回通過する場合に比べて、インダクタンスの変化点が少ない。この結果、インダクタンス成分の変動が抑えられ伝送特性に与える影響も低く抑えることができる。   According to the structure of one embodiment of the present invention, the connection between the mounting substrate 16 and the second package substrate 12 is made via the solder balls 15, and a plurality of package substrates and solder balls for connection between them are provided. There are fewer inductance change points than when passing multiple times. As a result, the fluctuation of the inductance component can be suppressed and the influence on the transmission characteristics can be suppressed low.

さらに、本発明の一実施形態の構造によると、第２パッケージ基板１２に凸部１７が設けられており、これによって第２の半田ボール群１５の半田ボール１５の大きさが図３に示す従来の半田ボール３５と比べ小さくなっている。従来の構造では第２の半田ボール群３５の半田ボール３５が大きいため、多くの半田ボール３５を第２層目のパッケージ３２の周囲に配置することが難しく、電源経路・グランド経路を多く確保することが困難であった。本発明の構造では、第２の半田ボール群１５の半田ボール１５を小径とすることができるため多くの半田ボール１５を第２パッケージ基板１２の周囲に配置することが可能である。この結果、第２パッケージ基板１２への電源経路・グランド経路を並列に多く形成することができるので、パッケージ基板１２全体のインダクタンス成分を低くすることができる。この結果、電源経路・グランド経路に起因するノイズの影響が低減され、より高品質な伝送特性を実現することができる。   Furthermore, according to the structure of one embodiment of the present invention, the convex portion 17 is provided on the second package substrate 12, whereby the size of the solder ball 15 of the second solder ball group 15 is shown in FIG. It is smaller than the solder ball 35. In the conventional structure, since the solder balls 35 of the second solder ball group 35 are large, it is difficult to arrange many solder balls 35 around the package 32 of the second layer, and a large number of power supply paths and ground paths are secured. It was difficult. In the structure of the present invention, the solder balls 15 of the second solder ball group 15 can have a small diameter, so that a large number of solder balls 15 can be arranged around the second package substrate 12. As a result, since many power supply paths and ground paths to the second package substrate 12 can be formed in parallel, the inductance component of the entire package substrate 12 can be reduced. As a result, the influence of noise caused by the power supply path / ground path is reduced, and higher quality transmission characteristics can be realized.

また、本発明は第１の半田ボール１４と第２の半田ボール１５を同じ大きさ、同じ材質のものとしている。半田ボール１４，１５は加熱されてある融解温度に達すると融解し、再び温度が下がることで固まり上下の基板を接合する。実装基板１６上に積層型半導体パッケージを形成し、実装する際にも加熱によって半田ボール１４，１５を融解させてパッケージ基板１１，１２および実装基板１６を接合させるが、使用する半田ボール１４，１５に融解温度の差がある場合各々の接合状態にばらつきが生じ、安定した実装が困難になる。   In the present invention, the first solder ball 14 and the second solder ball 15 are made of the same size and the same material. When the solder balls 14 and 15 are heated and reach a melting temperature, the solder balls 14 and 15 are melted, and the temperature lowers again to solidify and join the upper and lower substrates. When the stacked semiconductor package is formed on the mounting substrate 16 and mounted, the solder balls 14 and 15 are melted by heating to bond the package substrates 11 and 12 and the mounting substrate 16, but the solder balls 14 and 15 to be used are used. When there is a difference in melting temperature, variations occur in each bonding state, and stable mounting becomes difficult.

これを調整するために半田ボール１４，１５の材質を変更したり、半田ボール１４，１５の直径の大きさを変更したりすると、その調整に手間がかかり、実装プロセスが煩雑になることが考えられる。これに対し本発明では全ての半田ボール１４，１５が同一の形状および材質となっているため、常に安定した実装が可能になり、接合状態の調整などの手間もかからない。   If the material of the solder balls 14 and 15 is changed or the diameter of the solder balls 14 and 15 is changed in order to adjust this, the adjustment takes time and the mounting process becomes complicated. It is done. On the other hand, in the present invention, since all the solder balls 14 and 15 have the same shape and material, stable mounting is always possible, and it is not necessary to adjust the joining state.

本積層型半導体パッケージに用いられる半田ボールの材質として、Ｓｎ−Ｂｉ（すず-ビスマス），Ｎｉ−Ｐｄ−Ａｕ（ニッケル-パラジウム-金）またはＳｎ−Ａｇ−Ｃｕ（すず-銀-銅）等が挙げられる。半田ボールの直径は、積層型半導体パッケージの用途に応じて、適宜決めればよい。   As the material of the solder balls used in the stacked semiconductor package, Sn-Bi (tin-bismuth), Ni-Pd-Au (nickel-palladium-gold), Sn-Ag-Cu (tin-silver-copper), etc. Can be mentioned. The diameter of the solder ball may be appropriately determined according to the use of the stacked semiconductor package.

以上のように本発明によれば、電源経路またはグランド経路のインダクタンス成分を効果的に低減させると共に、容易で安定した実装基板１６への実装を可能とする積層型半導体パッケージを提供することができる。   As described above, according to the present invention, it is possible to provide a stacked semiconductor package that can effectively reduce the inductance component of the power supply path or the ground path and can be easily and stably mounted on the mounting substrate 16. .

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更を加えることは何ら差し支えない。例えば、図５，図６，図７にそれぞれ実施の形態の他の例として示すものでもよい。   In addition, this invention is not limited to the example of the above embodiment, A various change may be added in the range which does not deviate from the summary of this invention. For example, FIGS. 5, 6, and 7 may be shown as other examples of the embodiment.

すなわち、図５は第２パッケージ基板４２のキャビティ部に複数の第１パッケージ基板４１を積層したものを収容した構造である。この結果、第１パッケージ基板４１がいくつあっても第２パッケージ基板４２には安定した電源またはグランド電位を供給することができる。   That is, FIG. 5 shows a structure in which a plurality of first package substrates 41 are stacked in the cavity portion of the second package substrate 42. As a result, a stable power supply or ground potential can be supplied to the second package substrate 42 no matter how many first package substrates 41 are present.

図６は第２パッケージ基板５２の外周部の一部のみに凸部５７を形成した例である。第２パッケージ基板５２の大きさに制限がある場合でも、この構造を用いることによって第２パッケージ基板５２に安定した電源・グランド電位を供給することができる。   FIG. 6 shows an example in which convex portions 57 are formed only on a part of the outer peripheral portion of the second package substrate 52. Even when the size of the second package substrate 52 is limited, a stable power supply / ground potential can be supplied to the second package substrate 52 by using this structure.

図７は第１パッケージ基板６１を第２パッケージ基板６２のキャビティ部に収容し、さらにこれらを第２パッケージ基板６３のキャビティ部に収容する構造としたものである。この構造によれば第２パッケージ基板６２と第２パッケージ基板６３とに同時に安定した電源・グランド電位を供給することができる。   FIG. 7 shows a structure in which the first package substrate 61 is accommodated in the cavity portion of the second package substrate 62 and further these are accommodated in the cavity portion of the second package substrate 63. According to this structure, a stable power supply / ground potential can be supplied to the second package substrate 62 and the second package substrate 63 simultaneously.

また図５，図６，図７において、第１の半田ボール群４３，５３，６４および第２の半田ボール群４４，５４，６５のそれぞれの直径を略同一に揃えた大きさ、同様の材質のものとしているため、常に安定した実装が可能となる。   5, 6, and 7, the first solder ball groups 43, 53, 64 and the second solder ball groups 44, 54, 65 have substantially the same diameter and the same material. Therefore, stable implementation is always possible.

本発明の積層型半導体パッケージの実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the laminated semiconductor package of this invention. 図１の積層型半導体パッケージを積層方向から見た透視図である。FIG. 2 is a perspective view of the stacked semiconductor package of FIG. 1 viewed from a stacking direction. 従来の積層型半導体パッケージの実施の形態例を示す断面図である。It is sectional drawing which shows the example of embodiment of the conventional laminated semiconductor package. 図３の積層型半導体パッケージを積層方向から見た透視図である。FIG. 4 is a perspective view of the stacked semiconductor package of FIG. 3 as viewed from the stacking direction. 本発明の積層型半導体パッケージの実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the laminated semiconductor package of this invention. 本発明の積層型半導体パッケージの実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the laminated semiconductor package of this invention. 本発明の積層型半導体パッケージの実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the laminated semiconductor package of this invention.

符号の説明Explanation of symbols

１１：第１パッケージ基板
１２：第２パッケージ基板
１３：半導体素子
１４：第１の半田ボール群
１５：第２の半田ボール群
１６：積層基板
１７：凸部
１８：キャビティ 11: First package substrate 12: Second package substrate 13: Semiconductor element 14: First solder ball group 15: Second solder ball group 16: Multilayer substrate 17: Convex portion 18: Cavity

Claims (5)

半導体素子が実装される複数枚のパッケージ基板が積層されており、実装基板に実装される積層型半導体パッケージにおいて、前記実装基板側から数えて第１層目に配置され、半導体素子を搭載するとともに、前記実装基板と接合するための第１の半田ボール群を有した第１パッケージ基板と、該第１パッケージ基板よりも上層に配置され、半導体素子を搭載するとともに外周部に前記実装基板側へ向けて突出する凸部を有し、該凸部に前記実装基板と接合するための第２の半田ボール群を有した第２パッケージ基板とを具備していることを特徴とする積層型半導体パッケージ。 A plurality of package substrates on which semiconductor elements are mounted are stacked, and in the stacked semiconductor package mounted on the mounting substrate, the semiconductor element is mounted on the first layer counting from the mounting substrate side. A first package substrate having a first solder ball group for joining to the mounting substrate, and disposed on an upper layer than the first package substrate to mount a semiconductor element and to an outer peripheral portion toward the mounting substrate. And a second package substrate having a second solder ball group for joining to the mounting substrate on the convex portion. . 前記第１および前記第２の半田ボール群は、同じ大きさおよび同じ材質の半田ボールで構成されていることを特徴とする請求項１記載の積層型半導体パッケージ。 2. The stacked semiconductor package according to claim 1, wherein the first and second solder ball groups are composed of solder balls having the same size and the same material. 前記第２の半田ボール群の一部は、前記第２パッケージ基板に電源を供給するための経路を成すことを特徴とする請求項１または請求項２記載の積層型半導体パッケージ。 3. The stacked semiconductor package according to claim 1, wherein a part of the second solder ball group forms a path for supplying power to the second package substrate. 4. 前記第２の半田ボール群の一部は、前記第２パッケージ基板にグランド電位を供給するための経路を成すことを特徴とする請求項１または請求項２記載の積層型半導体パッケージ。 3. The stacked semiconductor package according to claim 1, wherein a part of the second solder ball group forms a path for supplying a ground potential to the second package substrate. 前記第２パッケージ基板は、前記実装基板側に開口するキャビティ構造を有しており、該キャビティの周囲が前記凸部として用いられて前記第２の半田ボール群を有するとともに、前記キャビティ内に前記第１パッケージ基板が収容されていることを特徴とする請求項１乃至請求項４のいずれかに記載の積層型半導体パッケージ。 The second package substrate has a cavity structure that opens to the mounting substrate side, and the periphery of the cavity is used as the convex portion to have the second solder ball group, and the cavity is formed in the cavity. The stacked semiconductor package according to claim 1, wherein the first package substrate is accommodated.
JP2008045551A 2008-02-27 2008-02-27 Stacked semiconductor package Pending JP2009206230A (en)

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WO2018139045A1 (en) * 2017-01-27 2018-08-02 株式会社村田製作所 Circuit module and interposer

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JP2014003202A (en) * 2012-06-20 2014-01-09 Ngk Spark Plug Co Ltd Photo-electric consolidation unit and element mounting module
WO2018139045A1 (en) * 2017-01-27 2018-08-02 株式会社村田製作所 Circuit module and interposer
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