WO2015056430A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2015056430A1
WO2015056430A1 PCT/JP2014/005164 JP2014005164W WO2015056430A1 WO 2015056430 A1 WO2015056430 A1 WO 2015056430A1 JP 2014005164 W JP2014005164 W JP 2014005164W WO 2015056430 A1 WO2015056430 A1 WO 2015056430A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
semiconductor device
partial region
resin
semiconductor
Prior art date
Application number
PCT/JP2014/005164
Other languages
French (fr)
Japanese (ja)
Inventor
裕貴 山下
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2015056430A1 publication Critical patent/WO2015056430A1/en

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Definitions

  • the present disclosure relates to a semiconductor device in which a signal processing chip is stacked on a sensor chip.
  • the semiconductor module disclosed in Patent Document 1 is provided in a first semiconductor chip in which a photoelectric conversion region is formed and a region in which no photoelectric conversion region is formed on the first semiconductor chip. And a second semiconductor chip electrically connected. Furthermore, the first semiconductor chip and the second semiconductor chip are accommodated, and at least a region facing the photoelectric conversion region is formed of a light-transmitting material, and the second semiconductor chip and the package are thermally bonded. And a heat conducting member to be connected.
  • the present disclosure in a configuration in which a second semiconductor chip is mounted on a circuit surface of a first semiconductor chip, a parasitic capacitance of a resin formed in a gap between two chips with respect to an output signal from a sensor unit of the first semiconductor chip
  • the present invention provides a semiconductor device that can reduce the deterioration of the waveform due to the addition of, and improve the signal quality.
  • the semiconductor device in the present disclosure includes a first semiconductor chip having a first electrode and a first partial region on a first surface, and a first partial region on a first surface of the first semiconductor chip. And a second semiconductor chip mounted so as to be avoided. Further, the connection member is joined to the first electrode and electrically connects the first semiconductor chip and the second semiconductor chip, and the connection member is surrounded by the gap between the first semiconductor chip and the second semiconductor chip. And a resin disposed on the surface. The protruding amount of the resin is characterized in that it is formed smaller on the first partial region side of the second semiconductor chip than on the facing side of the first partial region.
  • the semiconductor device is based on the resin for the output wiring from the first partial region of the first semiconductor chip by minimizing the protrusion of the resin on the first partial region side of the second semiconductor chip. Minimizing parasitic capacitance and improving the quality of the output signal.
  • Sectional drawing of the semiconductor device which concerns on 1st Embodiment The top view of the semiconductor device concerning a 1st embodiment 1 is a block diagram showing circuit operation of a semiconductor device according to a first embodiment.
  • the top view which shows the modification 1 of the semiconductor device which concerns on 1st Embodiment The top view which shows the modification 2 of the semiconductor device which concerns on 1st Embodiment
  • the top view which shows the modification 4 of the semiconductor device which concerns on 1st Embodiment The top view which shows the modification 5 of the semiconductor device which concerns on 1st Embodiment.
  • Sectional drawing which shows the modification 6 of the semiconductor device which concerns on 1st Embodiment The top view which shows the modification 6 of the semiconductor device which concerns on 1st Embodiment.
  • FIGS. 4A to 4C are plan views showing a method for manufacturing a semiconductor device according to the first embodiment.
  • FIGS. 4A to 4C are plan views showing a method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 1A (First embodiment)
  • FIG. 1B (First embodiment)
  • FIG. 1B (First embodiment)
  • FIG. 1A is a cross-sectional view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • a semiconductor device 100 shown in FIG. 1A includes a first semiconductor chip 1, a second semiconductor chip 3 mounted avoiding the sensor unit 2 on the first semiconductor chip 1, the first semiconductor chip 1, and the first semiconductor chip 1 Connecting members 4 a and 4 b for electrically connecting the two semiconductor chips 3, and a resin 5 filled in a gap between the first semiconductor chip 1 and the second semiconductor chip 3.
  • the first semiconductor chip 1 is a semiconductor chip formed by forming a circuit on a semiconductor substrate made of silicon or the like, and has a sensor electrode 2 and a first electrode 6 connected to the second semiconductor chip 3 on the main surface. And a second electrode 7.
  • the sensor unit 2 is, for example, a photoelectric conversion region in which photoelectric conversion circuits are arranged in a matrix, and receives incident light and converts it into an electrical signal.
  • a wiring 8 for sending an output signal from the sensor unit 2 is connected to the first electrode 6.
  • the first electrode 6 is disposed on the sensor unit 2 side, and the second electrode 7 is disposed on the external electrode terminal 9 side while avoiding the route of the wiring 8 from the sensor unit 2.
  • the second electrode 7 and the external electrode terminal 9 are connected by the wiring 10 of the first semiconductor chip 1.
  • the second semiconductor chip 3 is a semiconductor chip in which a circuit is formed on a semiconductor substrate made of silicon or the like, and has a circuit that performs electrical exchange with the first semiconductor chip 1 on the main surface.
  • a driving circuit for driving the sensor unit 2 of the first semiconductor chip 1 and an analog front end (AFE: Analog Front End) circuit for converting an analog image electrical signal from the first semiconductor chip 1 into a digital signal. May be included.
  • the second semiconductor chip 3 is arranged avoiding the sensor unit 2. This is because, for example, when the sensor unit 2 is a photoelectric conversion region, the light is not disturbed. When the sensor unit 2 is a piezoelectric conversion region, the sound wave is not disturbed. is there.
  • a third electrode 11 and a fourth electrode 12 are disposed on the main surface of the second semiconductor chip 3, and the third electrode 11 is disposed on the sensor unit 2 side of the first semiconductor chip 1 and the fourth electrode 12. Is arranged on the external electrode terminal 9 side. At this time, the third electrode 11 is electrically connected to the first electrode 6 via the connection member 4a, and the fourth electrode 12 is electrically connected to the second electrode 7 via the connection member 4b.
  • connection members 4a and 4b are conductive members, for example, metal bumps.
  • the resin 5 is filled in the gap between the main surface of the first semiconductor chip 1 and the second semiconductor chip 3 to reinforce the joint, and is formed so as to surround the connection members 4a and 4b.
  • the resin 5 is, for example, an underfill material that is an adhesive strength enhancer, and the material can be used from a liquid epoxy resin, a resin sheet, an anisotropic conductive film (ACF), or the like.
  • the amount of protrusion of the resin 5 is biased between the sensor portion side of the second semiconductor chip 3 and its facing side, and is smaller on the sensor portion 2 side of the second semiconductor chip 3 than on the facing side of the sensor portion 2. It is formed.
  • the protruding amount of the resin 5 refers to the size of the protruding region of the resin 5 at a portion protruding from the second semiconductor chip 3 in FIG. 1B, for example. That is, the amount of protrusion of the resin 5 refers to the size of the region of the resin 5 that extends from the end face of the second semiconductor chip 3 to the outside of the second semiconductor chip 3 in plan view.
  • the semiconductor device 100 provides a bias in the amount of protrusion of the resin 5 filled in the gap between the first semiconductor chip 1 and the second semiconductor chip 3, and the sensor of the second semiconductor chip 3.
  • the protrusion from the side opposite to the part 2 is increased, and the protrusion from the sensor part 2 side is suppressed.
  • the parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6 is reduced, and the output signal from the sensor unit 2 is prevented from being deteriorated, and the power consumption is reduced and the signal transmission speed is improved. it can.
  • the sensor unit 2 and the second semiconductor chip 3 can be arranged close to each other, and the first The area of the semiconductor chip can be reduced, yield per chip can be improved, signal degradation can be suppressed by shortening the length of the wiring 8, power consumption can be reduced, and signal transmission speed can be improved.
  • the amount of protrusion of the resin 5 may be controlled by, for example, electrodes or connection members 4a and 4b arranged in the gap between the first semiconductor chip 1 and the second semiconductor chip 3.
  • FIG. 1B is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment. Only the outer shape of the second semiconductor chip 3 is shown by a frame, and the connection member 4a, the resin 5 and the like arranged thereunder are visible.
  • the semiconductor device 100 shown in FIG. 1B is arranged such that the density of the first electrode 6 and the connection member 4a on the sensor unit 2 side is higher than the density of the second electrode 7 and the connection member 4b that do not face the sensor unit 2.
  • the density means the arrangement density. That is, the distance between the electrodes 6 and 7 in the vertical direction of the paper in FIG. 1B, and the smaller the distance, the higher the density.
  • the diameters of the first electrode 6 and the connection member 4a may be made larger than the second electrode and the connection member 4b, and the number of rows may be reduced. May be more.
  • the pitch may be narrowed.
  • the fluidity of the resin 5 can be controlled by adjusting the diameter, the number of rows, and the pitch. That is, when the diameter is increased or the number of rows is increased, the flow resistance of the resin 5 is increased, and the protrusion can be suppressed.
  • the amount of protrusion of the resin from the sensor unit 2 side can be made relatively smaller than the amount of protrusion from the side opposite to the sensor unit 2.
  • the parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6 is reduced, preventing deterioration of the output signal from the sensor unit 2, reducing power consumption, and improving the signal transmission speed. it can.
  • the resin 5 flows on the opposite side of the sensor part 2 with less restriction of resin protrusion.
  • the amount of protrusion on the sensor unit 2 side is suppressed. That is, the influence of the parasitic capacitance on the wiring 8 due to the resin 5 is minimized.
  • FIG. 2 is a block diagram schematically illustrating an example of an internal circuit and an example of the operation of the first semiconductor chip 1 and the second semiconductor chip 3 in the semiconductor device 100.
  • the sensor unit 2 of the first semiconductor chip 1 includes a plurality of photoelectric conversion circuits 13 arranged in a matrix, a vertical transfer unit 14 provided corresponding to each column of the photoelectric conversion circuits 13, and a horizontal transfer unit. 15 are arranged.
  • Each photoelectric conversion unit photoelectrically converts incident light to generate a signal charge.
  • the vertical transfer unit 14 reads the signal charge generated by each photoelectric conversion circuit 13 and transfers it to the horizontal transfer unit 15.
  • the horizontal transfer unit 15 transfers the transferred signal charge to the output circuit unit 16 in the same first semiconductor chip 1.
  • the output circuit unit 16 converts the transferred signal charge into an analog image electrical signal and outputs it to the second semiconductor chip 3. At this time, the analog image electrical signal is input to the second semiconductor chip 3 via the wiring 8 of the first semiconductor chip 1.
  • the second semiconductor chip 3 includes a drive circuit 17, an AFE circuit 18, and a timing generator (TG: Timing Generator) 19.
  • the drive circuit 17 generates a drive pulse based on the timing signal generated by the TG 19 and outputs it to the first semiconductor chip 1.
  • the drive pulse includes a drive pulse for driving each of the vertical transfer unit 14, the horizontal transfer unit 15, and the output circuit unit 16.
  • the AFE circuit 18 converts the analog image electrical signal output from the output circuit unit 16 into a digital signal (ADC: Analog Digital Converter) based on the timing signal generated by the TG 19.
  • ADC Analog Digital Converter
  • ADC Automatic Gain Control
  • the electrical image signal output from the first semiconductor chip 1 to the second semiconductor chip 3 is sent from the first electrode 6 to the third electrode 11 of the second semiconductor chip 3.
  • the digital signal output from the second semiconductor chip 3 is sent from the fourth electrode 12 of the second semiconductor chip 3 to the second electrode 7 and then via the second electrode 7 and the wiring 10. To the externally connected external electrode terminal 9.
  • the first semiconductor chip 1 is a CCD image sensor
  • a CMOS image sensor or an image sensor using another mechanism may be used.
  • Use of a CMOS image sensor is effective in suppressing power consumption.
  • any device that captures a subject image and generates image data may be used.
  • the circuit mounted on the second semiconductor chip 3 is not limited to the drive circuit 17, the AFE circuit 18, and the TG 19 described above, and may be one that does not include them or that has other functions. Also good.
  • any physical configuration may be used as long as it receives an electrical image signal and outputs a digital signal.
  • ADC is essential for the function of the AFE circuit 18, but other functions can be selectively mounted.
  • FIG. 3 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the gap portion 20 where the second electrode 7 and the connection member 4 b are not disposed is larger than the pitch of the first electrode 6 and the connection member 4 a bonded thereto on the opposite side of the sensor unit 2. Is formed.
  • the fluidity of the resin 5a can be selectively controlled. That is, by forming the gap portion 20 corresponding to the portion where the external electrode terminal 9a is not disposed, the resin 5a flows toward the gap portion 20, and therefore, the resin 5a can be retreated to an area where the resin 5a does not have an influence. it can. Thereby, the protrusion of the resin 5a to the sensor unit 2 side can be suppressed. This is also effective when the number of the first electrodes 6 provided on the sensor unit 2 side cannot be increased, or when the amount of protrusion of the resin 5a increases due to variations in coating weight and bonding between chips.
  • FIG. 4 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the resin 5b does not protrude from the side on the sensor unit 2 side.
  • the circuit surface of the end portion of the second semiconductor chip 3 is also protected by protruding the resin 5b from the chip end, but a fragile interlayer insulating film is used.
  • a fragile interlayer insulating film is used.
  • Such a configuration may be used when it is not required or when strong reliability is not required.
  • the distance between the sensor unit 2 and the second semiconductor chip 3 can be further reduced as compared with the configurations of the first embodiment and other modified examples, and the area of the first semiconductor chip 1 can be further reduced. It can be expected that yield per chip is improved, signal deterioration is suppressed by shortening the length of the wiring 8, power consumption is reduced, and signal transmission speed is improved.
  • FIG. 5 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the second electrode 7 a of the second semiconductor chip 3 a is formed in the vertical direction of the side facing the sensor unit 2.
  • the external electrode terminal 9b connected to the second electrode 7a may be formed in the vertical direction of the side facing the sensor unit 2 on the main surface of the first semiconductor chip 1a.
  • FIG. 6 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the external electrode terminal 9c is provided on the opposite side of the photoelectric conversion region, a region for the external electrode terminal 9c is specially provided.
  • the area of the semiconductor chip 1b increases.
  • the semiconductor device 140 shown in FIG. 6 has a configuration in which the sensor unit 2a is smaller than the second semiconductor chip 3b, and the external electrode terminal 9c is formed on the same side as the sensor unit 2a when viewed from the second semiconductor chip 3b. ing. With such a configuration, the area of the first semiconductor chip 1b can be reduced.
  • the region closer to the sensor portion 2a than the second electrode 7b and the connection member 4b in the region close to the external electrode terminal 9c Since the first electrode 6a and the connecting member 4a are formed with high density, the protrusion of the resin 5 on the wiring 8a connected to the sensor portion 2a is suppressed.
  • FIG. 7 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the dummy connection portion 21 is disposed in addition to the first electrode 6 b connected to the wiring 8 b from the sensor portion 2.
  • the dummy connection portion 21 may be formed by a third electrode formed on the main surface of the first semiconductor chip 1 and a connection member (not shown) joined to the third electrode.
  • FIG. 8A is a cross-sectional view schematically showing a configuration of a semiconductor device according to this modification.
  • FIG. 8A is a cross-sectional view schematically showing a configuration of a semiconductor device according to this modification.
  • a semiconductor device 160 shown in FIG. 8A includes a first semiconductor chip 1c, an extended portion 22 extended outward from the side end surface of the first semiconductor chip 1c, and an extended portion from the main surface of the first semiconductor chip 1c. 22 and a rewiring layer 23 formed over 22. Furthermore, the second semiconductor chip 3 placed across the first semiconductor chip 1c and the extended portion 22, the connection member 4a for electrically connecting the first semiconductor chip 1c and the second semiconductor chip 3, The resin 5 filled in the gap between the first semiconductor chip 1c and the second semiconductor chip 3 is included.
  • the first semiconductor chip 1c is a semiconductor chip in which a circuit is formed on a semiconductor substrate such as silicon, and includes a first electrode 6c connected to the sensor unit 2 on the main surface.
  • the sensor unit 2 is, for example, a photoelectric conversion region in which photoelectric conversion circuits are arranged in a matrix, and receives incident light and converts it into an electrical signal.
  • the first electrode 6c is disposed on the sensor unit 2 side.
  • the extended portion 22 is formed by extending outward from the side end surface of the first semiconductor chip 1c, and a material such as an epoxy resin that is easy to mold and process is suitable for the material.
  • a rewiring layer 23 including a rewiring 24 and a protective film 25 covering the rewiring 24 is formed from the main surface of the first semiconductor chip 1 c to the upper surface of the extended portion 22. Since the rewiring 24 is generally formed by electroplating using photolithography, the wiring thickness can be about 3 to 5 ⁇ m and the width can be arbitrarily formed. It is characterized by a large size and a small electrical resistance compared to the wiring inside the semiconductor chip.
  • PI polyimide
  • PBO polybenzoxazole
  • a fifth electrode 26 disposed in the region of the first semiconductor chip 1 c in the mounting region of the second semiconductor chip 3 and connected to the first electrode 6 c through the rewiring 24.
  • the sixth electrode 27 disposed in the region of the extended portion 22 is formed.
  • the fifth electrode 26 is connected to the third electrode 11 of the second semiconductor chip 3 via the connection member 4a
  • the sixth electrode 27 is connected to the fourth electrode 12 of the second semiconductor chip via the connection member 4b.
  • an external electrode terminal 9 d connected to the sixth electrode 27 by the rewiring 24 is arranged on the outer periphery from the mounting region of the second semiconductor chip 3.
  • the external electrode terminal 9d may be formed of copper or nickel, or may be a laminated structure of copper / solder or nickel / gold.
  • the composition of the solder includes, for example, tin-silver, tin-copper, tin-bismuth, and tin-indium alloys having excellent mechanical properties.
  • FIG. 8B is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
  • the rewiring layer 23 is formed avoiding the sensor portion 2 of the first semiconductor chip 1c, and the sensor portion 2 is exposed from the rewiring layer 23.
  • the external electrode terminal 9d may be arranged not only in the area of the extension part 22 but also in the area of the first semiconductor chip 1c as long as it is outside the area where the second semiconductor chip 3 is mounted.
  • the second semiconductor chip 3 is a semiconductor chip in which a circuit is formed on a semiconductor substrate such as silicon, and has a circuit that performs electrical exchange with the first semiconductor chip 1c on the main surface.
  • the second semiconductor chip 3 is arranged from the peripheral part of the first semiconductor chip 1c to the extension part 22 avoiding the sensor part 2.
  • the resin 5 is filled in the gap between the main surface of the second semiconductor chip 3 and the first semiconductor chip 1c and the main surface of the extended portion 22 to reinforce the joint portion.
  • the resin 5 is disposed on the rewiring layer 23 so as to surround the connection members 4a and 4b.
  • the amount of protrusion of the resin 5 is biased between the sensor portion side of the second semiconductor chip 3 and its facing side, and is smaller on the sensor portion 2 side of the second semiconductor chip 3 than on the facing side of the sensor portion 2. It is formed.
  • This bias may be formed by differentiating the densities of the fifth electrode 26 and the connection member 4a, and the sixth electrode 27 and the connection member 4b.
  • the protrusion of the resin 5 on the sensor unit 2 side can be suppressed as in the first embodiment and the first to fifth modifications.
  • the parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6c is reduced, so that the output signal from the sensor unit 2 can be prevented from being deteriorated, and the power consumption can be reduced and the signal transmission speed can be improved.
  • the circuits of the first semiconductor chip 1c and the second semiconductor chip 3 are accordingly provided. Design becomes easy, and deterioration of the chip design period and design cost can be prevented.
  • a semiconductor substrate made of silicon or the like is provided in a region where the resin 5 protrudes little, and an extended portion 22 made of resin or the like is provided in a region where the resin 5 protrudes greatly.
  • the area of the expensive silicon substrate can be minimized, and the yield per chip can be improved and the manufacturing cost can be reduced.
  • the effect of the present disclosure becomes more prominent when the first semiconductor chip 1c has a higher pixel count.
  • the circuit size of the second semiconductor chip 3 increases and the chip size increases with the increase in the number of pixels, the mounting area of the second semiconductor chip 3 is secured by adjusting the area of the extension portion 22. Therefore, the size of the first semiconductor chip 1c can be kept small.
  • 9A to 9E are cross-sectional views schematically showing the manufacturing method of the present embodiment.
  • a circuit is formed in the first semiconductor chip 1 by a diffusion process.
  • the sensor unit 2 the wirings 8 and 10, the first electrode 6, the second electrode 7, the external electrode terminal 9, and the like are formed on the main surface of the first semiconductor chip 1.
  • connection member 4 a is bonded to the first electrode 6 of the first semiconductor chip 1, and the connection member 4 b is bonded to the second electrode 7.
  • connection members may be formed for the third electrode 11 and the fourth electrode 12 for the second semiconductor chip 3 (not shown).
  • a resin 5 is applied to the mounting region of the second semiconductor chip 3 on the main surface of the first semiconductor chip 1.
  • the resin 5 is applied to the place where the first electrode 6 and the connection member 4a are disposed.
  • the second semiconductor chip 3 is mounted while spreading the previously applied resin 5 wet.
  • the first electrode 6 and the third electrode 11 are joined to each other via the connection member 4a
  • the second electrode 7 and the fourth electrode 12 are joined to each other via the connection member 4b.
  • FIG. 9E is a completed drawing.
  • the resin 5 is stably injected even when the pitch of the joint portion between the first semiconductor chip 1 and the second semiconductor chip 3 becomes a narrow pitch (for example, 40 ⁇ m pitch or less). be able to.
  • the viscosity of the resin is 10 to 50 Pa ⁇ s at room temperature in order to increase the resin fluid.
  • the viscosity at room temperature is mainly 30 to 160 Pa ⁇ s so that it does not spread when wet. Therefore, in the method of applying the resin 5 before the flip chip bonding, the viscosity of the resin 5 is high after the flip chip bonding, so that the resin 5 does not spread more than necessary. The amount of protrusion can be suppressed.
  • the application pattern of the resin 5 is preferably symmetrical with respect to the center of the mounting region 28 of the second semiconductor chip 3 because it is easy to manufacture. Moreover, it is desirable that the resin 5 is formed continuously. By being formed continuously, it is possible to avoid defects in entrainment voids. In addition, the pattern of application
  • the first embodiment and its modifications have been described as examples of the technology disclosed in the present invention.
  • the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed.
  • the external electrode terminal 9 is formed on the main surface of the first semiconductor chip 1, but it is not always necessary to form the external electrode terminal 9 on the main surface. You may pull it out.
  • the second semiconductor chip 3 does not necessarily have the circuit surface opposed to the first semiconductor chip 1.
  • the circuit surface is directed upward, and the second semiconductor chip 3 is electrically pulled out to the back surface with a through electrode or the like.
  • One semiconductor chip may be electrically connected.
  • the signal output from the sensor unit 2 and flowing through the wiring 8 is not limited to an analog signal, and may be a digital signal. In other words, it is not limited to analog signal wiring, but may be digital signal wiring. However, the analog signal has a greater influence when the absolute value of the waveform is lost due to the parasitic capacitance of the resin 5, and enjoys the effect of the present disclosure more.
  • the circuit area formed outside the second semiconductor chip mounting area in the first semiconductor chip is merely an example.
  • the present disclosure is most suitable for a semiconductor device in which a second semiconductor chip electrically connected to a first semiconductor chip is mounted on a first semiconductor chip having a sensor unit. Specifically, the present disclosure is applicable to an imaging device in which an ADC chip is mounted on an optical chip that includes a photoelectric conversion unit.

Abstract

　Provided is a semiconductor device in which, in a configuration for mounting a second semiconductor chip on a circuit surface of a first semiconductor chip, there is reduced waveform degradation of an output signal from a sensor portion of the first semiconductor chip resulting from parasitic capacitance in a resin formed in the gap between the two chips, and signal quality can be improved. This semiconductor device is provided, on a first surface, with: the first semiconductor chip, which has a first electrode and a sensor portion; the second semiconductor chip, which is mounted on the first surface of the first semiconductor chip so as to avoid the sensor portion; and a connecting member bonded to the first electrode, the connecting member electrically connecting the first semiconductor chip to the second semiconductor chip. The semiconductor apparatus is characterized in being provided with a resin disposed surrounding the connecting member in the gap between the first semiconductor chip and the second semiconductor chip, the amount by which the resin protrudes being less on the sensor portion side of the second semiconductor chip than on the surface facing the sensor portion.

Description

半導体装置Semiconductor device
　本開示は、センサーチップに信号処理チップを積層した半導体装置に関する。 The present disclosure relates to a semiconductor device in which a signal processing chip is stacked on a sensor chip.
　特許文献１に開示された半導体モジュールは、光電変換領域が形成された第１の半導体チップと、第１の半導体チップ上における光電変換領域が形成されていない領域に設けられ、第１の半導体チップと電気的に接続された第２の半導体チップとを備える。さらに、第１の半導体チップ、第２の半導体チップを収容するとともに、少なくとも光電変換領域と対向する領域が透光性材料で形成されたパッケージと、第２の半導体チップとパッケージとを熱的に連結する熱伝導部材とを備える。 The semiconductor module disclosed in Patent Document 1 is provided in a first semiconductor chip in which a photoelectric conversion region is formed and a region in which no photoelectric conversion region is formed on the first semiconductor chip. And a second semiconductor chip electrically connected. Furthermore, the first semiconductor chip and the second semiconductor chip are accommodated, and at least a region facing the photoelectric conversion region is formed of a light-transmitting material, and the second semiconductor chip and the package are thermally bonded. And a heat conducting member to be connected.
特開２０１２－１２４３０５号公報JP 2012-124305 A
　本開示は、第１の半導体チップの回路面に第２の半導体チップを搭載する構成において、第１の半導体チップのセンサー部からの出力信号に対し２つのチップの隙間に形成した樹脂の寄生容量が加わることによる波形の劣化を軽減し、信号品質の向上を可能とする半導体装置を提供する。 In the present disclosure, in a configuration in which a second semiconductor chip is mounted on a circuit surface of a first semiconductor chip, a parasitic capacitance of a resin formed in a gap between two chips with respect to an output signal from a sensor unit of the first semiconductor chip The present invention provides a semiconductor device that can reduce the deterioration of the waveform due to the addition of, and improve the signal quality.
　本開示における半導体装置は、第１の面に、第１の電極と第１の部分領域を有する第１の半導体チップと、第１の半導体チップの第１の面に、第１の部分領域を避けて搭載された第２の半導体チップとを備える。さらに第１の電極と接合され、第１の半導体チップと第２の半導体チップを電気的に接続する接続部材と、第１の半導体チップと第２の半導体チップの隙間に、接続部材を囲むように配置された樹脂とを備える。この樹脂のはみ出し量は、第２の半導体チップの第１の部分領域側において、第１の部分領域の対面側よりも小さく形成されることを特徴とする。 The semiconductor device in the present disclosure includes a first semiconductor chip having a first electrode and a first partial region on a first surface, and a first partial region on a first surface of the first semiconductor chip. And a second semiconductor chip mounted so as to be avoided. Further, the connection member is joined to the first electrode and electrically connects the first semiconductor chip and the second semiconductor chip, and the connection member is surrounded by the gap between the first semiconductor chip and the second semiconductor chip. And a resin disposed on the surface. The protruding amount of the resin is characterized in that it is formed smaller on the first partial region side of the second semiconductor chip than on the facing side of the first partial region.
　本開示における半導体装置は、第２の半導体チップの第１の部分領域側の樹脂のはみ出しを最小限にすることで、第１の半導体チップの第１の部分領域からの出力配線に対する、樹脂による寄生容量を最小限にし、出力信号の品質の向上を可能とする。 The semiconductor device according to the present disclosure is based on the resin for the output wiring from the first partial region of the first semiconductor chip by minimizing the protrusion of the resin on the first partial region side of the second semiconductor chip. Minimizing parasitic capacitance and improving the quality of the output signal.
第１の実施形態に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の平面図The top view of the semiconductor device concerning a 1st embodiment 第１の実施形態に係る半導体装置の回路動作を示したブロック図1 is a block diagram showing circuit operation of a semiconductor device according to a first embodiment. 第１の実施形態に係る半導体装置の変形例１を示す平面図The top view which shows the modification 1 of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の変形例２を示す平面図The top view which shows the modification 2 of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の変形例３を示す平面図The top view which shows the modification 3 of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の変形例４を示す平面図The top view which shows the modification 4 of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の変形例５を示す平面図The top view which shows the modification 5 of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の変形例６を示す断面図Sectional drawing which shows the modification 6 of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の変形例６を示す平面図The top view which shows the modification 6 of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment 第１の実施形態に係る半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment （ａ）～（ｃ）第１の実施形態に係る半導体装置の製造方法を示す平面図FIGS. 4A to 4C are plan views showing a method for manufacturing a semiconductor device according to the first embodiment. FIGS.
　以下、適宜図面を参照しながら、実施の形態を詳細に説明する。但し、必要以上に詳細な説明は省略する場合がある。例えば、既によく知られた事項の詳細説明や実質的に同一の構成に対する重複説明を省略する場合がある。これは、以下の説明が不必要に冗長になるのを避け、当業者の理解を容易にするためである。 Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.
　なお、添付図面および以下の説明は当業者が本開示を十分に理解するためのものであって、これらによって請求の範囲に記載の主題を限定することを意図するものではない。 It should be noted that the accompanying drawings and the following description are intended to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims.
　（第１の実施形態）
　以下、図１Ａ、図１Ｂおよび図２を用いて、第１の実施形態を説明する。 (First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1A, 1B, and 2. FIG.
　図１Ａは、本実施形態にかかる半導体装置の構成を模式的に示す断面図である。 FIG. 1A is a cross-sectional view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図１Ａに示す半導体装置１００は、第１の半導体チップ１と、第１の半導体チップ１上のセンサー部２を避けて搭載された第２の半導体チップ３と、第１の半導体チップ１と第２の半導体チップ３を電気的に接続する接続部材４ａ、４ｂと、第１の半導体チップ１と第２の半導体チップ３の隙間に充填された樹脂５とを有する。 A semiconductor device 100 shown in FIG. 1A includes a first semiconductor chip 1, a second semiconductor chip 3 mounted avoiding the sensor unit 2 on the first semiconductor chip 1, the first semiconductor chip 1, and the first semiconductor chip 1 Connecting members 4 a and 4 b for electrically connecting the two semiconductor chips 3, and a resin 5 filled in a gap between the first semiconductor chip 1 and the second semiconductor chip 3.
　第１の半導体チップ１は、シリコン等からなる半導体基板に回路が形成されて成る半導体チップであり、主面に、センサー部２と、第２の半導体チップ３と接続される第１の電極６と、第２の電極７を備える。センサー部２は、例えば光電変換回路が行列状に配置された光電変換領域であり、入射光を受光して電気信号に変換する。センサー部２からの出力信号を送る配線８は第１の電極６に接続される。第１の電極６はセンサー部２側に配置され、第２の電極７はセンサー部２からの配線８の経路を避け、外部電極端子９側に配置されている。第２の電極７と外部電極端子９は、第１の半導体チップ１の配線１０で接続されている。 The first semiconductor chip 1 is a semiconductor chip formed by forming a circuit on a semiconductor substrate made of silicon or the like, and has a sensor electrode 2 and a first electrode 6 connected to the second semiconductor chip 3 on the main surface. And a second electrode 7. The sensor unit 2 is, for example, a photoelectric conversion region in which photoelectric conversion circuits are arranged in a matrix, and receives incident light and converts it into an electrical signal. A wiring 8 for sending an output signal from the sensor unit 2 is connected to the first electrode 6. The first electrode 6 is disposed on the sensor unit 2 side, and the second electrode 7 is disposed on the external electrode terminal 9 side while avoiding the route of the wiring 8 from the sensor unit 2. The second electrode 7 and the external electrode terminal 9 are connected by the wiring 10 of the first semiconductor chip 1.
　第２の半導体チップ３は、シリコン等からなる半導体基板に回路が形成されて成る半導体チップであり、主面に第１の半導体チップ１と電気的なやりとりを行う回路を有する。例えば、第１の半導体チップ１のセンサー部２を駆動する駆動回路や、第１の半導体チップ１からのアナログの画像電気信号をデジタル信号に変換するアナログフロントエンド（ＡＦＥ：Ａｎａｌｏｇ　Ｆｒｏｎｔ　Ｅｎｄ）回路を含んでもよい。 The second semiconductor chip 3 is a semiconductor chip in which a circuit is formed on a semiconductor substrate made of silicon or the like, and has a circuit that performs electrical exchange with the first semiconductor chip 1 on the main surface. For example, a driving circuit for driving the sensor unit 2 of the first semiconductor chip 1 and an analog front end (AFE: Analog Front End) circuit for converting an analog image electrical signal from the first semiconductor chip 1 into a digital signal. May be included.
　第２の半導体チップ３は、センサー部２を避けて配置される。これは、例えばセンサー部２が光電変換領域であった場合は、集光を妨げないようにするため、センサー部２が圧電変換領域であった場合は、音波等を妨げないようにするためである。第２の半導体チップ３の主面には第３の電極１１と第４の電極１２が配置され、第３の電極１１が第１の半導体チップ１のセンサー部２側に、第４の電極１２が外部電極端子９側に配置されている。このとき第３の電極１１は第１の電極６と接続部材４ａを介して、第４の電極１２は第２の電極７と接続部材４ｂを介して、それぞれ電気的に接続される。 The second semiconductor chip 3 is arranged avoiding the sensor unit 2. This is because, for example, when the sensor unit 2 is a photoelectric conversion region, the light is not disturbed. When the sensor unit 2 is a piezoelectric conversion region, the sound wave is not disturbed. is there. A third electrode 11 and a fourth electrode 12 are disposed on the main surface of the second semiconductor chip 3, and the third electrode 11 is disposed on the sensor unit 2 side of the first semiconductor chip 1 and the fourth electrode 12. Is arranged on the external electrode terminal 9 side. At this time, the third electrode 11 is electrically connected to the first electrode 6 via the connection member 4a, and the fourth electrode 12 is electrically connected to the second electrode 7 via the connection member 4b.
　接続部材４ａ、４ｂは導電性の部材であり、例えば金属バンプである。 The connection members 4a and 4b are conductive members, for example, metal bumps.
　樹脂５は、第１の半導体チップ１の主面と第２の半導体チップ３の隙間に、接合部の補強のために充填されており、接続部材４ａ、４ｂを囲んで形成されている。樹脂５は、例えば接着力強化剤であるアンダーフィル材であり、その材料は、液状エポキシ樹脂、樹脂シート、異方性導電フィルム（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）等から採用できる。樹脂５のはみ出し量は、第２の半導体チップ３のセンサー部側とその対面側とで偏りを有し、第２の半導体チップ３のセンサー部２側において、センサー部２の対面側よりも小さく形成される。ここで、樹脂５のはみ出し量とは、例えば図１Ｂにおいて第２の半導体チップ３よりはみ出す部分の樹脂５のはみ出し領域の大きさのことをいう。すなわち、樹脂５のはみ出し量とは、平面視における第２の半導体チップ３の端面から第２の半導体チップ３の外方へ延伸した樹脂５の領域の大きさのことをいう。 The resin 5 is filled in the gap between the main surface of the first semiconductor chip 1 and the second semiconductor chip 3 to reinforce the joint, and is formed so as to surround the connection members 4a and 4b. The resin 5 is, for example, an underfill material that is an adhesive strength enhancer, and the material can be used from a liquid epoxy resin, a resin sheet, an anisotropic conductive film (ACF), or the like. The amount of protrusion of the resin 5 is biased between the sensor portion side of the second semiconductor chip 3 and its facing side, and is smaller on the sensor portion 2 side of the second semiconductor chip 3 than on the facing side of the sensor portion 2. It is formed. Here, the protruding amount of the resin 5 refers to the size of the protruding region of the resin 5 at a portion protruding from the second semiconductor chip 3 in FIG. 1B, for example. That is, the amount of protrusion of the resin 5 refers to the size of the region of the resin 5 that extends from the end face of the second semiconductor chip 3 to the outside of the second semiconductor chip 3 in plan view.
　以上、本実施の形態において、半導体装置１００は、第１の半導体チップ１と第２の半導体チップ３の隙間に充填される樹脂５のはみ出し量に偏りを設け、第２の半導体チップ３のセンサー部２と反対側からのはみ出しを増やし、センサー部２側からのはみ出しを抑える。 As described above, in the present embodiment, the semiconductor device 100 provides a bias in the amount of protrusion of the resin 5 filled in the gap between the first semiconductor chip 1 and the second semiconductor chip 3, and the sensor of the second semiconductor chip 3. The protrusion from the side opposite to the part 2 is increased, and the protrusion from the sensor part 2 side is suppressed.
　これにより、センサー部２と第１の電極６とを結ぶ配線８への寄生容量は小さくなり、センサー部２からの出力信号の劣化を防ぐとともに、消費電力の削減、信号伝送速度の向上を実現できる。 As a result, the parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6 is reduced, and the output signal from the sensor unit 2 is prevented from being deteriorated, and the power consumption is reduced and the signal transmission speed is improved. it can.
　また、本実施の形態においては、センサー部２側の樹脂５のはみ出しを抑制出来るので、センサー部２と第２の半導体チップ３との距離を近づけて配置することが可能であり、第１の半導体チップ面積を縮小でき、チップ当たりの歩留まり向上、配線８の長さ短縮による信号劣化の抑制、消費電力の削減、信号伝送速度の向上が期待できる。 Further, in the present embodiment, since the protrusion of the resin 5 on the sensor unit 2 side can be suppressed, the sensor unit 2 and the second semiconductor chip 3 can be arranged close to each other, and the first The area of the semiconductor chip can be reduced, yield per chip can be improved, signal degradation can be suppressed by shortening the length of the wiring 8, power consumption can be reduced, and signal transmission speed can be improved.
　本実施の形態において、樹脂５のはみ出し量コントロールは、例えば第１の半導体チップ１と第２の半導体チップ３の隙間に配置される電極や接続部材４ａ、４ｂなどにより実現されてもよい。 In the present embodiment, the amount of protrusion of the resin 5 may be controlled by, for example, electrodes or connection members 4a and 4b arranged in the gap between the first semiconductor chip 1 and the second semiconductor chip 3.
　図１Ｂは、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。第２の半導体チップ３については外形のみを枠で示し、その下に配置された接続部材４ａや樹脂５などが見える図にしている。 FIG. 1B is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment. Only the outer shape of the second semiconductor chip 3 is shown by a frame, and the connection member 4a, the resin 5 and the like arranged thereunder are visible.
　図１Ｂに示す半導体装置１００は、センサー部２側の第１の電極６および接続部材４ａの密度を、センサー部２に対向しない第２の電極７および接続部材４ｂの密度より高くなるように配置する。ここでいう密度とは配置密度のことをいう。すなわち、電極６または電極７の、図１Ｂにおいて紙面の上下方向における間隔のことであり、当該間隔が狭いほど密度が大きい、ということである。 The semiconductor device 100 shown in FIG. 1B is arranged such that the density of the first electrode 6 and the connection member 4a on the sensor unit 2 side is higher than the density of the second electrode 7 and the connection member 4b that do not face the sensor unit 2. To do. The density here means the arrangement density. That is, the distance between the electrodes 6 and 7 in the vertical direction of the paper in FIG. 1B, and the smaller the distance, the higher the density.
　センサー部２側の密度を相対的に高くするためには、第２の電極および接続部材４ｂに比して、第１の電極６および接続部材４ａの径を大きくしてもよく、列数を多くしてもよい。または、ピッチを狭くしてもよい。径や列数、ピッチを調整することにより、樹脂５の流動性をコントロールすることが出来る。すなわち、径を大きくしたり、列数を多くすると、樹脂５の流動抵抗が上がり、はみ出しを抑えることが可能となる。 In order to relatively increase the density on the sensor unit 2 side, the diameters of the first electrode 6 and the connection member 4a may be made larger than the second electrode and the connection member 4b, and the number of rows may be reduced. May be more. Alternatively, the pitch may be narrowed. The fluidity of the resin 5 can be controlled by adjusting the diameter, the number of rows, and the pitch. That is, when the diameter is increased or the number of rows is increased, the flow resistance of the resin 5 is increased, and the protrusion can be suppressed.
　これにより、簡易な回路設計で、センサー部２側からの樹脂のはみ出し量を、センサー部２と反対側からのはみ出し量より相対的に少なくすることができる。その結果、センサー部２と第１の電極６とを結ぶ配線８への寄生容量は小さくなり、センサー部２からの出力信号の劣化を防ぐとともに、消費電力の削減、信号伝送速度の向上を実現できる。 Thereby, with a simple circuit design, the amount of protrusion of the resin from the sensor unit 2 side can be made relatively smaller than the amount of protrusion from the side opposite to the sensor unit 2. As a result, the parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6 is reduced, preventing deterioration of the output signal from the sensor unit 2, reducing power consumption, and improving the signal transmission speed. it can.
　特に、高速大容量伝送などの要請に応え、センサー部２からの出力信号を送る配線８を多数設ける場合は、配線８と接続される第１の電極６のピッチも狭くなるため、より簡易な設計変更で本実施の形態の効果を得ることができる。 In particular, when a large number of wirings 8 for sending output signals from the sensor unit 2 are provided in response to a request for high-speed and large-capacity transmission, the pitch of the first electrodes 6 connected to the wirings 8 is also narrowed. The effect of this embodiment can be obtained by design change.
　さらに、樹脂の塗布量や、第１の半導体チップ１と第２の半導体チップ３の接合高さがばらついた場合でも、樹脂のはみ出し規制の少ないセンサー部２の反対側に樹脂５が流れるため、センサー部２側のはみ出し量が抑制される。すなわち樹脂５による配線８への寄生容量の影響が最小限に抑えられる。 Furthermore, even when the amount of resin applied or the bonding height of the first semiconductor chip 1 and the second semiconductor chip 3 varies, the resin 5 flows on the opposite side of the sensor part 2 with less restriction of resin protrusion. The amount of protrusion on the sensor unit 2 side is suppressed. That is, the influence of the parasitic capacitance on the wiring 8 due to the resin 5 is minimized.
　図２は、半導体装置１００における第１の半導体チップ１と第２の半導体チップ３の内部回路の一例、および動作の一例を模式的に示すブロック図である。 FIG. 2 is a block diagram schematically illustrating an example of an internal circuit and an example of the operation of the first semiconductor chip 1 and the second semiconductor chip 3 in the semiconductor device 100.
　第１の半導体チップ１のセンサー部２には、行列状に配置された複数の光電変換回路１３と、光電変換回路１３の列毎に対応して設けられた垂直転送部１４と、水平転送部１５とが配置される。各光電変換部は、入射光を光電変換して信号電荷を生成する。垂直転送部１４は、各光電変換回路１３で生成された信号電荷を読み出し、水平転送部１５に転送する。水平転送部１５は、転送された信号電荷を同じ第１の半導体チップ１内の出力回路部１６に転送する。出力回路部１６は、転送された信号電荷をアナログの画像電気信号に変換して第２の半導体チップ３に出力する。このとき、アナログの画像電気信号は、第１の半導体チップ１の配線８を経由して第２の半導体チップ３に入力される。 The sensor unit 2 of the first semiconductor chip 1 includes a plurality of photoelectric conversion circuits 13 arranged in a matrix, a vertical transfer unit 14 provided corresponding to each column of the photoelectric conversion circuits 13, and a horizontal transfer unit. 15 are arranged. Each photoelectric conversion unit photoelectrically converts incident light to generate a signal charge. The vertical transfer unit 14 reads the signal charge generated by each photoelectric conversion circuit 13 and transfers it to the horizontal transfer unit 15. The horizontal transfer unit 15 transfers the transferred signal charge to the output circuit unit 16 in the same first semiconductor chip 1. The output circuit unit 16 converts the transferred signal charge into an analog image electrical signal and outputs it to the second semiconductor chip 3. At this time, the analog image electrical signal is input to the second semiconductor chip 3 via the wiring 8 of the first semiconductor chip 1.
　第２の半導体チップ３は、駆動回路１７と、ＡＦＥ回路１８と、タイミングジェネレータ（ＴＧ：Ｔｉｍｉｎｇ　Ｇｅｎｅｒａｔｏｒ）１９とを備える。駆動回路１７は、ＴＧ１９で生成されるタイミング信号に基づいて駆動パルスを生成し、第１の半導体チップ１に出力する。ここで、駆動パルスには、垂直転送部１４、水平転送部１５および出力回路部１６のそれぞれを駆動する駆動パルスが含まれる。第１の半導体チップ１では、これらの駆動パルスに基づいて、上述のような光電変換回路１３で生成された信号電荷の読み出しから、出力回路部１６からの画像電気信号の出力までの一連の動作が行われる。ＡＦＥ回路１８は、ＴＧ１９で生成されるタイミング信号に基づいて、出力回路部１６から出力されたアナログの画像電気信号を、デジタル信号に変換（ＡＤＣ：Ａｎａｌｏｇ　Ｄｉｇｉｔａｌ　Ｃｏｎｖｅｒｔｅｒ）する。ＡＤＣの前処理として、相関二重サンプリング（ＣＤＳ：Ｃｏｒｒｅｌａｔｅｄ　Ｄｏｕｂｌｅ　Ｓａｍｐｌｉｎｇ）、自動利得調整（ＡＧＣ：Ａｕｔｏ　Ｇａｉｎ　Ｃｏｎｔｒｏｌ）を行ってもよい。変換されたデジタル信号は、第２の半導体チップ３の外部に出力される。 The second semiconductor chip 3 includes a drive circuit 17, an AFE circuit 18, and a timing generator (TG: Timing Generator) 19. The drive circuit 17 generates a drive pulse based on the timing signal generated by the TG 19 and outputs it to the first semiconductor chip 1. Here, the drive pulse includes a drive pulse for driving each of the vertical transfer unit 14, the horizontal transfer unit 15, and the output circuit unit 16. In the first semiconductor chip 1, based on these drive pulses, a series of operations from reading the signal charge generated by the photoelectric conversion circuit 13 as described above to outputting the image electrical signal from the output circuit unit 16. Is done. The AFE circuit 18 converts the analog image electrical signal output from the output circuit unit 16 into a digital signal (ADC: Analog Digital Converter) based on the timing signal generated by the TG 19. As pre-processing of the ADC, correlated double sampling (CDS: Correlated Double Sampling) and automatic gain adjustment (AGC: Auto Gain Control) may be performed. The converted digital signal is output to the outside of the second semiconductor chip 3.
　第１の半導体チップ１から第２の半導体チップ３に出力される画像電気信号は、第１の電極６から第２の半導体チップ３の第３の電極１１へ送られる。また、第２の半導体チップ３から出力されるデジタル信号は、第２の半導体チップ３の第４の電極１２から第２の電極７へ送られた後、第２の電極７と配線１０を介して電気的に接続された外部電極端子９に送られる。 The electrical image signal output from the first semiconductor chip 1 to the second semiconductor chip 3 is sent from the first electrode 6 to the third electrode 11 of the second semiconductor chip 3. The digital signal output from the second semiconductor chip 3 is sent from the fourth electrode 12 of the second semiconductor chip 3 to the second electrode 7 and then via the second electrode 7 and the wiring 10. To the externally connected external electrode terminal 9.
　前述の内部回路の一例では、第１の半導体チップ１がＣＣＤイメージセンサの場合を説明したが、ＣＭＯＳイメージセンサや、その他のメカニズムによるイメージセンサであってもよい。ＣＭＯＳイメージセンサを用いれば、消費電力の抑制に有効である。要するに、被写体像を撮像して画像データを生成するものであればよい。また、第２の半導体チップ３に実装する回路は、前述の駆動回路１７、ＡＦＥ回路１８、ＴＧ１９に限らず、それらを含まないものであっても、もしくはその他の機能を備えたものであってもよい。要するに、画像電気信号を受けてデジタル信号を出力するものであれば、物理的にどのように構成してもよい。 In the example of the internal circuit described above, the case where the first semiconductor chip 1 is a CCD image sensor has been described. However, a CMOS image sensor or an image sensor using another mechanism may be used. Use of a CMOS image sensor is effective in suppressing power consumption. In short, any device that captures a subject image and generates image data may be used. Further, the circuit mounted on the second semiconductor chip 3 is not limited to the drive circuit 17, the AFE circuit 18, and the TG 19 described above, and may be one that does not include them or that has other functions. Also good. In short, any physical configuration may be used as long as it receives an electrical image signal and outputs a digital signal.
　また、第２の半導体チップ３の代わりに、もしくは第２の半導体チップ３に加えて、半導体チップ以外の電子部品を搭載してもよい。また、ＡＦＥ回路１８の機能は、ＡＤＣは必須だが、その他の機能は選択的に搭載できる。 Further, instead of the second semiconductor chip 3 or in addition to the second semiconductor chip 3, electronic components other than the semiconductor chip may be mounted. In addition, ADC is essential for the function of the AFE circuit 18, but other functions can be selectively mounted.
　（第１の実施形態の変形例１）
　以下、図３を用いて、第１の実施形態の変形例１を説明する。 (Modification 1 of the first embodiment)
Hereinafter, a first modification of the first embodiment will be described with reference to FIG.
　図３は、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 3 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図３に示す半導体装置１１０は、センサー部２の対面側に第１の電極６およびそれと接合する接続部材４ａのピッチよりも大きな、第２の電極７および接続部材４ｂが配置されない隙間部２０が形成されている。このような隙間部２０を形成することにより、選択的に樹脂５ａの流動性をコントロールすることが出来る。すなわち、外部電極端子９ａが配置されない部分に対応して隙間部２０を形成することにより、樹脂５ａが隙間部２０に向けて流動するため、樹脂５ａのはみ出しの影響のない領域に退避させることができる。これにより、センサー部２側への樹脂５ａのはみ出しを抑制できる。センサー部２側に設ける第１の電極６の数を増やせない場合や、塗布重量やチップ間の接合のばらつきで、樹脂５ａのはみ出し量が増えた場合にも有効である。 In the semiconductor device 110 illustrated in FIG. 3, the gap portion 20 where the second electrode 7 and the connection member 4 b are not disposed is larger than the pitch of the first electrode 6 and the connection member 4 a bonded thereto on the opposite side of the sensor unit 2. Is formed. By forming such a gap portion 20, the fluidity of the resin 5a can be selectively controlled. That is, by forming the gap portion 20 corresponding to the portion where the external electrode terminal 9a is not disposed, the resin 5a flows toward the gap portion 20, and therefore, the resin 5a can be retreated to an area where the resin 5a does not have an influence. it can. Thereby, the protrusion of the resin 5a to the sensor unit 2 side can be suppressed. This is also effective when the number of the first electrodes 6 provided on the sensor unit 2 side cannot be increased, or when the amount of protrusion of the resin 5a increases due to variations in coating weight and bonding between chips.
　（第１の実施形態の変形例２）
　以下、図４を用いて、第１の実施形態の変形例２を説明する。 (Modification 2 of the first embodiment)
Hereinafter, the modification 2 of 1st Embodiment is demonstrated using FIG.
　図４は、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 4 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図４に示す半導体装置１２０は、センサー部２側の辺において、樹脂５ｂのはみ出しがない。第１の実施形態および他の変形例では、樹脂５ｂのチップ端からのはみ出しにより、第２の半導体チップ３の端部の回路面の保護も行っているが、脆弱な層間絶縁膜が使用されていない場合や、強固な信頼性が要求されない場合はこのような構成にしてもよい。これにより、第１の実施形態および他の変形例の構成よりもセンサー部２と第２の半導体チップ３の距離をさらに縮めることが可能となり、第１の半導体チップ１の面積をさらに縮小でき、チップ当たりの歩留まり向上、配線８の長さ短縮による信号劣化の抑制、消費電力の削減、信号伝送速度の向上がより期待できる。 In the semiconductor device 120 shown in FIG. 4, the resin 5b does not protrude from the side on the sensor unit 2 side. In the first embodiment and other modified examples, the circuit surface of the end portion of the second semiconductor chip 3 is also protected by protruding the resin 5b from the chip end, but a fragile interlayer insulating film is used. Such a configuration may be used when it is not required or when strong reliability is not required. Thereby, the distance between the sensor unit 2 and the second semiconductor chip 3 can be further reduced as compared with the configurations of the first embodiment and other modified examples, and the area of the first semiconductor chip 1 can be further reduced. It can be expected that yield per chip is improved, signal deterioration is suppressed by shortening the length of the wiring 8, power consumption is reduced, and signal transmission speed is improved.
　（第１の実施形態の変形例３）
　以下、図５を用いて、第１の実施形態の変形例３を説明する。 (Modification 3 of the first embodiment)
Hereinafter, Modification 3 of the first embodiment will be described with reference to FIG.
　図５は、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 5 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図５に示す半導体装置１３０は、第２の半導体チップ３ａの第２の電極７ａが、センサー部２に対向する辺の垂直方向に形成されている。このような構成にすることで、センサー部２の対面側に第２の電極７ａおよび接続部材４ｂを設ける必要がなく、センサー部２の対面側の樹脂の流動性が高くなり、センサー部２側における樹脂５のはみ出しの極小化の効果が大きくなる。 In the semiconductor device 130 shown in FIG. 5, the second electrode 7 a of the second semiconductor chip 3 a is formed in the vertical direction of the side facing the sensor unit 2. With such a configuration, it is not necessary to provide the second electrode 7a and the connection member 4b on the facing side of the sensor unit 2, and the fluidity of the resin on the facing side of the sensor unit 2 is increased, so that the sensor unit 2 side The effect of minimizing the protrusion of the resin 5 is increased.
　第２の電極７ａと接続される外部電極端子９ｂは、第１の半導体チップ１ａの主面において、センサー部２に対向する辺の垂直方向に形成されてもよい。 The external electrode terminal 9b connected to the second electrode 7a may be formed in the vertical direction of the side facing the sensor unit 2 on the main surface of the first semiconductor chip 1a.
　（第１の実施形態の変形例４）
　以下、図６を用いて、第１の実施形態の変形例４を説明する。 (Modification 4 of the first embodiment)
Hereinafter, the modification 4 of 1st Embodiment is demonstrated using FIG.
　図６は、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 6 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　センサー部２ａの面積が第２の半導体チップ３ｂよりも小さい場合、外部電極端子９ｃを光電変換領域の対辺側に設けると、外部電極端子９ｃのための領域を特別に設けることになり第１の半導体チップ１ｂの面積が増大してしまう。 When the area of the sensor unit 2a is smaller than that of the second semiconductor chip 3b, if the external electrode terminal 9c is provided on the opposite side of the photoelectric conversion region, a region for the external electrode terminal 9c is specially provided. The area of the semiconductor chip 1b increases.
　図６に示す半導体装置１４０は、センサー部２ａが第２の半導体チップ３ｂより小さい構成で、第２の半導体チップ３ｂから見て、外部電極端子９ｃが、センサー部２ａと同じ辺側に形成されている。このような構成にすることで、第１の半導体チップ１ｂの面積を縮小することが出来る。 The semiconductor device 140 shown in FIG. 6 has a configuration in which the sensor unit 2a is smaller than the second semiconductor chip 3b, and the external electrode terminal 9c is formed on the same side as the sensor unit 2a when viewed from the second semiconductor chip 3b. ing. With such a configuration, the area of the first semiconductor chip 1b can be reduced.
　本変形例においては、第２の半導体チップ３ｂの、センサー部２ａ側の辺において、外部電極端子９ｃに近い領域の第２の電極７ｂと接続部材４ｂに比して、センサー部２ａに近い領域の第１の電極６ａおよび接続部材４ａの密度が高く形成されるため、センサー部２ａと接続された配線８ａ上への、樹脂５のはみ出しは抑制される。 In the present modification, on the side of the second semiconductor chip 3b on the sensor portion 2a side, the region closer to the sensor portion 2a than the second electrode 7b and the connection member 4b in the region close to the external electrode terminal 9c. Since the first electrode 6a and the connecting member 4a are formed with high density, the protrusion of the resin 5 on the wiring 8a connected to the sensor portion 2a is suppressed.
　（第１の実施形態の変形例５）
　以下、図７を用いて、第１の実施形態の変形例５を説明する。 (Modification 5 of the first embodiment)
Hereinafter, the modification 5 of 1st Embodiment is demonstrated using FIG.
　図７は、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 7 is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図７に示す半導体装置１５０は、センサー部２からの配線８ｂと接続する第１の電極６ｂ以外に、ダミー接続部２１が配置されている。ダミー接続部２１は、第１の半導体チップ１の主面に形成された第３の電極と、第３の電極と接合する接続部材（図示せず）とにより形成されてもよい。このような構成により、センサー部２からの信号配線８ｂの本数が少ない場合も、配線レイアウトを変更することなく第１の実施形態と同様の効果を得ることができる。 In the semiconductor device 150 shown in FIG. 7, the dummy connection portion 21 is disposed in addition to the first electrode 6 b connected to the wiring 8 b from the sensor portion 2. The dummy connection portion 21 may be formed by a third electrode formed on the main surface of the first semiconductor chip 1 and a connection member (not shown) joined to the third electrode. With such a configuration, even when the number of signal wirings 8b from the sensor unit 2 is small, the same effect as that of the first embodiment can be obtained without changing the wiring layout.
　（第１の実施形態の変形例６）
　以下、図８Ａ、図８Ｂを用いて、第１の実施形態の変形例６を説明する。 (Modification 6 of the first embodiment)
Hereinafter, Modification 6 of the first embodiment will be described with reference to FIGS. 8A and 8B.
　図８Ａは、本変形例にかかる半導体装置の構成を模式的に示す断面図である。以下、第１の実施形態との相違点を中心に説明するため、説明を簡略化したり、省略したりする構成もある。 FIG. 8A is a cross-sectional view schematically showing a configuration of a semiconductor device according to this modification. Hereinafter, in order to describe mainly the differences from the first embodiment, there are configurations in which the description is simplified or omitted.
　図８Ａに示す半導体装置１６０は、第１の半導体チップ１ｃと、第１の半導体チップ１ｃの側端面から外方に拡張された拡張部２２と、第１の半導体チップ１ｃの主面から拡張部２２に亘って形成された再配線層２３とを有する。さらに第１の半導体チップ１ｃと拡張部２２にまたがって載置された第２の半導体チップ３と、第１の半導体チップ１ｃと第２の半導体チップ３を電気的に接続する接続部材４ａと、第１の半導体チップ１ｃと第２の半導体チップ３の隙間に充填された樹脂５とを有する。 A semiconductor device 160 shown in FIG. 8A includes a first semiconductor chip 1c, an extended portion 22 extended outward from the side end surface of the first semiconductor chip 1c, and an extended portion from the main surface of the first semiconductor chip 1c. 22 and a rewiring layer 23 formed over 22. Furthermore, the second semiconductor chip 3 placed across the first semiconductor chip 1c and the extended portion 22, the connection member 4a for electrically connecting the first semiconductor chip 1c and the second semiconductor chip 3, The resin 5 filled in the gap between the first semiconductor chip 1c and the second semiconductor chip 3 is included.
　第１の半導体チップ１ｃは、シリコン等の半導体基板に回路が形成されて成る半導体チップであり、主面に、センサー部２と接続される第１の電極６ｃを備える。センサー部２は、例えば光電変換回路が行列状に配置された光電変換領域であり、入射光を受光して電気信号に変換する。第１の電極６ｃはセンサー部２側に配置されている。 The first semiconductor chip 1c is a semiconductor chip in which a circuit is formed on a semiconductor substrate such as silicon, and includes a first electrode 6c connected to the sensor unit 2 on the main surface. The sensor unit 2 is, for example, a photoelectric conversion region in which photoelectric conversion circuits are arranged in a matrix, and receives incident light and converts it into an electrical signal. The first electrode 6c is disposed on the sensor unit 2 side.
　拡張部２２は、第１の半導体チップ１ｃの側端面から外方に拡張されて成り、材料は、例えば成型、加工が容易なエポキシ等の樹脂が適している。第１の半導体チップ１ｃの主面から拡張部２２の上面に亘っては、再配線２４と、再配線２４を覆う保護膜２５とを含む再配線層２３が形成されている。再配線２４は、一般的にはフォトリソグラフィーを用いた電気めっきにより形成するため、配線厚みは約３～５μｍ程度、幅は任意で作製可能である。半導体チップ内部の配線と比較して寸法が大きく、電気抵抗が小さいのが特徴である。再配線２４には、電気めっきなど簡易な工程で形成可能で、電気伝導性にも優れた銅が適している。保護膜２５には、ポリイミド（ＰＩ：Ｐｏｌｙｉｍｉｄｅ）やポリベンゾオキサゾール（ＰＢＯ：ｐｏｌｙ　ｂｅｎｚ　ｏｘａｚｏｌｅ）等の樹脂を適用すると、加工が容易であり、高い保護効果を果たす。 The extended portion 22 is formed by extending outward from the side end surface of the first semiconductor chip 1c, and a material such as an epoxy resin that is easy to mold and process is suitable for the material. A rewiring layer 23 including a rewiring 24 and a protective film 25 covering the rewiring 24 is formed from the main surface of the first semiconductor chip 1 c to the upper surface of the extended portion 22. Since the rewiring 24 is generally formed by electroplating using photolithography, the wiring thickness can be about 3 to 5 μm and the width can be arbitrarily formed. It is characterized by a large size and a small electrical resistance compared to the wiring inside the semiconductor chip. For the rewiring 24, copper that can be formed by a simple process such as electroplating and has excellent electrical conductivity is suitable. When a resin such as polyimide (PI) or polybenzoxazole (PBO) is applied to the protective film 25, processing is easy and a high protective effect is achieved.
　再配線層２３には、第２の半導体チップ３の搭載領域において、第１の半導体チップ１ｃの領域に配置され、再配線２４を介して第１の電極６ｃと接続された第５の電極２６と、拡張部２２の領域に配置された第６の電極２７とが形成される。第５の電極２６は接続部材４ａを介して第２の半導体チップ３の第３の電極１１と、第６の電極２７は接続部材４ｂを介して第２の半導体チップの第４の電極１２と接続される。また、第２の半導体チップ３の搭載領域より外周には、第６の電極２７と再配線２４で接続された外部電極端子９ｄが配置される。外部電極端子９ｄは、銅やニッケルにより形成されてもよいし、銅／はんだやニッケル／金などの積層構造であってもよい。はんだの組成は、例えば機械的特性に優れた錫－銀系、錫－銅系、錫－ビスマス系、錫－インジウム系の合金がある。 In the rewiring layer 23, a fifth electrode 26 disposed in the region of the first semiconductor chip 1 c in the mounting region of the second semiconductor chip 3 and connected to the first electrode 6 c through the rewiring 24. And the sixth electrode 27 disposed in the region of the extended portion 22 is formed. The fifth electrode 26 is connected to the third electrode 11 of the second semiconductor chip 3 via the connection member 4a, and the sixth electrode 27 is connected to the fourth electrode 12 of the second semiconductor chip via the connection member 4b. Connected. In addition, an external electrode terminal 9 d connected to the sixth electrode 27 by the rewiring 24 is arranged on the outer periphery from the mounting region of the second semiconductor chip 3. The external electrode terminal 9d may be formed of copper or nickel, or may be a laminated structure of copper / solder or nickel / gold. The composition of the solder includes, for example, tin-silver, tin-copper, tin-bismuth, and tin-indium alloys having excellent mechanical properties.
　図８Ｂは、本実施形態にかかる半導体装置の構成を模式的に示す平面図である。 FIG. 8B is a plan view schematically showing the configuration of the semiconductor device according to the present embodiment.
　図８Ｂに示すように、半導体装置１６０では、再配線層２３は、第１の半導体チップ１ｃのセンサー部２を避けて形成され、センサー部２は再配線層２３より露出している。また、外部電極端子９ｄは、第２の半導体チップ３の搭載領域外であれば、拡張部２２の領域だけでなく、第１の半導体チップ１ｃの領域にも配置されていてもよい。 As shown in FIG. 8B, in the semiconductor device 160, the rewiring layer 23 is formed avoiding the sensor portion 2 of the first semiconductor chip 1c, and the sensor portion 2 is exposed from the rewiring layer 23. Further, the external electrode terminal 9d may be arranged not only in the area of the extension part 22 but also in the area of the first semiconductor chip 1c as long as it is outside the area where the second semiconductor chip 3 is mounted.
　第２の半導体チップ３は、シリコン等の半導体基板に回路が形成されて成る半導体チップであり、主面に第１の半導体チップ１ｃと電気的なやりとりを行う回路を有する。 The second semiconductor chip 3 is a semiconductor chip in which a circuit is formed on a semiconductor substrate such as silicon, and has a circuit that performs electrical exchange with the first semiconductor chip 1c on the main surface.
　第２の半導体チップ３は、センサー部２を避けて、第１の半導体チップ１ｃの周縁部から拡張部２２に亘って配置される。 The second semiconductor chip 3 is arranged from the peripheral part of the first semiconductor chip 1c to the extension part 22 avoiding the sensor part 2.
　第２の半導体チップ３と第１の半導体チップ１ｃの主面および拡張部２２の主面との隙間に、接合部の補強のために樹脂５が充填される。樹脂５は、再配線層２３の上で、接続部材４ａ、４ｂを囲むよう配置される。樹脂５のはみ出し量は、第２の半導体チップ３のセンサー部側とその対面側とで偏りを有し、第２の半導体チップ３のセンサー部２側において、センサー部２の対面側よりも小さく形成される。この偏りは、第５の電極２６と接続部材４ａ、第６の電極２７と接続部材４ｂとの密度を異ならせることによって形成してもよい。 The resin 5 is filled in the gap between the main surface of the second semiconductor chip 3 and the first semiconductor chip 1c and the main surface of the extended portion 22 to reinforce the joint portion. The resin 5 is disposed on the rewiring layer 23 so as to surround the connection members 4a and 4b. The amount of protrusion of the resin 5 is biased between the sensor portion side of the second semiconductor chip 3 and its facing side, and is smaller on the sensor portion 2 side of the second semiconductor chip 3 than on the facing side of the sensor portion 2. It is formed. This bias may be formed by differentiating the densities of the fifth electrode 26 and the connection member 4a, and the sixth electrode 27 and the connection member 4b.
　以上、第１の実施形態の変形例６にかかる半導体装置１６０では、第１の実施形態やその変形例１～５と同様、センサー部２側での樹脂５のはみ出しを抑制することができるため、センサー部２と第１の電極６ｃとを結ぶ配線８への寄生容量は小さくなり、センサー部２からの出力信号の劣化を防ぐとともに、消費電力の削減、信号伝送速度の向上を実現できる。 As described above, in the semiconductor device 160 according to the sixth modification of the first embodiment, the protrusion of the resin 5 on the sensor unit 2 side can be suppressed as in the first embodiment and the first to fifth modifications. The parasitic capacitance to the wiring 8 connecting the sensor unit 2 and the first electrode 6c is reduced, so that the output signal from the sensor unit 2 can be prevented from being deteriorated, and the power consumption can be reduced and the signal transmission speed can be improved.
　また、外部電極端子９ｄの配置など、第２の半導体チップ３からの外部への電気的な引き出しは拡張部２２で行うため、その分第１の半導体チップ１ｃおよび第２の半導体チップ３の回路設計が容易になり、チップ設計期間や設計コストの悪化を防止することができる。 Further, since the electrical lead-out from the second semiconductor chip 3 to the outside, such as the arrangement of the external electrode terminals 9d, is performed by the extended portion 22, the circuits of the first semiconductor chip 1c and the second semiconductor chip 3 are accordingly provided. Design becomes easy, and deterioration of the chip design period and design cost can be prevented.
　また、樹脂５のはみ出しの小さな領域においてはシリコン等からなる半導体基板を、樹脂５のはみ出しの大きな領域において樹脂等からなる拡張部２２を備える。これにより、高価なシリコン基板の面積を最小限に抑えることができ、チップ当たりの歩留まり向上、製造コストの削減が期待できる。 In addition, a semiconductor substrate made of silicon or the like is provided in a region where the resin 5 protrudes little, and an extended portion 22 made of resin or the like is provided in a region where the resin 5 protrudes greatly. As a result, the area of the expensive silicon substrate can be minimized, and the yield per chip can be improved and the manufacturing cost can be reduced.
　なお、本開示の効果は、第１の半導体チップ１ｃが高画素化するとより顕著になる。すなわち、高画素化に伴い第２の半導体チップ３の回路規模が増大し、チップサイズが大きくなった場合も、拡張部２２の領域を調整することで第２の半導体チップ３の搭載領域を確保できるため、第１の半導体チップ１ｃのサイズは小さく保つことができる。 Note that the effect of the present disclosure becomes more prominent when the first semiconductor chip 1c has a higher pixel count. In other words, even when the circuit size of the second semiconductor chip 3 increases and the chip size increases with the increase in the number of pixels, the mounting area of the second semiconductor chip 3 is secured by adjusting the area of the extension portion 22. Therefore, the size of the first semiconductor chip 1c can be kept small.
　（第１の実施形態の製造方法）
　以下、図９Ａ～Ｅおよび図１０を用いて、第１の実施形態の製造方法を説明する。 (Manufacturing method of the first embodiment)
Hereinafter, the manufacturing method of the first embodiment will be described with reference to FIGS. 9A to 9E and FIG.
　図９Ａ～Ｅは、本実施形態の製造方法を模式的に示す断面図である。 9A to 9E are cross-sectional views schematically showing the manufacturing method of the present embodiment.
　まず、図９Ａに示すように、第１の半導体チップ１に拡散工程で回路を形成する。この工程では、第１の半導体チップ１の主面に、センサー部２や配線８、１０、第１の電極６、第２の電極７、外部電極端子９などを形成する。 First, as shown in FIG. 9A, a circuit is formed in the first semiconductor chip 1 by a diffusion process. In this step, the sensor unit 2, the wirings 8 and 10, the first electrode 6, the second electrode 7, the external electrode terminal 9, and the like are formed on the main surface of the first semiconductor chip 1.
　次に、図９Ｂに示すように、第１の半導体チップ１の第１の電極６に、接続部材４ａを接合し、第２の電極７に接続部材４ｂを接合する。ここで、第２の半導体チップ３に関しても同様に、第３の電極１１、第４の電極１２に対し、それぞれ接続部材を形成してもよい（図示せず）。 Next, as shown in FIG. 9B, the connection member 4 a is bonded to the first electrode 6 of the first semiconductor chip 1, and the connection member 4 b is bonded to the second electrode 7. Here, similarly, connection members may be formed for the third electrode 11 and the fourth electrode 12 for the second semiconductor chip 3 (not shown).
　次に、図９Ｃに示すように、第１の半導体チップ１の主面上の第２の半導体チップ３の搭載領域に樹脂５を塗布する。樹脂５は、第１の電極６や接続部材４ａの配置された箇所に塗布される。 Next, as shown in FIG. 9C, a resin 5 is applied to the mounting region of the second semiconductor chip 3 on the main surface of the first semiconductor chip 1. The resin 5 is applied to the place where the first electrode 6 and the connection member 4a are disposed.
　次に、図９Ｄに示すように、先に塗布した樹脂５を濡れ広げながら、第２の半導体チップ３を実装する。このとき、第１の電極６と第３の電極１１とを、接続部材４ａを介して、第２の電極７と第４の電極１２とを、接続部材４ｂを介して、それぞれ接合する。 Next, as shown in FIG. 9D, the second semiconductor chip 3 is mounted while spreading the previously applied resin 5 wet. At this time, the first electrode 6 and the third electrode 11 are joined to each other via the connection member 4a, and the second electrode 7 and the fourth electrode 12 are joined to each other via the connection member 4b.
　図９Ｅは完成図である。 FIG. 9E is a completed drawing.
　以上のような製造工法により、第１の半導体チップ１と第２の半導体チップ３の接合部のピッチが狭ピッチ（例えば４０μｍピッチ以下）になった場合にも、安定的に樹脂５を注入することができる。 By the manufacturing method as described above, the resin 5 is stably injected even when the pitch of the joint portion between the first semiconductor chip 1 and the second semiconductor chip 3 becomes a narrow pitch (for example, 40 μm pitch or less). be able to.
　また、通常、樹脂をフリップチップ接合後に注入する工法において、樹脂の流動体を上げるため、常温で樹脂の粘度は１０～５０Ｐａ・ｓのものが主流である。フリップチップの前に塗布する場合、塗布した時点で濡れ広がらないように常温での粘度は３０～１６０Ｐａ・ｓのものが主流である。そのため、フリップチップ接合前に樹脂５を塗布する工法において、フリップチップ接合後に樹脂５の粘度が高いため、必要以上に広がることがないので、フリップチップ接合後に樹脂を注入する工法に比べ樹脂５のはみ出し量を抑えることができる。 In general, in the method of injecting resin after flip-chip bonding, the viscosity of the resin is 10 to 50 Pa · s at room temperature in order to increase the resin fluid. When applying before flip chip, the viscosity at room temperature is mainly 30 to 160 Pa · s so that it does not spread when wet. Therefore, in the method of applying the resin 5 before the flip chip bonding, the viscosity of the resin 5 is high after the flip chip bonding, so that the resin 5 does not spread more than necessary. The amount of protrusion can be suppressed.
　図１０（ａ）、（ｂ）、（ｃ）はそれぞれ図９Ｃにおける塗布パターンの例を示したものである。樹脂５の塗布パターンとしては第２の半導体チップ３の搭載領域２８の中心に対して対称なものが、製造が容易で好ましい。また樹脂５が連続的に形成されていることが望ましい。連続的に形成されていることにより、巻き込みボイドの不良を回避することが可能である。なお、塗布のパターンは、これらに限るものではない。 10 (a), (b), and (c) show examples of application patterns in FIG. 9C, respectively. The application pattern of the resin 5 is preferably symmetrical with respect to the center of the mounting region 28 of the second semiconductor chip 3 because it is easy to manufacture. Moreover, it is desirable that the resin 5 is formed continuously. By being formed continuously, it is possible to avoid defects in entrainment voids. In addition, the pattern of application | coating is not restricted to these.
　以上のように、本発明において開示する技術の例示として、第１の実施形態とその変形例を説明した。しかしながら、本開示における技術は、これに限定されず、適宜、変更、置き換え、付加、省略などを行った実施の形態にも適用可能である。また、上記第１の実施形態および変形例で説明した各構成要素を組み合わせて、新たな実施の形態とすることも可能である。 As described above, the first embodiment and its modifications have been described as examples of the technology disclosed in the present invention. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to combine each component demonstrated in the said 1st Embodiment and the modification, and can be set as a new embodiment.
　例えば、第１の実施形態および変形例では、外部電極端子９は第１の半導体チップ１の主面に形成されたが、必ずしも主面に形成する必要は無く、配線１０を介して側面や裏面に引き出してもよい。 For example, in the first embodiment and the modification, the external electrode terminal 9 is formed on the main surface of the first semiconductor chip 1, but it is not always necessary to form the external electrode terminal 9 on the main surface. You may pull it out.
　また、第２の半導体チップ３は、必ずしも回路面を第１の半導体チップ１に対向させる必要は無く、回路面を上に向けたうえで、貫通電極等で裏面まで電気的に引き出して、第１の半導体チップと電気的な接続をとっても構わない。 Further, the second semiconductor chip 3 does not necessarily have the circuit surface opposed to the first semiconductor chip 1. The circuit surface is directed upward, and the second semiconductor chip 3 is electrically pulled out to the back surface with a through electrode or the like. One semiconductor chip may be electrically connected.
　また、センサー部２から出力され配線８を流れる信号は、アナログ信号に限られず、デジタル信号であってもよい。言い換えれば、アナログ信号配線に限られず、デジタル信号配線であってもよい。但し、アナログ信号のほうが、樹脂５の寄生容量により波形の絶対値が損なわれたときの影響が大きく、本開示の効果をより享受する。 The signal output from the sensor unit 2 and flowing through the wiring 8 is not limited to an analog signal, and may be a digital signal. In other words, it is not limited to analog signal wiring, but may be digital signal wiring. However, the analog signal has a greater influence when the absolute value of the waveform is lost due to the parasitic capacitance of the resin 5, and enjoys the effect of the present disclosure more.
　以上のように、本開示における技術の例示として、実施の形態およびその変形例を説明した。そのために、添付図面および詳細な説明を提供した。 As described above, the embodiments and the modifications thereof have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.
　したがって、添付図面および詳細な説明に記載された構成要素の中には、課題解決のために必須な構成要素だけでなく、上記技術を例示するために、課題解決のためには必須でない構成要素も含まれ得る。そのため、それらの必須ではない構成要素が添付図面や詳細な説明に記載されていることをもって、直ちに、それらの必須ではない構成要素が必須であるとの認定をするべきではない。例えば、添付図面および詳細な説明では、第１の半導体チップとしてセンサー部を備えた構成を取り上げて説明した。しかし、本発明は、相対的に大きな第１の半導体チップと相対的に小さい第２の半導体チップとが積層形成された際に、第１および第２の半導体チップ間の隙間に配置された樹脂が、第１の半導体チップにおける第２の半導体チップ搭載領域外へ延伸する配線領域上を被覆して寄生容量となって生じる配線を伝わる出力信号の波形劣化を軽減し、信号品質を向上させることが目的である。そのため、第１の半導体チップにおける第２の半導体チップ搭載領域外に形成される回路領域がセンサー部であることは一例に過ぎない。 Accordingly, among the components described in the accompanying drawings and the detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to illustrate the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description. For example, in the accompanying drawings and detailed description, the configuration including the sensor unit as the first semiconductor chip has been described. However, according to the present invention, when the relatively large first semiconductor chip and the relatively small second semiconductor chip are laminated, the resin disposed in the gap between the first and second semiconductor chips. However, it is possible to reduce the waveform deterioration of the output signal transmitted through the wiring generated as a parasitic capacitance by covering the wiring region extending outside the second semiconductor chip mounting region in the first semiconductor chip, and improve the signal quality. Is the purpose. Therefore, the circuit area formed outside the second semiconductor chip mounting area in the first semiconductor chip is merely an example.
　また、上述の実施の形態およびその変形例は、本開示における技術を例示するためのものであるから、請求の範囲またはその均等の範囲において種々の変更、置き換え、付加、省略などを行うことができる。 Moreover, since the above-mentioned embodiment and its modification are for illustrating the technique in the present disclosure, various modifications, replacements, additions, omissions, etc. may be made within the scope of the claims or an equivalent scope thereof. it can.
　本開示は、センサー部を有する第１の半導体チップに、第１の半導体チップと電気的に接続する第２の半導体チップを搭載する半導体装置に最適である。具体的には、光電変換部を備えた光学チップ上にＡＤＣチップを搭載する撮像装置などに、本開示は適用可能である。 The present disclosure is most suitable for a semiconductor device in which a second semiconductor chip electrically connected to a first semiconductor chip is mounted on a first semiconductor chip having a sensor unit. Specifically, the present disclosure is applicable to an imaging device in which an ADC chip is mounted on an optical chip that includes a photoelectric conversion unit.
　１，１ａ，１ｂ，１ｃ　第１の半導体チップ
　２，２ａ　センサー部
　３，３ａ，３ｂ，３ｃ　第２の半導体チップ
　４ａ，４ｂ　接続部材
　５，５ａ，５ｂ　樹脂
　６，６ａ，６ｂ，６ｃ，７，７ａ，７ｂ，１１，１２，２６，２７　電極
　８，８ａ，８ｂ，１０，１０ａ，１０ｂ，１０ｃ　配線
　９，９ａ，９ｂ，９ｃ，９ｄ　外部電極端子
　２１　ダミー接続部
　２２　拡張部
　２３　再配線層
　２４　再配線
　２５　保護膜 1, 1a, 1b, 1c 1st semiconductor chip 2, 2a Sensor part 3, 3a, 3b, 3c 2nd semiconductor chip 4a, 4b Connection member 5, 5a, 5b Resin 6, 6a, 6b, 6c, 7, 7a, 7b, 11, 12, 26, 27 Electrode 8, 8a, 8b, 10, 10a, 10b, 10c Wiring 9, 9a, 9b, 9c, 9d External electrode terminal 21 Dummy connection portion 22 Expansion portion 23 Rewiring layer 24 Rewiring 25 Protective film

Claims (14)

  1. 　第１の面に、電極と第１の部分領域とを有する第１の半導体チップと、
    　前記第１の半導体チップの前記第１の面に、前記第１の部分領域を避けて搭載された第２の半導体チップと、
    　前記電極と接合され、前記第１の半導体チップと前記第２の半導体チップを電気的に接続する接続部材と、
    　前記第１の半導体チップと前記第２の半導体チップの隙間に、前記接続部材を囲むように配置された樹脂とを備え、
    　前記樹脂のはみ出し量は、前記第２の半導体チップの前記第１の部分領域側において、前記第１の部分領域の対面側よりも小さく形成されることを特徴とする半導体装置。     A first semiconductor chip having an electrode and a first partial region on a first surface;
    A second semiconductor chip mounted on the first surface of the first semiconductor chip avoiding the first partial region;
    A connection member joined to the electrode and electrically connecting the first semiconductor chip and the second semiconductor chip;
    A resin disposed so as to surround the connection member in a gap between the first semiconductor chip and the second semiconductor chip;
    The semiconductor device is characterized in that the amount of protrusion of the resin is smaller on the first partial region side of the second semiconductor chip than on the facing side of the first partial region.
  2. 　前記樹脂のはみ出し量は、平面視における前記第２の半導体チップの端面から前記第２の半導体チップの外方へ延伸した領域の大きさであることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the amount of protrusion of the resin is a size of a region extending from an end face of the second semiconductor chip to the outside of the second semiconductor chip in a plan view. .
  3. 　前記第１の半導体の主面に、前記第１の部分領域と前記電極とを接続する配線を備えることを特徴とする請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, further comprising a wiring connecting the first partial region and the electrode on a main surface of the first semiconductor.
  4. 　前記配線はアナログ信号配線であることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the wiring is an analog signal wiring.
  5. 　前記第１の部分領域側の接続部材の密度が、前記第１の部分領域と反対側の接続部材の密度より大きいことを特徴とする請求項１から４のいずれか１項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein a density of the connection member on the first partial region side is larger than a density of the connection member on the side opposite to the first partial region. 6. .
  6. 　前記第１の部分領域側の接続部材のピッチが、前記第１の部分領域と反対側の接続部材のピッチより小さいことを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein a pitch of the connection member on the first partial region side is smaller than a pitch of the connection member on the opposite side to the first partial region. .
  7. 　前記第１の部分領域側の接続部材の列数が、前記第１の部分領域と反対側の接続部材の列数より多いことを特徴とする請求項１から６のいずれか１項に記載の半導体装置。 The number of rows of connection members on the first partial region side is greater than the number of rows of connection members on the side opposite to the first partial region. Semiconductor device.
  8. 　前記第１の部分領域と反対側の接続部材の配列において、前記第１の部分領域側の接続部材のピッチよりも大きな隙間部を持つことを特徴とする請求項１から７のいずれか１項に記載の半導体装置。 The arrangement of the connection members on the side opposite to the first partial region has a gap portion that is larger than the pitch of the connection members on the first partial region side. A semiconductor device according to 1.
  9. 　前記接続部材において、前記第１の部分領域側において前記樹脂のはみ出しがないことを特徴とする請求項１から８のいずれか１項に記載の半導体装置。 9. The semiconductor device according to claim 1, wherein in the connection member, the resin does not protrude on the first partial region side.
  10. 　前記第１の半導体チップの側端面より外方に拡張された拡張部を有しており、
    　前記第１の半導体チップの側面が前記第２の半導体チップの下部に存在することを特徴とする請求項１から９のいずれか１項に記載の半導体装置。     Having an extended portion extended outward from the side end face of the first semiconductor chip;
    10. The semiconductor device according to claim 1, wherein a side surface of the first semiconductor chip is present below the second semiconductor chip. 11.
  11. 　前記第２の半導体チップが信号処理素子であることを特徴とする請求項１から１０のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10, wherein the second semiconductor chip is a signal processing element.
  12. 　前記第１の部分領域が受光素子であり、前記信号処理素子がＡＤコンバータであることを特徴とする請求項１１に記載の半導体装置。 12. The semiconductor device according to claim 11, wherein the first partial region is a light receiving element, and the signal processing element is an AD converter.
  13. 　前記第１の部分領域と前記第２の半導体チップの外縁までの距離が、前記外部電極端子と前記第２の半導体チップの外縁までの距離より小さいことを特徴とする請求項１から１２のいずれか１項に記載の半導体装置。 The distance from the first partial region to the outer edge of the second semiconductor chip is smaller than the distance from the external electrode terminal to the outer edge of the second semiconductor chip. 2. The semiconductor device according to claim 1.
  14. 　前記第１の部分領域はセンサー部であることを特徴とする請求項１から１３のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first partial region is a sensor unit.
PCT/JP2014/005164 2013-10-16 2014-10-10 Semiconductor device WO2015056430A1 (en)

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