JP2009200210A - Semiconductor package and substrate used for the same - Google Patents

Semiconductor package and substrate used for the same Download PDF

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JP2009200210A
JP2009200210A JP2008039711A JP2008039711A JP2009200210A JP 2009200210 A JP2009200210 A JP 2009200210A JP 2008039711 A JP2008039711 A JP 2008039711A JP 2008039711 A JP2008039711 A JP 2008039711A JP 2009200210 A JP2009200210 A JP 2009200210A
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substrate
semiconductor package
metal pattern
dummy metal
package according
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Wen-Jeng Fan
文正 范
Yi-Ling Liu
怡伶 劉
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package restraining warpage in the side of a substrate, preventing fracture in the substrate, and avoiding damage to the surface of a chip and the side, and to provide a substrate used for the semiconductor package. <P>SOLUTION: The substrate 210 of the semiconductor package 200 includes a plurality of signal fingers 211, a dummy metal pattern 212, and at least one peripheral recessed groove 213 passing through the substrate 210. The dummy metal pattern 212 is extended to a position 213 of the peripheral recessed groove, and is electrically insulated from the signal finger 211. The chip 220 is installed on the substrate 210 and includes a plurality of bonding pads 221, 222, and electrically connects the bonding pad of the chip to the signal finger 211 of the substrate via an electric connection element 230. A sealing body 240 seals the electric connection element 230 and is filled into the peripheral recessed groove 213. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体パッケージに関し、特に周辺小ウインドーを持つ半導体パッケージとそれに用いる基板に関するものである。   The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a small peripheral window and a substrate used therefor.

集積回路実装の領域において、ウインドー型半導体パッケージ（Window type semiconductor package）は、チップを搭載する一つの回路基板にウインドーを形成し、金属ボンディングワイヤ或いは従来の電気接続素子をこのウインドーに通して基板とチップとを電気接続させる構造となる。従来のウインドーは基板中央に形成される細長いスロットであり、チップの複数の中央ボンディングパッドを露出させる。また、通常チップが有する周辺ボンディングパッドの数は中央ボンディングパッドの数よりも少なく、あるいは、周辺ボンディングパッドを持たなくてもよい。ゆえに、基板の周辺にあるウインドーの形状は長方形や正方形の孔にしてもよいが、周辺小ウインドーとしての長方形および正方形の孔は、モールド封止剤の収容体積が小さいので、モールド封止剤の溢れや隙間の発生といった問題が起き易くなる。以下、図面を参照しながら具体的に構造を説明する。   In the area of integrated circuit mounting, a window type semiconductor package forms a window on one circuit board on which a chip is mounted, and a metal bonding wire or a conventional electrical connection element is passed through the window to form a substrate. The structure is to electrically connect the chip. A conventional window is an elongated slot formed in the center of the substrate, exposing a plurality of central bonding pads of the chip. In addition, the number of peripheral bonding pads that a normal chip has is smaller than the number of central bonding pads, or the peripheral bonding pads may not be provided. Therefore, the shape of the window around the substrate may be a rectangular or square hole, but the rectangular and square holes as the peripheral small window have a small volume of the mold sealant. Problems such as overflow and gaps are likely to occur. The structure will be specifically described below with reference to the drawings.

図１に示すように、周辺小ウインドーを持つ従来の半導体パッケージ１００は、基板１１０、チップ１２０、複数の電気接続素子１３０、例えばボンディングワイヤ、及び封止体１４０を含む。基板１１０は複数のフィンガー１１１、中央スロット１１７、及び基板１１０を通る複数の周辺小ウインドー１１３を有する。基板１１０の上表面１１４には、図２に示すようにチップ１２０の設置に用いるチップ配設領域１１４Ａを有し、基板１１０の下表面１１５には、外部との接合に用いる複数の外接パッド１１８を有する。また、図１及び図２に示すように、周辺小ウインドー１１３は基板１１０の側辺に形成された略長方形や正方形の孔であり、一個か複数個の周辺ボンディングパッド１２２を露出させる。電気接続素子１３０の多くは中央スロット１１７を通してチップ１２０の複数の中央ボンディングパッド１２１と基板１１０とを電気的に接続し、他の少数の電気接続素子１３０は周辺小ウインドー１１３を通してチップ１２０の少数の周辺ボンディングパッド１２２と基板１１０とを電気接続している。なお、複数の外接端子１５０、例えば従来のボンディングボールは、パッケージ全体が外部との電気接続用として外接パッド１１８に設置されうる。封止体１４０はチップ１２０を密封し、かつ電気接続素子１３０を密封するために、中央スロット１１７と周辺小ウインドー１１３とに充填されている。周辺小ウインドー１１３の形状は正方形や長方形となり、それらの寸法は中央スロット１１７よりも遥かに小さいため、チップ１２０の側辺の構造を弱くしすぎるものとはならないが、孔の成形が困難となりかつ基板の製造コストが高くなる。なお、封止体１４０を形成するモールド封止剤は周辺小ウインドー１１３に充填しにくいので、モールド封止剤の溢れ現象が起きる。   As shown in FIG. 1, a conventional semiconductor package 100 having a small peripheral window includes a substrate 110, a chip 120, a plurality of electrical connection elements 130, for example, bonding wires, and a sealing body 140. The substrate 110 has a plurality of fingers 111, a central slot 117, and a plurality of peripheral small windows 113 that pass through the substrate 110. As shown in FIG. 2, the upper surface 114 of the substrate 110 has a chip placement region 114A used for installing the chip 120, and the lower surface 115 of the substrate 110 has a plurality of circumscribed pads 118 used for bonding to the outside. Have Also, as shown in FIGS. 1 and 2, the peripheral small window 113 is a substantially rectangular or square hole formed on the side of the substrate 110 and exposes one or a plurality of peripheral bonding pads 122. Many of the electrical connection elements 130 electrically connect the plurality of central bonding pads 121 of the chip 120 and the substrate 110 through the central slot 117, and a small number of other electrical connection elements 130 pass through the peripheral small window 113 to form a small number of the chip 120. The peripheral bonding pad 122 and the substrate 110 are electrically connected. A plurality of external terminals 150, for example, conventional bonding balls, can be installed on the external pads 118 for electrical connection with the outside of the entire package. The sealing body 140 is filled in the central slot 117 and the peripheral small window 113 for sealing the chip 120 and sealing the electrical connection element 130. The shape of the peripheral small window 113 is a square or a rectangle, and their dimensions are much smaller than the central slot 117, so that the structure of the side of the chip 120 will not be too weak, but it is difficult to form a hole and The manufacturing cost of the substrate increases. In addition, since the mold sealant forming the sealing body 140 is difficult to fill the peripheral small window 113, an overflow phenomenon of the mold sealant occurs.

本発明の目的は、ウインドーを有する構造の半導体パッケージとそれに用いる基板を提供することである。   An object of the present invention is to provide a semiconductor package having a window structure and a substrate used therefor.

上記目的を達成するために本発明では、次に述べる技術が提案されている。本発明による半導体パッケージは、基板、チップ、複数の電気接続素子、及び封止体を備える。この基板は複数の信号フィンガー、ダミー金属パターン、及び少なくとも一つの周縁凹み溝を有し、ダミー金属パターンは周縁凹み溝の位置まで延びており、かつ、信号フィンガーとは電気的に絶縁している。チップは基板の上に設置され、かつ、複数のボンディングパッドを有する。それぞれ電気接続素子を介して、チップのボンディングパッドと基板の信号フィンガーとは電気的に接続している。封止体は電気接続素子を密封し、かつ、周縁凹み溝にも充填されている。なお、本発明はさらに上記の半導体パッケージに用いる基板を開示している。   In order to achieve the above object, the following techniques are proposed in the present invention. A semiconductor package according to the present invention includes a substrate, a chip, a plurality of electrical connection elements, and a sealing body. The substrate has a plurality of signal fingers, a dummy metal pattern, and at least one peripheral recess groove, and the dummy metal pattern extends to the position of the peripheral recess groove and is electrically insulated from the signal finger. . The chip is placed on the substrate and has a plurality of bonding pads. The bonding pads of the chip and the signal fingers of the substrate are electrically connected to each other through electrical connection elements. The sealing body seals the electrical connection element and fills the peripheral recess groove. The present invention further discloses a substrate used for the semiconductor package.

本発明の半導体パッケージにおいて、少なくとも２つの電気接続素子は周縁凹み溝を通過するものでありうる。
本発明の半導体パッケージにおいて、ダミー金属パターンは少なくとも２つの補強側縁部を有し、補強側縁部は周縁凹み溝の開口方向とほぼ垂直になったものでありうる。
本発明の半導体パッケージにおいて、ダミー金属パターンは２つの補強側縁部を提供するため、細長形状でありうる。 In the semiconductor package of the present invention, the at least two electrical connection elements may pass through the peripheral recess groove.
In the semiconductor package of the present invention, the dummy metal pattern may have at least two reinforcing side edges, and the reinforcing side edges may be substantially perpendicular to the opening direction of the peripheral recess groove.
In the semiconductor package of the present invention, the dummy metal pattern may have an elongated shape to provide two reinforcing side edges.

本発明の半導体パッケージにおいて、ダミー金属パターンはくしのように配列する複数の支持フィンガーを有してもよい。
本発明の半導体パッケージにおいて、ダミー金属パターンと信号フィンガーとは基板の同一配線層に形成されてもよい。
本発明の半導体パッケージにおいて、配線層は基板の下表面に位置するものでありうる。 In the semiconductor package of the present invention, the dummy metal pattern may have a plurality of support fingers arranged like combs.
In the semiconductor package of the present invention, the dummy metal pattern and the signal finger may be formed on the same wiring layer of the substrate.
In the semiconductor package of the present invention, the wiring layer may be located on the lower surface of the substrate.

本発明の半導体パッケージにおいて、ダミー金属パターンは基板の上表面に位置するものでありうる。
本発明の半導体パッケージにおいて、周縁凹み溝は閉鎖スロットとなっていてもよい。
本発明の半導体パッケージにおいて、基板はさらにその隅にダミー孔を複数有し、封止体は各ダミー孔にも充填され、かつ基板の下表面に突起状に出ていることにより、複数の支持バンプを形成したものでありうる。 In the semiconductor package of the present invention, the dummy metal pattern may be located on the upper surface of the substrate.
In the semiconductor package of the present invention, the peripheral recess groove may be a closed slot.
In the semiconductor package of the present invention, the substrate further includes a plurality of dummy holes at the corners, and the sealing body is filled in each dummy hole and protrudes in a protruding shape on the lower surface of the substrate, thereby supporting a plurality of supports. A bump may be formed.

本発明の半導体パッケージにおいて、ダミー孔は周縁凹み溝の両端向きに位置するものとされうる。
本発明の半導体パッケージにおいて、基板はさらに中央スロットを有してもよい。
本発明の半導体パッケージにおいて、ダミー金属パターンは基板半田マスク層に被覆されてもよい。
本発明の半導体パッケージにおいて、ダミー金属パターンは電源／接地フィンガーと接続してもよく、このとき電源／接地フィンガーは周縁凹み溝の一端に隣接している。
本発明の半導体パッケージにおいて、ダミー金属パターンは信号フィンガーと接続してもよく、このとき信号フィンガーは周縁凹み溝の一端に隣接している。 In the semiconductor package of the present invention, the dummy holes may be located toward both ends of the peripheral recess groove.
In the semiconductor package of the present invention, the substrate may further have a central slot.
In the semiconductor package of the present invention, the dummy metal pattern may be covered with a substrate solder mask layer.
In the semiconductor package of the present invention, the dummy metal pattern may be connected to the power / ground finger, and at this time, the power / ground finger is adjacent to one end of the peripheral recess groove.
In the semiconductor package of the present invention, the dummy metal pattern may be connected to the signal finger, and at this time, the signal finger is adjacent to one end of the peripheral recess groove.

（発明の効果）
上述した本発明の半導体パッケージの構成によると、基板の周縁凹み溝は、モールド封止剤を充填し易く、かつ、複数の周辺小ウインドーと連通していることによりモールド封止剤の溢れ現象を防止する。また、ダミー金属パターンは周縁凹み溝まで延びているので、基板の反りを抑えることができ、さらに基板の断裂が生じることを防ぐ。かつ、この周縁凹み溝は、半導体パッケージの温度変化を繰り返す環境下での耐熱応力性を向上させるので、チップの表面や側辺の損傷を防ぐことができる。 (The invention's effect)
According to the configuration of the semiconductor package of the present invention described above, the peripheral recess groove of the substrate is easily filled with the mold sealant and communicates with a plurality of peripheral small windows, thereby preventing the mold sealant from overflowing. To prevent. Further, since the dummy metal pattern extends to the peripheral recess groove, it is possible to suppress the warpage of the substrate and further prevent the substrate from being torn. In addition, since the peripheral recess groove improves the heat stress resistance in an environment where the temperature change of the semiconductor package is repeated, it is possible to prevent damage to the chip surface and sides.

（第１実施形態）
本発明の第１実施形態による半導体パッケージとそれに用いる基板について図面を用いて説明する。
図３および図４に示すように、第１実施形態による半導体パッケージ構造２００は、基板２１０、チップ２２０、複数の電気接続素子２３０、及び封止体２４０を含む。基板２１０は、複数の信号フィンガー２１１、ダミー金属パターン２１２（dummy metal pattern）、及び基板２１０を通る孔である少なくとも一つの周縁凹み溝２１３を有する。ここで、ダミー金属パターン２１２は周縁凹み溝２１３よりも基板の平面上外側まで延びており、かつ短絡現象が起きないように信号フィンガー２１１とは電気的に絶縁している。また、基板２１０はチップ搭載に用いられるため単層或いは多層の配線構造となり、例えば、単層或いは多層のＰＣＢ（printed circuit board）である。本実施形態において、基板２１０はさらに中央スロット２１７を有する。この中央スロット２１７は、基板２１０の中央エリアに形成されて電気接続素子２３０をそれぞれ通し、封止体２４０の充填に利用されている。 (First embodiment)
A semiconductor package according to a first embodiment of the present invention and a substrate used therefor will be described with reference to the drawings.
As shown in FIGS. 3 and 4, the semiconductor package structure 200 according to the first embodiment includes a substrate 210, a chip 220, a plurality of electrical connection elements 230, and a sealing body 240. The substrate 210 includes a plurality of signal fingers 211, a dummy metal pattern 212, and at least one peripheral recess groove 213 that is a hole passing through the substrate 210. Here, the dummy metal pattern 212 extends from the peripheral recess groove 213 to the outside on the plane of the substrate, and is electrically insulated from the signal finger 211 so as not to cause a short circuit phenomenon. Further, since the substrate 210 is used for chip mounting, it has a single-layer or multilayer wiring structure, for example, a single-layer or multilayer PCB (printed circuit board). In the present embodiment, the substrate 210 further has a central slot 217. The central slot 217 is formed in the central area of the substrate 210, passes through the electrical connection elements 230, and is used for filling the sealing body 240.

図８に示すように、各周縁凹み溝２１３は、複数の周辺小ウインドー及び周辺小ウインドーに、ダミー連通溝が連続している溝である。ここで、周辺小ウインドーは、チップ２２０の周辺ボンディングパッド２２２を露出させる基板２１０の孔であり、図８に示した周縁凹み溝２１３の上下両端の位置をいう。また、ダミー連通溝は、この周辺小ウインドー同士を連通するための基板２１０の溝であり、図８に示した周縁凹み溝２１３においては、ボンディングパッドを露出している両端を除いた中央部分をいう。また、周縁凹み溝２１３は中央スロット２１７と同様の構成であるが、その長さは中央スロットに比べて短くてもよい。周縁凹み溝２１３によって、孔を開ける工程の複雑さと孔の数が低減され、モールド封止剤の充填に役立ち、かつモールド封止剤の溢れを防ぐことができる。しかしながら、基板２１０側辺の構造の強度は弱くなる。   As shown in FIG. 8, each peripheral recess groove 213 is a groove in which a dummy communication groove is continuous with a plurality of peripheral small windows and the peripheral small windows. Here, the peripheral small window is a hole in the substrate 210 that exposes the peripheral bonding pad 222 of the chip 220, and refers to the positions of the upper and lower ends of the peripheral recess groove 213 shown in FIG. Further, the dummy communication groove is a groove of the substrate 210 for communicating the peripheral small windows. In the peripheral concave groove 213 shown in FIG. Say. The peripheral recessed groove 213 has the same configuration as the central slot 217, but its length may be shorter than that of the central slot. The peripheral recess groove 213 reduces the complexity of the process of opening the holes and the number of holes, helps to fill the mold sealant, and prevents the mold sealant from overflowing. However, the strength of the structure on the side of the substrate 210 is weakened.

ここで、図６に示すようにダミー金属パターン２１２を周縁凹み溝２１３の位置まで延びるように設ける方式により、基板２１０の周縁凹み溝２１３側辺の構造の強度を増強することが可能である。本実施形態において、ダミー金属パターン２１２と信号フィンガー２１１とは、図４に蔭をつけて示すように、基板２１０の同一配線層に形成される。配線層は基板２１０の下表面２１５に形成され、それにより、基板２１０の周縁凹み溝２１３側辺の反りを抑えることができ、さらに基板２１０の断裂の可能性を低下させ、かつ、周縁凹み溝２１３は温度サイクルの環境での耐熱応力性を向上させてチップ２２０の表面や側辺の損傷を避けることを可能にする。   Here, as shown in FIG. 6, it is possible to enhance the strength of the structure on the side of the peripheral recess groove 213 of the substrate 210 by providing the dummy metal pattern 212 so as to extend to the position of the peripheral recess groove 213. In the present embodiment, the dummy metal pattern 212 and the signal finger 211 are formed on the same wiring layer of the substrate 210 as shown with a ridge in FIG. The wiring layer is formed on the lower surface 215 of the substrate 210, thereby suppressing warping of the side edge of the peripheral recess groove 213 of the substrate 210, further reducing the possibility of tearing of the substrate 210, and the peripheral recess groove 213 improves the heat stress resistance in the environment of the temperature cycle and makes it possible to avoid damage to the surface and side of the chip 220.

図３及び図５に示すように、基板２１０の上表面２１４にチップ配設領域２１４Ａを定義する。配設領域２１４Ａはチップ２２０の設置に利用されている。チップ２２０は一方の面に複数の中央ボンディングパッド２２１と周辺ボンディングパッド２２２とを有する。中央ボンディングパッド２２１は、チップ２２０の一方の面の中心線に単列や多列の方式で配列され、周辺ボンディングパッド２２２はチップ２２０の中央ボンディングパッド２２１と同じ面の両側周辺に配列され、中央ボンディングパッド２２１よりもその数が少ない。なお、周辺ボンディングパッド２２２は周縁凹み溝２１３の両端に位置を合わせ、中央ボンディングパッド２２１は中央スロット２１７に位置を合わせることにより、後の電気的な接続の作業に便利である。また、ダイアタッチング材、例えば、Ｂ‐ステージ（B-stage）印刷剤層或いはＰＩ（polyimide）付きテープなどを用いてチップ２２０の上述した一方の面を基板２１０の上表面２１１に貼付している。   As shown in FIGS. 3 and 5, a chip placement region 214 </ b> A is defined on the upper surface 214 of the substrate 210. The arrangement area 214 </ b> A is used for installing the chip 220. The chip 220 has a plurality of central bonding pads 221 and peripheral bonding pads 222 on one surface. The central bonding pads 221 are arranged in a single-row or multi-row manner on the center line of one surface of the chip 220, and the peripheral bonding pads 222 are arranged on both sides of the same surface as the central bonding pad 221 of the chip 220. The number is smaller than that of the bonding pads 221. The peripheral bonding pad 222 is aligned with both ends of the peripheral recess groove 213, and the central bonding pad 221 is aligned with the central slot 217, which is convenient for subsequent electrical connection work. Further, the above-described one surface of the chip 220 is attached to the upper surface 211 of the substrate 210 using a die attaching material, for example, a B-stage printing agent layer or a tape with PI (polyimide). .

図３に示すように、複数の電気接続素子２３０の大部分は、中央スロット２１７を通してチップ２２０の中央ボンディングパッド２２１と基板２１０の信号フィンガー２１１とをそれぞれ電気接続させるのに利用されるが、少なくとも２つの電気接続素子２３０は、周縁凹み溝２１３を通してチップ２２０の周辺ボンディングパッド２２２と、基板２１０の信号フィンガー２１１或いは図６に示す電源／接地フィンガー２１９とを電気的に接続している。本実施形態において、電気接続素子２３０はワイヤーボンディング方式で形成されるボンディングワイヤである。   As shown in FIG. 3, most of the plurality of electrical connection elements 230 are used to electrically connect the central bonding pads 221 of the chip 220 and the signal fingers 211 of the substrate 210 through the central slot 217, respectively. The two electrical connection elements 230 electrically connect the peripheral bonding pad 222 of the chip 220 and the signal finger 211 of the substrate 210 or the power / ground finger 219 shown in FIG. 6 through the peripheral recess groove 213. In the present embodiment, the electrical connection element 230 is a bonding wire formed by a wire bonding method.

封止体２４０は、チップ２２０と電気接続素子２３０とを密封し、かつ、周縁凹み溝２１３と中央スロット２１７とに充填されることによって、実装における適切な保護効果を提供して電気的な短絡現象とゴミによる汚染を防止することができる。一般に、封止体２４０としては、ＥＭＣ（epoxy molding compound）を用いる。
具体的には、図４に示すように、基板２１０は複数の外接パッド２１８、例えば円形のボール置きパッドのような構成を有し、外接パッド２１８は基板２１０の下表面２１５に設置されている。図３に示すように、半導体パッケージ２００は、さらに外接パッド２１８に設置される複数の外接端子２５０を有し、外接端子２５０は半導体パッケージ２００の外部との入力／出力用として図示しない外部ＰＣＢと接続することができる。外接端子２５０としては金属ボール、ペースト（paste）、接触パッド、接触ピンなどを採用することができ、本実施形態においては、図３に示すように、外接端子２５０は半田ボールである。 The sealing body 240 seals the chip 220 and the electrical connection element 230, and fills the peripheral recess groove 213 and the central slot 217, thereby providing an appropriate protective effect in mounting and electrical shorting. Phenomenon and contamination by garbage can be prevented. In general, EMC (epoxy molding compound) is used as the sealing body 240.
Specifically, as shown in FIG. 4, the substrate 210 has a configuration such as a plurality of circumscribed pads 218, for example, circular ball rest pads, and the circumscribed pads 218 are installed on the lower surface 215 of the substrate 210. . As shown in FIG. 3, the semiconductor package 200 further has a plurality of external terminals 250 installed on the external pads 218, and the external terminals 250 are connected to an external PCB (not shown) for input / output with the outside of the semiconductor package 200. Can be connected. As the external terminal 250, a metal ball, paste, contact pad, contact pin, or the like can be adopted. In this embodiment, the external terminal 250 is a solder ball as shown in FIG.

図３及び図４に示すように、基板２１０はさらにその隅に位置する複数のダミー孔２１６を有することが好ましく、封止体２４０はダミー孔２１６に充填されかつ基板２１０の下表面２１５に突状に出ていることにより、図４に示すように バンプ形成領域２４１に位置しかつ下表面２１５に突出している複数の支持バンプを形成している。具体的に言えば、ダミー孔２１６は周縁凹み溝２１３の両端方向に位置するので、周縁凹み溝２１３内にあるモールドの流れる速度を緩めることができ、そして、モールド封止剤の溢れ現象を改善することもできる。また、ダミー金属パターン２１２をダイシングする時の固定に便利になるため、基板半田マスク層を用いてダミー金属パターン２１２を被覆しているとき、外接端子２５０の設置のため外接パッド２１８の一部または全部を露出することができる。   As shown in FIGS. 3 and 4, the substrate 210 preferably further includes a plurality of dummy holes 216 located at the corners thereof, and the sealing body 240 is filled in the dummy holes 216 and protrudes from the lower surface 215 of the substrate 210. As shown in FIG. 4, a plurality of support bumps that are located in the bump formation region 241 and protrude from the lower surface 215 are formed. More specifically, since the dummy holes 216 are located at both ends of the peripheral recessed groove 213, the flow rate of the mold in the peripheral recessed groove 213 can be reduced, and the overflow phenomenon of the mold sealant is improved. You can also Further, in order to facilitate fixing when the dummy metal pattern 212 is diced, when the dummy metal pattern 212 is covered with a substrate solder mask layer, a part of the external pad 218 or All can be exposed.

図６は、本発明で半導体パッケージに用いる基板の周縁凹み溝を示す部分拡大図であり、本実施例においては、ダミー金属パターン２１２は基板２１０の下表面２１５に位置して少なくとも２つの補強側縁部２１２Ａを有し、この２つの補強側縁部２１２Ａは、周縁凹み溝２１３の開口方向２１３Ａとほぼ垂直になっている。ダミー金属パターン２１２は通常銅で製作され、他に従来の高硬度金属を利用することもできる。なお、ダミー金属パターン２１２は、接地や電源伝送用として周縁凹み溝２１３の一端に隣接する電源／接地フィンガー２１９と接続可能である。   FIG. 6 is a partially enlarged view showing a peripheral recess groove of a substrate used in a semiconductor package according to the present invention. In this embodiment, the dummy metal pattern 212 is located on the lower surface 215 of the substrate 210 and has at least two reinforcing sides. The two reinforcing side edges 212A are substantially perpendicular to the opening direction 213A of the peripheral recessed groove 213. The dummy metal pattern 212 is usually made of copper, and a conventional high-hardness metal can also be used. The dummy metal pattern 212 can be connected to a power / ground finger 219 adjacent to one end of the peripheral recess groove 213 for grounding or power transmission.

図３に示すように、本実施形態において、ダミー金属パターン２１２は細長形状となって２つの補強側縁部２１２Ａを提供し、かつダミー金属パターン２１２の幅は７５μｍまたはそれ以上の大きさとなることで有効な基板支持力を提供している。さらに、周縁凹み溝２１３は温度変化、例えば、基板の加熱硬化、封止体の固体化、後の熱循環作業などによる温度上昇環境での熱応力を受ける時、その支持力を向上させることができ、周縁凹み溝２１３の断裂及び基板２１０の反りといった現象が起きないように改善し、かつ周縁凹み溝２１３と対応するチップ２２０の表面や側辺の損傷を防ぐことが可能である。   As shown in FIG. 3, in this embodiment, the dummy metal pattern 212 has an elongated shape to provide two reinforcing side edges 212A, and the dummy metal pattern 212 has a width of 75 μm or more. Provides effective substrate support. Further, the peripheral recessed groove 213 can improve its supporting force when subjected to thermal stress in a temperature rising environment due to temperature change, for example, heat curing of the substrate, solidification of the sealing body, and subsequent heat circulation work. It is possible to improve the phenomenon such that the peripheral recess groove 213 is not broken and the substrate 210 is warped, and damage to the surface and the side of the chip 220 corresponding to the peripheral recess groove 213 can be prevented.

図７は、本発明の半導体パッケージが用いる基板の周縁凹み溝を形成する前の状態を示す部分拡大図である。周縁凹み溝２１３が形成される前に、ダミー金属パターン２１２は、基板２１０の周縁凹み溝２１３の所定領域まで延びて被覆し、ルーティング（routing）或いはパンチング（punching）の技術を用いて周縁凹み溝２１３を形成し、ここで、図７に示す上方のダミー金属パターン２１２は周縁凹み溝２１３と一致している。周縁凹み溝２１３は閉鎖スロットにすることが好ましく、それにより、周縁凹み溝２１３の両側と一致するダミー金属パターン２１２が設置されることで、基板が製造される時に周縁凹み溝２１３も効率よく形成することができ、中央スロット２１７と同一ステップで形成することができるので、基板に開口を作るためのコストを低減する効果がある。   FIG. 7 is a partially enlarged view showing a state before the peripheral recess groove of the substrate used by the semiconductor package of the present invention is formed. Before the peripheral recess groove 213 is formed, the dummy metal pattern 212 extends to and covers a predetermined region of the peripheral recess groove 213 of the substrate 210, and the peripheral recess groove is formed by using a routing or punching technique. The upper dummy metal pattern 212 shown in FIG. 7 is coincident with the peripheral recess groove 213. The peripheral recess groove 213 is preferably a closed slot, whereby dummy metal patterns 212 that coincide with both sides of the peripheral recess groove 213 are provided, so that the peripheral recess groove 213 is efficiently formed when the substrate is manufactured. Since it can be formed in the same step as the central slot 217, there is an effect of reducing the cost for making an opening in the substrate.

（第２実施形態）
本発明の第２実施形態において、第１実施形態と基本的な構成および効果において実質的に同等であり、第一実施形態の構成に代えて下記の構成を有する半導体パッケージを示す。本実施例の半導体パッケージは、基板、チップ、複数の電気接続素子及び封止体を備える。図９は本実施例の半導体パッケージに用いる基板の周縁凹み溝を示す部分拡大図である。基板３１０は複数の信号フィンガー３１１、ダミー金属パターン３１２及び基板３１０を通る少なくとも一つの周縁凹み溝３１３を有する。周縁凹み溝３１３は、基板３１０の一側縁部に隣接しかつチップの周辺ボンディングパッドを露出させる複数の周辺小ウインドーと周辺小ウインドーに連通するダミー溝を有する。ダミー金属パターン３１２は周縁凹み溝３１３の位置まで延び、かつ信号フィンガー３１１と電気的に絶縁している。他の構成は第１実施形態の対応する構成と同様であるので説明を省略する。図９に示すように、本実施形態において、ダミー金属パターン３１２は基板３１０の上表面３１４に設けることができ、くしのように配列される複数の支持フィンガー３１２Ｂを有し、それにより、少なくとも四つ或いはより数多くの補強側縁部３１２Ａを提供してダミー金属パターン３１２の耐反り強度を増強させる。なお、補強側縁部３１２Ａは周縁凹み溝３１３の開口方向３１３Ａとほぼ垂直になるので、熱応力をより有効に抑えて周縁凹み溝３１３の断裂及び基板３１０の反りという現象が起きないように改善している。さらに、周縁凹み溝３１３に位置するチップ３２０の表面や側辺の損傷を防止可能である。本実施形態において、ダミー金属パターン３１２は、信号フィンガー３１１或いは電源／接地フィンガー３１９と接続し、信号フィンガー３１１或いは電源／接地フィンガー３１９はボンディングワイヤと接続するため周縁凹み溝３１３の一端に隣接している。 (Second Embodiment)
In the second embodiment of the present invention, a semiconductor package that is substantially the same in basic configuration and effect as the first embodiment and has the following configuration instead of the configuration of the first embodiment is shown. The semiconductor package of this embodiment includes a substrate, a chip, a plurality of electrical connection elements, and a sealing body. FIG. 9 is a partially enlarged view showing the peripheral recess groove of the substrate used in the semiconductor package of this embodiment. The substrate 310 includes a plurality of signal fingers 311, a dummy metal pattern 312, and at least one peripheral recess groove 313 that passes through the substrate 310. The peripheral recessed groove 313 has a plurality of peripheral small windows adjacent to one side edge of the substrate 310 and exposing the peripheral bonding pads of the chip, and dummy grooves communicating with the peripheral small windows. The dummy metal pattern 312 extends to the position of the peripheral recess groove 313 and is electrically insulated from the signal finger 311. Other configurations are the same as the corresponding configurations of the first embodiment, and thus the description thereof is omitted. As shown in FIG. 9, in this embodiment, the dummy metal pattern 312 can be provided on the upper surface 314 of the substrate 310, and has a plurality of support fingers 312B arranged like combs, whereby at least four One or more reinforcing side edges 312A are provided to increase the warp resistance of the dummy metal pattern 312. Since the reinforcing side edge 312A is substantially perpendicular to the opening direction 313A of the peripheral recessed groove 313, the thermal stress is more effectively suppressed so that the phenomenon of the peripheral recessed groove 313 tearing and the substrate 310 warping does not occur. is doing. Further, it is possible to prevent damage to the surface or side of the chip 320 located in the peripheral recess groove 313. In this embodiment, the dummy metal pattern 312 is connected to the signal finger 311 or the power / ground finger 319, and the signal finger 311 or the power / ground finger 319 is adjacent to one end of the peripheral recess groove 313 to connect to the bonding wire. Yes.

図１０は本実施例の半導体パッケージに用いる基板の周縁凹み溝を形成する前の状態を示す部分拡大図である。ダミー金属パターン３１２にくしのように配列されている複数の支持フィンガー３１２Ｂは、ダイシングする前に周縁凹み溝３１３の所定の領域まで延びて被覆している。そして、ルーティング（routing）或いはパンチング（punching）の技術を用いて周縁凹み溝３１３を形成すると同時にダミー金属パターン３１２を周縁凹み溝３１３の位置まで延ばせることにより、支持フィンガー３１２Ｂがより容易に形成されて製造上では利便性がある。
以上、本発明をその好適な実施形態に基づいて説明したが、本発明の保護範囲は特許請求の範囲で限定されて、この保護範囲に基づいて、本発明の精神と範囲内における変更や修正を行うことは本発明の保護範囲に属する。 FIG. 10 is a partially enlarged view showing a state before the peripheral recess groove of the substrate used in the semiconductor package of this embodiment is formed. The plurality of support fingers 312B arranged like combs on the dummy metal pattern 312 extends to a predetermined region of the peripheral recess groove 313 and covers it before dicing. Then, the support finger 312B is more easily formed by forming the peripheral recess groove 313 by using a routing or punching technique and simultaneously extending the dummy metal pattern 312 to the position of the peripheral recess groove 313. There is convenience in manufacturing.
Although the present invention has been described based on the preferred embodiments thereof, the protection scope of the present invention is limited by the scope of the claims, and changes and modifications within the spirit and scope of the present invention based on the protection scope. It is within the protection scope of the present invention.

従来のＢＧＡパッケージを示す断面図である。It is sectional drawing which shows the conventional BGA package. 従来のＢＧＡパッケージが用いる基板の表面を示す平面図である。It is a top view which shows the surface of the board | substrate which a conventional BGA package uses. 本発明の第１実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by 1st Embodiment of this invention. 本発明の第１実施形態による半導体パッケージが用いる基板の図３下側の表面を示す平面図である。It is a top view which shows the surface of FIG. 3 lower side of the board | substrate which the semiconductor package by 1st Embodiment of this invention uses. 本発明の第１実施形態による半導体パッケージが用いる基板の図４上側の表面を示す平面図である。FIG. 5 is a plan view showing the upper surface of FIG. 4 of the substrate used by the semiconductor package according to the first embodiment of the present invention. 本発明の第１実施形態による半導体パッケージが用いる基板の周縁凹み溝を示す部分拡大図である。It is the elements on larger scale which show the peripheral recess groove | channel of the board | substrate which the semiconductor package by 1st Embodiment of this invention uses. 本発明の第１実施形態による半導体パッケージが用いる基板の周縁凹み溝が形成される前の状態を示す部分拡大図である。It is the elements on larger scale which show the state before the peripheral recess groove | channel of the board | substrate which the semiconductor package by 1st Embodiment of this invention uses is formed. 本発明の第１実施形態による半導体パッケージが用いる基板のダイアタッチング後の周縁凹み溝を示す部分拡大図である。It is the elements on larger scale which show the peripheral recessed groove after die-attaching of the board | substrate which the semiconductor package by 1st Embodiment of this invention uses. 本発明の第２実施形態による半導体パッケージが用いる基板の周縁凹み溝を示す部分拡大図である。It is the elements on larger scale which show the peripheral recess groove | channel of the board | substrate which the semiconductor package by 2nd Embodiment of this invention uses. 本発明の第２実施形態による半導体パッケージが用いる基板の周縁凹み溝が形成される前の状態を示す部分拡大図である。It is the elements on larger scale which show the state before the peripheral recess groove | channel of the board | substrate which the semiconductor package by 2nd Embodiment of this invention uses is formed.

符号の説明Explanation of symbols

２００：半導体パッケージ、２１０：基板、２１１：信号フィンガー、２１２：ダミー金属パターン、２１２Ａ：補強側縁部、２１３：周縁凹み溝、２１３Ａ：開口方向、２１４：上表面、２１４Ａ：チップ配設領域、２１５：下表面、２１６：ダミー孔、２１７：中央スロット、２１８：外接パッド、２１９：電源／接地フィンガー、２２０：チップ、２２１：中央ボンディングパッド、２２２：周辺ボンディングパッド、２３０：電気接続素子、２４０：封止体、２４１：バンプ形成領域、２５０：外接端子、３１０：基板、３１１：信号フィンガー、３１４：上表面、３１９：電源／接地フィンガー、３１２：ダミー金属パターン、３１２Ａ：補強側縁部、３１２Ｂ：支持フィンガー、３１３：周縁凹み溝、３１３Ａ：開口方向   200: Semiconductor package, 210: Substrate, 211: Signal finger, 212: Dummy metal pattern, 212A: Reinforcement side edge, 213: Peripheral recessed groove, 213A: Opening direction, 214: Upper surface, 214A: Chip placement region, 215: lower surface, 216: dummy hole, 217: center slot, 218: circumscribing pad, 219: power / ground finger, 220: chip, 221: center bonding pad, 222: peripheral bonding pad, 230: electrical connection element, 240 : Sealing body, 241: bump formation region, 250: external terminal, 310: substrate, 311: signal finger, 314: upper surface, 319: power / ground finger, 312: dummy metal pattern, 312A: reinforcement side edge, 312B: support finger, 313: peripheral recess groove, 313A: opening direction

Claims (19)

複数の信号フィンガー、ダミー金属パターン及び少なくとも一つの周縁凹み溝を有する基板であって、前記ダミー金属パターンは前記周縁凹み溝の位置まで延び、かつ前記信号フィンガーと電気的に絶縁している基板と、
前記基板の上に設置され、かつ複数のボンディングパッドを有するチップと、
前記チップの前記複数のボンディングパッドと前記基板の前記複数の信号フィンガーとをそれぞれ電気的に接続している複数の電気接続素子と、
前記複数の電気接続素子を密封し、かつ前記周縁凹み溝に充填されている封止体と、
を備えることを特徴とする半導体パッケージ。 A substrate having a plurality of signal fingers, a dummy metal pattern and at least one peripheral recess groove, wherein the dummy metal pattern extends to the position of the peripheral recess groove and is electrically insulated from the signal finger; ,
A chip installed on the substrate and having a plurality of bonding pads;
A plurality of electrical connection elements respectively electrically connecting the plurality of bonding pads of the chip and the plurality of signal fingers of the substrate;
A sealing body that seals the plurality of electrical connection elements and is filled in the peripheral recess groove;
A semiconductor package comprising: 前記電気接続素子は、そのうちの少なくとも２つが前記周縁凹み溝を通過していることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein at least two of the electrical connection elements pass through the peripheral recess groove. 前記ダミー金属パターンは少なくとも２つの補強側縁部を有し、前記補強側縁部は前記周縁凹み溝の開口方向とほぼ垂直になっていることを特徴とする請求項１に記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein the dummy metal pattern has at least two reinforcing side edges, and the reinforcing side edges are substantially perpendicular to the opening direction of the peripheral recess groove. 前記ダミー金属パターンは、２つの前記補強側縁部を提供するために細長形状であることを特徴とする請求項３に記載の半導体パッケージ。   The semiconductor package according to claim 3, wherein the dummy metal pattern has an elongated shape to provide two reinforcing side edges. 前記ダミー金属パターンは、くし状に配列される複数の支持フィンガーを有することを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the dummy metal pattern has a plurality of support fingers arranged in a comb shape. 前記ダミー金属パターンと前記複数の信号フィンガーとは、前記基板の同一配線層に形成されていることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the dummy metal pattern and the plurality of signal fingers are formed in the same wiring layer of the substrate. 前記周縁凹み溝は閉鎖スロットとなっていることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the peripheral recess groove is a closed slot. 前記基板は、さらに前記基板の隅に位置する複数のダミー孔を有し、前記封止体は前記複数のダミー孔に充填され、かつ前記基板の下表面に突起状に出ていることにより、複数の支持バンプを形成していることを特徴とする請求項１に記載の半導体パッケージ。   The substrate further includes a plurality of dummy holes located at corners of the substrate, the sealing body is filled in the plurality of dummy holes, and protrudes in a protruding shape on the lower surface of the substrate, The semiconductor package according to claim 1, wherein a plurality of support bumps are formed. 前記ダミー金属パターンは基板半田マスク層に被覆されていることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the dummy metal pattern is covered with a substrate solder mask layer. 前記ダミー金属パターンはフィンガーと接続し、前記フィンガーは前記周縁凹み溝の一端に隣接していることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the dummy metal pattern is connected to a finger, and the finger is adjacent to one end of the peripheral recess groove. 複数の信号フィンガーと、
ダミー金属パターンと、
少なくとも一つの周縁凹み溝と、
を有し、
前記ダミー金属パターンは前記周縁凹み溝処まで延び、かつ前記信号フィンガーと電気的に絶縁していることを特徴とする半導体パッケージに用いる基板。 Multiple signal fingers;
With a dummy metal pattern,
At least one peripheral recessed groove;
Have
The substrate used for a semiconductor package, wherein the dummy metal pattern extends to the peripheral recess groove and is electrically insulated from the signal finger. 前記ダミー金属パターンは少なくとも２つの補強側縁部を有し、前記補強側縁部は前記周縁凹み溝の開口方向とほぼ垂直になっていることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   12. The semiconductor package according to claim 11, wherein the dummy metal pattern has at least two reinforcing side edges, and the reinforcing side edges are substantially perpendicular to an opening direction of the peripheral recess groove. Substrate used. 前記ダミー金属パターンは２つの前記補強側縁部を提供するために細長形状であることを特徴とする請求項１２に記載の半導体パッケージに用いる基板。   13. The substrate for use in a semiconductor package according to claim 12, wherein the dummy metal pattern has an elongated shape to provide the two reinforcing side edges. 前記ダミー金属パターンはくし状に配列される複数の支持フィンガーを有することを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the dummy metal pattern has a plurality of support fingers arranged in a comb shape. 前記ダミー金属パターンと前記複数の信号フィンガーとは、前記基板において同一の配線層に形成されていることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the dummy metal pattern and the plurality of signal fingers are formed in the same wiring layer in the substrate. 前記周縁凹み溝は閉鎖スロットとなっていることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the peripheral recess groove is a closed slot. 前記基板はさらに前記基板の隅に位置する複数のダミー孔を有し、前記ダミー孔には封止体が充填されていることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the substrate further includes a plurality of dummy holes located at corners of the substrate, and the dummy holes are filled with a sealing body. 前記ダミー金属パターンは、基板半田マスク層に被覆されていることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the dummy metal pattern is covered with a substrate solder mask layer. 前記ダミー金属パターンはフィンガーと接続し、前記フィンガーは前記周縁凹み溝の一端に隣接していることを特徴とする請求項１１に記載の半導体パッケージに用いる基板。   The substrate used for a semiconductor package according to claim 11, wherein the dummy metal pattern is connected to a finger, and the finger is adjacent to one end of the peripheral recess groove.
JP2008039711A 2008-02-21 2008-02-21 Semiconductor package and substrate used for the same Pending JP2009200210A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231859A (en) * 2000-11-30 2002-08-16 Toshiba Corp Semiconductor device and manufacturing method of the semiconductor device
JP2003086736A (en) * 2001-09-10 2003-03-20 Shinko Electric Ind Co Ltd Semiconductor device and substrate therefor
JP2005294569A (en) * 2004-03-31 2005-10-20 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231859A (en) * 2000-11-30 2002-08-16 Toshiba Corp Semiconductor device and manufacturing method of the semiconductor device
JP2003086736A (en) * 2001-09-10 2003-03-20 Shinko Electric Ind Co Ltd Semiconductor device and substrate therefor
JP2005294569A (en) * 2004-03-31 2005-10-20 Toshiba Corp Semiconductor device

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