JP2009200165A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2009200165A
JP2009200165A JP2008039049A JP2008039049A JP2009200165A JP 2009200165 A JP2009200165 A JP 2009200165A JP 2008039049 A JP2008039049 A JP 2008039049A JP 2008039049 A JP2008039049 A JP 2008039049A JP 2009200165 A JP2009200165 A JP 2009200165A
Authority
JP
Japan
Prior art keywords
diffusion layer
pattern
sub
con
contact diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2008039049A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009200165A5 (https=
Inventor
Hiroyuki Uno
裕之 夘野
Yasuaki Kobayashi
靖明 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2008039049A priority Critical patent/JP2009200165A/ja
Priority to US12/379,288 priority patent/US20090206451A1/en
Publication of JP2009200165A publication Critical patent/JP2009200165A/ja
Publication of JP2009200165A5 publication Critical patent/JP2009200165A5/ja
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2008039049A 2008-02-20 2008-02-20 半導体装置 Abandoned JP2009200165A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008039049A JP2009200165A (ja) 2008-02-20 2008-02-20 半導体装置
US12/379,288 US20090206451A1 (en) 2008-02-20 2009-02-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008039049A JP2009200165A (ja) 2008-02-20 2008-02-20 半導体装置

Publications (2)

Publication Number Publication Date
JP2009200165A true JP2009200165A (ja) 2009-09-03
JP2009200165A5 JP2009200165A5 (https=) 2011-01-20

Family

ID=40954328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008039049A Abandoned JP2009200165A (ja) 2008-02-20 2008-02-20 半導体装置

Country Status (2)

Country Link
US (1) US20090206451A1 (https=)
JP (1) JP2009200165A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5667893B2 (ja) * 2011-01-20 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102403735B1 (ko) 2017-09-07 2022-05-30 삼성전자주식회사 비대칭적인 엔딩 셀들을 포함하는 집적 회로 및 시스템 온 칩

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0179898B1 (ko) * 1996-02-28 1999-04-15 문정환 반도체소자의 바디-콘택 구조
US5946564A (en) * 1997-08-04 1999-08-31 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法

Also Published As

Publication number Publication date
US20090206451A1 (en) 2009-08-20

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