JP2009199482A - Band-gap reference circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a band-gap reference circuit capable of obtaining highly accurate reference voltage with little variation in a reference voltage value even though an error occurs in the channel length or channel width of a MOS transistor constituting a current mirror circuit while using a comparatively simple circuit configuration. <P>SOLUTION: The circuit comprises: a plurality of first semiconductor elements having PN junctions with power potential V<SB>SS</SB>connected to an N type semiconductor; a plurality of first P channel MOS transistors for feeding currents to P type semiconductors of the plurality of first semiconductor elements respectively through a plurality of first N channel MOS transistors; a second semiconductor element having PN junctions, the number of parallel connections or size of which is different from the first semiconductor elements with the power potential V<SB>SS</SB>connected to the N type semiconductor; and a second P channel MOS transistor for feeding current to P type semiconductors of the second semiconductor elements through an impedance element and the second N channel MOS transistor and constituting a current mirror circuit together with the plurality of first P channel MOS transistors. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bandgap reference circuit that generates a reference voltage and a reference current using a bandgap of a semiconductor element such as a diode or a transistor.

  Conventionally, a band gap reference circuit has been used to generate a reference voltage or a reference current that is a reference for operation in various circuits. According to the bandgap reference circuit, a highly accurate and stable reference voltage or reference current can be obtained even if the temperature, the power supply voltage, or the like fluctuates. The basic configuration and operation of the bandgap reference circuit are described in Non-Patent Document 1, for example.

FIG. 5 is an example of a circuit diagram showing a configuration of a conventional bandgap reference circuit. This band gap reference circuit includes diodes D1 to D3 having PN junctions, P channel MOS transistors QP1 to QP3, N channel MOS transistors QN1 and QN2, and resistors R2 and R3, and has a first power supply potential. V _DD and a second power supply voltage _{V SS} is operated is supplied.

  In FIG. 5, for each of the P channel MOS transistor and the N channel MOS transistor, the transistors QP1 to QP3 and QN1 to QN2 having the same channel length and channel width form a current mirror circuit. The magnitudes of the flowing currents are ideally equal to each other. Further, since the number or area of parallel connections of PN junctions in the diode D2 is K times the number or area of parallel connections of PN junctions in the diode D1, the magnitudes of currents flowing through the diodes D1 and D2 are equal to each other. Are set so that their current densities are different from each other.

Here, if the saturation current of the diode D1 and _{I S,} the saturation current of the diode D2 becomes K · _{I S.} If the currents flowing through the transistors QP1 to QP3 are I, the voltages across the diodes _{D1 to D3} are V _{D1 to} V _D3 , and the resistances R2 and R3 are R ₂ and R ₃ , respectively, To establish. Note that k is a Boltzmann constant, T is an absolute temperature, and q is an electron charge.
V _D1 = (kT / q) ln (I / I _S ) (1)
V _D2 = (kT / q) ln (I / (K · I _S )) (2)
V _D1 = I · R ₂ + V _D2 (3)

By transforming equation (3) and substituting equation (1) and equation (2), the following equation (4) is obtained.
I = (V _D1 −V _D2 ) / R ₂ = (kT / qR ₂ ) ln (K) (4)
Therefore, the reference voltage V _REF output from the drain of the transistor QP3 is expressed by the following equation (5).
V _REF = I · R ₃ + V _D3
= (R ₃ / R ₂ ) (kT / q) ln (K) + V _D3 (5)

In order to cancel the temperature dependency of the reference voltage V _REF , the value obtained by differentiating the equation (5) with the absolute temperature T may be zero.
dV _REF / dT = (R ₃ / R ₂ ) (k / q) ln (K) + dV _D3 / dT = 0
... (6)
In the equation (6), dV _D3 / dT has a negative temperature characteristic. Therefore, if the value of (R ₃ / R ₂ ) (k / q) ln (K) is a positive value commensurate with this, It is possible to cancel the temperature dependence of the reference voltage _VREF .

However, when the channel lengths or channel widths of the transistors QP1 to QP3 and QN1 to QN2 constituting the current mirror circuit vary, an error occurs in the current or voltage of those transistors, and the reference voltage V _REF As a result, the reference voltage with high accuracy cannot be obtained.
Kenji Taniguchi, “Introduction to CMOS Analog Circuits” 3rd edition, CQ Publishing Co., Ltd., September 1, 2005, p. 120

  Therefore, in view of the above points, the present invention is a highly accurate circuit that uses a relatively simple circuit configuration and has little variation in the reference voltage even if an error occurs in the channel length or channel width of the transistors constituting the current mirror circuit. An object of the present invention is to provide a bandgap reference circuit capable of obtaining a reference voltage.

In order to solve the above problems, a bandgap reference circuit according to a first aspect of the present invention includes a plurality of first semiconductor elements having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor, Gates and drains connected to each other, and a plurality of first N-channel MOS transistors each having a source connected to a P-type semiconductor of the plurality of first semiconductor elements, and gates of the plurality of first N-channel MOS transistors, A plurality of first P-channel MOS transistors each having a drain connected to the drain and supplying a current to the plurality of first semiconductor elements via the plurality of first N-channel MOS transistors; Includes a PN junction having a different number or size of parallel connection, a second semiconductor element in which a power supply potential _VSS is connected to an N-type semiconductor, and a second semiconductor. An impedance element having a first terminal connected to the P-type semiconductor of the body element, a gate connected to the gates and drains of the plurality of first N-channel MOS transistors, and a source connected to the second terminal of the impedance element The gates and drains of the second N-channel MOS transistors and the gates of the plurality of first P-channel MOS transistors are connected to the drains of the second N-channel MOS transistors. And a second P-channel MOS transistor for supplying a current to the second semiconductor element through the channel MOS transistor and the impedance element.

  The band gap reference circuit according to the first aspect of the present invention forms a current mirror circuit with a plurality of first P-channel MOS transistors and second P-channel MOS transistors, and supplies a current from the drain. A channel MOS transistor, a second impedance element that generates a reference potential, and a third semiconductor element having a PN junction may be further provided, connected to the drain of the third P-channel MOS transistor.

The band gap reference circuit according to the second aspect of the present invention includes a first semiconductor element having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor, and a gate and a drain connected to each other. A first N-channel MOS transistor having a source connected to the P-type semiconductor of the first semiconductor element, and a drain connected to the gate and drain of the first N-channel MOS transistor, The first P-channel MOS transistor for supplying current to the first semiconductor element via the first semiconductor element and the first semiconductor element each have a PN junction having a different number or size of parallel connection, and the N-type semiconductor has a power supply potential V A plurality of second semiconductor elements to which _SS is connected and a plurality of impedance elements each having a first terminal connected to a P-type semiconductor of the plurality of second semiconductor elements. A plurality of second N-channel MOS transistors having gates connected to the gates and drains of the first N-channel MOS transistors and sources connected to second terminals of the plurality of impedance elements; A gate and a drain are connected to the gate of each of the P-channel MOS transistors, a gate and a drain are respectively connected to the drains of the plurality of second N-channel MOS transistors, and the plurality of second N-channel MOS transistors and the plurality of impedance elements And a plurality of second P-channel MOS transistors for supplying currents to the plurality of second semiconductor elements through the first and second semiconductor elements, respectively.

  The band gap reference circuit according to the second aspect of the present invention forms a current mirror circuit with the first P-channel MOS transistor and the plurality of second P-channel MOS transistors, and supplies a third P from the drain. A channel MOS transistor, a second impedance element that generates a reference potential, and a third semiconductor element having a PN junction may be further provided, connected to the drain of the third P-channel MOS transistor.

Furthermore, the band gap reference circuit according to the third aspect of the present invention includes a plurality of first semiconductor elements each having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor, and a gate and a drain connected to each other. The drains are connected to the gates and drains of the plurality of first N-channel MOS transistors that are connected and the sources are respectively connected to the P-type semiconductors of the plurality of first semiconductor elements. The plurality of first P-channel MOS transistors that supply currents to the plurality of first semiconductor elements through the plurality of first N-channel MOS transistors, respectively, and the first semiconductor elements are connected in number or size in parallel. A plurality of second semiconductor elements each having a different PN junction and having a power supply potential _VSS connected to an N-type semiconductor, and a plurality of second semiconductor elements A plurality of impedance elements each having a first terminal connected to the P-type semiconductor of the body element; and a second terminal of the plurality of impedance elements having a gate connected to the gates and drains of the plurality of first N-channel MOS transistors. The gates and drains are respectively connected to the gates of the plurality of second N-channel MOS transistors whose sources are respectively connected to the gates and the plurality of first P-channel MOS transistors, and are connected to the drains of the plurality of second N-channel MOS transistors. A plurality of second N-channel MOS transistors each having a gate and a drain connected thereto, and a plurality of second P-channel MOS transistors that respectively supply current to the plurality of second semiconductor elements via the plurality of impedance elements. To do.

  A bandgap reference circuit according to a third aspect of the present invention includes a plurality of first P-channel MOS transistors and a plurality of second P-channel MOS transistors and a current mirror circuit, and supplies a current from a drain. And a third impedance element connected to the drain of the third P-channel MOS transistor for generating a reference potential and a third semiconductor element having a PN junction. .

  According to the present invention, a relatively simple circuit is provided by providing a plurality of current paths each including a plurality of first semiconductor elements and / or a plurality of current paths including a plurality of second semiconductor elements. While using the configuration, even if an error occurs in the channel length or channel width of the transistors forming the current mirror circuit, the error given to the reference voltage value can be reduced.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a circuit diagram showing a configuration of a bandgap reference circuit according to the first embodiment of the present invention. The band gap reference circuit, the first power supply potential V _DD and a second power supply voltage V _SS is operated is supplied. In general, the difference between the first power supply potential _{V DD} and a second power supply voltage _{V SS (V} DD _{-V SS)} is the power supply voltage, a second power supply voltage _{V SS} is at ground potential (0V) In this case, V _DD is the power supply voltage.

  In the first embodiment of the present invention, M current paths including a semiconductor element corresponding to the diode D1 shown in FIG. 5 are provided. Here, M is an integer of 2 or more. 1 shows current paths A1, A2, A3,... Each including diodes D11, D12, D13,... As semiconductor elements having PN junctions. As a semiconductor element having a PN junction, a bipolar transistor or a junction FET (field effect transistor) can be used in addition to a diode.

Here, since the number or area of parallel connections of PN junctions in the diode D2 is K times the number or area of parallel connections of PN junctions in the diode D11 or the like, the magnitudes of currents flowing through the diodes D11 and D2 are mutually different. Even if they are equal, their current densities are set to be different from each other. In equation (6) described above, dV _D3 / dT has a negative temperature characteristic of about −1.5 mV / ° C., and d / dT · (kT / q) is a positive value of about 0.087 mV / ° C. Therefore, the value of (R ₃ / R ₂ ) ln (K) is set to about 17 to 23, for example, with R ₃ : R ₂ = 10: 1 and K = 6. it can.

  In current path A1, P channel MOS transistor QP11, N channel MOS transistor QN11, and diode D11 are connected in series. In current path A2, P channel MOS transistor QP12, N channel MOS transistor QN12, The diode D12 is connected in series. In the current path A3, the P-channel MOS transistor QP13, the N-channel MOS transistor QN13, and the diode D13 are connected in series.

On the other hand, in current path B, P-channel MOS transistor QP2, N-channel MOS transistor QN2, resistor R2 as an impedance element, and diode D2 are connected in series, and in current path C, P-channel MOS transistor A transistor QP3, a resistor R3 as an impedance element, and a diode D3 are connected in series. The reference voltage _VREF is output from the drain of the transistor QP3. As the impedance element, in addition to the resistor, a transistor in which a gate and a drain are connected to each other can be used.

  In FIG. 1, the gates of transistors QP11, QP12,... Having the same channel length and channel width, the gate and drain of transistor QP2, and the gate of transistor QP3 are connected to each other. Further, the gates and drains of the transistors QN11, QN12,... Having the same channel length and channel width and the gate of the transistor QN2 are connected to each other. As a result, the transistors QP11, QP12,..., QP2, QP3 and the transistors QN11, QN12,..., QN2 form a current mirror circuit. It should be equal to each other.

However, in reality, since the channel length or channel width of the transistors varies, an error occurs in the current or voltage of the transistors, and the value of the reference voltage V _REF varies, resulting in a highly accurate reference voltage. I can't get it. Therefore, in the first embodiment of the present invention, by connecting the current paths A2, A3,... In parallel with the current path A1, the influence of the current or voltage error in the M current paths A is averaged. Thus, the variation in the value of the reference voltage V _REF is reduced, so that a highly accurate reference voltage can be obtained.

FIG. 2 is a circuit diagram showing a configuration of a bandgap reference circuit used for confirming the effect of the present invention by simulation. In this bandgap reference circuit, PNP bipolar transistors Q11 to Q13 and Q2 are used in place of the diodes D11 to D13 and D2 shown in FIG. 1, and the current output from the drain of the transistor QP3 is measured voltage V. _In order to convert to _M , the gate and drain of the N-channel MOS transistor QN3 are connected to the drain of the transistor QP3 instead of the resistor R3 and the diode D3 shown in FIG. Here, the measurement voltage V _M when the predetermined current path of the current path A1~A3 including transistors Q11~Q13 respectively are connected, is calculated using a general-purpose simulation program. An NPN bipolar transistor may be used instead of the PNP bipolar transistor.

FIG. 3 is a diagram showing the result of simulation for confirming the effect of the present invention. 3, curve (1a) ~ (3a), the channel length of the transistor represents the measured voltage _{V M} of the case where as the design value (6 [mu] m). Curve (1a) represents the measured voltage V _M when only current path A1 is connected, the curve (2a) represents the measured voltage V _M when the current path A1 and A2 are connected and the curve (3a) represents the measured voltage _{V M} when the current path A1~A3 is connected. As shown in FIG. 3, the results are the same.

3, the curve (1b) ~ (3b) shows the measured voltage _{V M} when the channel length of the transistor QN11 shown in FIG. 2 becomes 5μm deviates from 6μm a design value. Curve (1b) represents the measured voltage V _M when only current path A1 is connected, the curve (2b) represents the measured voltage V _M when the current path A1 and A2 are connected and the curve (3b) represents the measured voltage _{V M} when the current path A1~A3 is connected.

  As shown in FIG. 3, it can be seen that the error in the current output from the transistor QP3 decreases as the number (M) of the current paths A increases. Specifically, when M = 2, the error is about ½, and when M = 3, the error is about ３. Therefore, the larger the value of M, the better. However, in order to reduce the error to about 1/10 or less, it is desirable that M ≧ 10.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing a configuration of a bandgap reference circuit according to the second embodiment of the present invention. In the second embodiment of the present invention, N current paths including a semiconductor element corresponding to the diode D2 shown in FIG. 5 are provided. Here, N is an integer of 2 or more. 4 shows current paths B1, B2, B3,... Each including diodes D21, D22, D23,... As semiconductor elements having PN junctions. As a semiconductor element having a PN junction, a bipolar transistor or a junction FET (field effect transistor) can be used in addition to a diode.

Here, since the number or area of parallel connections of PN junctions in the diode D21 or the like is K times the number or area of parallel connections of PN junctions in the diode D1, the magnitudes of currents flowing through the diodes D1 and D21 are mutually different. Even if they are equal, their current densities are set to be different from each other. In equation (6) described above, dV _D3 / dT has a negative temperature characteristic of about −1.5 mV / ° C., and d / dT · (kT / q) is a positive value of about 0.087 mV / ° C. Therefore, the value of (R ₃ / R ₂ ) ln (K) is set to about 17 to 23, for example, R ₃ : R ₂ = 10: 1 and K = 6. it can.

  In current path A, P-channel MOS transistor QP1, N-channel MOS transistor QN1, and diode D1 are connected in series. On the other hand, in current path B1, P channel MOS transistor QP21, N channel MOS transistor QN21, resistor R21 as an impedance element, and diode D21 are connected in series, and in current path B2, P channel MOS transistor A transistor QP22, an N channel MOS transistor QN22, a resistor R22 as an impedance element, and a diode D22 are connected in series. In the current path B3, a P channel MOS transistor QP23, an N channel MOS transistor QN23, A resistor R23 as an impedance element and a diode D23 are connected in series.

In the current path C, a P-channel MOS transistor QP3, a resistor R3 as an impedance element, and a diode D3 are connected in series. The reference voltage _VREF is output from the drain of the transistor QP3. Note that, as the impedance element, a transistor in which a gate and a drain are connected to each other can be used instead of a resistor.

  4, the gate of the transistor QP1 having the same channel length or channel width, the gates and drains of the transistors QP21, QP22,... And the gate of the transistor QP3 are connected to each other. Further, the gate and drain of the transistor QN1 having the same channel length or channel width and the gates of the transistors QN21, QN22,... Are connected to each other. As a result, the transistors QP1, QP21, QP22,..., QP3 and the transistors QN1, QN21, QN22,... Constitute a current mirror circuit. It should be equal to each other.

However, in actuality, variations occur in the channel length or channel width of the transistors, and an error occurs in the current or voltage of those transistors, making it impossible to obtain the expected value of the reference voltage _VREF . Therefore, in the second embodiment of the present invention, by connecting the current paths B2, B3,... In parallel with the current path B1, the influence of current or voltage errors in the N current paths B is averaged. In order to obtain the expected value of the reference voltage V _REF .

  As the number (N) of current paths B increases, the error in the current output from the transistor QP3 decreases. Specifically, the error is about ½ when N = 2, and the error is about ３ when N = 3. Therefore, the larger the value of N, the better. However, in order to reduce the error to about 1/10 or less, it is desirable that N ≧ 10.

  Further, M current paths A and N current paths B may be provided by combining the first embodiment and the second embodiment of the present invention. In that case, the influence of variations in channel length or channel width of the transistor can be further reduced.

  By the way, in a semiconductor integrated circuit such as an ASIC (Application Specific IC), a plurality of cells for realizing various logic circuits are combined and arranged in a layout region, and the cells are wired. Thus, the layout design is performed. Among various types of cells, the number of I / O cells (input / output cells) is large. Therefore, in the library used for layout design, the current paths A2, A3,. If the current paths B2, B3,... Are previously incorporated in the I / O cell, the band gap reference circuit according to the present invention can be easily realized.

1 is a circuit diagram of a bandgap reference circuit according to a first embodiment of the present invention. The circuit diagram of the band gap reference circuit for confirming the effect of this invention. The figure which shows the result of the simulation for confirming the effect of this invention. The circuit diagram of the band gap reference circuit which concerns on the 2nd Embodiment of this invention. The circuit diagram of the conventional band gap reference circuit.

Explanation of symbols

  D1-D23 diode, QP1-QP23 P-channel MOS transistor, QN1-QN23 N-channel MOS transistor, R2-R23 resistance

Claims (6)

A plurality of first semiconductor elements each having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor;
A plurality of first N-channel MOS transistors whose gates and drains are connected to each other, and whose sources are respectively connected to the P-type semiconductors of the plurality of first semiconductor elements;
A plurality of drains connected to the gates and drains of the plurality of first N-channel MOS transistors, respectively, and a plurality of currents supplied to the plurality of first semiconductor elements via the plurality of first N-channel MOS transistors, respectively. A first P-channel MOS transistor;
A second semiconductor element having a PN junction having a different number or size of parallel connection from the first semiconductor element and having a power supply potential _VSS connected to an N-type semiconductor;
An impedance element having a first terminal connected to a P-type semiconductor of the second semiconductor element;
A second N-channel MOS transistor having a gate connected to a gate and a drain of the plurality of first N-channel MOS transistors and a source connected to a second terminal of the impedance element;
The gates and drains are connected to the gates of the plurality of first P-channel MOS transistors, the gates and drains are connected to the drains of the second N-channel MOS transistors, the second N-channel MOS transistors and the impedance A second P-channel MOS transistor for supplying current to the second semiconductor element via the element;
A bandgap reference circuit comprising: A third P-channel MOS transistor which forms a current mirror circuit with the second P-channel MOS transistor and supplies current from the drain;
A third semiconductor element having a PN junction and a second impedance element that is connected to a drain of the third P-channel MOS transistor and generates a reference potential;
The bandgap reference circuit according to claim 1, further comprising: A first semiconductor element having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor;
A first N-channel MOS transistor having a gate and a drain connected to each other and a source connected to a P-type semiconductor of the first semiconductor element;
A first P-channel MOS transistor having a drain connected to the gate and drain of the first N-channel MOS transistor, and supplying a current to the first semiconductor element via the first N-channel MOS transistor;
A plurality of second semiconductor elements each having a PN junction having a different number or size of parallel connection from the first semiconductor element, the power supply potential _VSS being connected to the N-type semiconductor;
A plurality of impedance elements each having a first terminal connected to a P-type semiconductor of the plurality of second semiconductor elements;
A plurality of second N-channel MOS transistors each having a gate connected to a gate and a drain of the first N-channel MOS transistor, and a source connected to a second terminal of the plurality of impedance elements;
A gate and a drain are respectively connected to a gate of the first P-channel MOS transistor, and a gate and a drain are respectively connected to drains of the plurality of second N-channel MOS transistors, and the plurality of second N-channel MOSs A plurality of second P-channel MOS transistors that respectively supply current to the plurality of second semiconductor elements via the transistors and the plurality of impedance elements;
A bandgap reference circuit comprising: A third P-channel MOS transistor which forms a current mirror circuit with the plurality of second P-channel MOS transistors and supplies current from the drain;
A third semiconductor element having a PN junction and a second impedance element that is connected to a drain of the third P-channel MOS transistor and generates a reference potential;
The band gap reference circuit according to claim 3, further comprising: A plurality of first semiconductor elements each having a PN junction and having a power supply potential _VSS connected to an N-type semiconductor;
A plurality of first N-channel MOS transistors whose gates and drains are connected to each other, and whose sources are respectively connected to the P-type semiconductors of the plurality of first semiconductor elements;
A plurality of drains connected to the gates and drains of the plurality of first N-channel MOS transistors, respectively, and a plurality of currents supplied to the plurality of first semiconductor elements via the plurality of first N-channel MOS transistors, respectively. A first P-channel MOS transistor;
A plurality of second semiconductor elements each having a PN junction having a different number or size of parallel connection from the first semiconductor element, the power supply potential _VSS being connected to the N-type semiconductor;
A plurality of impedance elements each having a first terminal connected to a P-type semiconductor of the plurality of second semiconductor elements;
A plurality of second N-channel MOS transistors having gates connected to gates and drains of the plurality of first N-channel MOS transistors, and sources connected to second terminals of the plurality of impedance elements;
Gates and drains are respectively connected to gates of the plurality of first P-channel MOS transistors, and gates and drains are respectively connected to drains of the plurality of second N-channel MOS transistors, and the plurality of second N-channel MOS transistors are connected. A plurality of second P-channel MOS transistors that respectively supply current to the plurality of second semiconductor elements via the channel MOS transistors and the plurality of impedance elements;
A bandgap reference circuit comprising: A third P-channel MOS transistor which forms a current mirror circuit with the plurality of second P-channel MOS transistors and supplies current from the drain;
A third semiconductor element having a PN junction and a second impedance element that is connected to a drain of the third P-channel MOS transistor and generates a reference potential;
The bandgap reference circuit according to claim 5, further comprising:

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