JP2008176617A - Reference voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit which maintains PSRR in a low voltage operation and while preventing the increase in circuit area and compensating temperature. <P>SOLUTION: The reference voltage generation circuit includes a differential amplifier circuit 101, current sources Is1 to Is4, PN junctions D1 to D3, and resistors R2 to R4. The differential amplifier circuit 101 has an inverted input terminal connected to a positive terminal of the current source Is1 and has a non-inverted input terminal connected to a positive terminal of the current source Is2 and has an output terminal connected to respective control terminals of current sources Is1 to Is4, and respective negative terminals of current sources Is1 to Is4 are connected to a supply voltage, and the positive terminal of the current source Is1 is connected to a P-type area of the PN junction D1, and the positive terminal of the current source Is2 is connected to one end of the resistor R2, and the positive terminal of the current source Is3 is connected to one end of the resistor R3, and the positive terminal of the current source Is4 is connected to the other end of the resistor R3, and the other end of the resistor R2 is connected to a P-type area of the PN junction D2, and the other end of the resistor R3 is connected to a P-type area of the PN junction D3, and the resistor R4 has one end connected to a positive terminal of the current source Is3 and has the other end connected to a ground voltage, and respective N-type areas of PN junctions D1 to D3 are connected to the ground voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reference voltage generating circuit, and more particularly to a reference voltage generating circuit that operates at a low voltage.

  In a conventional analog circuit, a bandgap reference circuit known as a reference voltage generation circuit is often used in order to realize a bias circuit having low temperature dependency and low power supply voltage dependency.

  Here, FIG. 3 shows a conventional general band gap reference circuit. As shown in FIG. 3, the band cap reference circuit 2 outputs a control voltage Vctrl corresponding to an input voltage difference (voltage Vb−voltage Va), and an input voltage difference between the differential amplifier circuit 201 and PMOS transistors M1 to M3 functioning as current sources whose current decreases in accordance with increase, PNP bipolar transistors Q1 to Q3 whose base terminals and collector terminals function as diodes, and resistors R2 and R3 are provided. Yes. The differential amplifier circuit 201 has an inverting input terminal connected to the drain terminal of the PMOS transistor M1, a non-inverting input terminal connected to the drain terminal of the PMOS transistor M2, and an output terminal connected to the gate terminals of the PMOS transistors M1 to M3. . Further, the source terminals of the PMOS transistors M1 to M3 are the power supply voltage, the drain terminal of the PMOS transistor M1 is the emitter terminal of the bipolar transistor Q1, the drain terminal of the PMOS transistor M2 is one end of the resistor R2, and the drain terminal of the PMOS transistor M3. Is connected to one end of the resistor R3, the other end of the resistor R2 is connected to the emitter terminal of the bipolar transistor Q2, the other end of the resistor R3 is connected to the emitter terminal of the bipolar transistor Q3, and the base terminals of the bipolar transistors Q1 to Q3 are connected to the ground voltage. ing.

  The transistor sizes of the PMOS transistors M1 to M3 are all the same, the junction area of the PN junction in the bipolar transistor Q2 is N times the junction area of the PN junction in the bipolar transistor Q1, and the junction of the PN junction in the bipolar transistor Q3. The area is the same as the junction area of the PN junction in bipolar transistor Q1.

  The band cap reference circuit 2 shown in FIG. 3 has a predetermined forward voltage difference (having a positive temperature coefficient) between the bipolar transistor Q1 and the bipolar transistor Q2 as a value of the forward voltage of the bipolar transistor Q3 having a negative temperature coefficient. A value multiplied by several times is added, and by taking such a configuration, a reference voltage (reference voltage) having no temperature dependency is generated. In the band gap reference circuit 2, a bipolar transistor is used as a diode. However, since the band gap reference circuit 2 is configured to add the forward voltage of each diode, the minimum value of the reference voltage that can be output is about 1.25V.

  In recent years, process miniaturization has progressed, and along with this, the power supply voltage of the analog circuit has been reduced, and a power supply voltage of 1.2 V or less has been used. In the conventional bandgap reference circuit 2 shown in FIG. 3, particularly when the power supply voltage becomes a low voltage of 1.2 V or less, there is a possibility that the normal operation is not performed and the temperature compensation cannot be performed. For this reason, various bandgap reference circuits that enable temperature compensation have been proposed even in an analog circuit that uses a low-voltage power supply voltage (see, for example, Patent Document 1, Patent Document 2, and Non-Patent Document 1).

  Here, FIG. 4 shows an example of a conventional bandgap reference circuit that can operate with a low power supply voltage. The output voltage of the bandgap reference circuit 2 shown in FIG. A voltage reference voltage is generated. More specifically, as shown in FIG. 4, the band gap reference circuit 3 has one end connected to the drain terminal (output node) of the PMOS transistor M3 in addition to the components of the band gap reference circuit 2 shown in FIG. A resistor R4 having an end connected to the ground voltage is provided.

  Next, the operation principle of the band gap reference circuit 3 shown in FIG. 4 will be described.

4, assuming that the forward voltage of the bipolar transistor Q1 is Vf ₁ , the thermal voltage is V _T , the value of the current flowing in the PMOS transistor M1 is I1, and the transport saturation current of the transistor M1 is Is, the differential amplifier circuit 201 The input voltage Va of the inverting input terminal is obtained by the following formula 1.

[Equation 1]
Va = Vf ₁ = V _T × {ln (I1 / Is)}

  On the other hand, assuming that the resistance value of the resistor R2 is r2 and the current flowing through the PMOS transistor M2 is I2, the input voltage Vb of the non-inverting input terminal of the differential amplifier circuit 201 is obtained by the following equation (2).

[Equation 2]
Vb = Vf ₂ + r2 × I2 = V _T × {ln (I2 / (N × Is))} + r2 × I2

  As described above, although the junction areas of the PN junctions of the bipolar transistor Q1 and the bipolar transistor Q2 are different, since the bipolar transistor Q1 and the bipolar transistor Q2 have the same structure, transport saturation flowing through the bipolar transistor Q1 and the bipolar transistor Q2 The current Is is the same. Further, since the non-inverting input terminal and the inverting input terminal of the differential amplifier circuit 201 are virtually short-circuited during normal operation and the respective input voltages are the same, the relationship of Equation 3 is obtained during normal operation.

[Equation 3]
Va = Vb

  As described above, since the transistor sizes of the PMOS transistors M1 to M3 are all the same, during normal operation, the gate-source voltages of the PMOS transistors M1 to M3 are the same, and the PMOS transistors M1 to M3 have the same size. The flowing currents I1 to I3 are the same.

[Equation 4]
I1 = I2 = I3 = I

Therefore, the forward voltage Vf ₁ of the bipolar transistor Q1 is obtained by the following equation 5 from the equations ₁ to 4.

[Equation 5]
Vf ₁
= Vf ₂ + r2 × I
= V _T × {ln (I1 / Is)}
= V _T × {ln (I1 / (N × Is))} + r2 × I

  From Equation 5, the current I is obtained by the following Equation 6.

[Equation 6]
I = (Vf ₁ −Vf ₂ ) / r2 = V _T × (lnN) × 1 / r2

  Furthermore, if the resistance value of the resistor R3 is r3, the resistance value of the resistor R4 is r4, the current flowing through the bipolar transistor Q3 and the resistor R3 is I3a, and the current flowing through the resistor R4 is I3b, this is the output voltage of the bandgap reference circuit 3. The reference voltage Vref is expressed by the following formula 7.

[Equation 7]
_{Vref = r3 × I3a + Vf 3} = r4 × I3b

  Further, from the current I3 = I3a + I3b flowing through the PMOS transistor M3, the following relationship of Equation 8 is obtained.

[Equation 8]
V _T × (lnN) × 1 / r2 = (Vref−Vf ₃ ) / r3 + Vref / r4

  Therefore, the reference voltage Vref of the bandgap reference circuit 3 is obtained by the following formula 9.

[Equation 9]
Vref
= {R4 / (r3 + r4)} × {Vf ₃ + (r3 / r2) × V _T × lnN}

Here, since Vf ₃ is a forward voltage of the diode (bipolar transistor Q3) and has a negative temperature coefficient, and the thermal voltage Vt has a positive temperature coefficient, N, r3 and r2 are appropriately determined from Equation 9. By setting to a small value, the temperature coefficient of the reference voltage Vref can be made zero. Further, according to Equation 9, the value of Vref can be set by appropriately setting the value of r4 according to the value of r3.

Here, if {Vf ₃ + (r ₃ / r 2) × V _T × lnN} is defined as Vref 0, the following formula 10 is obtained. Note that Vref0 is equal to the reference voltage when there is no resistor R4 (configuration in FIG. 3, r4 = ∞).

[Equation 10]
Vref = {r4 / (r3 + r4)} × Vref0

  In detail, since the temperature coefficient of the forward voltage of the diode is generally −1.6 mV / ° C. and the temperature coefficient of the thermal voltage Vt is +0.087 mV / ° C., in Equation 9, N = 8 In this case, if r3 / r2 is set to 8.8, the temperature coefficient of the reference voltage Vref becomes 0.0 mV / ° C. In general, since the forward voltage of the diode is +0.7 V and the thermal voltage Vt is +0.025 V, the voltage Vref0 when the temperature coefficient of the reference voltage Vref is 0.0 mV / ° C. is 1. 15V. Therefore, by adjusting the value of r4, the reference voltage Vref can be set smaller than the voltage Vref0 (corresponding to the reference voltage of the reference voltage generating circuit shown in FIG. 3).

JP 2000-174600 A US Pat. No. 6,642,778 “Floating reference voltage generation circuit for AD converter”, Toru Ogawa et al., IEICE Transactions, Vol. J85-C, No. 11, pp. 1000-1003, November 2002

  By the way, in the band gap reference circuit 3 shown in FIG. 4, when the power supply voltage is set to 1.2 V and the reference voltage Vref is set to 1.0 V, for example, when the power supply voltage is set to 1.0 V, the source-drain voltage of the PMOS transistor M3 is The voltage margin is reduced to 0.2V. As the voltage margin becomes smaller, the influence of the noise of the power supply voltage on the reference voltage becomes larger and PSRR deteriorates. Therefore, it is desirable to reduce the value of the reference voltage Vref. In order to set the reference voltage Vref high, the resistance value r4 of the resistor R4 needs to be set large, and a resistor with a larger resistance value requires a larger circuit area. Therefore, it is desirable to reduce the value of the reference voltage Vref in terms of maintaining PSRR (Power Signal Rejection Ratio) and circuit area.

  However, in the band gap reference circuit 3 shown in FIG. 4, when the reference voltage Vref is set to be small, it is necessary to set the resistance value r4 of the resistor R4 to be small. In this case, the value of the current I3b flowing through the resistor R4 increases. Since the value of the current I3 supplied from the PMOS transistor M3 which is a current source is constant, the value of the current I3a flowing through the bipolar transistor Q3 decreases as the value of the current I3b increases from the relationship of I3 = I3a + I3b. In particular, since the value of the current I3 is small during low voltage operation, if the value of the current I3b is large, the value of the current I3a is considerably small, and the current density of the bipolar transistor Q3 may change. In this case, the temperature coefficient of the bipolar transistor Q3 may change. If the temperature coefficient of the bipolar transistor Q3 changes, temperature compensation becomes very difficult.

  That is, in the conventional reference voltage generation circuit, during low voltage operation, the value of the reference voltage Vref needs to be reduced in order to maintain PSRR and prevent an increase in circuit area. Since it is necessary to set a large value, it has been difficult to simultaneously maintain PSRR, prevent an increase in circuit area, and perform temperature compensation. For this reason, in an analog circuit that operates at a low voltage, when generating a reference voltage Vref of 1.25 V or less, a reference that can simultaneously maintain PSRR and prevent an increase in circuit area and temperature compensation. A voltage generation circuit is desired.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a reference voltage generation circuit capable of simultaneously maintaining PSRR and preventing an increase in circuit area and temperature compensation during low voltage operation. It is in.

  In order to achieve the above object, a reference voltage generating circuit according to the present invention includes a differential amplifier circuit that outputs a control voltage corresponding to an input voltage difference, and a current that increases according to an increase in the input voltage difference of the differential amplifier circuit. The first current source, the second current source, the third current source, and the fourth current source, the first PN junction, the second PN junction, and the third PN junction, the first resistance, the second resistance, and the third resistance, The differential amplifier circuit has an inverting input terminal as a positive terminal of the first current source, a non-inverting input terminal as a positive terminal of the second current source, an output terminal as the first current source, and the first current source. 2 current sources, the third current source, and the fourth current source are connected to control terminals of each of the first current source, the second current source, the third current source, and the fourth current source. Is connected to the first power supply voltage, and the positive terminal of the first current source is connected to the first PN. A positive terminal of the second current source is connected to one end of the first resistor, a positive terminal of the third current source is connected to one end of the second resistor, and the fourth A positive terminal of a current source is connected to the other end of the second resistor, the other end of the first resistor is connected to a P-type region of the second PN junction, and the other end of the second resistor is connected to the third PN junction. Connected to a P-type region, one end of the third resistor is connected to the positive terminal of the third current source, the other end is connected to a second power supply voltage lower than the first power supply voltage, the first PN junction, A first feature is that N-type regions of the second PN junction and the third PN junction are connected to the second power supply voltage.

  The reference voltage generation circuit according to the present invention having the above characteristics is characterized in that the first power supply voltage is a predetermined positive voltage, and the second power supply voltage is a ground voltage.

  In the reference voltage generation circuit according to the present invention having the above characteristics, each of the first current source, the second current source, the third current source, and the fourth current source includes a PMOS transistor. The negative terminal of each current source corresponding to the source terminal, the positive terminal of each current source corresponding to each drain terminal, and the control terminal of each current source corresponding to each gate terminal are configured. The third feature.

  In the reference voltage generation circuit according to the present invention having the above characteristics, each of the first PN junction, the second PN junction, and the third PN junction is configured using a PNP transistor in which a base terminal and a collector terminal are connected to each other, A fourth feature is that a P-type region of each PN junction corresponding to each emitter terminal of the PNP transistor is configured as an N-type region of each PN junction corresponding to each base terminal.

  According to the present invention having the above characteristics, the reference voltage generation circuit is configured to include the third resistor for setting the value of the reference voltage Vref to be small and the fourth current source for compensating the amount of current flowing through the third PN junction. Therefore, when the value of the reference voltage Vref is set to be small during low voltage operation, it is possible to prevent a change in current density due to a decrease in the current amount of the third PN junction. As a result, the temperature coefficient of the third PN junction can be prevented from changing, particularly during low voltage operation, and temperature compensation can be achieved. Note that, when the value of the reference voltage Vref is set to be small during low voltage operation, a voltage margin between the power supply voltage and the reference voltage Vref can be secured, so that the PSRR can be prevented from being deteriorated and the resistance value of the third resistor is made small. As a result, an increase in circuit area can be prevented. Therefore, according to the present invention having the above characteristics, a reference voltage generating circuit capable of simultaneously maintaining PSRR and preventing an increase in circuit area and temperature compensation with a relatively simple circuit configuration, particularly during low voltage operation. can do.

  Furthermore, in the present invention having the above characteristics, if each current source is composed of a PMOS transistor and each PN junction is composed of a PNP transistor, the reference voltage generating circuit according to the present invention can be created by a normal CMOS process. Become.

  Embodiments of a reference voltage generation circuit according to the present invention (hereinafter, abbreviated as “the circuit of the present invention” as appropriate) will be described with reference to the drawings.

<First Embodiment>
A first embodiment of the circuit of the present invention will be described with reference to FIG.

  First, the configuration of the circuit of the present invention will be described with reference to FIG. Here, FIG. 1 is a schematic circuit diagram showing a basic configuration example of the circuit of the present invention. As shown in FIG. 1, the circuit 1 of the present invention includes a differential amplifier circuit 101 that outputs a control voltage Vctrl corresponding to an input voltage difference, and a current that decreases as the input voltage difference of the differential amplifier circuit 101 increases. Source Is1 (first current source), current source Is2 (second current source), current source Is3 (third current source) and current source Is4 (fourth current source), PN junction D1 (first PN junction), PN junction D2 (second PN junction), PN junction D3 (third PN junction), resistor R2 (first resistor), resistor R3 (second resistor), and resistor R4 (third resistor). Further, in the differential amplifier circuit 101, the inverting input terminal is the plus terminal of the current source Is1, the non-inverting input terminal is the plus terminal of the current source Is2, the output terminals are the current source Is1, the current source Is2, the current source Is3, and the current. The negative terminals of the current source Is1, the current source Is2, the current source Is3, and the current source Is4 are connected to the first power supply voltage, and the positive terminal of the current source Is1 is connected to the P of the PN junction D1. The positive terminal of the current source Is2 is connected to one end of the resistor R2, the positive terminal of the current source Is3 is connected to one end of the resistor R3, and the positive terminal of the current source Is4 is connected to the other end of the resistor R3. The other end of the resistor R2 is connected to the P-type region of the PN junction D2, the other end of the resistor R3 is connected to the P-type region of the PN junction D3, and one end of the resistor R4 is connected to the positive terminal of the current source Is3. End connected from the first power supply voltage to the second power supply voltage of the low voltage, PN junction D1, PN junction D2 and the PN junction D3 respective N-type region is connected to the second power supply voltage.

  More specifically, the circuit 1 of the present embodiment of the present embodiment has the same configuration of the current sources Is1 to Is3, and is configured such that the same control voltage Vctrl is supplied to the control terminals of the current sources Is1 to Is3. Therefore, the current sources Is1 to Is3 supply the same current to the circuit. Moreover, the junction area of PN junction D1 and PN junction D3 is the same, and the junction area of PN junction D2 is set to N times the junction area of PN junction D1. In this embodiment, the power supply voltage of the analog circuit is assumed as the first power supply voltage and the ground voltage is assumed as the second power supply voltage. However, the present invention is not limited to this.

  Next, the operation principle of the circuit 1 of the present invention will be described with reference to FIG.

In FIG. 1, when the forward voltage of the PN junction D1 is Vf ₁ , the thermal voltage is V _T , the current supplied by the current source Is1 is I1, and the transport saturation current of each current source is Is, the differential amplifier circuit 101 The input voltage Va at the inverting input terminal is obtained by the following equation (11).

[Equation 11]
Va = Vf ₁ = V _T × {ln (I1 / Is)}

  On the other hand, assuming that the resistance value of the resistor R2 is r2 and the current flowing through the current source Is2 is I2, the input voltage Vb of the non-inverting input terminal of the differential amplifier circuit 101 is obtained by the following equation (12).

[Equation 12]
Vb = Vf ₂ + r2 × I2 = V _T × {ln (I2 / (N × Is))} + r2 × I2

  Further, during normal operation, the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit 101 are virtually short-circuited and the respective input voltages are the same, and therefore the relationship of Equation 13 is obtained.

[Equation 13]
Va = Vb

  As described above, since the current sources Is1 to Is3 have the same configuration and the same control voltage Vctrl is supplied, the magnitudes of the currents I1 to I3 supplied by the current sources Is1 to Is3 are the same. Become.

[Formula 14]
I1 = I2 = I3 = I

Therefore, from the formulas 11 to 14, the forward voltage Vf ₁ of the PN junction D1 is obtained by the following formula 15.

[Equation 15]
Vf ₁
= Vf ₂ + r2 × I
= V _T × {ln (I1 / Is)}
= V _T × {ln (I1 / (N × Is))} + r2 × I

  From Equation 15, the current I is obtained by the following Equation 16.

[Equation 16]
I = (Vf ₁ −Vf ₂ ) / r2 = V _T × (lnN) × 1 / r2

  Further, if the resistance value of the resistor R3 is r3, the resistance value of the resistor R4 is r4, the current flowing through the PN junction D3 and the resistor R3 is I3a, and the current flowing through the resistor R4 is I3b, the reference voltage that is the output voltage of the circuit 1 of the present invention. The voltage Vref is expressed by Equation 17 below.

[Equation 17]
_{Vref = r3 × I3a + Vf 3} = r4 × I3b

  Further, from the current I3 = I3a + I3b flowing through the current source Is3, the following relationship of Expression 18 is obtained.

[Equation 18]
V _T × (lnN) × 1 / r2 = (Vref−Vf ₃ ) / r3 + Vref / r4

  Therefore, the reference voltage Vref of the circuit 1 of the present invention is obtained by the following equation (19).

[Equation 19]
Vref
= {R4 / (r3 + r4)} × {Vf ₃ + (r3 / r2) × V _T × lnN}
= {R4 / (r3 + r4)} * Vref0

Here, Vref0 ₌ a {Vf 3 + (r3 / r2 ) × V T × lnN}, Vref0 corresponds to the reference voltage of the reference voltage generating circuit shown in FIG. In Equation 19, since Vf ₃ is a forward voltage of the PN junction D3, it has a negative temperature coefficient, and the thermal voltage Vt has a positive temperature coefficient, so N, r3, and r2 are set to appropriate values. By doing so, the temperature coefficient of the reference voltage Vref can be made zero. Further, from the equation 19, the value of Vref can be set by appropriately setting the value of r4 according to the value of r3.

  In the circuit 1 of the present invention, a part of the current I3 supplied from the current source Is3 flows through the resistor R4. Here, if the configuration of the current source Is4 is adjusted and the current I4 supplied from the current source Is4 to the PN junction D3 is set to the same magnitude as the current I3b flowing through the resistor R4, the current I3d flowing through the PN junction D3 is The current I1 (= I) flowing through the other PN junction D1 and the current I2 (= I) flowing through the PN junction D2 can be made equal. In this case, the current I3d flowing through the PN junction D3 is obtained by the following equation (20).

[Equation 20]
I3d = I3a + I4 = (I3-I3b) + I4 = I

Second Embodiment
A second embodiment of the circuit of the present invention will be described with reference to FIG. In the present embodiment, a case will be described in which PMOS transistors M1 to M4 are used as the current sources Is1 to Is4 and PNP transistors (bipolar transistors) Q1 to Q3 are used as the PN junctions D1 to D3 in the first embodiment.

  FIG. 2 is a schematic circuit diagram showing the configuration of the inventive circuit 1 of the present embodiment. In the circuit 1 of the present invention of the present embodiment, the current source Is1 includes a PMOS transistor M1, the source terminal of the PMOS transistor M1 is the minus terminal of the current source Is1, the drain terminal is the plus terminal of the current source Is1, and the gate terminal is Each control terminal of the current source Is1 is configured. Similarly, the current source Is2 includes a PMOS transistor M2, the source terminal of the PMOS transistor M2 is the minus terminal of the current source Is2, the drain terminal is the plus terminal of the current source Is2, and the gate terminal is the control terminal of the current source Is2. Each is composed. The current source Is3 includes a PMOS transistor M3. The source terminal of the PMOS transistor M3 constitutes the minus terminal of the current source Is3, the drain terminal constitutes the plus terminal of the current source Is3, and the gate terminal constitutes the control terminal of the current source Is3. ing. The current source Is4 includes a PMOS transistor M4. The source terminal of the PMOS transistor M4 constitutes the minus terminal of the current source Is4, the drain terminal constitutes the plus terminal of the current source Is4, and the gate terminal constitutes the control terminal of the current source Is4. ing.

  In the present embodiment, the PMOS transistors M1 to M3 are configured to supply the same current to the circuit by the same control voltage Vctrl, so that the transistor sizes are set to be the same. The PMOS transistor M4 sets the transistor size so that a current having the same magnitude as the current I3b flowing through the resistor R4 is supplied to the circuit.

  Furthermore, in the inventive circuit 1 of the present embodiment, the PN junction D1 is configured using a PNP transistor Q1 whose base terminal and collector terminal are connected to each other, and the emitter terminal of the PNP transistor Q1 is a P-type of the PN junction D1. Each of the regions constitutes an N-type region whose base terminal is a PN junction D1. Similarly, the PN junction D2 is configured using a PNP transistor Q2 having a base terminal and a collector terminal connected to each other. The emitter terminal of the PNP transistor Q2 is a P-type region of the PN junction D2, and the base terminal is a PN junction D2. N-type regions are respectively configured. The PN junction D3 includes a PNP transistor Q3 having a base terminal and a collector terminal connected to each other. The emitter terminal of the PNP transistor Q3 is a P-type region of the PN junction D3, and the base terminal is an N-type of the PN junction D3. Each area is composed.

Table 1 shows an example of a comparison result regarding the value of PSRR and the presence or absence of temperature compensation in the conventional reference voltage generating circuit 3 and the circuit 1 of the present invention shown in FIG. For comparison, for each parameter of the conventional reference voltage generation circuit 3 and the circuit 1 of the present invention, the W of the PMOS transistors M1 to M4 is 5 μm, L is 1 μm, the resistance value r2 of the resistor R2 is 7.9 kΩ, and the resistance R3 Resistance value r3 is 47 kΩ, resistance R4 resistance value r4 is 70 kΩ, W of PNP transistors Q1 and Q3 is 10 μm, L is 10 μm (area = 10 ⁻¹⁰ m ² ), N is 24 (PNP transistor Q2 has W = 10 μm, 24 PNP transistors of L = 10 μm are connected in parallel), and the current I (= I1 = I2 = I3 = I4) is set to 10 μA.

  From the results shown in Table 1, the circuit 1 of the present invention is capable of temperature compensation at the time of low voltage operation and maintains a good value of PSRR as compared with the conventional reference voltage generating circuit 3 shown in FIG. Yes.

1 is a schematic circuit diagram showing a basic configuration example of a reference voltage generating circuit according to the present invention. 1 is a schematic circuit diagram showing a configuration example of a reference voltage generating circuit according to the present invention. Schematic circuit diagram showing a configuration example of a reference voltage generation circuit according to the prior art Schematic circuit diagram showing a configuration example of a reference voltage generation circuit according to the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference voltage generation circuit 2 which concerns on this invention Reference voltage generation circuit 3 which concerns on a prior art Reference voltage generation circuit 101 which concerns on a prior art Differential amplifier circuit 201 Differential amplifier circuit Is1 Current source Is2 Current source Is3 Current source Is4 Current source M1 PMOS transistor M2 PMOS transistor M3 PMOS transistor M4 PMOS transistor R2 Resistor R3 Resistor R4 Resistor D1 PN junction D2 PN junction D3 PN junction Q1 Bipolar transistor Q2 Bipolar transistor Q3 Bipolar transistor

Claims (4)

A differential amplifier circuit that outputs a control voltage according to the input voltage difference;
A first current source, a second current source, a third current source, and a fourth current source, the current of which decreases as the input voltage difference of the differential amplifier circuit increases;
A first PN junction, a second PN junction, and a third PN junction;
A first resistor, a second resistor, and a third resistor;
In the differential amplifier circuit, an inverting input terminal is a plus terminal of the first current source, a non-inverting input terminal is a plus terminal of the second current source, and an output terminal is the first current source and the second current source. , Connected to control terminals of the third current source and the fourth current source,
A negative terminal of each of the first current source, the second current source, the third current source, and the fourth current source is connected to a first power supply voltage;
A positive terminal of the first current source is connected to a P-type region of the first PN junction;
A positive terminal of the second current source is connected to one end of the first resistor;
A positive terminal of the third current source is connected to one end of the second resistor;
A positive terminal of the fourth current source is connected to the other end of the second resistor;
The other end of the first resistor is connected to the P-type region of the second PN junction;
The other end of the second resistor is connected to the P-type region of the third PN junction;
One end of the third resistor is connected to a positive terminal of the third current source, and the other end is connected to a second power supply voltage lower than the first power supply voltage;
An N-type region of each of the first PN junction, the second PN junction, and the third PN junction is connected to the second power supply voltage.   The reference voltage generation circuit according to claim 1, wherein the first power supply voltage is a predetermined positive voltage, and the second power supply voltage is a ground voltage.   Each of the first current source, the second current source, the third current source, and the fourth current source includes a PMOS transistor, and each source terminal of the PMOS transistor corresponds to a minus terminal of each current source. 3. The reference voltage according to claim 1, wherein a positive terminal of each of the current sources to which each drain terminal corresponds and a control terminal of each of the current sources to which each gate terminal corresponds are configured. Generation circuit. The first PN junction, the second PN junction, and the third PN junction are each configured by using a PNP transistor in which a base terminal and a collector terminal are connected to each other, and each of the emitter terminals of the PNP transistor corresponds to the corresponding PN. 4. The reference voltage generating circuit according to claim 1, wherein a P-type region of the junction is configured as an N-type region of each of the PN junctions to which each base terminal corresponds.

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