JP2004206633A

JP2004206633A - Semiconductor integrated circuit and electronic circuit

Info

Publication number: JP2004206633A
Application number: JP2002378101A
Authority: JP
Inventors: Morohisa Yamamoto; 師久山本; Hisataka Tsunoda; 尚隆角田; Satoru Matsumura; 哲松村; Masaru Kubota; 勝窪田; Kazuki Watanabe; 一希渡邊
Original assignee: Renesas Technology Corp; Hitachi ULSI Systems Co Ltd
Current assignee: Renesas Technology Corp; Hitachi Solutions Technology Ltd
Priority date: 2002-12-26
Filing date: 2002-12-26
Publication date: 2004-07-22

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit with the less number of circuit elements by generating the reference voltage of ≤ about 1.2V to which temperature compensation and power supply voltage compensation are performed. <P>SOLUTION: The reference voltage generation circuit allows to flow a prescribed current in proportion with current of a band gap part to an output reproduction part (RGN) as a current path other than that of the band gap part by a control signal (Vc) for making first voltage (V1) and second voltage (V2) to be generated based on difference of current flowing to a pair of joint type load elements (11, 12) of the band gap part (BGP) coincide with each other. The current path of the output reproduction part includes a serial circuit between a joint type load element (13) and a resister (25) and a resistor (26) arranged in parallel with it, and voltage of a coupling node between the serial circuit and the parallel resistor can be made lower in comparison with a case that no parallel resistor is arranged. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路の基準電圧発生技術、特に、バンドギャップ型の低基準電圧発生回路に関し、例えばパワーオンリセット機能や電気的に消去及び書き込み可能な不揮発性メモリなどを備え低電圧動作されるマイクロコンピュータに適用して有効な技術に関する。
【０００２】
【従来の技術】
基準電圧を必要とする半導体集積回路の機能には、例えばディジタル回路のイニシャライズ動作いわゆるパワーオンリセット機能、Ａ−Ｄ変換（アナログ・ディジタル変換）機能や、Ｄ−Ａ変換（ディジタル・アナログ変換）機能、ＥＥＰＲＯＭ（ＥｌｅｃｔｒｉｃＥｒａｓａｂｌｅＰｒｏｇｒａｍａｂｌｅＲｅａｄＯｎｌｙＭｅｍｏｒｙ）等書き込みのための高電圧をチャージポンプで生成する回路、電圧レギュレータ等がある。
【０００３】
回路のパワーオンリセット機能とは、電源電圧投入時に所定の電源電圧になった場合に、所定の回路出力状態を所定の状態にリセットする機能で、該リセット信号を発生するためには電源電圧を監視するための基準電圧を必要とする。パワーオンリセット機能が必要な具体的な半導体集積回路としては、マイクロコンピュータ、映像信号・音声信号をディジタル処理するディジタル回路やアナログ・ディジタル混在回路、携帯機器・パーソナルコンピュータ等で代表される通信・情報機器での信号処理のためのディジタル回路やアナログ・ディジタル混在回路等である。
【０００４】
Ａ−Ｄ変換回路やＤ−Ａ変換回路では、アナログ信号量を検量するためや規定されたアナログ量に変換するするために基準電圧が必要である。また、ＥＥＰＲＯＭ等のメモリに書き込むために必要な高電圧をチャージポンプで生成するとき昇圧電圧を所定の範囲の電圧に制御するために基準電圧が必要である。
【０００５】
従来の基準電圧発生回路には、温度依存性と電源電圧依存性を低減するために、ＰＮ接合ダイオードもしくはバイポーラトランジスタのＰＮ接合を用いたバンドギャップ型の例がある。
【０００６】
特許文献１は、ＰＮ接合ダイオードと電流源との直列接続ノード電圧と、ダイオードに抵抗を接続した回路と電流源との直列接続ノード電圧とが一致するように双方の電流源を制御すると共に別の電流源を制御し、その電流源を用いて、前記ダイオードと電流源との直列径路に流れる電流と相関を持つ電流を再生すると共にダイオードの負の温度特性を相殺するのに当該直列径路に抵抗を挿入した回路構成を開示する。
【０００７】
特許文献２は、基準電圧の低電圧化に対応した基準電圧発生回路を開示する。即ち、ダイオード接続されたバイポーラトランジスタを用いてバイアス電圧を形成し、このバイアス電圧で制御される電流源バイポーラトランジスタを夫々持つ電流径路の一方にダイオード接続されたバイポーラトランジスタを挿入し、双方の電流源バイポーラトランジスタのコレクタ間に抵抗の直列接続体を挿入し、当該直列接続体の接続点から低電圧の基準電圧を得る構成を開示する。
【０００８】
特許文献３は、ダイオードのＰＮ接合における順方向電圧及びその差を電流変換した後、加算することで、温度依存性を無くしながら任意の値の基準電圧や基準電流を発生させる構成を開示する。
【０００９】
【特許文献１】
特開２０００−２４２３４９号公報
【特許文献２】
特開平８−３６４３５号公報
【特許文献３】
特開平１１−４５１２５号公報
【００１０】
【発明が解決しようとする課題】
本発明者は基準電圧の低電圧化について検討した。すなわち、これまでの０．５μｍプロセスや０．３５μｍプロセスの半導体デバイスは、電源電圧が５Ｖや３Ｖであり、バンドギャップ型基準電圧発生回路が発生する約１．２Ｖ近傍の電圧は、基準電圧として回路的に使いやすいものであった。しかしながら、半導体集積回路では微細プロセス化が図られ、０．２μｍ以下の微細プロセスに進むと、デバイスの耐圧が下がり、供給可能な電源電圧も１．５V以下に下がり、結果的に上述の約１．２Ｖ近傍の電圧を発生するバンドギャップ型基準電圧発生回路では、低電圧での動作つまり動作開始最小電源電圧の確保が困難になるという問題点のあることが明らかにされた。具体的には、例えば特許文献１において、ＰＮ接合ダイオードと電流源との直列接続ノード電圧と、ダイオードに抵抗を接続した回路と電流源との直列接続ノード電圧とを比較する差動アンプの動作特性にリニアリティがあること、動作電源電圧が基準電圧より十分大きいことが必須であり、微細プロセスでの電源電圧が例えば１．５Ｖ以下に下がり、約１．２Ｖの基準電圧と同等の電源電圧では温度補償された基準電圧を発生させることができなくなる。前記特許文献２，３記載の技術は基準電圧の低電圧化に資することができるが、回路素子数が多く、チップ占有面積が大きくなる。
【００１１】
本発明の目的は、温度補償と電源電圧補償された約１．２Ｖ以下の基準電圧を発生することが可能であり、回路素子数も少なくすることが可能な基準電圧発生回路を備えた半導体集積回路、更には当該半導体集積回路を適用した電子回路を提供することにある。
【００１２】
本発明の別の目的は、約１．２Ｖの基準電圧を発生するバンドギャップ型基準電圧発生回路の電源電圧以下の供給電源電圧で、温度補償と電源電圧補償された基準電圧を発生することが可能であり、回路素子数も少なくすることが可能な基準電圧発生回路を備えた半導体集積回路、更には当該半導体集積回路を適用した電子回路を提供することにある。
【００１３】
本発明の前記並びにその他の目的と新規な特徴は本明細書の記述及び添付図面から明らかになるであろう。
【００１４】
【課題を解決するための手段】
本願において開示される発明のうち代表的なものの概要を簡単に説明すれば下記の通りである。
【００１５】
〔１〕半導体集積回路は基準電圧発生回路を備え、この基準電圧発生回路は、電流源を介し一対の接合型負荷素子に流れる電流差に基いて第１の電圧と第２の電圧を生成するバンドギャップ部と、前記第１の電圧と第２の電圧を一致させるように前記電流源を介して前記一対の接合型負荷素子に流れる電流を制御するのに利用される制御信号を生成する比較部と、接合型負荷素子と抵抗の直列回路を有し前記制御信号に基いてその直列回路に前記バンドギャップ部の接合型負荷素子に流れる電流に比例する電流を再生する出力再生部とから成る。前記出力再生部の前記直列回路に抵抗が並列接続され、前記出力再生部から基準電圧が取り出されるようにされる。
【００１６】
上記基準電圧発生回路は、前記バンドギャップ部の一対の接合型負荷素子に流れる電流差に基いて生成される第１の電圧と第２の電圧を一致させる制御信号によって、前記バンドギャップ部とは別の電流径路である出力再生部に、バンドギャップ部の電流に比例する所定の電流を流す。出力再生部の電流径路は接合型負荷素子と抵抗の直列回路とそれに並列された抵抗を含み、前記直列回路と並列抵抗の結合ノードの電圧は前記並列抵抗を配置しない場合に比べて低くすることができる。出力再生部の電流径路における接合型負荷素子は負の温度特性を有し、抵抗は前記負の温度特性を相殺しようとする正の温度特性を持ち、また、バンドギャップ部における一対の接合型負荷素子に流れる電流差は電源電圧に依存しないようにしようとされる。したがって、温度補償と電源電圧補償された約１．２Ｖ以下の基準電圧を発生することが可能である。もしくは、約１．２Ｖの基準電圧を発生するバンドギャップ型基準電圧発生回路の電源電圧以下の供給電源電圧で、温度補償と電源電圧補償された基準電圧を発生することが可能である。また、基準電圧発生回路はバンドギャップ部に２つの電流源径路を持ち、出力再生部に１つの電流源径路を持てば充分であるから、回路素子数も少なくすることが可能である。
【００１７】
本発明の具体的な形態では、前記バンドギャップ部は電流源として前記第１信号をゲートに受けて制御される電流源ＭＯＳトランジスタを有する。前記出力再生部は前記第１信号をゲートに受けて制御される電流源ＭＯＳトランジスタを有する。また、別の具体的な形態では、前記出力再生部は前記第１信号をゲートに受けて制御される電流制御ＭＯＳトランジスタとこれに直列されたダイオード接続形態の電流源ＭＯＳトランジスタを有する。前記バンドギャップ部は前記電流制御ＭＯＳトランジスタとカレントミラー形態で接続された電流源ＭＯＳトランジスタを有する。
【００１８】
〔２〕本発明の更に別の観点による半導体集積回路の基準電圧発生回路は、第１の接合型負荷素子に第１の電流源を直列接続した接続ノードの第１の電圧と、第２の接合型負荷素子と第１の抵抗の直列径路に第２の電流源を直列接続した接続ノードの第２の電圧とを一致させるように前記第１の電流源と第２の電流源を制御する制御電圧を生成する第１回路と、第３の接合型負荷素子と第２の抵抗の直列径路に前記制御電圧で制御される第３の電流源を直列接続し、前記第３の接合型負荷素子と前記第２の抵抗の直列径路に第３の抵抗を並列接続した第２回路とから成り、第２回路から基準電圧が取り出される基準電圧発生回路を有する。
【００１９】
上記基準電圧発生回路は、第１の電圧と第２の電圧を一致させるように電流源を制御する制御電圧によって、別の電流径路である第２回路に、前記第２の接合型負荷素子、第１の抵抗及び第２の電流源に流れる電流に比例する所定の電流を流す。第２の回路の電流径路は第３の接合型負荷素子と第２の抵抗の直列回路とそれに並列された第３の抵抗を含み、前記直列回路と第３の抵抗の結合ノードの電圧は前記第３の抵抗を配置しない場合に比べて低くすることができる。第２回路の電流径路における第３の接合型負荷素子は負の温度特性を有し、第２及び第３の抵抗は前記負の温度特性を相殺しようとする正の温度特性を持ち、また、前記第１の接合型負荷素子及び第１の電流源にの直列回路に流れる電流と前記第２の接合型負荷素子、第１の抵抗及び第２の電流源の直列回路に流れる電流との差は電源電圧に依存しないようにしようとされる。したがって、温度補償と電源電圧補償された約１．２Ｖ以下の基準電圧を発生することが可能である。もしくは、約１．２Ｖの基準電圧を発生するバンドギャップ型基準電圧発生回路の電源電圧以下の供給電源電圧で、温度補償と電源電圧補償された基準電圧を発生することが可能である。また、基準電圧発生回路は第１及び第２の電圧を形成するのに２つの電流源径路を持ち、第２の回路に１つの電流源径路を持てば充分であるから、回路素子数も少なくすることが可能である。
【００２０】
前記第１乃至第３の接合型負荷素子は例えば、ＰＮ接合ダイオード、或は、ダイオード接続されたバイポーラトランジスタである。前記第１乃至第３の電流源は例えばｐチャンネル型ＭＯＳトランジスタ又はｎチャンネル型ＭＯＳトランジスタである。
【００２１】
前記基準電圧は、前記第３の接合型負荷素子と第２の抵抗の直列径路に第３の電流源を直列接続した接続ノードの電圧である。また、前記基準電圧は、前記第３の抵抗の所定の分圧ノードの電圧である。生成される基準電圧は前者に比べ後者の方を低くすることができる。
【００２２】
〔３〕本発明の更に具体的な形態による半導体集積回路の基準電圧発生回路を説明する。
【００２３】
第１例として、接合型負荷素子にＰＮ接合ダイオードを用いる。即ち、基準電圧発生回路は、所定の電流値比の第１の電流源、第２電流源及び第３の電流源と、所定の面積比の第１のＰＮ接合ダイオード、第２のＰＮ接合ダイオード及び第３のＰＮ接合ダイオードと、所定の抵抗比の第１の抵抗、第２の抵抗及び第３の抵抗と、前記第１乃至第３の電流源を共通に制御する比較回路とから成る。前記第１の電流源は、前記第１のＰＮ接合ダイオードを負荷回路として第１の電圧を発生し、前記第２の定電流源は、前記第２のＰＮ接合ダイオードと第１の抵抗が直列に接続された第１の直列接続回路を負荷回路として第２の電圧を発生し、前記比較回路は、前記第１の電圧と前記第２の電圧を比較して、前記第１の電圧と前記第２の電圧を同一にするように前記第１乃至第３の電流源を共通に制御する。前記第３の電流源は、前記第３のＰＮ接合ダイオードと第２の抵抗が直列に接続された第２の直列接続回路と、かつ前記第２の直列接続回路と並列に第３の抵抗が接続された負荷回路に接続される。前記基準電圧発生回路は基準電圧として前記第３の電圧を出力する。
【００２４】
第２例として、接合型負荷素子にダイオード接続されたバイポーラトランジスタを用いる。即ち、基準電圧発生回路は、所定の電流値比の第１の電流源、第２の電流源及び第３の電流源と、所定の面積比の第１のダイオード接続されたバイポーラトランジスタ、第２のダイオード接続されたバイポーラトランジスタ及び第３のダイオード接続されたバイポーラトランジスタと、所定の抵抗比の第１の抵抗、第２の抵抗及び第３の抵抗と、前記第１乃至第３の電流源を共通に制御する比較回路とから成る。前記第１の電流源は、前記第１のダイオード接続されたバイポーラトランジスタを負荷回路として第１の電圧を発生する。前記第２の定電流源は、前記第２のダイオード接続されたバイポーラトランジスタと第１の抵抗が直列に接続された第１の直列接続回路を負荷回路として第２の電圧を発生する。前記比較回路は、前記第１の電圧と前記第２の電圧を比較して、前記第１の電圧と前記第２の電圧を同一にするように前記第１乃至第３の電流源を共通に制御する。前記第３の電流源は、前記第３のダイオード接続されたバイポーラトランジスタと第２の抵抗が直列に接続された第２の直列接続回路と、かつ前記第２の直列接続回路と並列に第３の抵抗が接続された負荷回路に接続される。前記基準電圧発生回路は基準電圧として前記第３の電圧を出力する。
【００２５】
第３の例として、回路の接地電位とは異なるアナロググランドのような電位を用いて規準電圧を発生させる。即ち、基準電圧発生回路は、所定の電流値比の第１の電流源、第２の電流源及び第３の電流源と、所定の面積比の第１のバイポーラトランジスタ、第２のバイポーラトランジスタ及び第３のバイポーラトランジスタと、所定の抵抗比の第１の抵抗、第２の抵抗及び第３の抵抗と、前記３つの電流源を共通に制御する比較回路とから成る。前記第１の電流源は、前記第１のバイポーラトランジスタを負荷回路として第１の電圧を発生する。前記第２の定電流源は、前記第２のバイポーラトランジスタと第１の抵抗が直列に接続された第１の直列接続回路を負荷回路として第２の電圧を発生する。前記比較回路は、前記第１の電圧と前記第２の電圧を比較して、前記第１の電圧と前記第２の電圧を同一にするように前記第１乃至第３の電流源を共通に制御する。前記第３の電流源は、前記第３のバイポーラトランジスタと第２の抵抗が直列に接続された第２の直列接続回路と、かつ前記第２の直列接続回路と並列に第３の抵抗が接続された負荷回路に接続される。前記第１と第２のバイポーラトランジスタのベース電位は共通の第４の電位にバイアスされる。前記第３のバイポーラトランジスタのベース電位ならびに前記第３の抵抗は前記第４の電位と異なる電位にバイアスされる。前記基準電圧発生回路は基準電圧として前記第３の電圧を出力する。
【００２６】
同様に、上記第1の例において第１のＰＮ接合ダイオードと第２のＰＮ接合ダイオードを共通の第４の電位に接続し、前記第３のＰＮ接合ダイオード及び前記第３の抵抗を前記第４の電位と異なる電位にバイアスしてよい。また、上記第２の例において、第１のダイオード接続されたバイポーラトランジスタと第２のダイオード接続されたバイポーラトランジスタを共通の第４の電位に接続し、前記第３のダイオード接続されたバイポーラトランジスタ及び前記第３の抵抗を前記第４の電位と異なる電位にバイアスしてよい。
【００２７】
上記第１乃至第３の例において、前記第３の抵抗を所定の分圧比で２分割し、２分割点の結合ノードから基準電圧を取り出してもよい。
【００２８】
半導体集積回路は前記基準電圧発生回路の基準電圧を入力する回路モジュール、例えばＡ−Ｄ変換モジュール、Ｄ−Ａ変換モジュール、電圧レギュレータ、パワーオンリセット回路、又はフラッシュメモリ等の高電圧発生用チャージポンプ回路を有する。電子回路は、実装基板にそのような半導体集積回路と別の単数又は複数の半導体集積回路が実装されて構成される。
【００２９】
【発明の実施の形態】
図１には本発明に係る半導体集積回路が保有する基準電圧発生回路の第１の例が示される。
【００３０】
同図に示される基準電圧発生回路は、電源端子３２側に所定の電流値比の電流源としてｐチャンネル型の電流源ＭＯＳトランジスタ１，２，３が配置され、回路の接地端子３５側には所定の面積比のＰＮ接合型負荷素子としてＰＮ接合ダイオード１１，１２，１３、が配置される。電流源ＭＯＳトランジスタ２による電流径路には抵抗２１が配置され、電流源ＭＯＳトランジスタ３による電流径路には抵抗２５，２６が配置される。抵抗２５はＰＮ接合ダイオード１３に直列され、抵抗２６は前記抵抗２５はＰＮ接合ダイオード１３の直列径路に並列される。電源端子３２には電源電圧ＶＤＤが供給され、接地端子３５には回路の接地電圧ＶＳＳが供給される。
【００３１】
前記電流源ＭＯＳトランジスタ１は前記ＰＮ接合ダイオード１１を負荷回路として第１の電圧Ｖ１を発生する。前記電流源ＭＯＳトランジスタ２は前記ＰＮ接合ダイオード１２と抵抗２１が直列に接続された第１の直列接続回路を負荷回路として第２の電圧Ｖ２を発生する。前記比較回路３１は、前記第１の電圧と前記第２の電圧を比較して制御電圧Ｖｃを生成し、前記第１の電圧Ｖ１と前記第２の電圧Ｖ２を同一にするように前記電流源ＭＯＳトランジスタ１，２，３を共通に制御する。比較回路３１は差動アンプによって構成される。出力端子３３には電流源ＭＯＳトランジスタ３のドレイン電圧が出力電圧Ｖｂｇｏｕｔ’として出力され、この電圧Ｖｂｇｏｕｔ’が基準電圧として利用される。
【００３２】
前記電流源ＭＯＳトランジスタ１，２、抵抗２１、ＰＮ接合ダイオード１１，１２から成る前記第１の電圧と第２の電圧Ｖ２を生成する回路はバンドギャップ部ＢＧＰの一例である。比較回路３１は比較部ＣＭＰの一例を成す。前記電流源ＭＯＳトランジスタ３、抵抗２５，２６、ＰＮ接合ダイオード１３から成る回路は前記バンドギャップ部の接合型負荷素子に流れる電流に比例する電流を再生する出力再生部ＲＧＮの一例を成す。
【００３３】
基準電圧発生回路の作用を概略的に説明する。上記基準電圧発生回路は、前記バンドギャップ部ＢＧＰの一対のＰＮ接合ダイオード１１，１２に流れる電流Ｉ４１，Ｉ４２の電流差に基いて生成される第１電圧Ｖ１と第２電圧Ｖ２を一致させる制御電圧Ｖｃによって、前記バンドギャップ部ＢＧＰとは別の電流径路である出力再生部ＲＧＮに、バンドギャップ部の電流Ｉ４２に比例する所定の電流Ｉ４４を流す。出力再生部ＲＧＮの電流径路はＰＮ接合ダイオード１３と抵抗２５の直列回路とそれに並列された抵抗２６を含み、前記直列回路と並列抵抗の結合ノードの電圧Ｖｂｇｏｕｔ’は前記並列抵抗を配置しない場合に比べて低くすることができる。出力再生部ＲＧＮの電流径路におけるＰＮ接合ダイオード１３は負の温度特性を有し、抵抗２５，２６は前記負の温度特性を相殺しようとする正の温度特性を持ち、また、バンドギャップ部ＢＧＰにおける一対のＰＮ接合ダイオード１１，１２に流れる電流差は電源電圧ＶＤＤに依存しないようにしようとされる。したがって、温度補償と電源電圧補償された約１．２Ｖ以下の基準電圧を発生することが可能である。もしくは、約１．２Ｖの基準電圧を発生するバンドギャップ型基準電圧発生回路の電源電圧以下の供給電源電圧で、温度補償と電源電圧補償された基準電圧を発生することが可能である。また、基準電圧発生回路はバンドギャップ部ＢＧＰに２つの電流源径路を持ち、出力再生部ＲＧＮに１つの電流源径路を持てば充分であるから、回路素子数も少なくて済む。
【００３４】
図１の基準電圧発生回路の作用を更に詳細に説明する。その説明に当たっては理解を容易化するために、本発明の基本となる２種類の基準電圧発生回路を図２、図３に提示してその作用から説明していく。
【００３５】
図２にはバンドギャップ型基準電圧発生回路の基本型を示す。図２において、抵抗２３（抵抗値＝Ｒ２３）に流れる電流Ｉ４１による降下電圧と抵抗２２（抵抗値＝Ｒ２２）流れるＩ４２による降下電圧が一致するように端子３３の出力電圧Ｖｂｇｏｕｔが制御される。すなわち、電流Ｉ４１によるＰＮ接合ダイオード１１の順方向電圧が、電流Ｉ４２によるダイオード１２の順方向電圧と抵抗２１（抵抗値＝Ｒ２１）による降下電圧とを加えた電圧に一致するように制御される。
【００３６】
ＰＮ接合ダイオード１１と１２の順方向電圧ＶＦ１とＶＦ２と、バイアス電流値Ｉ４１とＩ４２との関係は、
Ｉ４１＝Ｓ１１＊ＩＳ０＊ＥＸＰ｛ｑ＊ＶＦ１／（ｋ＊Ｔ）−１}…（１）
Ｉ４２＝Ｓ１２＊ＩＳ０＊ＥＸＰ｛ｑ＊ＶＦ２／（ｋ＊Ｔ）−１}…（２）
のように示される。
【００３７】
ここで、上記式に用いられている記号について、ＩＳ０はダイオードの単位面積あたりの飽和電流、ｋはボルツマン定数、ｑは電子の単位電荷、Ｔは絶対温度を意味する。また、ダイオード１１、１２のそれぞれの面積をＳ１１とＳ１２としている。＊は乗算器号、／は除算記号である。
【００３８】
ダイオード１１と１２の順方向電圧差ΔＶＦ＝ＶＦ１−ＶＦ２は式（１）、式（２）を簡略化して、
ΔＶＦ＝（ｋ＊Ｔ／ｑ）＊ｌｎ｛Ｉ４１／Ｉ４２｝…（３）
で示される。一方Ｉ４１／Ｉ４２＝Ｒ２２／Ｒ２３＝Ｍ（Ｍは正の実数）で示されるので、Ｓ１２／Ｓ１１＝Ｎ（Ｎは、正の実数）とすると、
（Ｉ４１／Ｉ４２）＊（Ｓ１２／Ｓ１１）＝Ｍ＊Ｎ…（４）
と置きかえられ、また、Ｒ２２／Ｒ２１＝Ｌ（Ｌは、正の実数）と設定される。これにより、出力電圧Ｖｂｇｏｕｔは、
Ｖｂｇｏｕｔ＝ＶＦ１＋Ｌ＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）…（５）
と記述される。式（５）の第２項は、回路デバイスの物理的定数比で制御されることを意味し、かつ正の温度特性を得ることを示している。また式（５）の第１項は、上述したようにダイオードの順方向電圧を示しており、式（３）からの簡略化で
ＶＦ１＝（ｋ＊Ｔ／ｑ）＊ｌｎ｛Ｉ４１／（Ｓ１１＊ＩＳ０）｝…（６）
と示されるが、実際のデバイスはＩＳ０の温度特性が主であるため、ＶＦ１としては例えば約−２ｍＶ／℃という物理的定数から決定される負の温度特性を有している。
【００３９】
従って、式（５）で示される出力電圧Ｖｂｇｏｕｔは
δ（ＶＦ１）／δＴ＝−Ｌ＊（ｋ／ｑ）＊ｌｎ（Ｍ＊Ｎ）…（７）
となる条件のもとで、ほぼ温度依存性のない状態を得て、約１．２Ｖの電圧を発生し得る。要するに、ΔＶＦ＝ＶＦ１−ＶＦ２は物理定数だけで決まり、抵抗２２の端子間電圧はＲ２２＊Ｉ４１＝Ｒ２２＊ΔＶＦ／Ｒ２１となって抵抗２１，２２による正の温度特性を持ち、ＶＦ１はＰＮ接合の負の温度特性を持ち、前記正の温度特性と負の温度特性がほぼ相殺されて、ほぼ温度依存性のない状態で約１．２Ｖの基準電圧を発生する。
【００４０】
図２の回路から図１の回路に至る前の回路として図３の基準電圧発生回路を検討した。図３の回路において図２の回路構成と異なるところは、第１に、電流Ｉ４１とＩ４２の発生に抵抗を用いるかわりにＭＯＳ（ＭｅｔａｌＯｘｃｉｄｅＳｅｍｉｃｏｎｄｕｃｔｏｒ）トランジスタの電流源ペアのＰＭＯＳトランジスタ１とＰＭＯＳトランジスタ２を用い、第２に、電圧比較用ダイオード１１、１２と異なるペアダイオード１３と、前述のＰＭＯＳトランジスタ１，２と異なるｐチャンネル型ペア電流源ＭＯＳトランジスタ３と、抵抗２４を別回路系に設けて出力電圧Ｖｂｇｏｕｔを得る点である。電流源ＭＯＳトランジスタ１，２，３を用いることで比較回路３１の動作レンジを有利にしている。要するに、図２よりも電源電圧ＶＤＤが低くても比較回路３１の動作を保証することができる。
【００４１】
図３の基準電圧発生回路の作用を説明する。図３において、ダイオード１１、１２、１３の面積比が１：Ｎ：Ｋ１（Ｋ１は正の実数）であって、電流源ＭＯＳトランジスタ１、２、３のそれぞれの電流Ｉ４１、Ｉ４２とＩ４３には、
Ｉ４１：Ｉ４２：Ｉ１３＝Ｍ：１：（Ｍ＊Ｋ２）
の関係（Ｋ２は正の実数）があり、比較回路３１によるフィードバック制御がかかることによって、抵抗２１（抵抗値＝Ｒ２１）には、上述の図２と同様な考え方に基き、
ΔＶ＝（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）…（８）
の電圧差が発生し、
Ｉ４２＝（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１…（９）
が流れる。すると
Ｉ４１＝Ｍ＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１…（１０）
Ｉ４３＝（Ｍ＊Ｋ２）＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１…（１１）
という電流が供給され、ダイオード１１と１３の順方向電圧ＶＦ１、ＶＦ３は単位面積あたりの電流密度が異なる分だけ、以下の
ＶＦ１＝ＶＦ３＋（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｋ１／Ｋ２）…（１２）
というずれが発生する。このとき、抵抗２１と抵抗２４（抵抗値＝Ｒ２４）が
Ｒ２４＝Ｌ／（Ｍ＊Ｋ２）＊Ｒ２１…（１３）
で設定されていると、その結果、
Ｖｂｇｏｕｔ＝ＶＦ３＋Ｌ＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）…（１４）
が出力される。この場合、
δ（Ｖｂｇｏｕｔ）／δＴ＝δＶＦ３／δＴ＋Ｌ＊（ｋ／ｑ）＊ｌｎ（Ｍ＊Ｎ）＝０…（１５）
となり、これにより、
δＶＦ３／δＴ＝−Ｌ＊（ｋ／ｑ）＊ｌｎ（Ｍ＊Ｎ）…（１６）
という設定で温度依存のない基準電圧Ｖｂｇｏｕｔが発生される。
【００４２】
具体的に、Ｋ１＝１、Ｋ２＝１では、式（１２）からＶＦ１＝ＶＦ３であり、式（１４）（１６）は図２で説明した式（５）（７）と同一の結果が得られる。
【００４３】
半導体集積回路では微細プロセス化が図られ、０．２μｍ以下の微細プロセスに進むと、デバイスの耐圧が下がり、供給可能な電源電圧も１．５V以下に下がり、結果的に上述の図２、図３の約１．２Ｖ近傍の電圧を発生するバンドギャップ型基準電圧発生回路では、低電圧での動作つまり動作開始最小電源電圧の確保が困難になるという問題点がある。具体的には、上述した図２および図３で示した基準電圧発生方式においては、比較回路３０，３１の動作特性にリニアリティを保証できる範囲の動作電源を用いることが条件であり、供給電源電圧ＶＤＤがＶｂｇｏｕｔより十分大きいことも必須であり、微細プロセスでの電源電圧が例えば１．５Ｖ以下に下がり、Ｖｂｇｏｕｔ＝約１．２Ｖと同等の電源電圧では温度補償された基準電圧を供給することが出来なくなる。これを解消するのが図１の回路である。
【００４４】
図１に示す回路動作について詳述する。ダイオード１１、１２、１３があって、それらのの面積比が１：Ｎ：Ｋ１であって、それぞれに接続されたｐチャンネル型電流源ＭＯＳトランジスタ１、２、３のそれぞれの電流Ｉ４１、Ｉ４２とＩ４４には、
Ｉ４１：Ｉ４２：Ｉ４４＝Ｍ：１：（Ｍ＊Ｋ２）
の関係（Ｍ＊Ｋ２＞１）があり、比較回路３１によるフィードバック制御がかかることによって、抵抗２１（抵抗値＝Ｒ２１）には、式（８）に示される、
ΔＶ＝（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）
の電圧差ΔＶが発生し、かつ同じく式（９）、（１０）に示される
Ｉ４２＝（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１
Ｉ４１＝Ｍ＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１
による電流Ｉ４２、Ｉ４１が流れる。また、Ｉ４４として
Ｉ４４＝（Ｍ＊Ｋ２）＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）／Ｒ２１…（１７）
という電流が供給される。電流Ｉ４４の負荷回路として、抵抗２５とダイオード１３の直列接続回路と、抵抗２６があって、これらから仮の出力電圧Ｖｂｇｏｕｔ’を求めると、
Ｖｂｇｏｕｔ’＝（Ｍ＊Ｋ２）＊（Ｒ２６／Ｒ２１）＊（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）＊Ｒ２５／（Ｒ２６＋Ｒ２５）＋ＶＦ３＊Ｒ２６／（Ｒ２６＋Ｒ２５）…（１８）
となる。これに温度微分を施すと、
δ（Ｖｂｇｏｕｔ’）／δＴ＝（Ｍ＊Ｋ２）＊（Ｒ２６／Ｒ２１）＊（ｋ／ｑ）＊ｌｎ（Ｍ＊Ｎ）＊Ｒ２５／（Ｒ２６＋Ｒ２５）−Ｌ＊（ｋ／ｑ）＊ｌｎ（Ｍ＊Ｎ）＊Ｒ２６／（Ｒ２６＋Ｒ２５）…（１９）
となる。式（１９）で示された温度係数がゼロとなる条件を求めると、
（Ｍ＊Ｋ２）＊Ｒ２５＝Ｌ＊Ｒ２１…（２０）
となる。これを式（１８）に代入すると、
Ｖｂｇｏｕｔ’＝Ｒ２６／（Ｒ２６＋Ｌ＊Ｒ２１／（Ｍ＊Ｋ２））＊{（ｋ＊Ｔ／ｑ）＊ｌｎ（Ｍ＊Ｎ）＊Ｌ＋ＶＦ３}…（２１）
と示される。これをさらに式（１４）の関係を用いて表わすと、
Ｖｂｇｏｕｔ’＝Ｒ２６／（Ｒ２６＋Ｌ＊Ｒ２１／（Ｍ＊Ｋ２））＊Ｖｂｇｏｕｔ…（２２）
となる。つまり、
Ｒ２６／（Ｒ２６＋Ｌ＊Ｒ２１／（Ｍ＊Ｋ２））＜１
であるから、
Ｖｂｇｏｕｔ'＜Ｖｂｇｏｕｔ
となる温度依存のない出力電圧を得ることが出来ることを意味する。
【００４５】
なお、ダイオード１３にＩ４２同等のレベルの電流Ｉ４５を流すには、
Ｉ４２＊Ｒ２５＋ＶＦ３（Ｉ４２）≒Ｉ４２＊（Ｍ＊Ｋ２―１）＊Ｒ２６
である必要がある。即ち、
ＶＦ３（Ｉ４２）≒Ｉ４２＊｛（Ｍ＊Ｋ２―１）＊Ｒ２６−Ｒ２５｝
であることが必要である。従って、少なくとも、Ｍ＊Ｋ２＞１、Ｒ２６＞Ｒ２５が必要とされる。
【００４６】
図１の回路特性を具体的数値例で示す。例えば、
Ｍ＊Ｋ２＝２、
Ｒ２５＝Ｌ＊Ｒ２１／２
Ｒ２６＝１．５＊Ｌ＊Ｒ２１
とすると、
Ｖｂｇｏｕｔ’＝Ｒ２６／（Ｒ２６＋Ｌ＊Ｒ２１／（Ｍ＊Ｋ２））＊Ｖｂｇｏｕｔ
Ｖｂｇｏｕｔ’＝{１．５／（１．５＋０．５）}＊Ｖｂｇｏｕｔ
Ｖｂｇｏｕｔ’＝０．７５＊Ｖｂｇｏｕｔ
Ｖｂｇｏｕｔ’≒０．９Ｖ
が得られることになる。また、別の例では、
Ｍ＊Ｋ２＝３／２
Ｒ２５＝２＊Ｌ＊Ｒ２１／３
Ｒ２６＝（４／３）＊Ｌ＊Ｒ２１
とすると、
Ｖｂｇｏｕｔ’＝{（４／３）／（４／３＋２／３）}＊Ｖｂｇｏｕｔ
Ｖｂｇｏｕｔ’＝２／３＊Ｖｂｇｏｕｔ
Ｖｂｇｏｕｔ’≒０．８Ｖ
が得られ、１．２Ｖよりも低い基準電圧が得られることが示される。
【００４７】
図１の回路構成では、３つの抵抗２１，２５，２６のペア性と、３つのダイオード１１，１２，１３のペア性と、３つのＭＯＳトランジスタ１，２，３のペア性により、出力電圧Ｖｂｇｏｕｔのバラツキが決定されるが、本回路をマイクロアンペアのオーダの低電流で実現する場合、抵抗２６は５００ｋΩ以上の抵抗になり、他の抵抗２１、２５とのペア性を確保する必要があるが、これらは抵抗２６よりも小さい抵抗でありペア性が採り易いというメリットがある。
【００４８】
図４には本発明に係る半導体集積回路が保有する基準電圧発生回路の第２の例が示される。図４では、図１に示したダイオード１１、１２、１３の代わりにダイオード接続されたＮＰＮバイポーラトランジスタ５１、５２、５３を採用する。それらのＰＮ接合の面積比は、同様に１：Ｎ：Ｋ１で、同様な条件で低電圧の基準電圧を発生することができる。
【００４９】
図５には本発明に係る半導体集積回路が保有する基準電圧発生回路の第３の例が示される。図５では、図１に示したダイオード１１、１２、１３の代わりに、ダイオード接続されたＰＮＰバイポーラトランジスタ６１、６２、６３を採用する。それらのＰＮ接合の面積比は、同様に１：Ｎ：Ｋ１で、同様な条件で低電圧の基準電圧を発生することができる。
【００５０】
図６には本発明に係る半導体集積回路が保有する基準電圧発生回路の第４の例が示される。図６の構成は、図１のｐチャンネル型電流源ＭＯＳトランジスタをそれとコンプリメンタリなｎチャンネル型電流源ＭＯＳトランジスタ８１，８２，８３で構成し、電流源ＭＯＳトランジスタ８１，８２，８３は比較回路３４の出力によってコンダクタンス制御され、ダイオード７１，７２，７３は電源端子３２側に配置される。この基準電圧発生回路は、電源端子３２の電源電圧ＶＤＤに対して端子３３に基準電圧を出力する回路形式とされる。
【００５１】
図７には本発明に係る半導体集積回路が保有する基準電圧発生回路の第５の例が示される。図７の構成は、図１に示したｐチャンネル型電流源ＭＯＳトランジスタ１，２，３の他に、ｐチャンネル型ＭＯＳトランジスタ４、５、６とバイアス端子３５を設けて、電流源をカスコード接続にして、電源端子３２の電源電圧ＶＤＤが大きく変化しても各ＭＯＳトランジスタの耐圧電圧を越さないようにする一方、電源電圧依存性を低減させる構成としている。
【００５２】
図８には本発明に係る半導体集積回路が保有する基準電圧発生回路の第６の例が示される。図８の構成は、図１に示した出力端子３３から出力を得るよりも更に低電圧を発生可能にするものである。即ち、図１の抵抗２６を分割して２６ａと２６ｂの抵抗で分割電圧を分圧端子３６に発生する。この分圧端子３６の分割電圧も上述した端子３３の出力電圧と同様の温度特性や電源電圧依存特性を持つ。要するに、温度依存性や電源電圧依存性が低減され、更にレベルの低い基準電圧を生成することができる。
【００５３】
図９には本発明に係る半導体集積回路が保有する基準電圧発生回路の第７の例が示される。図９の構成は、図１の構成に対し、出力再生部ＲＧＮの抵抗２６とダイオード１３に回路の接地電圧ＶＳＳとは異なる別の電圧Ｖｂｉｓを印加するようにしたものである。例えば電圧Ｖｂｉｓをアナロググランドとして動作するアナログ回路に端子３３の電圧を基準電圧として用いるような場合に好適である。
【００５４】
図１０には本発明に係る半導体集積回路が保有する基準電圧発生回路の第８の例が示される。図１０の構成は、図４の構成に対し、図９と同じく出力再生部ＲＧＮの抵抗２６とダイオード１３に回路の接地電圧ＶＳＳとは異なる別の電圧Ｖｂｉｓを印加するようにしたものである。例えば電圧Ｖｂｉｓをアナロググランドとして動作するアナログ回路に端子３３の電圧を基準電圧として用いるような場合に好適である。
【００５５】
図１１には本発明に係る半導体集積回路が保有する基準電圧発生回路の第９の例が示される。図１１の構成では、前記出力再生部ＲＧＮは前記制御電圧Ｖｃをゲートに受けて制御される電流制御ＭＯＳトランジスタ７とこれに直列されたダイオード接続形態の電流源ＭＯＳトランジスタ８を有する。前記バンドギャップ部ＢＧＰは前記電流源ＭＯＳトランジスタ８とカレントミラー形態で接続された電流源ＭＯＳトランジスタ１，２を有する。特に図示はしないが、比較回路３１の反転入力端子（−）と反転入力端子（＋）を入れ替え、電流制御ＭＯＳトランジスタ７をｎチャンネル型に変更してもよい。
【００５６】
図１２には本発明に係る半導体集積回路の一例であるマイクロコンピュータが例示される。同図に示されるマイクロコンピュータ１０１は、特に制限されないが、単結晶シリコンなどの１個の半導体基板若しくは半導体チップにＣＭＯＳなどの半導体集積回路製造技術によって形成される。
【００５７】
マイクロコンピュータ１０１は、ＣＰＵ１０２、ワークＲＡＭとしてのＲＡＭ（ランダム・アクセス・メモリ）１０４、タイマ１０５、フラッシュメモリ１０６、クロック生成回路１０９、マスクＲＯＭ（リード・オンリ・メモリ）１１０、システムコントロールロジック１１１、入出力ポート（Ｉ／Ｏポート）１１２、データバス１１３、アドレスバス１１４、基準電圧発生回路１１５、及びその他周辺回路ユニット１０７を有する。
【００５８】
前記マスクＲＯＭ１１０はＣＰＵ１０２の動作プログラム（インタフェース制御プログラム等）及びデータを格納するのに利用される。前記ＲＡＭ１０４はＣＰＵ１０２のワーク領域又はデータの一時記憶領域とされ、例えばＳＲＡＭ（スタティック・ランダム・アクセス・メモリ）若しくはＤＲＡＭ（ダイナミック・ランダム・アクセス・メモリ）から成る。前記ＣＰＵ１０２は、マスクＲＯＭ１１０から命令をフェッチし、フェッチした命令をデコードし、デコード結果に基づいてオペランドフェッチやデータ演算を行う。その他集権回路ユニット１０７は、Ａ−Ｄ変換器１２０、Ｄ−Ａ変換器１２１、及びパワーオンリセット回路１２２を有する。Ｉ／Ｏポート１１２はデータの入出力と外部割り込み信号の入力等に利用される。Ｉ／Ｏポート１１２はデータバス１１３に結合され、データバス１１３には前記ＣＰＵ１０２、ＲＡＭ１０４、タイマ１０５、フラッシュメモリ１０６、及びその他周辺回路ユニット１０７等が接続される。マイクロコンピュータ１０１においてＣＰＵ１０２がバスマスタモジュールとされ、前記ＲＡＭ１０４、タイマ１０５、フラッシュメモリ１０６、マスクＲＯＭ１１０及びその他周辺回路ユニット１０７に接続されるアドレスバス１１４にアドレス信号を出力可能にされる。システムコントロールロジック１１１はマイクロコンピュータ１０１の動作モードの制御及び割り込み制御を行う。マイクロコンピュータ１はリセット動作が指示されると、内部が初期化され、ＣＰＵ１０２はフラッシュメモリ１０６のプログラムの先頭番地から命令実行を開始する。クロック生成回路１０９は外部クロック信号ＣＬＫを受けて内部クロック信号ＣＫを生成する。マイクロコンピュータ１０１は内部クロック信号ＣＫに同期動作される。
【００５９】
前記フラッシュメモリ１０６は、記憶情報を電気的に消去処理及び書込み可能にされる。フラッシュメモリ１０６に代えてＥＥＰＲＯＭ（エレクトリカリ・イレーザブル・アンド・プログラマブル・リード・オンリ・メモリ）或は高誘電体メモリなどの不揮発性メモリを採用してもよい。
【００６０】
前記基準電圧発生回路１１５は図１、図４乃至図１１で説明した回路構成を備え、これによって生成される基準電圧Ｖｂｇｏｕｔ’は、例えば、Ａ−Ｄ変換器１２０、Ｄ−Ａ変換器１２１に供給されて変換の基準電圧に利用され、パワーオンリセット回路１２２に供給されてパワーオン電圧検出基準にされ、また、フラッシュメモリ１０６に供給されて消去・書き込み用高電圧を生成するチャージポンプ回路の昇圧制御電圧に利用される。基準電圧Ｖｂｇｏｕｔ’は、電源電圧ＶＤＤが１．５Ｖ程度であっても０．８Ｖのような電圧である。これにより、マイクロコンピュータ１０１は低基準電圧を生成可能という点において低電圧動作もしくは微細プロセスに好適である。
【００６１】
図１３には前記マイクロコンピュータ１０１を適用した電子回路としてプロセッサボード１３９の概略的な構成が例示される。プロセッサボード１３９はプリント配線基板に種々の半導体集積回路チップや回路モジュールが実装されて構成される。このプロセッサボード１３９に実装されたマイクロコンピュータ１０１には、ノースブリッジ（North Bridge）と呼ばれるチップセット等のブリッジチップ１４１が接続され、このブリッジチップ１４１にグラフィックチップ１４２、ＳＤＲＡＭ（シンクロナス・ダイナミック・ランダム・アクセス・メモリ）等から成るメインメモリ１４３、ＰＣＩ（ペリフェラル・コンポーネント・インターコネクト）バス１４４が接続される。グラフィックチップ１４２には図示を省略する液晶ディスプレイが接続される。ＰＣＩバス１４４にはサウスブリッジ（South Bridge）と呼ばれるチップセット等のブリッジチップ１４５、モデムユニット１４６等が接続される。ブリッジチップ１４５はＩＤＥ（インテグレーテッド・デバイス・エレクトロニクス）ポート１４８、ＩＳＡ（インダストリー・スタンダード・アーキテクチャ）バス１４９、ＵＳＢバス１５０に接続される。前記ＩＤＥポート１４８にはそれぞれ図示を省略するＣＤ−ＲＯＭ（コンパクト・ディスク−リード・オンリ・メモリ）やＨＤＤ（ハード・ディスク・ドライブ）等が接続される。ＩＳＡバス（又はＬＰＣ）１４９にはサウンドユニット１５２などが接続される。ＵＳＢバス１５０にはＵＳＢインタフェース回路１５３接続され、メモリカード等が着脱可能にされる。
【００６２】
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。例えば、電流源はトランジスタと他のデバイス例えば抵抗を組み合わせて構成してもよい。比較回路を構成する差動アンプの構成については適宜選択可能である。本明細書においてＭＯＳトランジスタは絶縁ゲート電界効果型トランジスタを総称する。本発明は、基準電圧発生回路を備えた半導体集積回路、ならびに当該当該半導体集積回路を適用した電子回路に広く利用することができる。
【００６３】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記の通りである。
【００６４】
すなわち、基準電圧発生回路の出力再生部を構成する接合型負荷素子と抵抗の直列径路に並列に抵抗を設けたから、温度補償と電源電圧補償された約１．２Ｖ以下の基準電圧を発生することが可能である。もしくは、約１．２Ｖの基準電圧を発生するバンドギャップ型基準電圧発生回路の電源電圧以下の供給電源電圧で、温度補償と電源電圧補償された基準電圧を発生することが可能である。更に、基準電圧発生回路はバンドギャップ部に２つの電流源径路を持ち、出力再生部に１つの電流源径路を持てば充分であるから、回路素子数も少なくすることが可能である。
【図面の簡単な説明】
【図１】本発明に係る半導体集積回路が保有する基準電圧発生回路にＰＮ接合ダイオードを用いた第１の例を示す回路図である。
【図２】バンドギャップ型基準電圧発生回路の基本型を例示する回路図である。
【図３】図１の回路構成を発展させて図１の回路に至る前の基準電圧発生回路を例示する回路図である。
【図４】本発明に係る半導体集積回路が保有する基準電圧発生回路にＮＰＮバイポーラトランジスタを用いた第２の例を示す回路図である。
【図５】本発明に係る半導体集積回路が保有する基準電圧発生回路にＰＮＰバイポーラトランジスタを用いた第３の例を示す回路図である。
【図６】本発明に係る半導体集積回路が保有する基準電圧発生回路に図１とは導電型の異なる電流源ＭＯＳトランジスタをを用いた第４の例を示す回路図である。
【図７】本発明に係る半導体集積回路が保有する基準電圧発生回路にカスコード接続形態の電流源を用いた第５の例を示す回路図である。
【図８】本発明に係る半導体集積回路が保有する基準電圧発生回路に並列抵抗の分圧電圧出力形式を採用した第６の例を示す回路図である。
【図９】本発明に係る半導体集積回路が保有する基準電圧発生回路の第７の例を示す回路図である。
【図１０】本発明に係る半導体集積回路が保有する基準電圧発生回路の第８の例を示す回路図である。
【図１１】本発明に係る半導体集積回路が保有する基準電圧発生回路の第９の例を示す回路図である。
【図１２】本発明に係る半導体集積回路の一例であるマイクロコンピュータを例示するブロック図である。
【図１３】図１２の前記マイクロコンピュータを適用した電子回路としてプロセッサボード３９の概略的な構成を例示するブロック図である。
【符号の説明】
１、２、３、４、５、６、７、８ｐチャンネル型ＭＯＳトランジスタ
１１、１２、１３、７１、７２、７３ＰＮ接合ダイオード
２１、２２、２３、２４、２５、２６、２６ａ，２６ｂ抵抗
３０、３１、３４比較回路
３２電源端子
３３基準電圧出力端子
３５バイアス端子
３６分圧端子
５１、５２、５３ＮＰＮバイポーラトランジスタ
６１，６２、６３ＰＮＰバイポーラトランジスタ
８１、８２、８３ｎチャンネル型ＭＯＳトランジスタ
１０１マイクロコンピュータ
１０２ＣＰＵ
１３９プロセッサボード[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reference voltage generation technique for a semiconductor integrated circuit, particularly to a bandgap type low reference voltage generation circuit, and includes a power-on reset function, an electrically erasable and writable nonvolatile memory, and the like, which is operated at a low voltage. The present invention relates to a technique that is effective when applied to a microcomputer.
[0002]
[Prior art]
The functions of the semiconductor integrated circuit requiring the reference voltage include, for example, an initialization operation of a digital circuit, a so-called power-on reset function, an A / D conversion (analog / digital conversion) function, and a D / A conversion (digital / analog conversion) function. , An EEPROM (Electrical Erasable Programmable Read Only Memory), a circuit for generating a high voltage for writing by a charge pump, a voltage regulator, and the like.
[0003]
The power-on reset function of a circuit is a function of resetting a predetermined circuit output state to a predetermined state when the power supply voltage reaches a predetermined power supply voltage.To generate the reset signal, the power supply voltage must be reset. Requires a reference voltage to monitor. Specific semiconductor integrated circuits that require a power-on reset function include microcomputers, digital circuits for digitally processing video and audio signals, mixed analog / digital circuits, and communication and information represented by portable devices and personal computers. It is a digital circuit or a mixed analog / digital circuit for signal processing in equipment.
[0004]
In an AD conversion circuit or a DA conversion circuit, a reference voltage is required to calibrate an analog signal amount or to convert the analog signal amount into a specified analog amount. Further, when a high voltage required for writing to a memory such as an EEPROM is generated by a charge pump, a reference voltage is required to control the boosted voltage to a voltage within a predetermined range.
[0005]
Conventional reference voltage generation circuits include a bandgap type using a PN junction diode or a PN junction of a bipolar transistor in order to reduce temperature dependency and power supply voltage dependency.
[0006]
Patent Document 1 controls both current sources so that a series connection node voltage of a PN junction diode and a current source matches a series connection node voltage of a circuit in which a resistor is connected to the diode and a current source, and separates the two. The current source is controlled, and the current source is used to regenerate a current having a correlation with the current flowing in the series path of the diode and the current source, and to cancel the negative temperature characteristic of the diode. A circuit configuration in which a resistor is inserted is disclosed.
[0007]
Patent Literature 2 discloses a reference voltage generation circuit corresponding to a lower reference voltage. That is, a bias voltage is formed by using a diode-connected bipolar transistor, and a diode-connected bipolar transistor is inserted into one of the current paths each having a current source bipolar transistor controlled by the bias voltage. Disclosed is a configuration in which a series connection of resistors is inserted between collectors of bipolar transistors to obtain a low reference voltage from a connection point of the series connection.
[0008]
Patent Literature 3 discloses a configuration in which a forward voltage at a PN junction of a diode and a difference between the voltages are subjected to current conversion and then added to generate a reference voltage or a reference current having an arbitrary value while eliminating temperature dependency.
[0009]
[Patent Document 1]
JP-A-2000-242349
[Patent Document 2]
JP-A-8-36435
[Patent Document 3]
JP-A-11-45125
[0010]
[Problems to be solved by the invention]
The inventor has studied lowering the reference voltage. That is, the power supply voltage of the conventional semiconductor device of the 0.5 μm process or the 0.35 μm process is 5 V or 3 V, and the voltage around 1.2 V generated by the bandgap type reference voltage generating circuit is used as the reference voltage. It was easy to use in terms of circuitry. However, in semiconductor integrated circuits, microfabrication is being pursued. With the progress of microfabrication of 0.2 μm or less, the breakdown voltage of the device is reduced, and the power supply voltage that can be supplied is also reduced to 1.5 V or less. It has been clarified that the bandgap reference voltage generating circuit that generates a voltage of about 0.2 V has a problem that it is difficult to operate at a low voltage, that is, to secure a minimum power supply voltage at which operation is started. Specifically, for example, in Patent Document 1, the operation of a differential amplifier that compares a series connection node voltage of a PN junction diode and a current source with a series connection node voltage of a circuit in which a resistor is connected to the diode and a current source is described. It is essential that the characteristics have linearity and the operating power supply voltage is sufficiently higher than the reference voltage. For example, the power supply voltage in the fine process is reduced to 1.5 V or less, and the power supply voltage is equivalent to the reference voltage of about 1.2 V. It becomes impossible to generate a temperature-compensated reference voltage. The techniques described in Patent Documents 2 and 3 can contribute to lowering the reference voltage, but the number of circuit elements is large and the chip occupation area is large.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit having a reference voltage generating circuit capable of generating a reference voltage of about 1.2 V or less which is temperature compensated and power supply voltage compensated and capable of reducing the number of circuit elements. It is another object of the present invention to provide a circuit and an electronic circuit to which the semiconductor integrated circuit is applied.
[0012]
It is another object of the present invention to generate a temperature-compensated and power-supply-voltage-compensated reference voltage at a power supply voltage equal to or lower than the power supply voltage of a bandgap-type reference voltage generation circuit that generates a reference voltage of about 1.2 V. It is an object of the present invention to provide a semiconductor integrated circuit including a reference voltage generation circuit capable of reducing the number of circuit elements and an electronic circuit to which the semiconductor integrated circuit is applied.
[0013]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0015]
[1] A semiconductor integrated circuit includes a reference voltage generation circuit, and the reference voltage generation circuit generates a first voltage and a second voltage based on a current difference flowing between a pair of junction-type load elements via a current source. A comparison that generates a bandgap portion and a control signal used to control a current flowing through the pair of junction-type load elements via the current source so as to match the first voltage and the second voltage. And an output reproducing unit that has a series circuit of a junction type load element and a resistor and reproduces a current proportional to a current flowing through the junction type load element of the band gap part in the series circuit based on the control signal. . A resistor is connected in parallel to the series circuit of the output reproduction unit, and a reference voltage is extracted from the output reproduction unit.
[0016]
The reference voltage generation circuit is configured to control the bandgap unit by a control signal that matches a first voltage and a second voltage generated based on a difference between currents flowing through a pair of junction-type load elements of the bandgap unit. A predetermined current proportional to the current in the band gap portion is caused to flow through the output reproducing portion, which is another current path. The current path of the output regeneration unit includes a series circuit of a junction type load element and a resistor and a resistor parallel to the series circuit, and a voltage at a connection node between the series circuit and the parallel resistor is lower than that in a case where the parallel resistor is not arranged. Can be. The junction-type load element in the current path of the output regeneration section has a negative temperature characteristic, the resistance has a positive temperature characteristic that tends to offset the negative temperature characteristic, and a pair of junction-type loads in the band gap section. An attempt is made to make the current difference flowing through the element independent of the power supply voltage. Therefore, it is possible to generate a reference voltage of about 1.2 V or less which is temperature compensated and power supply voltage compensated. Alternatively, it is possible to generate a reference voltage that has been subjected to temperature compensation and power supply voltage compensation with a supply power supply voltage that is equal to or less than the power supply voltage of a bandgap reference voltage generation circuit that generates a reference voltage of about 1.2 V. In addition, the reference voltage generation circuit has two current source paths in the band gap section and one current source path in the output reproduction section. It is sufficient that the number of circuit elements can be reduced.
[0017]
In a specific embodiment of the present invention, the band gap section includes a current source MOS transistor which is controlled by receiving the first signal at a gate as a current source. The output reproducing unit includes a current source MOS transistor controlled by receiving the first signal at a gate. In another specific embodiment, the output reproducing section includes a current control MOS transistor controlled by receiving the first signal at a gate, and a diode-connected current source MOS transistor in series with the MOS transistor. The band gap section includes a current source MOS transistor connected to the current control MOS transistor in a current mirror form.
[0018]
[2] A reference voltage generation circuit for a semiconductor integrated circuit according to still another aspect of the present invention includes a first voltage at a connection node in which a first current source is connected in series to a first junction-type load element; The first current source and the second current source are controlled so that a second voltage of a connection node in which a second current source is connected in series with a series path of the junction type load element and the first resistor is made equal. A first circuit for generating a control voltage, a third current source controlled by the control voltage connected in series to a series path of a third junction load element and a second resistor, and the third junction load There is provided a reference voltage generating circuit comprising a second circuit in which a third resistor is connected in parallel to a series path of the element and the second resistor, and a reference voltage is extracted from the second circuit.
[0019]
The reference voltage generating circuit is configured to control the current source so as to make the first voltage and the second voltage coincide with each other, and to the second circuit, which is another current path, by using the second junction-type load element. A predetermined current proportional to the current flowing through the first resistor and the second current source flows. The current path of the second circuit includes a series circuit of a third junction-type load element and a second resistor, and a third resistor in parallel with the third junction-type load element. This can be reduced compared to the case where the third resistor is not provided. The third junction-type load element in the current path of the second circuit has a negative temperature characteristic, the second and third resistors have a positive temperature characteristic that attempts to cancel the negative temperature characteristic, and The difference between the current flowing in the series circuit of the first junction type load element and the first current source and the current flowing in the series circuit of the second junction type load element, the first resistor and the second current source Is made independent of the power supply voltage. Therefore, it is possible to generate a reference voltage of about 1.2 V or less which is temperature compensated and power supply voltage compensated. Alternatively, it is possible to generate a reference voltage that has been subjected to temperature compensation and power supply voltage compensation with a supply power supply voltage that is equal to or less than the power supply voltage of a bandgap reference voltage generation circuit that generates a reference voltage of about 1.2 V. In addition, the reference voltage generating circuit has two current source paths to generate the first and second voltages, and it is sufficient to have one current source path in the second circuit, so that the number of circuit elements is small. It is possible to do.
[0020]
The first to third junction-type load elements are, for example, PN junction diodes or diode-connected bipolar transistors. The first to third current sources are, for example, p-channel MOS transistors or n-channel MOS transistors.
[0021]
The reference voltage is a voltage at a connection node where a third current source is connected in series to a series path of the third junction load element and a second resistor. Further, the reference voltage is a voltage of a predetermined voltage dividing node of the third resistor. The generated reference voltage can be lower in the latter than in the former.
[0022]
[3] A reference voltage generating circuit for a semiconductor integrated circuit according to a more specific embodiment of the present invention will be described.
[0023]
As a first example, a PN junction diode is used as a junction type load element. That is, the reference voltage generating circuit includes a first current source, a second current source, and a third current source having a predetermined current value ratio, a first PN junction diode having a predetermined area ratio, and a second PN junction diode. And a third PN junction diode, a first resistor, a second resistor, and a third resistor having a predetermined resistance ratio, and a comparison circuit for commonly controlling the first to third current sources. The first current source generates a first voltage using the first PN junction diode as a load circuit, and the second constant current source includes a second PN junction diode and a first resistor connected in series. A second voltage is generated by using a first series connection circuit connected to the first circuit as a load circuit, and the comparison circuit compares the first voltage with the second voltage, and compares the first voltage with the second voltage. The first to third current sources are commonly controlled so that the second voltage is the same. The third current source includes a second series connection circuit in which the third PN junction diode and a second resistance are connected in series, and a third resistance in parallel with the second series connection circuit. Connected to the connected load circuit. The reference voltage generation circuit outputs the third voltage as a reference voltage.
[0024]
As a second example, a bipolar transistor diode-connected to a junction type load element is used. That is, the reference voltage generating circuit includes a first current source, a second current source, and a third current source having a predetermined current value ratio, a first diode-connected bipolar transistor having a predetermined area ratio, and a second current source. A diode-connected bipolar transistor and a third diode-connected bipolar transistor, a first resistor, a second resistor, and a third resistor having a predetermined resistance ratio, and the first to third current sources. And a comparison circuit that performs common control. The first current source generates a first voltage using the first diode-connected bipolar transistor as a load circuit. The second constant current source generates a second voltage using a first series connection circuit in which the second diode-connected bipolar transistor and a first resistor are connected in series as a load circuit. The comparison circuit compares the first voltage and the second voltage, and commonly uses the first to third current sources so that the first voltage and the second voltage are the same. Control. The third current source includes a second series connection circuit in which the third diode-connected bipolar transistor and a second resistor are connected in series, and a third current source in parallel with the second series connection circuit. Is connected to the connected load circuit. The reference voltage generation circuit outputs the third voltage as a reference voltage.
[0025]
As a third example, a reference voltage is generated using a potential such as an analog ground that is different from the ground potential of the circuit. That is, the reference voltage generation circuit includes a first current source, a second current source, and a third current source having a predetermined current value ratio, a first bipolar transistor, a second bipolar transistor, and a predetermined area ratio. It comprises a third bipolar transistor, a first resistor, a second resistor and a third resistor having a predetermined resistance ratio, and a comparison circuit for commonly controlling the three current sources. The first current source generates a first voltage using the first bipolar transistor as a load circuit. The second constant current source generates a second voltage using a first series connection circuit in which the second bipolar transistor and a first resistor are connected in series as a load circuit. The comparison circuit compares the first voltage and the second voltage, and commonly uses the first to third current sources so that the first voltage and the second voltage are the same. Control. The third current source is connected to a second series connection circuit in which the third bipolar transistor and a second resistor are connected in series, and a third resistor is connected in parallel with the second series connection circuit. Connected to the specified load circuit. The base potentials of the first and second bipolar transistors are biased to a common fourth potential. The base potential of the third bipolar transistor and the third resistor are biased to potentials different from the fourth potential. The reference voltage generation circuit outputs the third voltage as a reference voltage.
[0026]
Similarly, in the first example, the first PN junction diode and the second PN junction diode are connected to a common fourth potential, and the third PN junction diode and the third resistor are connected to the fourth PN junction diode and the fourth resistor. May be biased to a potential different from that of. In the second example, the first diode-connected bipolar transistor and the second diode-connected bipolar transistor are connected to a common fourth potential, and the third diode-connected bipolar transistor and The third resistor may be biased to a potential different from the fourth potential.
[0027]
In the first to third examples, the third resistor may be divided into two parts at a predetermined voltage dividing ratio, and a reference voltage may be extracted from a coupling node at the two division points.
[0028]
The semiconductor integrated circuit is a circuit module for inputting a reference voltage of the reference voltage generation circuit, for example, an A / D conversion module, a D / A conversion module, a voltage regulator, a power-on reset circuit, or a charge pump for generating a high voltage such as a flash memory. Circuit. An electronic circuit is configured by mounting one or more semiconductor integrated circuits different from such a semiconductor integrated circuit on a mounting substrate.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a first example of a reference voltage generating circuit held by a semiconductor integrated circuit according to the present invention.
[0030]
In the reference voltage generating circuit shown in FIG. 1, p-channel type current source MOS transistors 1, 2, and 3 are arranged as a current source having a predetermined current value ratio on the power supply terminal 32 side, and on the ground terminal 35 side of the circuit. PN junction diodes 11, 12, and 13 are arranged as PN junction type load elements having a predetermined area ratio. A resistor 21 is arranged on the current path of the current source MOS transistor 2, and resistors 25 and 26 are arranged on a current path of the current source MOS transistor 3. The resistor 25 is connected in series with the PN junction diode 13, and the resistor 26 is connected in parallel with the series path of the PN junction diode 13. The power supply terminal 32 is supplied with the power supply voltage VDD, and the ground terminal 35 is supplied with the circuit ground voltage VSS.
[0031]
The current source MOS transistor 1 generates a first voltage V1 using the PN junction diode 11 as a load circuit. The current source MOS transistor 2 generates a second voltage V2 using a first series connection circuit in which the PN junction diode 12 and the resistor 21 are connected in series as a load circuit. The comparison circuit 31 compares the first voltage with the second voltage to generate a control voltage Vc, and controls the current source so that the first voltage V1 is equal to the second voltage V2. The MOS transistors 1, 2, 3 are commonly controlled. The comparison circuit 31 is constituted by a differential amplifier. The drain voltage of the current source MOS transistor 3 is output to the output terminal 33 as an output voltage Vbgout ', and this voltage Vbgout' is used as a reference voltage.
[0032]
A circuit including the current source MOS transistors 1 and 2, the resistor 21, and the PN junction diodes 11 and 12 for generating the first voltage and the second voltage V2 is an example of a band gap section BGP. The comparison circuit 31 is an example of a comparison unit CMP. The circuit including the current source MOS transistor 3, the resistors 25 and 26, and the PN junction diode 13 forms an example of an output reproduction unit RGN that reproduces a current proportional to a current flowing through the junction type load element in the band gap portion.
[0033]
The operation of the reference voltage generation circuit will be schematically described. The reference voltage generation circuit is configured to control the first voltage V1 and the second voltage V2 generated based on the current difference between the currents I41 and I42 flowing through the pair of PN junction diodes 11 and 12 of the band gap portion BGP. By Vc, a predetermined current I44 proportional to the current I42 of the bandgap portion is caused to flow through the output reproduction portion RGN, which is a different current path from the bandgap portion BGP. The current path of the output reproduction unit RGN includes a series circuit of the PN junction diode 13 and the resistor 25, and the resistor 26 in parallel with the series circuit. The voltage Vbgout 'of the connection node of the series circuit and the parallel resistor is set when the parallel resistor is not provided. It can be lower than that. The PN junction diode 13 in the current path of the output reproduction unit RGN has a negative temperature characteristic, the resistors 25 and 26 have a positive temperature characteristic that tries to cancel the negative temperature characteristic, and the band gap BGP. The difference between the currents flowing through the pair of PN junction diodes 11 and 12 does not depend on the power supply voltage VDD. Therefore, it is possible to generate a reference voltage of about 1.2 V or less which is temperature compensated and power supply voltage compensated. Alternatively, it is possible to generate a reference voltage that has been subjected to temperature compensation and power supply voltage compensation with a supply power supply voltage that is equal to or less than the power supply voltage of a bandgap reference voltage generation circuit that generates a reference voltage of about 1.2 V. In addition, the reference voltage generating circuit has two current source paths in the band gap section BGP and one current source path in the output reproduction section RGN. It is sufficient to reduce the number of circuit elements.
[0034]
The operation of the reference voltage generating circuit of FIG. 1 will be described in more detail. In order to facilitate understanding, two types of reference voltage generating circuits which are the basis of the present invention will be described with reference to FIGS.
[0035]
FIG. 2 shows a basic type of a bandgap type reference voltage generating circuit. In FIG. 2, the output voltage Vbgout of the terminal 33 is controlled such that the voltage drop caused by the current I41 flowing through the resistor 23 (resistance value = R23) matches the voltage drop caused by I42 flowing through the resistor 22 (resistance value = R22). That is, control is performed so that the forward voltage of the PN junction diode 11 due to the current I41 is equal to the voltage obtained by adding the forward voltage of the diode 12 due to the current I42 and the drop voltage due to the resistor 21 (resistance = R21).
[0036]
The relationship between the forward voltages VF1 and VF2 of the PN junction diodes 11 and 12 and the bias current values I41 and I42 is as follows.
I41 = S11 * IS0 * EXP {q * VF1 / (k * T) -1} (1)
I42 = S12 * IS0 * EXP {q * VF2 / (k * T) -1} (2)
Is shown as
[0037]
Here, with respect to the symbols used in the above equation, IS0 is the saturation current per unit area of the diode, k is the Boltzmann constant, q is the unit charge of electrons, and T means the absolute temperature. The areas of the diodes 11 and 12 are designated as S11 and S12, respectively. * Is a multiplier and / is a division symbol.
[0038]
The forward voltage difference ΔVF = VF1-VF2 between the diodes 11 and 12 is obtained by simplifying the equations (1) and (2).
ΔVF = (k * T / q) * ln {I41 / I42} (3)
Indicated by On the other hand, since I41 / I42 = R22 / R23 = M (M is a positive real number), if S12 / S11 = N (N is a positive real number),
(I41 / I42) * (S12 / S11) = M * N (4)
And R22 / R21 = L (L is a positive real number). Thus, the output voltage Vbgout is
Vbgout = VF1 + L * (k * T / q) * ln (M * N) (5)
Is described. The second term in equation (5) means that the control is performed by the physical constant ratio of the circuit device, and indicates that a positive temperature characteristic is obtained. The first term of the equation (5) indicates the forward voltage of the diode as described above, and is simplified from the equation (3).
VF1 = (k * T / q) * ln {I41 / (S11 * IS0)} (6)
However, since the actual device mainly has the temperature characteristic of IS0, the VF1 has a negative temperature characteristic determined from a physical constant of, for example, about −2 mV / ° C.
[0039]
Therefore, the output voltage Vbgout represented by equation (5) is
δ (VF1) / δT = −L * (k / q) * ln (M * N) (7)
Under the following conditions, a temperature-independent state can be obtained, and a voltage of about 1.2 V can be generated. In short, ΔVF = VF1-VF2 is determined only by the physical constant, the voltage between the terminals of the resistor 22 is R22 * I41 = R22 * ΔVF / R21, and has a positive temperature characteristic by the resistors 21 and 22, and VF1 is a PN junction. It has a negative temperature characteristic, and the positive temperature characteristic and the negative temperature characteristic are almost canceled to generate a reference voltage of about 1.2 V with almost no temperature dependency.
[0040]
As a circuit before the circuit from FIG. 2 to the circuit in FIG. 1, the reference voltage generating circuit in FIG. 3 was studied. 3 is different from the circuit configuration of FIG. 2 in that first, instead of using resistors for generating currents I41 and I42, a PMOS transistor 1 and a PMOS transistor 2 of a current source pair of MOS (Metal Oxide Semiconductor) transistors are used. Second, a pair diode 13 different from the voltage comparison diodes 11 and 12, a p-channel type pair current source MOS transistor 3 different from the PMOS transistors 1 and 2, and a resistor 24 are provided in a separate circuit system and output. The point is that the voltage Vbgout is obtained. The use of the current source MOS transistors 1, 2, 3 makes the operation range of the comparison circuit 31 advantageous. In short, the operation of the comparison circuit 31 can be guaranteed even when the power supply voltage VDD is lower than that in FIG.
[0041]
The operation of the reference voltage generation circuit of FIG. 3 will be described. In FIG. 3, the area ratio of the diodes 11, 12, and 13 is 1: N: K1 (K1 is a positive real number), and the currents I41, I42, and I43 of the current source MOS transistors 1, 2, and 3 are: ,
I41: I42: I13 = M: 1: (M * K2)
(K2 is a positive real number), and the feedback control by the comparison circuit 31 is applied to the resistor 21 (resistance = R21) based on the same concept as in FIG.
ΔV = (k * T / q) * ln (M * N) (8)
Voltage difference occurs,
I42 = (k * T / q) * ln (M * N) / R21 (9)
Flows. Then
I41 = M * (k * T / q) * ln (M * N) / R21 (10)
I43 = (M * K2) * (k * T / q) * ln (M * N) / R21 (11)
Is supplied, and the forward voltages VF1 and VF3 of the diodes 11 and 13 are different as follows due to the difference in current density per unit area.
VF1 = VF3 + (k * T / q) * ln (K1 / K2) (12)
Is generated. At this time, the resistance 21 and the resistance 24 (resistance value = R24)
R24 = L / (M * K2) * R21 (13)
As a result,
Vbgout = VF3 + L * (k * T / q) * ln (M * N) (14)
Is output. in this case,
δ (Vbgout) / δT = δVF3 / δT + L * (k / q) * ln (M * N) = 0 ... (15)
So that
δVF3 / δT = -L * (k / q) * ln (M * N) (16)
Thus, the reference voltage Vbgout having no temperature dependence is generated.
[0042]
Specifically, when K1 = 1 and K2 = 1, VF1 = VF3 from Expression (12), and Expressions (14) and (16) obtain the same results as Expressions (5) and (7) described in FIG. Can be
[0043]
2. Description of the Related Art In semiconductor integrated circuits, microfabrication is being pursued. With the progress of microfabrication of 0.2 μm or less, the withstand voltage of the device is reduced, and the power supply voltage that can be supplied is also reduced to 1.5 V or less. The bandgap type reference voltage generating circuit that generates a voltage of about 1.2 V of 3 has a problem that it is difficult to operate at a low voltage, that is, to secure a minimum power supply voltage for starting operation. Specifically, in the above-described reference voltage generation method shown in FIGS. 2 and 3, it is a condition that an operation power supply in a range that can guarantee linearity in the operation characteristics of the comparison circuits 30 and 31 is used. It is also essential that VDD is sufficiently larger than Vbgout, and the power supply voltage in the fine process is reduced to, for example, 1.5 V or less, and a temperature-compensated reference voltage is supplied at a power supply voltage equivalent to Vbgout = about 1.2 V. I cannot do it. The circuit of FIG. 1 solves this problem.
[0044]
The circuit operation shown in FIG. 1 will be described in detail. The diodes 11, 12, and 13 have an area ratio of 1: N: K1, and the currents I41 and I42 of the p-channel type current source MOS transistors 1, 2, and 3 connected to the diodes 11, 12, and 13, respectively. In I44,
I41: I42: I44 = M: 1: (M * K2)
(M * K2> 1), and the feedback control by the comparison circuit 31 is applied, so that the resistance 21 (resistance = R21) is expressed by the equation (8).
ΔV = (k * T / q) * ln (M * N)
And a voltage difference ΔV is generated in the same manner as shown in equations (9) and (10).
I42 = (k * T / q) * ln (M * N) / R21
I41 = M * (k * T / q) * ln (M * N) / R21
Currents I42 and I41 flow. Also, as I44
I44 = (M * K2) * (k * T / q) * ln (M * N) / R21 (17)
Is supplied. As a load circuit of the current I44, there are a series connection circuit of the resistor 25 and the diode 13, and the resistor 26. From these, a temporary output voltage Vbgout 'is obtained.
Vbgout '= (M * K2) * (R26 / R21) * (k * T / q) * ln (M * N) * R25 / (R26 + R25) + VF3 * R26 / (R26 + R25) (18)
It becomes. By performing temperature differentiation on this,
δ (Vbgout ′) / δT = (M * K2) * (R26 / R21) * (k / q) * ln (M * N) * R25 / (R26 + R25) −L * (k / q) * ln (M * N) * R26 / (R26 + R25) ... (19)
It becomes. When the condition where the temperature coefficient shown in the equation (19) becomes zero is obtained,
(M * K2) * R25 = L * R21 (20)
It becomes. Substituting this into equation (18) gives
Vbgout '= R26 / (R26 + L * R21 / (M * K2)) * {(k * T / q) * ln (M * N) * L + VF3} (21)
Is shown. This can be further expressed using the relationship of equation (14).
Vbgout '= R26 / (R26 + L * R21 / (M * K2)) * Vbgout (22)
It becomes. That is,
R26 / (R26 + L * R21 / (M * K2)) <1
Because
Vbgout '<Vbgout
This means that an output voltage independent of temperature can be obtained.
[0045]
In order to supply a current I45 of a level equivalent to I42 to the diode 13,
I42 * R25 + VF3 (I42) ≒ I42 * (M * K2-1) * R26
Need to be That is,
VF3 (I42) {I42 * {(M * K2-1) * R26-R25}
It is necessary to be. Therefore, at least M * K2> 1 and R26> R25 are required.
[0046]
The circuit characteristics of FIG. 1 are shown by specific numerical examples. For example,
M * K2 = 2,
R25 = L * R21 / 2
R26 = 1.5 * L * R21
Then
Vbgout '= R26 / (R26 + L * R21 / (M * K2)) * Vbgout
Vbgout '= {1.5 / (1.5 + 0.5)} * Vbgout
Vbgout '= 0.75 * Vbgout
Vbgout '≒ 0.9V
Is obtained. In another example,
M * K2 = 3/2
R25 = 2 * L * R21 / 3
R26 = (4/3) * L * R21
Then
Vbgout '= {(4/3) / (4/3 + 2/3)} * Vbgout
Vbgout '= 2/3 * Vbgout
Vbgout '≒ 0.8V
Is obtained, indicating that a reference voltage lower than 1.2 V is obtained.
[0047]
In the circuit configuration of FIG. 1, the output voltage Vbgout is obtained by the pairing of the three resistors 21, 25, 26, the pairing of the three diodes 11, 12, 13 and the pairing of the three MOS transistors 1, 2, 3. However, when this circuit is realized with a low current of the order of microamperes, the resistor 26 has a resistance of 500 kΩ or more, and it is necessary to ensure the pairing with the other resistors 21 and 25. However, these are resistors smaller than the resistor 26 and have an advantage that pairing can be easily obtained.
[0048]
FIG. 4 shows a second example of the reference voltage generation circuit possessed by the semiconductor integrated circuit according to the present invention. In FIG. 4, diode-connected NPN bipolar transistors 51, 52, and 53 are used instead of the diodes 11, 12, and 13 shown in FIG. The area ratio of those PN junctions is also 1: N: K1, and a low-voltage reference voltage can be generated under similar conditions.
[0049]
FIG. 5 shows a third example of the reference voltage generation circuit possessed by the semiconductor integrated circuit according to the present invention. In FIG. 5, diode-connected PNP bipolar transistors 61, 62, and 63 are used instead of the diodes 11, 12, and 13 shown in FIG. The area ratio of those PN junctions is also 1: N: K1, and a low-voltage reference voltage can be generated under similar conditions.
[0050]
FIG. 6 shows a fourth example of the reference voltage generation circuit possessed by the semiconductor integrated circuit according to the present invention. In the configuration shown in FIG. 6, the p-channel current source MOS transistor of FIG. 1 is composed of complementary n-channel current source MOS transistors 81, 82, and 83. The conductance is controlled by the output, and the diodes 71, 72, and 73 are arranged on the power supply terminal 32 side. This reference voltage generation circuit is of a circuit type that outputs a reference voltage to a terminal 33 with respect to a power supply voltage VDD of a power supply terminal 32.
[0051]
FIG. 7 shows a fifth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention. In the configuration of FIG. 7, p-channel MOS transistors 4, 5, 6 and a bias terminal 35 are provided in addition to the p-channel current source MOS transistors 1, 2, 3 shown in FIG. Thus, even if the power supply voltage VDD of the power supply terminal 32 greatly changes, it does not exceed the withstand voltage of each MOS transistor, while reducing the power supply voltage dependency.
[0052]
FIG. 8 shows a sixth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention. The configuration shown in FIG. 8 enables generation of a lower voltage than that obtained from the output terminal 33 shown in FIG. That is, the resistor 26 shown in FIG. 1 is divided, and a divided voltage is generated at the voltage dividing terminal 36 by the resistors 26a and 26b. The divided voltage of the voltage dividing terminal 36 also has the same temperature characteristics and power supply voltage dependent characteristics as the output voltage of the terminal 33 described above. In short, the temperature dependency and the power supply voltage dependency are reduced, and a reference voltage with a lower level can be generated.
[0053]
FIG. 9 shows a seventh example of the reference voltage generation circuit possessed by the semiconductor integrated circuit according to the present invention. The configuration of FIG. 9 is different from the configuration of FIG. 1 in that another voltage Vbis different from the circuit ground voltage VSS is applied to the resistor 26 and the diode 13 of the output reproduction unit RGN. For example, it is suitable for a case where the voltage of the terminal 33 is used as a reference voltage in an analog circuit that operates with the voltage Vbis as analog ground.
[0054]
FIG. 10 shows an eighth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention. The configuration of FIG. 10 is different from the configuration of FIG. 4 in that another voltage Vbis different from the ground voltage VSS of the circuit is applied to the resistor 26 and the diode 13 of the output reproduction unit RGN as in FIG. For example, it is suitable for a case where the voltage of the terminal 33 is used as a reference voltage in an analog circuit that operates with the voltage Vbis as analog ground.
[0055]
FIG. 11 shows a ninth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention. In the configuration of FIG. 11, the output reproduction unit RGN has a current control MOS transistor 7 controlled by receiving the control voltage Vc at its gate, and a diode-connected current source MOS transistor 8 connected in series with the current control MOS transistor 7. The band gap section BGP has current source MOS transistors 1 and 2 connected to the current source MOS transistor 8 in a current mirror form. Although not particularly shown, the inverting input terminal (−) and the inverting input terminal (+) of the comparison circuit 31 may be exchanged to change the current control MOS transistor 7 to an n-channel type.
[0056]
FIG. 12 illustrates a microcomputer as an example of the semiconductor integrated circuit according to the present invention. Although not particularly limited, the microcomputer 101 shown in FIG. 1 is formed on one semiconductor substrate or semiconductor chip such as single crystal silicon by a semiconductor integrated circuit manufacturing technique such as CMOS.
[0057]
The microcomputer 101 includes a CPU 102, a RAM (random access memory) 104 as a work RAM, a timer 105, a flash memory 106, a clock generation circuit 109, a mask ROM (read only memory) 110, a system control logic 111, It has an output port (I / O port) 112, a data bus 113, an address bus 114, a reference voltage generation circuit 115, and other peripheral circuit units 107.
[0058]
The mask ROM 110 is used to store an operation program (interface control program and the like) of the CPU 102 and data. The RAM 104 is a work area of the CPU 102 or a temporary storage area of data, and is composed of, for example, an SRAM (static random access memory) or a DRAM (dynamic random access memory). The CPU 102 fetches an instruction from the mask ROM 110, decodes the fetched instruction, and performs an operand fetch or data operation based on the decoded result. In addition, the centralized circuit unit 107 includes an AD converter 120, a DA converter 121, and a power-on reset circuit 122. The I / O port 112 is used for input / output of data, input of an external interrupt signal, and the like. The I / O port 112 is connected to a data bus 113, and the data bus 113 is connected to the CPU 102, the RAM 104, the timer 105, the flash memory 106, other peripheral circuit units 107, and the like. In the microcomputer 101, the CPU 102 is a bus master module, and can output an address signal to an address bus 114 connected to the RAM 104, timer 105, flash memory 106, mask ROM 110, and other peripheral circuit units 107. The system control logic 111 controls the operation mode of the microcomputer 101 and performs interrupt control. When a reset operation is instructed, the microcomputer 1 is internally initialized, and the CPU 102 starts executing instructions from the head address of the program in the flash memory 106. Clock generation circuit 109 receives external clock signal CLK and generates internal clock signal CK. The microcomputer 101 is operated in synchronization with the internal clock signal CK.
[0059]
The flash memory 106 is capable of electrically erasing and writing stored information. Instead of the flash memory 106, a nonvolatile memory such as an EEPROM (Electrically Eraseable and Programmable Read Only Memory) or a high dielectric memory may be employed.
[0060]
The reference voltage generation circuit 115 has the circuit configuration described with reference to FIGS. 1 and 4 to 11, and the reference voltage Vbgout ′ generated by the reference voltage generation circuit 115 is transmitted to, for example, the AD converter 120 and the DA converter 121. The charge pump circuit is supplied and used as a reference voltage for conversion, supplied to a power-on reset circuit 122 and used as a power-on voltage detection reference, and supplied to a flash memory 106 to generate a high voltage for erasure / writing. Used for boost control voltage. The reference voltage Vbgout 'is a voltage such as 0.8 V even when the power supply voltage VDD is about 1.5 V. Accordingly, the microcomputer 101 is suitable for a low-voltage operation or a fine process in that the microcomputer 101 can generate a low reference voltage.
[0061]
FIG. 13 illustrates a schematic configuration of a processor board 139 as an electronic circuit to which the microcomputer 101 is applied. The processor board 139 is configured by mounting various semiconductor integrated circuit chips and circuit modules on a printed wiring board. A bridge chip 141 such as a chipset called a North Bridge is connected to the microcomputer 101 mounted on the processor board 139. The bridge chip 141 is connected to a graphic chip 142 and an SDRAM (synchronous dynamic random access memory). An access memory) and a PCI (peripheral component interconnect) bus 144. A liquid crystal display (not shown) is connected to the graphic chip 142. The PCI bus 144 is connected to a bridge chip 145 such as a chipset called a South Bridge, a modem unit 146, and the like. The bridge chip 145 is connected to an IDE (Integrated Device Electronics) port 148, an ISA (Industry Standard Architecture) bus 149, and a USB bus 150. Each of the IDE ports 148 is connected to a CD-ROM (compact disk-read only memory), a HDD (hard disk drive), or the like (not shown). A sound unit 152 and the like are connected to the ISA bus (or LPC) 149. A USB interface circuit 153 is connected to the USB bus 150, and a memory card or the like is made detachable.
[0062]
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it goes without saying that the invention can be variously modified without departing from the gist thereof. For example, the current source may be configured by combining a transistor with another device such as a resistor. The configuration of the differential amplifier constituting the comparison circuit can be appropriately selected. In this specification, a MOS transistor is a generic term for an insulated gate field effect transistor. INDUSTRIAL APPLICABILITY The present invention can be widely used for a semiconductor integrated circuit including a reference voltage generation circuit, and an electronic circuit to which the semiconductor integrated circuit is applied.
[0063]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
[0064]
That is, since a resistor is provided in parallel with the series path of the junction type load element and the resistor constituting the output regeneration unit of the reference voltage generation circuit, it is possible to generate a reference voltage of about 1.2 V or less which is temperature compensated and power supply voltage compensated. Is possible. Alternatively, it is possible to generate a reference voltage that has been subjected to temperature compensation and power supply voltage compensation with a supply power supply voltage that is equal to or less than the power supply voltage of a bandgap reference voltage generation circuit that generates a reference voltage of about 1.2 V. Further, the reference voltage generating circuit has two current source paths in the band gap section and one current source path in the output reproduction section, which is sufficient. Therefore, the number of circuit elements can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first example in which a PN junction diode is used for a reference voltage generation circuit held by a semiconductor integrated circuit according to the present invention.
FIG. 2 is a circuit diagram illustrating a basic type of a bandgap type reference voltage generating circuit.
3 is a circuit diagram illustrating a reference voltage generating circuit before the circuit configuration of FIG. 1 is developed to reach the circuit of FIG. 1;
FIG. 4 is a circuit diagram showing a second example in which an NPN bipolar transistor is used for a reference voltage generation circuit possessed by the semiconductor integrated circuit according to the present invention.
FIG. 5 is a circuit diagram showing a third example in which a PNP bipolar transistor is used for a reference voltage generation circuit included in a semiconductor integrated circuit according to the present invention.
FIG. 6 is a circuit diagram showing a fourth example in which a current source MOS transistor having a different conductivity type from that of FIG. 1 is used for a reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention.
FIG. 7 is a circuit diagram showing a fifth example in which a cascode-connected current source is used for a reference voltage generation circuit held by a semiconductor integrated circuit according to the present invention.
FIG. 8 is a circuit diagram showing a sixth example in which a divided voltage output form of a parallel resistor is used for a reference voltage generation circuit included in a semiconductor integrated circuit according to the present invention.
FIG. 9 is a circuit diagram showing a seventh example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention.
FIG. 10 is a circuit diagram showing an eighth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention.
FIG. 11 is a circuit diagram showing a ninth example of the reference voltage generation circuit held by the semiconductor integrated circuit according to the present invention.
FIG. 12 is a block diagram illustrating a microcomputer as an example of a semiconductor integrated circuit according to the present invention.
FIG. 13 is a block diagram illustrating a schematic configuration of a processor board 39 as an electronic circuit to which the microcomputer of FIG. 12 is applied;
[Explanation of symbols]
1,2,3,4,5,6,7,8 p-channel MOS transistor
11, 12, 13, 71, 72, 73 PN junction diode
21, 22, 23, 24, 25, 26, 26a, 26b Resistance
30, 31, 34 comparison circuit
32 power terminal
33 Reference voltage output terminal
35 Bias terminal
36 voltage divider terminal
51, 52, 53 NPN bipolar transistor
61,62,63 PNP bipolar transistor
81, 82, 83 n-channel MOS transistors
101 microcomputer
102 CPU
139 Processor Board

Claims

A band gap section that generates a first voltage and a second voltage based on a difference between currents flowing through the pair of junction-type load elements via a current source, and the first voltage and the second voltage are made to match each other. A comparison unit that generates a control signal used to control a current flowing through the pair of junction-type load elements via a current source; and a series circuit including a junction-type load element and a resistor, and based on the control signal. An output regeneration unit that reproduces a current proportional to a current flowing through the junction-type load element of the band gap unit in the series circuit, wherein a resistor is connected in parallel to the series circuit of the output regeneration unit; A semiconductor integrated circuit having a reference voltage generating circuit from which a reference voltage is extracted.

The band gap unit includes a current source MOS transistor controlled by receiving the control signal at a gate as a current source,
2. The semiconductor integrated circuit according to claim 1, wherein the output reproducing unit includes a current source MOS transistor controlled by receiving the control signal at a gate.

The output reproducing unit includes a current control MOS transistor controlled by receiving the control signal at a gate, and a diode-connected current source MOS transistor in series with the current control MOS transistor.
2. The semiconductor integrated circuit according to claim 1, wherein said band gap portion includes a current source MOS transistor connected to said current control MOS transistor in a current mirror form.

A first voltage at a connection node where a first current source is connected in series with a first junction type load element, and a second current source is connected in series with a series path of a second junction type load element and a first resistor. A first circuit that generates a control voltage for controlling the first current source and the second current source so that the second voltage of the connection node matches the second voltage of the connection node.
A third current source controlled by the control voltage is connected in series to a series path of a third junction type load element and a second resistor, and a series path of the third junction type load element and the second resistor is connected. A second circuit in which a third resistor is connected in parallel to the second circuit, and a reference voltage generating circuit for extracting a reference voltage from the second circuit.

5. The semiconductor integrated circuit according to claim 4, wherein said first to third junction-type load elements are PN junction diodes.

5. The semiconductor integrated circuit according to claim 4, wherein said first to third junction-type load elements are diode-connected bipolar transistors.

5. The semiconductor integrated circuit according to claim 4, wherein said first to third current sources are p-channel MOS transistors or n-channel MOS transistors.

The said reference voltage is the voltage of the connection node which connected the 3rd current source to the series path of the said 3rd junction type load element and the 2nd resistance in series, The one of Claim 4 characterized by the above-mentioned. 2. The semiconductor integrated circuit according to claim 1.

8. The semiconductor integrated circuit according to claim 4, wherein the reference voltage is a voltage of a predetermined voltage dividing node of the third resistor.

A first current source, a second current source, and a third current source having a predetermined current value ratio;
A first PN junction diode, a second PN junction diode, and a third PN junction diode having a predetermined area ratio;
A first resistor, a second resistor, and a third resistor having a predetermined resistance ratio;
A reference voltage generation circuit including a comparison circuit for commonly controlling the first to third current sources;
The first current source generates a first voltage using the first PN junction diode as a load circuit;
The second constant current source generates a second voltage using a first series connection circuit in which the second PN junction diode and a first resistor are connected in series as a load circuit,
The comparison circuit compares the first voltage and the second voltage, and commonly uses the first to third current sources so that the first voltage and the second voltage are the same. Control and
The third current source includes a second series connection circuit in which the third PN junction diode and a second resistance are connected in series, and a third resistance in parallel with the second series connection circuit. Connected to the connected load circuit,
The semiconductor integrated circuit according to claim 1, wherein the reference voltage generation circuit outputs the third voltage as a reference voltage.

A first current source, a second current source, and a third current source having a predetermined current value ratio;
A first diode-connected bipolar transistor, a second diode-connected bipolar transistor and a third diode-connected bipolar transistor having a predetermined area ratio;
A first resistor, a second resistor, and a third resistor having a predetermined resistance ratio;
A reference voltage generation circuit including a comparison circuit for commonly controlling the first to third current sources;
The first current source generates a first voltage using the first diode-connected bipolar transistor as a load circuit,
The second constant current source generates a second voltage using a first series connection circuit in which the second diode-connected bipolar transistor and a first resistor are connected in series as a load circuit,
The comparison circuit compares the first voltage and the second voltage, and commonly uses the first to third current sources so that the first voltage and the second voltage are the same. Control and
The third current source includes a second series connection circuit in which the third diode-connected bipolar transistor and a second resistor are connected in series, and a third series connection circuit in parallel with the second series connection circuit. Is connected to the connected load circuit,
The semiconductor integrated circuit according to claim 1, wherein the reference voltage generation circuit outputs the third voltage as a reference voltage.

A first current source, a second current source, and a third current source having a predetermined current value ratio;
A first bipolar transistor, a second bipolar transistor, and a third bipolar transistor having a predetermined area ratio;
A first resistor, a second resistor, and a third resistor having a predetermined resistance ratio;
A reference voltage generation circuit including a comparison circuit that controls the three current sources in common;
The first current source generates a first voltage using the first bipolar transistor as a load circuit,
The second constant current source generates a second voltage using a first series connection circuit in which the second bipolar transistor and a first resistor are connected in series as a load circuit,
The comparison circuit compares the first voltage and the second voltage, and commonly uses the first to third current sources so that the first voltage and the second voltage are the same. Control and
The third current source is connected to a second series connection circuit in which the third bipolar transistor and a second resistor are connected in series, and a third resistor is connected in parallel with the second series connection circuit. Connected to the load circuit
The base potentials of the first and second bipolar transistors are biased to a common fourth potential,
The base potential of the third bipolar transistor and the third resistor are biased to potentials different from the fourth potential,
The semiconductor integrated circuit according to claim 1, wherein the reference voltage generation circuit outputs the third voltage as a reference voltage.

The first PN junction diode and the second PN junction diode are connected to a common fourth potential,
11. The semiconductor integrated circuit according to claim 10, wherein said third PN junction diode and said third resistor are biased to a potential different from said fourth potential.

A first diode-connected bipolar transistor and a second diode-connected bipolar transistor connected to a common fourth potential;
12. The semiconductor integrated circuit according to claim 11, wherein said third diode-connected bipolar transistor and said third resistor are biased to a potential different from said fourth potential.

15. The semiconductor integrated circuit according to claim 10, wherein the third resistor is divided into two by a predetermined voltage dividing ratio, and a reference voltage is extracted from a coupling node at the two division points.

16. The semiconductor integrated circuit according to claim 1, further comprising a circuit module for inputting a reference voltage of the reference voltage generation circuit.

17. An electronic circuit comprising: a mounting substrate on which one or more semiconductor integrated circuits different from the semiconductor integrated circuit according to claim 16 are mounted.