JP2009199343A - System memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a system memory control device for connecting a control signal and an address signal through a common bus. <P>SOLUTION: This system memory control device includes: a command synchronization device 14 for generating CME-0 and CME-1 which are made exclusively valid; a unit system memory control device 13a for generating CS-0, CTL-0 and AD-0 based on CME-0 and ACQ-0 from a data processor 16, and for outputting CTL-0 and AD-0 synchronously with CS-0; a unit system memory control device 13b for generating CS-1, CTL-1 and AD-1 based on CME-1 and ACQ-1 from the data processor 16, and for outputting CTL-1 and AD-1 synchronously with the CS-1; and a command selection device 15 for selecting CTL-0 and AD-0 or CTL-1 and AD-1, and for outputting it through a common bus to system memories 11a and 11b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a system memory control device in a system semiconductor device in which a plurality of system memories are connected to the outside.

  SDRAM (Synchronous DRAM), which is commonly used as a system memory, has been increased in capacity with the recent progress in miniaturization of semiconductor processes, and the number of bits of address signals necessary for control has increased. . For example, to access a 256M address space, 14 bits are required as an address signal.

  On the other hand, in a system semiconductor device that connects a plurality of system memories externally and accesses them at high speed in order to improve system performance, the system memory control device is connected to each system because the data bus for connecting the system memory is shared. It is necessary to control each system memory independently so that access to the memory does not occur in the same clock cycle (see, for example, “Patent Document 1”).

For this reason, in the system semiconductor device provided with the conventional system memory control device, there is a problem that the control signal and the address signal must be connected separately for each system memory.
JP-A-10-69432

  The present invention provides a system memory control device capable of connecting a control signal and an address signal via a common bus.

  According to one aspect of the present invention, there is provided a system memory control device that transfers data to the first and second system memories in synchronization with a clock signal based on an access request signal from a data processing device, Command synchronization means for generating a first command validity signal and a second command validity signal that are exclusively valid, the first command validity signal from the command synchronization means, and the first access request from the data processing device A first chip select signal, a first control signal, and a first address signal are generated based on the signal, and the first chip select signal is output to the first system memory. First unit system memory control for outputting a first address signal in synchronization with the first chip select signal And a second chip select signal, a second control signal, and a second address signal based on the second command valid signal from the command synchronization means and the second access request signal from the data processor. A second unit system that generates and outputs the second chip select signal to the second system memory and outputs the second control signal and the second address signal in synchronization with the second chip select signal. Based on the memory control means, the first chip select signal, and the second chip select signal, the first control signal and the first address signal from the first unit system memory control means, or the second The second control signal and the second address signal from the unit system memory control means are selected to select the first and System memory controller and having a command selection means for outputting via a common bus to a second system memory is provided.

  According to the present invention, the number of external connection pins for a system memory connected to the outside of the system semiconductor device can be greatly reduced, and the size and cost of the package can be reduced, and the convenience of mounting can be improved. .

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a system memory control apparatus according to an embodiment of the present invention. Here, as an example, the system memory control device incorporated in the system semiconductor device 12 that connects the two system memories 11a and 11b to the outside and the part related to the operation thereof are shown.

  The system memory control device according to the embodiment of the present invention includes two unit system memory control devices 13a and 13b, a command synchronization device 14, and a command selection device 15.

  A system memory access request signal 0 (hereinafter referred to as “ACQ-0”) from the data processing device 16 incorporated in the system semiconductor device 12 is input to the first input of the unit system memory control device 13a. A command valid signal 0 (hereinafter referred to as “CME-0”) from the command synchronizer 14 is input to the second input of the memory control device 13a, and the first input / output of the unit system memory control device 13a is input to the second input of the memory control device 13a. A request data signal 0 (hereinafter referred to as “RQD-0”) is input / output to / from the data processing device 16, and data is transferred to / from the system memory 11a as the second input / output of the unit system memory control device 13a. The signal 0 (hereinafter referred to as “DQ-0”) is input / output, and the first output of the unit system memory controller 13a is the control signal 0 (hereinafter referred to as “C”). TL-0 ”) and address signal 0 (hereinafter referred to as“ AD-0 ”) are supplied to the first input of the command selection device 15, and the second output of the unit system memory control device 13a is the chip select. The signal 0 (hereinafter referred to as “CS-0”) is supplied to the second input of the command selection device 15 and the first input of the system memory 11a.

  The system memory access request signal 1 (hereinafter referred to as “ACQ-1”) from the data processing device 16 is input to the first input of the unit system memory control device 13b, and the second input of the unit system memory control device 13b. The command valid signal 1 (hereinafter referred to as “CME-1”) from the command synchronizer 14 is input to the input, and the first input / output of the unit system memory controller 13b is connected to the data processor 16. A request data signal 1 (hereinafter referred to as “RQD-1”) is input / output, and a data signal 1 (hereinafter referred to as “DQ−”) is transmitted to the second input / output of the unit system memory controller 13b with the system memory 11b. 1 ”), and the first output of the unit system memory controller 13b is the control signal 1 (hereinafter referred to as“ CTL-1 ”) and the address signal. 1 (hereinafter referred to as “AD-1”) is supplied to the third input of the command selection device 15, and the second output of the unit system memory control device 13b is the chip select signal 1 (hereinafter referred to as “CS-1”). Is supplied to the fourth input of the command selection device 15 and the first input of the system memory 11b.

  The output of the command selection device 15 is a second input of the system memory 11a and a second input of the system memory 11b as a shared control signal (hereinafter referred to as “CCTL”) and a shared address signal (hereinafter referred to as “CADD”). Has been supplied to.

  The unit system memory control device 13a generates CS-0, CTL-0, and AD-0 based on CME-0 from the command synchronizer 14 and ACQ-0 from the data processing device 16, and CS-0 Are output to the system memory 11a and the command selection device 15, and CTL-0 and AD-0 are output to the command selection device 15 in synchronization with CS-0.

  The unit system memory controller 13a can control one system memory, and after a prescribed cycle of the clock cycle in which CME-0 is valid ("H") (after two cycles in the example described later in FIG. 2). A system memory command (a command specified by CTL-0 and AD-0) can be issued to the system memory 11a.

  Further, the unit system memory control device 13b generates CS-1, CTL-1, and AD-1 based on CME-1 from the command synchronizer 14 and ACQ-1 from the data processing device 16, and CS -1 is output to the system memory 11b and the command selection device 15, and CTL-1 and AD-1 are output to the command selection device 15 in synchronization with CS-1.

  The unit system memory control device 13b can control one system memory, and after a prescribed cycle of the clock cycle in which CME-1 is valid (“H”) (after two cycles in the example described later in FIG. 2). A system memory command (a command specified by CTL-1 and AD-1) can be issued to the system memory 11b.

  The command synchronizer 14 generates CME-0 and CME-1 that are mutually exclusive. For example, CME-0 is a signal that is inverted every cycle, and the inverted signal of CME-0 is CME-1.

  Based on CS-0 and CS-1, the command selection device 15 selects CTL-0 and AD-0 from the unit system memory control device 13a or CTL-1 and AD-1 from the unit system memory control device 13b. Is output as CCTL and CADD to the system memories 11a and 11b via the common bus.

  That is, the command selection device 15 outputs CTL-0 and AD-0 as CCTL and CADD when CS-0 is valid (“L”), and when CS-1 is valid (“L”). Outputs CTL-1 and AD-1 as CCTL and CADD.

Next, an example of the operation in the system memory control device will be described.
FIG. 2 is a timing diagram showing waveforms of signals in the operation of the system memory control apparatus according to the embodiment of the present invention. Here, as an example, the case where SDRAM is used for the system memories 11a and 11b is shown.

  CLK represents a clock signal, and the number given at the top of each clock cycle indicates a convenient cycle number for explanation.

  As shown in FIG. 2, CME-0 and CME-1 are a pair of complementary signals that are inverted every clock cycle. That is, CME-0 is valid (“H”) in even-numbered clock cycles, and CME-1 is valid (“H”) in odd-numbered clock cycles.

  CS-0 and CS-1 are negative logic signals and can only be valid ("L") after two cycles of CME-0 and CME-1, respectively. That is, CS-0 is always invalid (“H”) in odd-numbered clock cycles, and CS-1 is always invalid (“H”) in even-numbered clock cycles.

  In CTL-0 and CTL-1, commands (except No: No Operation) are output only in clock cycles in which CS-0 and CS-1 are valid ("L"), respectively. Since CS-0 and CS-1 are not enabled ("L") at the same time, the command for the system memory 11a and the command for the system memory 11b are not simultaneously output in the same clock cycle. Here, as an example, a case where continuous reading in the same bank is performed on the system memories 11a and 11b is shown. That is, in CTL-0, BPcg (bank precharge command) is output in the second cycle, Act (bank activate command) is output in the sixth cycle, and the eighth, tenth, twelfth, fourteenth, sixteenth Read (read command) is output in each of the 18th and 20th cycles, and BPcg is output in the 26th cycle. In CTL-1, BPcg is output in the third cycle, Act is output in the seventh cycle, and Read is performed in the ninth, eleventh, thirteenth, fifteenth, nineteenth, and twenty-first cycles. Is output, and BPcg is output in the 27th cycle.

  Addresses corresponding to CTL-0 and CTL-1 are output to AD-0 and AD-1, respectively. That is, in AD-0, A00 is output in the second cycle, A01 is output in the sixth cycle, A02 is output in the eighth cycle, A03 is output in the tenth cycle, and A04 is output in the twelfth cycle. A05 is output in the 14th cycle, A06 is output in the 16th cycle, A07 is output in the 18th cycle, A08 is output in the 20th cycle, and A09 is output in the 26th cycle. In AD-1, A10 is output in the third cycle, A11 is output in the seventh cycle, A12 is output in the ninth cycle, A13 is output in the eleventh cycle, and A14 is output in the twenty-second cycle. A15 is output in the 15th cycle, A16 is output in the 17th cycle, A17 is output in the 19th cycle, A18 is output in the 21st cycle, and A19 is output in the 27th cycle.

  CTL-0 or CTL-1 selected by the command selection device 15 based on CS-0 and CS-1 is output to CCTL. Similarly, AD-0 or AD-1 selected by the command selection device 15 is output to CADD.

  In this way, by combining the control signals (CTL-0 and CTL-1) and the address signals (AD-0 and AD-1) excluding CS-0 and CS-1 in the system memory control device, The system memories 11a and 11b can share these buses.

  According to the above embodiment, since the control signal and the address signal except for the chip select signals (CS-0 and CS-1) can be shared via the common bus, they are connected to the outside of the system semiconductor device 12. The number of external connection pins for the system memories 11a and 11b can be greatly reduced, and the package can be reduced in size and cost, and the convenience of mounting can be improved.

  In the above-described embodiment, the system memory control device is incorporated in the system semiconductor device 12. However, the present invention is not limited to this, and the system memory control device can be configured as a single IC chip. . Although the system memories 11a and 11b are SDRAMs, the present invention is not limited to this.

  In the above-described embodiment, there are two system memories. However, the present invention is not limited to this, and in principle, a plurality of command valid signals that are mutually exclusive are generated. Can be applied to any number of system memories.

  Furthermore, in the above-described embodiment, CS-0 and CS-1 are input to the command selection device 15 in consideration of compatibility between the conventional system memory control device and the unit system memory control devices 13a and 13b. The present invention is not limited to this. For example, the CME-0 and CME-1 may be directly input to the command selection device 15 to generate CCTL and CADD.

  Further, in the above-described embodiment, CME-0 and CME-1 are a pair of complementary signals that are inverted every clock cycle. However, the present invention is not limited to this and is effective exclusively from each other. Any signal can be applied in principle.

  Furthermore, in the above-described embodiment, CS-0 and CS-1 can be enabled only after two clock cycles when CME-0 and CME-1 are enabled, respectively. However, the present invention is not limited to this, and it may be configured to be effective after an arbitrary cycle as long as the number of the same constant cycle.

The circuit block diagram which shows the system memory control apparatus concerning the Example of this invention. The timing diagram which shows the waveform of each signal in operation | movement of the system memory control apparatus concerning the Example of this invention.

Explanation of symbols

11a, 11b System memory 12 System semiconductor devices 13a, 13b Unit system memory controller 14 Command synchronizer 15 Command selector 16 Data processor ACQ-0 System memory access request signal 0
ACQ-1 System memory access request signal 1
RQD-0 Request data signal 0
RQD-1 Request data signal 1
CME-0 command valid signal 0
CME-1 Command valid signal 1
CTL-0 Control signal 0
CTL-1 Control signal 1
AD-0 Address signal 0
AD-1 Address signal 1
DQ-0 Data signal 0
DQ-1 Data signal 1
CS-0 Chip select signal 0
CS-1 Chip select signal 1
CCTL shared control signal CADD shared address signal

Claims (5)

A system memory control device that transfers data to the first and second system memories in synchronization with a clock signal based on an access request signal from a data processing device,
Command synchronization means for generating a first command valid signal and a second command valid signal which are valid mutually exclusively;
Generating a first chip select signal, a first control signal, and a first address signal based on the first command valid signal from the command synchronization means and the first access request signal from the data processing device; First unit system memory control means for outputting the first chip select signal to the first system memory and outputting the first control signal and the first address signal in synchronization with the first chip select signal. When,
Generating a second chip select signal, a second control signal, and a second address signal based on the second command valid signal from the command synchronization means and the second access request signal from the data processing device; Second unit system memory control means for outputting the second chip select signal to the second system memory and outputting the second control signal and the second address signal in synchronization with the second chip select signal. When,
Based on the first chip select signal and the second chip select signal, the first control signal and the first address signal from the first unit system memory control means, or the second unit system memory control. And a command selecting means for selecting the second control signal and the second address signal from the means and outputting them to the first and second system memories via a common bus. apparatus.   2. The system memory control device according to claim 1, wherein the first command valid signal and the second command valid signal are a pair of complementary signals.   2. The system memory control device according to claim 1, wherein the first command valid signal and the second command valid signal are a pair of complementary signals that are inverted every cycle of the clock signal. The first chip select signal is output after N cycles (N is a natural number) of the clock signal from the first command valid signal,
2. The system memory control device according to claim 1, wherein the second chip select signal is output after N cycles from the second command valid signal. The first chip select signal is output after two cycles of the clock signal from the first command valid signal,
2. The system memory control device according to claim 1, wherein the second chip select signal is output two cycles after the clock signal from the second command valid signal.

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