JP4819326B2 - Clock signal supply device - Google Patents

Description

  The present invention relates to a clock signal supply device, and more particularly to a clock signal supply device capable of supplying a clock signal to two types of memories that operate in different operation modes based on the clock signal.

  The two types of memories are, for example, an SDR mode SDRAM and a DDR mode SDRAM.

  As a DRAM (Dynamic Random Access Memory) widely used as a main memory because of a low manufacturing cost per storage capacity, there is an SDRAM (Synchronous DRAM) as a memory capable of reading and writing data at a high speed. In the SDRAM, data is read and written in synchronization with an external clock signal.

  In recent years, SDRAM has come to be used as a main memory of various digital devices as the price of SDRAM decreases. Further, DDR (Double Data Rate) mode SDRAMs that can transfer data at both rising and falling timings of the clock signal to realize double data transfer are also widely used. Note that a normal method of transferring data only at the rising timing of the clock signal with respect to the DDR mode is referred to as an SDR (Single Data Rate) mode (see, for example, Patent Document 1).

  On the other hand, with the advancement of semiconductor technology, a system LSI, which is an ultra-multifunctional LSI in which many functions are integrated on one chip, has been developed. As a result, even when a given digital device is developed in a number of price ranges or categories and products are serialized, almost all functions of these series products can be controlled by the same type of system LSI. It is possible. For example, the same type of system LSI can be used as a controller for both low-priced consumer equipment and high-priced office equipment in the same series of products.

  In that case, a low-priced consumer device is connected to a system LSI with an SDR mode SDRAM, which is very inexpensive but has a low data transfer capability, while it is somewhat expensive for a high-priced office device. However, a DDR mode SDRAM having a high data transfer capability is connected to the system LSI.

  Conventionally, an output terminal for outputting two types of clock signals, that is, a clock signal and an inverted clock signal, is provided in the system LSI so that it can be connected to either of the SDR mode SDRAM and the DDR mode SDRAM. It was. That is, the clock signal output terminal of the system LSI is connected to the clock input terminal of the SDR mode SDRAM so that data transfer is performed at the rising timing of the clock signal in the SDR mode SDRAM, The clock input terminal and the inverted clock input terminal are connected to the clock signal output terminal and the inverted clock signal output terminal of the system LSI, respectively. In the DDR mode SDRAM, the rising timing of the clock signal and the rising timing of the inverted clock signal ( Data transfer is performed at a timing corresponding to the falling edge of the clock signal).

  In addition, a clock signal (inverted clock signal) is supplied to the DDR mode SDRAM and the SDR mode SDRAM through an interface (buffer). However, the electrical characteristics of the interface are different between the DDR mode SDRAM and the SDR mode SDRAM. Both the SSTL-2 interface buffer for the DDR mode SDRAM and the LVTTL interface buffer for the SDR mode SDRAM are mounted on the system LSI, and the buffer corresponding to the SDRAM mode connected to the system LSI is selected. It was possible to use it.

  Incidentally, the number of SDRAMs connected to the system LSI varies depending on the category of the device on which the system LSI is mounted.

  On the other hand, the LVTTL buffer in the SDR mode SDRAM is divided into a low drive type and a high drive type. When a plurality of SDRAMs are connected to one low drive type LVTTL buffer, the delay of the clock signal becomes large, and the high speed in the SDRAM. Operation becomes impossible. Since the high drive type LVTTL buffer has a complicated circuit configuration, the chip size of the system LSI increases, the chip cost increases, and the output of the high drive type LVTTL buffer is connected to a few SDRAMs. There is a problem that the waveform of the clock signal is disturbed.

In order to solve these problems, a system LSI is conventionally provided with a large number of low drive type LVTTL buffers and a number of clock output terminals connected to each LVTTL buffer, and each clock output terminal has one SDR mode. The configuration is such that the clock input terminal of the SDRAM is connected.
JP 2000-182399 A

  However, in the configuration in which a large number of low drive type LVTTL buffers and clock output terminals are provided in the system LSI like the conventional system LSI, the chip size of the system LSI increases and the chip cost increases. There was a problem that it was difficult to mount LSI on low-priced equipment.

  The present invention has been made in view of such problems, and an object thereof is to provide a clock signal supply device in which the number of clock signal output terminals of a system LSI is reduced.

To achieve the above object, the clock signal supplying apparatus of the present invention, in the clock signal supply device capable of supplying a clock signal to the two memories that operate in different operation modes from one another based on the clock signal, the first A plurality of first clock signal output means for outputting a first clock signal to be supplied to a different type of memory, and a second clock signal output means for outputting a second clock signal to be supplied to a second type of memory And third clock signal output means for outputting a third clock signal to be supplied to the second type of memory, and the first clock signal output from one of the plurality of first clock signal output means. And a first selection for selecting one of the second clock signal output from the second clock signal output means and outputting the selected one to the first output terminal. A first clock signal output from another one of the plurality of first clock signal output means, and the third clock signal output from the third clock signal output means. A second selection means for selecting one of them and outputting it to a second output terminal; and a flip-flop for holding a value for operating the first selection means or the second selection means in different operation modes And a CPU for setting different values in the flip-flops corresponding to the operation mode in order to operate the first selection unit or the second selection unit in different operation modes. .

  According to the present invention, the first clock signal output from the plurality of first clock signal output means and the second clock output from the second clock signal output means by the first and second selection means, respectively. Any one of the signal and the third clock signal output from the third clock signal output means can be selected in accordance with the operation mode of the first and second types of memory, and is provided in the system LSI. The number of power clock signal output terminals can be reduced. In addition, various numbers of first-type memories (SDR mode SDRAMs) can be connected to the system LSI without increasing the delay in the plurality of clock signal output means (LVTTL buffers). It is possible to operate various types of memories at high speed.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an SDRAM control device (clock signal supply device) according to an embodiment of the present invention. The entire configuration of the SDRAM control device shown in FIG. 1 is included in the system LSI.

  Reference numeral 1 denotes an SDRAM control unit, which is connected to the CPU 2 via the CPU bus 16 and performs data transfer with the SDRAM (not shown in FIG. 1) in response to a memory access request from the CPU 2. The flip-flop 3 is connected to the CPU bus 16 and is set to a value of 0 or 1 by the CPU 2. Reference numeral 4 denotes a clock generation unit that generates an operation clock of the SDRAM. Reference numeral 5 denotes an inverter that inverts the clock generated by the clock generator 4.

  Reference numerals 6 and 7 denote LVTTL buffers, both of which receive the clock generated by the clock generator 4. Reference numerals 8 and 9 denote SSTL-2 buffers each including a differential amplifier. The clock output from the clock generation unit 4 is input to one input terminal of the SSTL-2 buffer 8, and one of the SSTL-2 buffers 9 is also input. An inverted clock output from the inverter 5 is input to the input terminal. A reference voltage is input from the VREF terminal to the other input terminals of the SSTL-2 buffer 8 and the SSTL-2 buffer 9.

  Reference numerals 10 and 11 denote selectors. One input terminal of the selector 10 is connected to the output terminal of the LVTTL buffer 6, and the other input terminal is connected to the output terminal of the SSTL-2 buffer 8. Further, the output terminal of the LVTTL buffer 7 is connected to one input terminal of the selector 11, and the output terminal of the SSTL-2 buffer 9 is connected to the other input terminal. Each of the selectors 10 and 11 selects and outputs one of the two inputs according to the value set in the flip-flop 3. That is, when the set value of the flip-flop 3 is 1, the SDR mode is selected, the selector 10 selects the output of the LVTTL buffer 6 and outputs it to the output terminals CK1 / CK, and the selector 11 outputs the output of the LVTTL buffer 7 Is selected and output to the output terminal CK2 / CK #. On the other hand, when the set value of the flip-flop 3 is 0, the DDR mode is selected, the selector 10 selects the output of the SSTL-2 buffer 8 and outputs it to the output terminals CK1 / CK, and the selector 11 receives the SSTL-2. The output of the buffer 9 is selected and output to the output terminal CK2 / CK #. Thus, in the SDR mode, in-phase clocks (which are referred to as “clock CK1” and “clock CK2”) are output to the output terminals CK1 / CK and CK2 / CK #, respectively, and in the DDR mode. Output clocks of opposite phases (referred to as “clock CK” and “clock CK #”), respectively.

  The operation of the SDRAM control apparatus when various SDRAMs are connected to the SDRAM control apparatus having such a configuration will be described below with reference to FIGS.

  FIG. 2 is a block diagram showing a configuration when one SDR mode SDRAM 12 is connected to the SDRAM control apparatus shown in FIG.

  The SDRAM 12 is connected to the SDRAM control unit 1 through a plurality of terminals, and control, address, and data signals are transmitted and received between them. Further, the output terminal CK1 / CK of the selector 10 is connected to the clock input terminal CK of the SDRAM 12.

  In such a connection state, the CPU 2 sets 1 to the flip-flop 3. Therefore, the clock generated by the clock generation unit 4 is output to the output terminals CK1 / CK via the LVTTL buffer 6 and the selector 10, and the clock is supplied to the SDRAM 12.

  FIG. 3 is a block diagram showing a configuration when two SDR mode SDRAMs 12 and 13 are connected to the SDRAM control apparatus shown in FIG.

  Each of the SDRAMs 12 and 13 is connected to the SDRAM control unit 1 through a plurality of terminals, and controls, addresses, and data between the SDRAM 12 and the SDRAM control unit 1 and between the SDRAM 13 and the SDRAM control unit 1, respectively. Each signal is transmitted and received. Further, the output terminal CK1 / CK of the selector 10 is connected to the clock input terminal CK of the SDRAM 12, and the output terminal CK2 / CK # of the selector 11 is connected to the clock input terminal CK of the SDRAM 13.

  In such a connection state, the CPU 2 sets 1 to the flip-flop 3. Therefore, the clock generated by the clock generation unit 4 is output to the output terminals CK1 / CK via the LVTTL buffer 6 and the selector 10, and the clock is supplied to the SDRAM 12. The clock generated by the clock generation unit 4 is output to the output terminal CK2 / CK # via the LVTTL buffer 7 and the selector 11, and the clock is supplied to the SDRAM 13.

  In a conventional SDRAM control device (system LSI), for example, a clock signal output from the LVTTL buffer 6 is input to each clock input terminal of two SDRAMs in the SDR mode via the output terminals CK1 / CK, and these Since each SDRAM is driven, the delay of the clock signal in the LVTTL buffer 6 is larger than the connection of one SDR mode SDRAM, and the two SDR mode SDRAMs cannot operate at high speed.

  In the present embodiment shown in FIG. 3, since one LVTTL buffer corresponds to each SDR mode SDRAM and one LVTTL buffer supplies a clock to one SDRAM, there is no buffer delay, and the SDRAM Can be operated at high speed.

  1 and 3, the LVTTL buffers 6 and 7, selectors 10 and 11, and two clock output terminals CK1 / CK and CK2 / CK # are provided. However, a larger number of LVTTL buffers, selectors, and clock output terminals may be provided.

  FIG. 4 is a block diagram showing a configuration when two DDR mode SDRAMs 14 and 15 are connected to the SDRAM control device shown in FIG.

  Each of the SDRAMs 14 and 15 is connected to the SDRAM control unit 1 through a plurality of terminals, and controls, addresses, data, and the like between the SDRAM 14 and the SDRAM control unit 1 and between the SDRAM 15 and the SDRAM control unit 1, respectively. Each data strobe signal is transmitted and received. Further, the output terminal CK1 / CK of the selector 10 is connected to the clock input terminal CK of the SDRAM 14, and the output terminal CK2 / CK # of the selector 11 is connected to the inverted clock input terminal CK #. Similarly, the output terminal CK1 / CK of the selector 10 is connected to the clock input terminal CK of the SDRAM 15, and the output terminal CK2 / CK # of the selector 11 is connected to the inverted clock input terminal CK #.

  In such a connection state, the CPU 2 sets 0 to the flip-flop 3. Therefore, the clock generated by the clock generation unit 4 is output to the output terminals CK1 / CK via the SSTL-2 buffer 8 and the selector 10, and is supplied to the clock input terminals CK of the SDRAMs 14 and 15. The inverted clock output from the inverter 5 is output to the output terminal CK2 / CK # via the SSTL-2 buffer 9 and the selector 11 and supplied to the inverted clock input terminals CK # of the SDRAMs 14 and 15.

  A plurality of DDR mode SDRAMs 14 and 15 are connected to the clock output terminals CK1 / CK and CK2 / CK #, respectively. However, since the SSTL-2 buffers 8 and 9 are constituted by differential amplifiers, the SSTL-2 buffer No delay of the clock signal occurs at 8 and 9, and the DDR mode SDRAMs 14 and 15 can operate at high speed.

  As described above, since the selector can select the output of the LVTTL buffer or SSTL-2 buffer that supplies a clock signal to the SDRAM according to the SDRAM mode, the clock to be provided in the system LSI (SDRAM controller) The number of output terminals can be reduced. That is, for example, a system LSI (SDRAM controller) that can connect two SDRAMs in SDR mode conventionally requires four clock output terminals (two for SDR mode SDRAM and two for DDR mode SDRAM). However, in this embodiment, the number of clock output terminals can be reduced to two.

  As described above, the present embodiment shows the case where the LVTTL buffers 6 and 7, the selectors 10 and 11, and the two clock output terminals CK1 / CK and CK2 / CK # are provided. , LVTTL buffers, selectors, and clock output terminals are provided in a number corresponding to the number of SDR mode SDRAMs connected to the system LSI (SDRAM control device). However, regarding the DDR mode SDRAM connected to the system LSI (SDRAM control device), even if the number of connections increases, the number of SSTL-2 buffers and clock output terminals is not affected.

It is a block diagram which shows the structure of the SDRAM control apparatus which concerns on one embodiment of this invention. FIG. 2 is a block diagram showing a configuration when one SDR mode SDRAM is connected to the SDRAM control device shown in FIG. 1. FIG. 2 is a block diagram showing a configuration when two SDR mode SDRAMs are connected to the SDRAM control device shown in FIG. 1. FIG. 2 is a block diagram showing a configuration when two DDR mode SDRAMs are connected to the SDRAM control device shown in FIG. 1.

Explanation of symbols

1 SDRAM control unit 2 CPU
3 flip-flop 4 clock generator 5 inverter 6 LVTTL buffer (one of a plurality of first clock signal output means)
7 LVTTL buffer (another one of a plurality of first clock signal output means)
8 SSTL-2 buffer (second clock signal output means)
9 SSTL-2 buffer (third clock signal output means)
10 selector (first selection means)
11 Selector (second selection means)
12 SDR mode SDRAM (first type of memory)
13 SDR mode SDRAM (first type of memory)
14 DDR mode SDRAM (second type of memory)
15 DDR mode SDRAM (second type of memory)
16 CPU bus

Claims (9)

In a clock signal supply device capable of supplying a clock signal to two types of memories that operate in different operation modes based on the clock signal,
A plurality of first clock signal output means for outputting a first clock signal to be supplied to the first type of memory;
Second clock signal output means for outputting a second clock signal to be supplied to the second type of memory;
Third clock signal output means for outputting a third clock signal to be supplied to the second type of memory;
Select one of the first clock signal output from one of the plurality of first clock signal output means and the second clock signal output from the second clock signal output means A first selection means for outputting to the first output terminal;
One of the first clock signal output from the other one of the plurality of first clock signal output means and the third clock signal output from the third clock signal output means Second selecting means for selecting and outputting to the second output terminal;
A flip-flop holding a value for operating the first selection means or the second selection means in different operation modes;
In order to operate the first selection unit or the second selection unit in different operation modes, a CPU that sets different values in the flip-flops corresponding to the operation modes;
A clock signal supply device comprising: When the clock input terminal of the first type memory is connected to the first output terminal, the first selection means outputs the one output from one of the plurality of first clock signal output means. clock signal supply system according to claim 1, wherein the selecting and outputting the first clock signal.   A clock input terminal of the first type first memory is connected to the first output terminal, and a clock input terminal of the first type second memory is connected to the second output terminal. The first selecting means selects and outputs the first clock signal output from one of the plurality of first clock signal output means, and the second selecting means includes the plurality of the first clock signals. 2. The clock signal supply device according to claim 1, wherein the first clock signal output from the other one of the first clock signal output means is selected and output.   The first output terminal is connected to the clock input terminals of the first and second memories of the second type, and the second output terminal is connected to the inverted clock input terminals of the first and second memories. Are connected, the first selection means selects and outputs the second clock signal output from the second clock signal output means, and the second selection means outputs the third clock signal. 2. The clock signal supply device according to claim 1, wherein the third clock signal output from the clock signal output means is selected and output.   The third clock signal output from the third clock signal output means is a clock signal obtained by inverting the phase of the second clock signal output from the second clock signal output means. The clock signal supply device according to claim 1.   2. The clock signal supply device according to claim 1, wherein the two types of memories are an SDRAM in an SDR mode and an SDRAM in a DDR mode.   7. The clock signal supply apparatus according to claim 6, wherein the plurality of first clock signal output means are constituted by LVTTL buffers, and the second and third clock signal output means are constituted by SSTL-2 buffers. .   2. The clock signal supply apparatus according to claim 1, wherein the clock signal supply apparatus is included in a system LSI, and the two types of memories can be connected to the system LSI. Control means for transferring data to the first type memory or the second type memory, and a CPU bus connecting the CPU and the control means, the CPU being connected via the CPU bus The clock signal supply device according to claim 1 , wherein a value is set in the flip-flop.

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