KR20070036637A - Internal address generator and operation method - Google Patents

Abstract

The present invention is to provide an internal address generating apparatus having a low power consumption, the present invention for this purpose change detection means for detecting a change in the newly applied current address for the internal-address to output a comparison signal; Drive pulse supply means for supplying first to fourth drive pulses in response to the comparison signal; Input latch means for latching the current address and outputting the current address to the internal address in response to the comparison signal and the read / write signal; AL delay means for outputting the internal-address in synchronization with the first driving pulse to have a delay time corresponding to an additive latency; CL delay means for outputting the output address of the AL delay means in synchronism with the second driving pulse to have a delay time corresponding to the cascade latency; And outputting the output address of the AL delay means as a read-column address in synchronization with the third driving pulse, or outputting the output address of the CL delay means as a write-column address in synchronization with the fourth driving pulse. An internal address generating apparatus including latch means is provided.

Additive latency, cascade latency, address, power consumption, comparison

Description

Internal address generator and its driving method {INTERNAL ADDRESS GENERATOR AND OPERATION METHOD}

1 is an operation waveform diagram until a read command is applied and corresponding data is output to the outside.

2 is an operation waveform diagram while a write command and corresponding data are stored.

3 is a block diagram of an internal address generation device of a semiconductor memory device according to the prior art;

4 is an internal circuit diagram of an input latch unit of FIG. 3.

5 is an internal circuit diagram of the shift register in the AL delay unit and the CL delay unit.

6 is an internal circuit diagram of an address generator of a semiconductor memory device according to an embodiment of the present invention.

7 is an internal circuit diagram of the change detection unit of FIG. 6.

8 is an internal circuit diagram of an input latch unit of FIG. 6.

9 is an internal circuit diagram of a driving pulse supply unit of FIG. 6.

* Explanation of symbols for the main parts of the drawings

100: change detection unit

200: drive pulse supply unit

300: input latch unit

400: AL delay unit

500: CL delay unit

600: output latch unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to an internal address generator of a semiconductor memory device having low power consumption.

A typical DRAM has a function of extending the operability of a memory by allowing the operation of the DRAM to be set in a user's environment through a mode register set (MRS) and an extended mode register set (EMRS).

In particular, in the semiconductor memory device of DDR II SDRAM or more, the concept of additive latency (AL) and cas latency (CL) has been introduced. In this case, when the read command is applied from the outside, the latency is set by the logic configuration in the corresponding DRAM when the external read command is applied. Even though the clock frequency changes, the internal latency does not change. This is to ensure normal operation. This is set via MRS.

In addition, the additive latency is to increase the efficiency of the data bus, to apply a read command or a write command in the minimum ras to cas delay (tRCD_min), and to apply a command before the tRCD_min by the additive latency. This is set by the EMRS.

Meanwhile, as described above, a process in which a read command or a write command is applied and driving corresponding thereto is performed will be described in detail with reference to a timing diagram.

1 is an operation waveform diagram until a read command is applied and corresponding data is output to the outside.

As shown in FIG. 1, a read command RD and an address ADDR are applied, and are output as an external read signal EXT_RD and an external address EXT_ADDR in synchronization with an internal voltage level and an internal clock CLK. .

Subsequently, the external read signal EXT_RD and the external address EXT_ADDR are output as the internal read signal IRD and the read-column address IADDR after a time corresponding to the additive latency AL from the time of activation.

Subsequently, the device performs a read operation in response to the internal read signal IRD to output data stored in a cell corresponding to the read-column address IADDR. In this case, the time point at which the data DQ is output is after a delay time corresponding to the cascade latency CL from the time point at which the internal read signal IRD is activated.

Accordingly, the read latency RL, which means the time required until the read command RD is applied and the corresponding data DQ is output, may be expressed as the sum of the additive latency AL and the cascade latency CL. have.

2 is an operation waveform diagram while a write command and corresponding data are stored.

As shown in FIG. 2, the write command WT and the address ADDR are applied to be activated by the external write signal EXT_WT and the external address EXT_ADDR in synchronization with the internal voltage level and the internal clock CLK.

Next, the external write signal EXT_WT and the external address EXT_ADDR are internal write signals IWT and write-column address IADDR after a time corresponding to the write latency AL + CL -1 from the time of activation. Will be displayed.

In this case, since 4 bits of data are externally applied, the device performs a write operation of storing data applied to a cell corresponding to the write-column address IADDR in response to the internal write signal IWT.

Meanwhile, a block for generating an address applied together with a write command and a read command as an internal column address after a delay time corresponding to an additive latency or a write latency will be described.

3 is a block diagram of an internal address generator of a semiconductor memory device according to the prior art.

Referring to FIG. 3, an internal address generator according to the related art includes an input latch unit 10 for latching an address LA in response to a read write signal RDWT and outputting the internal address to the internal address INT_ADD. The AL delay unit 20 for outputting the delay time corresponding to the activity latency by synchronizing the address INT_ADD to the clock CLK and outputting the delay time to the AL delay address RDLA, and the AL delay address RDLA. ), The CL delay unit 30 for outputting to the CL delay-address (WTLA) by synchronizing the write-pulse (CLKWT) with the delay time corresponding to the cascade latency, and the AL delay-address (RDLA) and the CL delay. And an output latch section 40 for outputting the address WTLA to the read-column address RCA or the write-column address WCA in synchronization with the corresponding pulses IRDP and IWTP, respectively.

For reference, the read write signal RDWT is activated when a read command RD or a write command WT is applied, and a column type command such as a read command RD and a write command WT is applied. It is a flag signal to inform that.

In addition, the write-clock CLKWT is a clock that is activated when the write command WT is applied.

4 is an internal circuit diagram of the input latch unit 10 of FIG. 3.

Referring to FIG. 4, the input latch unit 10 latches an output signal of the transfer gate TG1 for transmitting the address LA and an output signal of the transfer gate TG1 in response to the read / write signal RDTW. And a latch 12 for outputting to the address INT_ADD.

Meanwhile, the driving of the internal address generator shown in FIGS. 3 and 4 will be briefly described.

First, the read / write signal RDWT is activated by application of the column-based command and address.

Subsequently, the input latch unit 10 latches the address LA in response to the read / write signal RDWT and outputs the internal address to the internal address INT_ADD.

Next, the AL delay unit 20 delays the internal address INT_ADD in synchronization with the clock CLK, but AL delay-address an address having a delay corresponding to the additive latency information signal AL <0: N>. Output as (RDLA).

Next, the CL delay unit 30 delays the AL delay-address RDLA in synchronization with the write-clock CLKWT, thereby delaying an address having a delay corresponding to the cascade latency information signal CL <2: M>. Output to address (WTLA).

Subsequently, when the write-drive signal IRDP is activated, the output latch unit 40 outputs the CL delay-address WTLA to the write-column address WCA in synchronization with the write-drive signal IRDP. When the read-drive signal IRDP is activated, the AL delay-address RDALA is output to the read-column address RCA in synchronization with the read-pulse.

For reference, the additive latency information signal AL <0: N> and the cascade latency information signal CL <0: N> are signals of a plurality of bits, and the set additive latency AL and the cascade latency CL are respectively set. The corresponding bit is activated.

In addition, the read-drive signal IRDP is activated after a delay time corresponding to the additive latency from the application of the read command RD. The read-drive signal IRDP is a signal indicating the output time of the read-column address RCA. The write-drive signal IRDP is a signal that is activated after a delay time corresponding to the write latency from the application of the write command WT and informs the output time of the write-column address WCA.

Meanwhile, the AL delay unit 20 and the CL delay unit 30 according to the related art are used to provide a delay corresponding to an additive latency or a cascade latency to an applied address, and include a plurality of shifts for delaying an input address. With a register. Since a plurality of shift registers have the same circuit implementation, only one is considered as an example.

5 is an internal circuit diagram of the shift register in the AL delay unit and the CL delay unit.

Referring to FIG. 5, the shift register is supplied with data as an input signal 'A' and a driving clock as 'B'. And the signals 'C' and 'D' are output signals.

For example, in the case of a shift register provided in the AL delay unit 20, the clock CLK is applied to the input signal 'B'. In the case of the shift register provided in the CL delay unit 30, the write-pulse CLKWT is applied to the input signal 'B'. That is, the shift register latches the input signal 'A' in response to the logic level of the input signal 'B', which is a driving clock, and outputs the output signals as 'C' and 'D'.

Accordingly, the shifter registers in the AL delay unit 20 and the CL delay unit 30 continue to drive while the drive clock is applied to consume power. For example, even when a drive is not required, such as a case where a newly applied address is the same as an existing address, it is driven to consume current.

As described above, the internal address generator according to the related art generates unnecessary current consumption since the internal address generator is driven continuously while the driving clock is applied even though the address is successively applied.

The present invention has been proposed in order to solve the above problems of the prior art, and an object thereof is to provide an internal address generator having low power consumption.

According to an aspect of the present invention, there is provided an apparatus for generating an internal address, the apparatus comprising: change detection means for detecting a change in a newly applied current address for an internal address and outputting a comparison signal; Drive pulse supply means for supplying first to fourth drive pulses in response to the comparison signal; Input latch means for latching the current address and outputting the current address to the internal address in response to the comparison signal and the read / write signal; AL delay means for outputting the internal-address in synchronization with the first driving pulse to have a delay time corresponding to an additive latency; CL delay means for outputting the output address of the AL delay means in synchronism with the second driving pulse to have a delay time corresponding to the cascade latency; And outputting the output address of the AL delay means as a read-column address in synchronization with the third driving pulse, or outputting the output address of the CL delay means as a write-column address in synchronization with the fourth driving pulse. A latch means is provided.

According to another aspect of the present invention, there is provided an apparatus for generating an internal address, the apparatus comprising: change detection means for detecting a change in a current address with respect to an internal address and outputting a comparison signal; Drive pulse supply means for supplying a read-drive pulse or a write-drive pulse in response to the comparison signal; Input latch means for latching the current address into the internal address in response to the comparison signal; Read address generation means for synchronizing with the read-drive pulse to output a delay corresponding to an additive latency to the internal-address and outputting the internal-read address; And write address generation means for giving a delay corresponding to a write latency to the internal-address in synchronization with the write-drive pulse and outputting the internal-write address.

According to still another aspect of the present invention, there is provided a method of driving an internal address generating apparatus, comprising: comparing a newly applied current address with an internal address and determining whether the internal address is different; And a generation step of giving a delay to the current address and outputting the inner-column address only when the value is different in the determining step.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

6 is an internal circuit diagram of an internal address generator of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, the apparatus for generating an internal address according to the present invention includes a change detection unit 100 for detecting a change in a current address LA with respect to an internal address INT_ADD and outputting it as a comparison signal COMP. The drive pulse supply unit 200 for supplying a plurality of drive pulses C_CLK, C_CLKWT, C_IRDP, and C_IWTP in response to the comparison signal COMP, and the current address in response to the comparison signal COMP and the read / write signal RDWT. The address generators 300, 400, 500, and 600 for synchronizing the LA to a plurality of driving pulses C_CLK, C_CLKWT, C_IRDP, and C_IWTP to give a delay and output the internal-column addresses RCA and WCA, respectively. Include.

Here, the address generator includes an input latch unit 300 for latching the current address LA and outputting the current address LA to the internal address INT_ADD in response to the comparison signal COMP and the read / write signal RDTW, and a read-drive pulse. A read address generator 400 or 600 for giving a delay corresponding to the additive latency to the internal address INT_ADD in synchronization with (C_CLK, C_IRDP) and outputting it to the read-column address RCA, and a write-drive. Write address generator 400, 500, 600 for outputting to write-column address WCA by giving delay corresponding to write latency to internal address INT_ADD in synchronization with pulses C_CLK, C_CLKWT, C_IWTP) ).

The read address generator generates an AL delay unit 400 and an AL delay unit 400 for outputting the internal-address INT_ADD in synchronization with the first driving pulse C_CLK to have a delay time corresponding to the additive latency. And an output latch unit 600 for outputting the output address to the read-column address RCA in synchronization with the third driving pulse C_IRDP.

Also, the write address generator generates an AL delay unit 400 for outputting the internal-address INT_ADD in synchronization with the first driving pulse C_CLK to have a delay time corresponding to the additive latency, and a second driving pulse ( CL drive unit 500 and the output address of CL delay unit 500 for outputting the output address of AL delay unit 400 having a delay time corresponding to cas latency in synchronization with C_CLKWT). And an output latch unit 600 for outputting to the read-column address RCA or the write-column address WCA in synchronization with (C_IWTP).

Meanwhile, the read address generator and the write address generator share the AL delay unit 300, and the output latch unit 600 is activated by receiving the output addresses of the AL delay unit 400 and the CL delay unit 500. In response to the third driving pulse C_IRDP or the fourth driving pulse C_IWTP, the corresponding addresses are output as read-column addresses RCA or write-column addresses WCA, respectively.

As described above, the semiconductor memory device according to the present invention detects whether or not the newly applied current address LA is the same as the previously applied latched internal-address INT_ADD through the change detector 100. The AL delay unit 400, the CL delay unit 500, and the output latch unit 600 are selectively driven by supplying a plurality of driving pulses through the driving pulse supply unit 200 only when the value of the address is changed. That is, the delay units are driven only when an address having a different value from the previous one is applied.

Therefore, the internal address generator according to the present invention does not activate the AL and CL delay units 400 and 500 when the newly applied address LA does not change, resulting in unnecessary driving of the delay units 400 and 500. Reduce current consumption

Meanwhile, the internal circuit diagram of each block will be described below.

FIG. 7 is an internal circuit diagram of the change detector 100 of FIG. 6.

Referring to FIG. 7, the change detector 100 has a delay unit 120 for delaying the internal address INT_ADD for a predetermined time, an output address and a current address LA of the delay unit 120 as inputs. A logic exclusive sum gate XOR1 for outputting the comparison signal COMP is provided.

Therefore, the change detection unit 100 deactivates the comparison signal COMP to the logic level 'L' when the previously-applied internal address INT_ADD and the newly applied address LA are the same. Activates the comparison signal COMP at a logic level 'H'.

FIG. 8 is an internal circuit diagram of the input latch unit 300 of FIG. 6.

Referring to FIG. 8, the input latch unit 300 includes a controller ND1 for activating a control signal when both the read / write signal RDWT and the comparison signal COMP are activated, and the current address when the control signal is activated. A transfer gate TG2 for delivering LA, and a latch 320 for latching an output signal of the transfer gate TG2 and outputting the internal signal to the internal address INT_ADD.

Here, the control unit includes a NAND gate ND1 for outputting a control signal by receiving the read / write signal RDWT and the comparison signal COMP.

Referring to the driving of the input latch unit 300 described above, when the read / write signal RDWT and the comparison signal COMP are activated, the applied current address LA is latched and output as the internal address INT_ADD. .

9 is an internal circuit diagram of the driving pulse supply unit 200 of FIG. 6.

Referring to FIG. 9, the driving pulse supply unit 200 may include a first pulse supply unit for outputting the clock CLK as the first driving pulse C_CLK when the comparison signal COMP is activated, and the comparison signal COMP. A second pulse supply unit for outputting the write-clock CLKWT to the second driving pulse C_CLKWT upon activation, and a read-drive signal IRDP to the third driving pulse C_IRDP when the comparison signal COMP is activated. And a fourth pulse supply unit for outputting the fourth pulse supply unit to output the write-drive signal IRDP as the fourth driving pulse C_IWTP when the comparison signal COMP is activated.

The first pulse supply unit includes an NAND gate ND2 having a clock CLK and a comparison signal COMP as an input, and an inverter for inverting an output signal of the NAND gate ND2 as a first driving pulse C_CLK. I2).

The second pulse supply unit is configured to invert the output signal of the NAND gate ND3 and the NAND gate ND3 having the write-clock CLKWT and the comparison signal COMP as an input and output the inverted output signal to the second driving pulse C_CLKWT. An inverter I3 is provided.

The third pulse supply unit inverts the NAND gate ND4 having the read-drive signal IRDP and the comparison signal COMP as an input and the output signal of the NAND gate ND4 to output the third driving pulse C_IRDP. Inverter I4 is provided.

The fourth pulse supply unit inverts the NAND gate ND5 having the write-drive signal IRDP and the comparison signal COMP as an input and the output signal of the NAND gate ND5 to output the fourth driving pulse C_IWTP. Inverter I5 is provided.

Briefly referring to the operation, the driving pulse supply unit 200 outputs a signal applied to the driving pulse when the comparison signal COMP is activated. In this case, when the read / write signal RDWT is activated by the write command WT, only the write-clock CLKWT and the write-drive signal IWTP are activated, so that the driving pulse supply unit 200 generates the first driving pulse. C_CLK, the second driving pulse C_CLKWT, and the fourth driving pulse C_IWTP are output. In addition, when the read / write signal RDWT is activated by the read command RD, only the read-drive signal IRDP is activated, so that the driving pulse supply unit 200 generates the first driving pulse C_CLK and the third driving pulse. Outputs (C_IRDP). For reference, the clock CLK is for driving a semiconductor memory device having an internal address generator and is always toggled regardless of input of a command.

In addition, when the comparison signal COMP is deactivated, the driving pulse supply unit 200 generates a clock CLK, a write-clock CLKWT, a read-drive signal IRDP, or a write drive signal by a corresponding read command or write command. Even if IWTP is activated, the first to fourth driving pulses C_CLK, C_CLKWT, C_IRDP, and C_IWTP are maintained at a logic level 'L' and output.

Meanwhile, the operation of the internal read address generator according to the present invention shown in FIGS. 6 to 9 will now be described.

First, it is assumed that a new address LA applied together with the read write signal RDWT is different from the previously applied and latched internal-address INT_ADD. It is assumed that the read write signal RDWT is activated by the read command RD.

The change detector 100 activates the comparison signal COMP because the current address LA has a different address value from the internal address INT_ADD.

Subsequently, the driving pulse supply unit 200 outputs the first driving pulse C_CLK and the third driving pulse C_IRDP in response to the activation of the comparison signal COMP.

In addition, the input latch unit 300 latches the current address LA and outputs it to the internal address INT_ADD in response to the activation of the read / write signal RDWT and the comparison signal COMP.

Next, the AL delay unit 400 delays the internal-address INT_ADD in synchronization with the first driving pulse C_CLK, and provides an address having a delay corresponding to the additive latency information signal AL <0: N>. Output as AL delay-address (RDLA).

Subsequently, the output latch unit 600 outputs the AL delay address RDLA to the read-column address RCA in synchronization with the activated third driving pulse C_IRDP.

On the other hand, it is assumed that the read write signal RDWT is activated by the write command WT, and the new address LA applied together is different from the previously applied and latched internal-address INT_ADD.

The change detector 100 activates the comparison signal COMP because the current address LA has a different address value from the internal address INT_ADD.

Subsequently, the driving pulse supply unit 200 outputs the first driving pulse C_CLK, the second driving pulse C_CLKWT, and the fourth driving pulse C_IWTP in response to the activation of the comparison signal COMP.

In addition, the input latch unit 300 latches the current address LA in response to the activation of the read / write signal RDTWT and the comparison signal COMP, and outputs the current address LA as an internal-address INT_ADD.

Next, the AL delay unit 400 delays the internal-address INT_ADD in synchronization with the first driving pulse C_CLK, and provides an address having a delay corresponding to the additive latency information signal AL <0: N>. Output as AL delay-address (RDLA).

Subsequently, the CL delay unit 500 delays the AL delay address RDLA in synchronization with the second driving pulse C_CLKWT, and stores an address having a delay corresponding to the cascade latency information signal CL <2: M>. Output in CL delay-address (WTLA).

Subsequently, the output latch unit 600 outputs the CL delay-address WTLA to the write-column address WCA in response to the activation of the fourth driving pulse C_IWTP.

Meanwhile, the operation according to the case where the newly applied current address LA together with the column address is the same as the internal address INT_ADD will be described.

The change detector 100 deactivates the comparison signal COMP because the current address LA has the same address value for the internal address INT_ADD.

Subsequently, the driving pulse supply unit 200 maintains and outputs all of the first to fourth driving pulses C_CLK, C_CLKWT, C_IRDP, and C_IWTP at logic level 'L' in response to the deactivation of the comparison signal COMP. Also, the input latch unit 300 does not receive the address LA in response to the deactivation of the comparison signal COMP.

Subsequently, the AL delay unit 400, the CL delay unit 500, and the output latch unit 600 are not activated because the driving pulses are not activated.

As described above, when the value of the newly applied current address LA is the same as the latched internal-address INT_ADD, the internal address generator according to the present invention uses the first to fourth driving pulses C_CLK, By deactivating C_CLKWT, C_IRDP, and C_IWTP, the AL delay unit 400, the CL delay unit 500, and the output latch unit 600 are not driven. That is, the internal address generation device does not change the current address, so that unnecessary driving for generating a new column-address corresponding thereto does not occur, thereby preventing power consumption. Such an internal address generator is provided for each bit unit of the address. For example, in the case of 512MB or 1GB semiconductor memory devices, since 11 internal address generators are provided, it can be obtained by preventing power consumption due to unnecessary driving. The effect is larger the greater the number of address bits.

Meanwhile, in the above-described present invention, only a block for generating a column address is illustrated, but the idea of the present invention may be applied to a block for generating a corresponding internal address by receiving a bank address or a row address, and the like. The same effect of reduction can be achieved.

In addition, by detecting whether the value of the newly applied current address is changed, the output of the buffer stage receiving the address is directly controlled to prevent unnecessary driving for generating a new column-address corresponding to the same address. It can prevent.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the above-described present invention, when a value applied to consecutive addresses is not changed for an address previously latched, driving for generating an address corresponding thereto is not performed, thereby preventing power consumption due to unnecessary driving.

Claims (22)

Change detection means for detecting a change in the newly applied current address for the internal address and outputting a comparison signal; Drive pulse supply means for supplying first to fourth drive pulses in response to the comparison signal; Input latch means for latching the current address and outputting the current address to the internal address in response to the comparison signal and the read / write signal; AL delay means for outputting the internal-address in synchronization with the first driving pulse to have a delay time corresponding to an additive latency; CL delay means for outputting the output address of the AL delay means in synchronism with the second driving pulse to have a delay time corresponding to the cascade latency; And An output latch for outputting the output address of the AL delay means to a read-column address in synchronization with the third drive pulse, or for outputting the output address of the CL delay means to a write-column address in synchronization with the fourth drive pulse; Way Internal address generation device comprising a. The method of claim 1, The change detection means, A delay unit for delaying the inner-address for a predetermined time; And a logic exclusive sum gate for outputting the comparison signal by taking the output address of the delay section and the current address as inputs; Address generating apparatus characterized in that. The method of claim 2, The drive pulse supply means, A first driving pulse supply unit for supplying a clock to the first driving pulse when the comparison signal is activated; A second driving pulse supply unit for supplying a write-pulse activated when the write command is applied to the second driving pulse in response to the activation of the comparison signal; A third drive pulse supply unit for supplying a read-drive signal activated when the read command is applied to the third drive pulse in response to the activation of the comparison signal; And a fourth driving pulse supply unit configured to supply a write-drive signal activated when the write command is applied to the fourth driving pulse in response to the activation of the comparison signal. An internal address generator, characterized in that. The method of claim 3, The input latch means, A controller for activating a control signal when both the comparison signal and the read / write signal are activated; A transfer gate for transferring the current address when the control signal is activated; And a latch for latching an output signal of the transfer gate to output the internal-address. An internal address generator, characterized in that. The method of claim 4, wherein And the control unit includes a NAND gate for outputting the control signal by receiving the read / write signal and the comparison signal as inputs. The method of claim 4, wherein The first driving pulse supply unit includes a first NAND gate having an input of the comparison signal and the clock, and a first inverter for inverting an output signal of the first NAND gate to output the first driving pulse, The second driving pulse supply unit includes a second NAND gate having an input of the comparison signal and the write-pulse, and a second inverter for inverting an output signal of the second NAND gate to output the second driving pulse. , The third drive pulse supply unit includes a third NAND gate having an input of the comparison signal and the read-drive signal, and a third inverter for inverting an output signal of the third NAND gate to output the first drive pulse. Include, The fourth driving pulse supply unit includes a fourth NAND gate having an input of the comparison signal and the write-drive signal, and a fourth inverter for inverting an output signal of the fourth NAND gate to output the fourth driving pulse. Including An internal address generator, characterized in that. Change detection means for detecting a change in the current address with respect to the inner address and outputting a comparison signal; Drive pulse supply means for supplying a read-drive pulse or a write-drive pulse in response to the comparison signal; Input latch means for latching the current address to the internal address in response to the comparison signal and the read / write signal; Read address generation means for synchronizing with the read-drive pulse to output a delay corresponding to an additive latency to the internal-address and outputting the internal-read address; And Write address generation means for outputting to an internal-write address by giving a delay corresponding to a write latency to the internal-address in synchronization with the write-drive pulse; Internal address generation device of a semiconductor memory device comprising a. The method of claim 7, wherein The change detection means, A delay unit for delaying the inner-address for a predetermined time; And a logic exclusive sum gate for outputting the comparison signal by taking the output address of the delay section and the current address as inputs; An internal address generator, characterized in that. The method of claim 8, The input latch means, A controller for activating a control signal when both the comparison signal and the read / write signal are activated; A transfer gate for transferring the current address when the control signal is activated; And a latch for latching an output signal of the transfer gate to output the internal-address. An internal address generator, characterized in that. The method of claim 9, The read address generating means, A first delay unit for giving a delay corresponding to an additive latency to the internal address in synchronization with a first read-drive pulse; And a read output unit configured to output an output address of the AL delay unit to the internal read address in synchronization with the second read-drive pulse. An internal address generator, characterized in that. The method of claim 10, The write address generating means is A second delay unit for synchronizing the internal-address with a first write-drive pulse to output a delay time corresponding to an additive latency; A third delay unit for outputting the output address of the second delay unit in synchronization with a second write-drive pulse having a delay time corresponding to the cascade latency; And a write output unit for outputting the output address of the third delay unit to the write-column address in synchronization with a third write-drive pulse. An internal address generator, characterized in that. The method of claim 11, The first read-drive pulse and the first write-drive pulse are the same signal that is activated when a read command or a write command is applied, Wherein the read and write address generation means share the first and second delay units that are driven in synchronization therewith An internal address generator, characterized in that. The method of claim 12, The drive pulse supply means, A first driving pulse supply unit for supplying a clock to the first read-drive pulse and the first write-drive pulse when the comparison signal is activated; A second driving pulse supply unit for supplying the write-pulse activated when the write command is applied to the second write-drive pulse in response to the activation of the comparison signal; A third driving pulse supply unit for supplying a read-drive signal activated when the read command is applied to the second read-drive pulse in response to activation of the comparison signal; And a fourth driving pulse supply unit configured to supply a write-drive signal activated when the write command is applied to the third write-drive pulse in response to activation of the comparison signal. An internal address generator, characterized in that. The method of claim 13, The first driving pulse supply unit inverts a first NAND gate having an input of the comparison signal and the clock, and an output signal of the first NAND gate to the first read-drive pulse and the first write-drive pulse. A first inverter for outputting, The second driving pulse supply unit includes a second NAND gate having the comparison signal and the write-pulse as an input, and a second inverter for inverting the output signal of the second NAND gate as the second write-drive pulse. Including; The third driving pulse supply unit includes a third NAND gate having an input of the comparison signal and the read-drive signal, and a third for inverting the output signal of the third NAND gate to output the second read-drive pulse. Including an inverter, The fourth driving pulse supply unit includes a fourth NAND gate having an input of the comparison signal and the write-drive signal, and a fourth for inverting the output signal of the fourth NAND gate to output the third write-drive pulse. Comprising an inverter An internal address generator, characterized in that. Change detection means for detecting a change in the current address with respect to the inner address and outputting a comparison signal; Drive pulse supply means for supplying a drive pulse in response to the comparison signal; And Delay means for outputting the current address to the internal address by synchronizing the current address with the driving pulse in response to a flag signal and the comparison signal; Internal address generation device comprising a. The method of claim 15, The change detection means, A first delay unit for delaying the inner-address for a predetermined time; And a logic exclusive sum gate for outputting the comparison signal by taking the output address of the delay section and the current address as inputs; Address generating apparatus characterized in that. The method of claim 16, The driving pulse supply unit, And a NAND gate having the comparison signal and an input pulse as an input, and an inverter for inverting the output signal of the NAND gate and outputting the driving pulse. An internal address generator, characterized in that. Comparing the newly applied current address with the value of the inner-address to determine whether it is different; And A generation step of giving a delay to the current address and outputting it to an inner-column address only when the value is different in the determining step Method of driving an internal address generating device comprising a. The method of claim 18, And if the values are the same in the determining step, driving of the generating step is not performed. The method of claim 19, The generating step, Receiving the current address as the internal address; Giving a delay corresponding to an additive latency or a cascade latency to the inner-address and outputting the delay to the inner-column address. A method of driving an internal address generator, characterized in that. The method of claim 20, In the output step, When the current address is applied together with a read command, only a delay corresponding to the additive latency is given. When the current address is applied together with a write command, a delay corresponding to the additive latency and the cascade latency is provided. Output to the inner-column address A method of driving an internal address generator, characterized in that. Comparing the N-th applied address with the N-th applied address to determine whether they are different; In the determining step, driving is terminated when the values are the same, and when the values are different, a delay is applied to the Nth applied address to generate an internal address and output the result. Method of driving an internal address generating device comprising a.

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