JP2008293413A - Accessing method for extension memory, electronic equipment, and memory module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To use a memory module having a data input/output terminal with bus width which is at least two times as wide as that of the internal bus of the electronic equipment as the extension memory of the electronic equipment. <P>SOLUTION: A plurality of segments obtained by dividing the data input/output part of an extension memory slot 3 by prescribed bit width are connected to a memory control means 6 in parallel by using segments for storing word data to be input/output as units, and this memory control means 6 is provided with a decode means 4 for decoding a signal to specify word data, and for generating a mask signal by removing the segment for storing word data assigned to the signal from the plurality of segments, and configured to transmit the generated mask signal to the extension memory slot 3 with the address. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of accessing an additional memory using a memory module having a data input / output terminal having a bus width at least twice as large as the internal bus of the electronic device, and an electronic device and a memory for executing the method Regarding modules.

For example, an electronic device such as a facsimile multifunction peripheral has a higher performance as it becomes a higher-end machine, and therefore, the higher-end machine generally tends to have a wider internal bus than a lower-end machine. However, if an additional memory corresponding to the bus width is prepared for each model having a different internal bus width, there is a problem in that parts management becomes complicated and costs increase.
As an example of the prior art applicable to this problem, in the following Patent Document 1, in a system including a processor and a memory, a bus arbitration circuit is provided between the memory and the system bus, and the bus width of the processor is determined. It is described that when the memory is 1 / N, the bus arbitration circuit converts one access of the processor into N accesses to the memory, and if this technique is applied, the internal bus of the electronic device is described. An additional memory with a bus width narrower than the width of the can be used.
Japanese Patent Application No. 4-114246

However, in order for an electronic device to fully perform, the expansion memory must have the same bus width as the internal bus of the device. In this case, in order not to sacrifice the performance of the high-end machine, it is desirable that the bus width of the additional memory is the width of the internal bus of the high-end machine.
Accordingly, the present invention provides an access method for an additional memory using a memory module having a data input / output terminal having a bus width at least twice that of the internal bus of the electronic device, and an electronic device for executing the method An object is to provide a memory module.

  In order to solve the above problems, an access method for an expansion memory according to claim 1 is an expansion memory that uses a memory module having a data input / output terminal having a bus width at least twice that of the internal bus of the electronic device. In this access method, part of a signal specifying word data to be processed is decoded, and word data assigned to the signal is accommodated from a plurality of segments obtained by dividing the data input / output terminals of the memory module. A step of generating a mask signal excluding a segment to be generated, a step of transmitting the generated mask signal together with an address to the memory module, and data input / output to / from a data input / output terminal of the memory module to accommodate word data Executing in parallel for each of the segments

  An electronic device according to a second aspect is an electronic device for executing the access method of the additional memory according to the first aspect, wherein the additional memory slot corresponding to a predetermined memory module and the additional memory slot Memory control means for controlling a memory module mounted on the memory module, and a data input / output section partitioned by the segment of the additional memory slot, in parallel, in units of segments containing word data of a predetermined bit width. And the memory control means decodes a part of the signal specifying the word data and excludes other segments excluding the segment to accommodate the word data assigned to the signal. Decoding means for generating a mask signal for masking, and the generated mask signal , Transmitted to the additional memory slot together with the address.

  The memory module according to claim 3 is the memory module according to claim 1, wherein the data input / output terminals divided into the segments, the mask terminals for inputting the mask signal, and the addresses are input. And a storage means having a function of invalidating input / output through a segment of the data input / output terminal corresponding to the input mask signal.

  According to the present invention, a memory module having a bus width wider than the width of the internal bus of the electronic device can be used. Therefore, it is sufficient to prepare only one type of bus width memory module as an extension memory for a plurality of models having different internal bus widths, which facilitates component management. Also, if the memory module is prepared for a high-end machine with a wide bus width, there is an effect that the performance of the high-end machine is not sacrificed.

  Hereinafter, the present invention will be described with reference to the drawings.

  FIG. 1 shows a first example of an electronic device to which the present invention is applied. The internal bus 7 of the device is 8 bits wide, but as an additional memory, a memory module 1 having a data input / output terminal of 64 bits wide. There is a feature in using.

  The memory module 1 includes data input / output terminals (DQ0 to DQ63), mask terminals (DQM0 to DQM7) for inputting mask signals, address terminals (A3 to An) for inputting addresses, and, for example, a synchronous dynamic random access memory. A storage means 2 composed of (SDRAM) is provided. The lower 3 bits (A0 to A2) of the address are assumed not to be used in the memory module 1 having a 64-bit width because it is assumed that an address is assigned to each word data having an 8-bit width in this embodiment.

  The SDRAM synchronizes various commands specified as combinations of control signals such as chip select (CS), row address strobe (RAS), column address strobe (CAS), and write enable (WE) and multiplexed addresses with the clock. The dynamic memory that receives and inputs and outputs data according to the command has a function of invalidating input and output through the data input and output terminals corresponding to the input mask signal.

  This function will be described for a commercially available SDRAM. In the × 4 bit configuration, the mask signal (DQM) controls data input / output (DQ0 to DQ3). That is, when the mask signal (DQM) is at the H level, the data of DQ0 to DQ3 is not output even if reading is performed, and the data of DQ0 to DQ3 is not written even if writing is performed. In the x8 bit configuration, the mask signal (DQM) controls the data input / output (DQ0 to DQ7) in the same manner. In the x16 bit configuration, the mask signal (LDQM) controls the data input / output (DQ0 to DQ7). The mask signal (UDQM) similarly controls data input / output (DQ8 to DQ15). In the × 32 bit configuration, the mask signal (DQM0) is data input / output (DQ0 to DQ7), the mask signal (DQM1) is data input / output (DQ7 to DQ15), and the mask signal (DQM2) is data input / output (DQM2). DQ16 to DQ23) and mask signal (DQM3) control data input / output (DQ24 to DQ31) in the same manner.

  The memory module 1 has a data input / output terminal having a 64-bit width by using these SDRAMs in parallel as the storage unit 2. For example, in the case of an SDRAM of x32 bit configuration, the memory module 1 can be realized by using at least two in parallel. The data input / output terminals (DQ0 to DQ63) are divided into 8-bit width segments respectively corresponding to the mask signals (DQM0 to DQM7). Note that the segment is not necessarily 8 bits wide, and if a memory of × 4 bits is used, for example, one segment may be 4 bits wide. The memory module 1 is also composed of a static random access memory (SRAM) having a function of invalidating input / output through a data input / output terminal corresponding to an input mask signal, similar to the SDRAM, and other memories. it can.

The expansion memory slot 3 is a slot into which the memory module 1 is detachably mounted. The expansion memory slot 3 has a connection portion corresponding to each terminal of the memory module, and controls the memory module 1 via the internal bus 8 of the device. The control means 6 is connected.
Similar to the memory module 1, the data input / output units (DQ0 to DQ63) of the additional memory slot 3 are divided into segments corresponding to the mask signals (DQM0 to DQM7). That is, the data input / output units of the additional memory slot 3 are (DQ0 to DQ7), (DQ8 to DQ15), (DQ16 to DQ23), (DQ24 to DQ31), (DQ32 to DQ39), (DQ40 to DQ47), ( Each of DQ48 to DQ55) and (DQ56 to DQ63) is a segment. At this time, word data having a width of 8 bits is accommodated in either of them.

The memory control means 6 is a memory interface for a CPU (not shown) of the apparatus, and is configured as a known SDRAM controller in this example, and generates a command for controlling the SDRAM and outputs it according to a clock. And a data input / output function for outputting word data of 8-bit width to be written to the memory module 1 or inputting word data of 8-bit width read from the memory module 1.
The addresses (A0 to An) output from the memory control means 6 are transmitted to the decoding means 4 and the multiplex means 5 through the address bus 8.
The decoding means 4 decodes the lower 3 bits (A0 to A2) of the transmitted address and generates a data mask signal (DQM0 to DQM7) according to the value. On the other hand, the multiplex means 5 multiplexes the addresses (A3 to An) excluding the lower 3 bits (A0 to A2).

  FIG. 2 is an example of a truth table showing the operation of the decoding means 4. As shown in this truth table, the decoding means 4 is assigned to the address from a plurality of segments that divide the data input / output unit of the memory module 1 in accordance with the value of the lower 3 bits of the address (A0 to A2). A mask signal excluding the segment that should contain the word data is generated. For example, when the value of the lower 3 bits (A0 to A2) of the address is “000”, the remaining segments (DQ8 to DQ15), (DQ16 to DQ23), (DQ24 to DQ31) excluding the segments (DQ0 to DQ7) ), (DQ32 to DQ39), (DQ40 to DQ47), (DQ48 to DQ55), and (DQ56 to DQ63) are invalidated to generate “01111111” as the mask signals (DQM0 to DQM7).

Access to the memory module 1 mounted in the additional memory slot 3 in the electronic apparatus having the above configuration is executed according to the following basic procedure.
That is, the lower 3 bits (A0 to A2) of the address (A0 to An) specifying the 8-bit wide word data to be processed are decoded, and the data input / output terminals (DQ0 to DQ63) of the memory module 1 are 8 bits. A step of generating a mask signal (DQM0 to DQM7) excluding a segment to accommodate word data assigned to the address (A0 to An) from a plurality of segments divided every time, and the generated mask signal (DQM0 to DQM0) DQM7) is transmitted to the memory module 1 together with other parts (A3 to An) of the address, and the data input / output to the data input / output terminals (DQ0 to DQ63) of the memory module is represented by segments (DQ0 to DQ7), ( DQ8 to DQ15), (DQ16 to DQ23), (DQ24 to DQ31), ( Q32~DQ39), (DQ40~DQ47), (DQ48~DQ55), and a step of executing in parallel to (DQ56~DQ63).

  FIG. 3 shows a second example of an electronic device to which the present invention is applied. The internal bus 7 of the device has a 16-bit width, but the additional memory has the same 64-bit width data as shown in FIG. A memory module 1 having input / output terminals is used. In the following, description of components common to the first embodiment will be omitted, and only differences will be described.

In this example, the expansion memory slot 3 is connected to a memory control means 6 that controls the memory module 1 via an internal bus 8 having a 16-bit width.
Similar to the memory module 1, the data input / output unit (DQ0 to DQ63) of the additional memory slot 3 is divided into segments corresponding to the mask signals (DQM0 to DQM7), and accommodates 16-bit word data. To do so, two segments are treated simultaneously as a set. For example, a set of 2 segments (DQ0 to DQ7) and (DQ32 to DQ39), a set of (DQ8 to DQ15), (DQ40 to DQ47), a set of (DQ16 to DQ23), and (DQ48 to DQ55), DQ24 to DQ31) and (DQ56 to DQ63) may be grouped. At this time, the word data having a 16-bit width is accommodated in one of the sets.

The memory control means 6 is different from the first embodiment in that word data having a 16-bit width is processed in one access. The addresses (A1 to An) output from the memory control means 6 are transmitted to the decoding means 4 and the multiplex means 5 through the address bus 8.
The decoding means 4 decodes the lower two bits (A1 to A2) of the transmitted address and generates data mask signals (DQM0 to DQM7) corresponding to the values. The multiplex means 5 multiplexes the addresses (A3 to An) excluding the lower 3 bits (A1 to A2).

  FIG. 4 is an example of a truth table showing the operation of the decoding means 4. As shown in this truth table, the decoding means 4 is assigned to the address from a plurality of segments that divide the data input / output unit of the memory module 1 according to the value of the lower 2 bits (A1 to A2) of the address. A mask signal excluding a set of segments that should contain the word data is generated. For example, when the value of the lower 3 bits (A1 to A2) of the address is “00”, the remaining segments (DQ8 to DQ15), (DQ16) excluding two segments (DQ0 to DQ7) and (DQ32 to DQ39) To DQ23), (DQ24 to DQ31), (DQ40 to DQ47), (DQ48 to DQ55), and (DQ56 to 63), "01110111" is generated as a mask signal (DQM0 to DQM7). On the other hand, the multiplex means 5 multiplexes the addresses (A3 to An) excluding the lower 2 bits (A1 to A2). The address (A0) is not used because the word data is 16 bits wide.

Access to the memory module 1 mounted in the additional memory slot 3 in the electronic apparatus having the above configuration is executed according to the following basic procedure.
That is, the lower 2 bits (A1 to A2) of the address (A1 to An) specifying the 16-bit width word data to be processed are decoded, and the data input / output terminals (DQ0 to DQ63) of the memory module 1 are 8 bits. A step of generating a mask signal (DQM0 to DQM7) excluding a set of segments that should contain word data assigned to the addresses (A1 to An) from a plurality of segments divided every time, and the generated mask signal ( DQM0 to DQM7) are transmitted to the memory module 1 together with other parts (A3 to An) of the address, and data input / output to the data input / output terminals (DQ0 to DQ63) of the memory module is a segment for accommodating word data (DQ0 to DQ7), (DQ32 to DQ39) and (DQ8 to DQ) 5) Steps executed in parallel with the set of (DQ40 to DQ47), the set of (DQ16 to DQ23), (DQ48 to DQ55), and the set of (DQ24 to DQ31) and (DQ56 to DQ63) Is executed.

  FIG. 5 shows a third example of an electronic device to which the present invention is applied. The internal bus 7 of the device has a 32-bit width, but the additional memory has the same 64-bit width data as shown in FIG. A memory module 1 having input / output terminals is used. In the following, description of components common to the first embodiment will be omitted, and only differences will be described.

In this example, the additional memory slot 3 is connected to the memory control means 6 that controls the memory module 1 via the internal bus 8 having a 32-bit width.
Similar to the memory module 1, the data input / output unit (DQ0 to DQ63) of the additional memory slot 3 is divided into segments corresponding to the mask signals (DQM0 to DQM7), and accommodates 32-bit wide word data. In order to do so, four segments are treated simultaneously as one set. For example, each of four segments (DQ0 to DQ7), (DQ16 to DQ23), (DQ32 to DQ39), (DQ48 to DQ55), (DQ8 to DQ15), (DQ24 to DQ31), (DQ40 to DQ47) , (DQ56 to DQ63). At this time, the 32-bit wide word data is accommodated in one of the sets.

The memory control means 6 is different from the first embodiment in that it processes 32-bit word data. The addresses (A2 to An) output from the memory control means 6 are transmitted to the decoding means 4 and the multiplex means 5 through the address bus 8.
The decoding means 4 decodes the lower 1 bit (A2) of the transmitted address and generates data mask signals (DQM0 to DQM7) corresponding to the value. On the other hand, the multiplexing means 5 has a function of multiplexing addresses (A3 to An) excluding the lower 3 bits (A2). The addresses (A0 to A1) are not used because one word is 32 bits.

FIG. 5 is an example of a truth table showing the operation of the decoding means 4 in this example. As shown in this truth table, the decoding means 4 uses a word assigned to the address from a plurality of segments that divide the data input / output unit of the memory module 1 according to the value of the lower 1 bit (A2) of the address. A mask signal excluding a segment that should contain data is generated.
For example, when the value of the lower 3 bits (A2) of the address is “0”, the remaining data input / output terminals (DQ0 to DQ7, DQ16 to DQ23, DQ32 to DQ39, DQ48 to DQ55) of the memory module 1 are excluded. As a mask signal (DQM0 to DQM7) for invalidating the data input / output terminals (DQ8 to DQ31, DQ40 to 63), “01110111” is generated. On the other hand, the multiplex means 5 has a function of multiplexing addresses (A3 to An) excluding the lower 2 bits (A1 to A2).

Access to the memory module 1 mounted in the additional memory slot 3 in the electronic apparatus having the above configuration is executed according to the following basic procedure.
That is, the lower 1 bit (A2) is decoded as a part of the address (A2 to An) specifying the 32-bit wide word data to be processed, and the 64-bit wide data input / output terminals (DQ0 to DQ63) of the memory module 1 are decoded. Generating a mask signal (DQM0 to DQM7) excluding a set of segments that should accommodate the word data allocated to the addresses (A2 to An) from a plurality of segments divided into 8 bits) The mask signal (DQM0 to DQM7) is transmitted to the memory module 1 together with other parts (A3 to An) of the address, and the data input / output to the data input / output terminals (DQ0 to DQ63) of the memory module Segments (DQ0 to DQ7), (DQ16 to DQ23), DQ32 to DQ39), (DQ48 to DQ55), and (DQ8 to DQ15), (DQ24 to DQ31), (DQ40 to DQ47), and (DQ56 to DQ63). Executed.

FIG. 7 shows a reference example of the present invention, in which the internal bus 7 of the device has a 64-bit width, and as an additional memory, a memory module having a data input / output terminal having the same 64-bit width as shown in FIG. 1 is used.
In this configuration, the additional memory slot 3 is connected to a memory control means 6 that controls the memory module 1 via an internal bus 8 having a 64-bit width.
The data input / output units (DQ0 to DQ63) of the expansion memory slot 3 are divided into segments corresponding to the mask signals (DQM0 to DQM7) respectively. However, in order to accommodate 64-bit wide word data, Segments are handled simultaneously.

  The memory control means 6 is different from the first embodiment in that it processes 64-bit wide word data. The addresses (A2 to An) output from the memory control means 6 are transmitted to the multiplex means 5 through the address bus 8. Note that the mask signals (DQM0 to DQM7) may always be “00000000”. In each of the above embodiments, the mask signal is generated by decoding the lower bits of the address, but the mask signal may be generated by decoding the upper bits of the address. Instead of the address, a mask signal may be generated by decoding a bank switching signal from the I / O.

  As can be understood from the configurations of the first to third examples and the reference example, in the present invention, the memory module 1 having the same configuration is provided with a plurality of electronic devices having different internal bus widths. It is characterized in that it can be used in common as a memory. Note that the memory module 1 is not limited to a 64-bit width as described here, and may have another bit width.

It is a schematic block diagram explaining the 1st example of the present invention. It is a truth table explaining operation | movement of the decoding means in a 1st Example. It is a schematic block diagram explaining the 2nd Example of this invention. It is a truth table explaining operation | movement of the decoding means in a 2nd Example. It is a schematic block diagram explaining the 3rd example of the present invention. It is a truth table explaining operation | movement of the decoding means in a 3rd Example. It is a schematic block diagram explaining the reference example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory module 2 Memory | storage means 3 Expansion memory slot 4 Decoding means 6 Memory control means 7 Internal bus

Claims (3)

An access method for an additional memory using a memory module having a data input / output terminal having a bus width at least twice that of the internal bus of the electronic device,
A mask obtained by decoding a part of a signal for specifying word data to be processed and excluding a segment for accommodating the word data assigned to the signal from a plurality of segments obtained by dividing the data input / output terminals of the memory module Generating a signal;
Transmitting the generated mask signal together with an address to the memory module;
And a method of executing data input / output to / from a data input / output terminal of the memory module in parallel with respect to each of the segments containing word data. An electronic device for executing the method for accessing an additional memory according to claim 1,
An expansion memory slot corresponding to a given memory module;
Memory control means for controlling the memory module mounted in the additional memory slot;
An internal bus connected to the memory control means in parallel, in units of segments containing word data of a predetermined bit width, the data input / output unit divided by the segment of the additional memory slot;
The memory control means includes
Decoding means for decoding a part of the signal specifying the word data and generating a mask signal for masking other segments excluding the segment to accommodate the word data assigned to the signal And transmitting the mask signal together with the address to the additional memory slot. The memory module according to claim 1,
A data input / output terminal divided into the segments; a mask terminal for inputting the mask signal; an address terminal for inputting the address;
And a memory module having a function of invalidating input / output through a segment of a data input / output terminal corresponding to an input mask signal.

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