JP2009194215A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, setting more accurately the orientation of a capacitive insulating film such as a ferroelectric film even when forming the film by a sol-gel method or a sputtering method. <P>SOLUTION: An amorphous Ir oxide film 54 as a part of a lower electrode film is formed and then a Pt film 91 is formed on the film 54. The Ir oxide film 54 is not oriented in any azimuth and hence the Pt film 91 is oriented itself and the Miller index of its surface is (111). Then, a Pt film 92 is formed on the Pt film 91. Since the Pt film 92 takes over the orientation of the Pt film 91, the Miller index of the surface of the Pt film 92 also is (111). Then, the capacitive insulating film 55 is formed on the Pt film 92 by the sputtering method. RTA is performed in an oxygen-containing atmosphere to form the entire capacitive insulating film 55 into a columnar crystal. The columnar crystal constituting the capacitive insulating film 55 takes over the orientation of the Pt film 92 and hence the Miller index of its surface is also (111). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method thereof.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, with respect to semiconductor memory devices, for example, in order to realize high integration of DRAM, as a capacitor insulating film of a capacitor element constituting the DRAM, a ferroelectric material or a high material is used instead of conventional silicon oxide or silicon nitride. Technologies using dielectric materials have been widely researched and developed.

  In addition, in order to realize a nonvolatile RAM that can perform a write operation and a read operation at a lower voltage and at a higher speed, a technique using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been actively researched and developed. Yes. Such a semiconductor memory device is called a ferroelectric memory (FeRAM).

  A ferroelectric memory stores information using the hysteresis characteristics of a ferroelectric. A ferroelectric memory is provided with a ferroelectric capacitor, and the ferroelectric capacitor is configured such that a ferroelectric film is sandwiched between a pair of electrodes as a capacitive dielectric film. The ferroelectric film generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. Further, if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read by detecting this spontaneous polarization. A ferroelectric memory operates at a lower voltage than a flash memory, and can be written at high speed with low power consumption. Then, use of a logic embedded chip (SoC: System on Chip) having a ferroelectric memory for an IC card or the like is being studied.

As the ferroelectric film, a PZT-based material film, a Bi layered structure compound film, or the like is used. Examples of the PZT-based material include lead zirconate titanate (PZT) itself and those obtained by doping a PZT film with La, Ca, Sr and / or Si. Examples of the Bi layer structure compound include SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ), and the like. The ferroelectric film is formed in an amorphous state or a fine equiaxed crystal (microcrystal) state on the lower electrode film by a sol-gel method or a sputtering method, and is then columnarized by heat treatment. Further, it may be formed in a columnar crystallized state on the lower electrode by MOCVD (Metal Organic Chemical Vapor Deposition) method.

  In addition, as a material for the electrode, a metal that is difficult to oxidize or a conductive oxide is used. For example, platinum, iridium, iridium oxide, etc. are mentioned. That is, platinum group metals or oxides thereof are mainly used. In addition, aluminum is mainly used as a wiring material.

The structure of the ferroelectric capacitor is roughly divided into a planar type structure and a stack type structure. Of these, the stack type structure is suitable for miniaturization. In the stack structure, the lower electrode is composed of a plurality of conductive films. Examples of such a conductive film include a TiN film, a TiAlN film, an Ir film, an IrO ₂ film, a Pt film, and a SrRuO ₃ film. A part of the conductive film also functions as a barrier metal film that prevents oxidation of the contact plug located under the lower electrode.

  The characteristics (especially switching charge amount) and yield of a ferroelectric capacitor often depend on the orientation of columnar crystals constituting the ferroelectric film. The orientation of the columnar crystals is easily affected by the orientation of the surface of the lower electrode. Therefore, in order to improve the characteristics and the yield, it is necessary to appropriately control the orientation of the crystals constituting the lower electrode.

  As described above, the ferroelectric film formation method mainly includes the MOCVD method, the sol-gel method, and the sputtering method. From the viewpoint of cost, the ferroelectric film is formed by using the sol-gel method or the sputtering method. It is preferable. In addition, when a ferroelectric film is formed by MOCVD, irregularities are likely to occur on the surface, and a sufficient amount of switching charge may not be obtained.

  Various proposals have been made regarding the structure of the lower electrode suitable for the sol-gel method or the sputtering method. However, so far, it is difficult to say that the ferroelectric film can be sufficiently aligned in any structure. For example, when a ferroelectric film is formed by a sol-gel method or a sputtering method on a conventional lower electrode having an Ir film on the outermost surface, variations in the orientation of the ferroelectric film become large. Further, in the conventional lower electrode in which the Pt film is positioned on the outermost surface of the lower electrode, the variation in the orientation of the Pt film is large, and the variation in the orientation of the ferroelectric film formed thereon is also large.

JP-A-9-22829 JP 2003-92391 A US Pat. No. 6,613,808 US Pat. No. 6,933,156 JP 2004-153006 A JP 2003-318371 A JP 2003-209179 A JP 2000-357777 A US 20002/0074581 Publication JP 2001-91539 A JP 2001-111007 A JP 2005-159165 A JP 2004-95638 A JP 2000-164818 A JP 2003-298136 A JP-A-11-145418 Japanese Patent No. 3654352 Japanese Patent No. 3412051 Japanese Patent No. 3738229 Japanese Patent No. 3641142

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can further align the orientation even when a capacitive insulating film such as a ferroelectric film is formed by a sol-gel method or a sputtering method. is there.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

  In one embodiment of the method for manufacturing a semiconductor device, a lower electrode film is formed above a substrate, and then a capacitive insulating film is formed on the lower electrode film. Next, an upper electrode film is formed on the capacitor insulating film. When forming the lower electrode film, an amorphous or microcrystalline metal oxide film is formed, and then a first noble metal film is formed on the metal oxide film at a first temperature. Then, a second noble metal film is formed on the first noble metal film at a second temperature higher than the first temperature.

  One embodiment of a semiconductor device includes a lower electrode formed above a substrate, a capacitive insulating film formed on the lower electrode, and an upper electrode formed on the capacitive insulating film. . The lower electrode includes a metal oxide film, a first noble metal film formed on the metal oxide film, and a crystal grain formed on the first noble metal film than the first noble metal film. And a second noble metal film having a large thickness.

  According to the present invention, since two appropriate noble metal films are formed on the metal oxide film in the lower electrode, the orientation of the surface of the lower electrode can be aligned in a desired direction. For this reason, the orientation of the capacitive insulating film formed thereon can also be made appropriate.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of each memory cell of the ferroelectric memory will be described together with its manufacturing method.

(First embodiment)
First, a first embodiment of the present invention will be described. 1A to 1S are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps.

  In the first embodiment, first, as shown in FIG. 1A, an STI (Shallow Trench Isolation) groove for defining an active region of a transistor is formed on the surface of an n-type or p-type semiconductor substrate 31. An element isolation insulating film 32 is formed by embedding an insulating film such as silicon oxide therein. Note that an element isolation insulating film may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, ap well 33 is formed by introducing a p-type impurity into the active region. Next, the gate insulating film 34 is formed by thermally oxidizing the surface of the active region. Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the semiconductor substrate 31, and this is patterned by a photolithography technique to form the gate electrode 35. At this time, the two gate electrodes 35 are arranged in parallel with each other on the p-well 33. These gate electrodes 35 function as part of the word line of the memory.

  Next, the extension layer 36 is formed on both sides of the gate electrode 35 by introducing n-type impurities (ion implantation) using the gate electrode 35 as a mask. Thereafter, an insulating film is formed on the entire upper surface of the semiconductor substrate 31 and etched back to form an insulating sidewall 38 beside the gate electrode 35. As the insulating film, for example, a silicon oxide film is formed by a CVD method.

  Subsequently, impurity diffusion layers 37 are formed on both sides of the gate electrode 35 by introducing n-type impurities (ion implantation) using the sidewall 38 and the gate electrode 35 as a mask. The two sets of extension layer 36 and impurity diffusion layer 37 constitute the source and drain of the MOS transistor.

  Next, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the semiconductor substrate 31 by sputtering, and this refractory metal layer is heated to react with silicon. As a result, a refractory metal silicide layer 39 is formed on the gate electrode 35, and a refractory metal silicide layer 40 is formed on the impurity diffusion layer 37. Then, the unreacted refractory metal layer on the element isolation insulating film 32 and the like is removed by wet etching.

  Next, for example, a silicon oxynitride film 41 having a thickness of about 200 nm is formed on the entire upper surface of the semiconductor substrate 31 by plasma CVD. Next, a silicon oxide film 42 having a thickness of about 1000 nm is formed on the silicon oxynitride film 41 by, for example, a plasma CVD method using TEOS gas as a source gas. Thereafter, the upper surface of the silicon oxide film 42 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. In this planarization, the thickness of the silicon oxide film 42 is set to about 700 nm from the upper surface of the semiconductor substrate 31.

  Next, a contact hole exposing the silicide layer 40 is formed by patterning the silicon oxide film 42 and the silicon oxynitride film 41 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film (adhesion film) 43 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 44 is formed in the contact hole and on the silicon oxide film 42. The thickness of the W film 44 is about 300 nm from the upper surface of the silicon oxide film 42. Subsequently, by performing CMP, the glue film 43 and the W film 44 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 43 and the W film 44 on the silicon oxide film 42 are completely removed.

  Next, for example, a silicon oxynitride film 45 having a thickness of about 130 nm is formed as an antioxidant film on the silicon oxide film 42 and the contact plug by plasma CVD. Further, a silicon oxide film 46 having a thickness of about 300 nm is formed on the silicon oxynitride film 45 by, for example, a plasma CVD method using TEOS gas as a source gas. A silicon nitride film or an aluminum oxide film may be formed as the antioxidant film instead of the silicon oxynitride film 45.

  Next, as shown in FIG. 1B, a contact hole exposing the silicide layer 40 is formed by patterning the silicon oxide film 46 and the silicon oxynitride film 45 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film 47 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and side portions of the contact hole. Thereafter, a tungsten film (W film) 48 is formed in the contact hole and on the silicon oxide film 46. The thickness of the W film 48 is about 300 nm from the upper surface of the silicon oxide film 46. Subsequently, by performing CMP, the glue film 47 and the W film 48 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 47 and the W film 48 on the silicon oxide film 46 are completely removed by overpolishing. As the slurry, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 46 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 46. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the semiconductor substrate 31 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the semiconductor substrate 31 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the semiconductor substrate 31 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

Next, a Ti film having a thickness of about 20 nm is formed on the silicon oxide film 46 and the contact plug. In the formation of the Ti film, for example, a sputtering apparatus in which a target is provided at a position separated from the semiconductor substrate 31 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 5 seconds in a state where the set temperature of the semiconductor substrate 31 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. In the present embodiment, since the NH ₃ plasma treatment is performed on the surface of the silicon oxide film 46 before the Ti film is formed, the Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film 46 is captured. The surface of the can be moved freely. As a result, the Ti film is self-organized and its surface is strongly oriented in the (002) plane. Thereafter, by performing RTA (Rapid Thermal Annealing) at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film is changed to a TiN film 51 whose surface is strongly oriented to the (111) plane as shown in FIG. 1C. . Note that a TaN film or the like may be formed instead of the TiN film 51 as the crystallinity-improving conductive adhesion film.

Subsequently, a TiAlN film 52 having a thickness of about 100 nm is formed on the TiN film 51 as an oxygen diffusion barrier film, for example, by reactive sputtering. At this time, for example, a target obtained by alloying Ti and Al is used. The set temperature of the semiconductor substrate 31 is 400 ° C., the pressure in the chamber is 253.3 Pa, Ar is supplied at a flow rate of 40 sccm, and N ₂ is supplied at a flow rate of 10 sccm. The sputter power is, for example, 1.0 kW. Instead of the TiAlN film 52, a conductive oxygen barrier film such as a TiAlON film, a TaAlN film, a TaAlON film, an Ir film, or a Ru film may be formed.

  Next, an Ir film 53 having a thickness of 50 nm to 100 nm (eg, 50 nm) is formed on the TiAlN film 52 by, eg, sputtering. At this time, the set temperature of the semiconductor substrate 31 is 425 ° C., the pressure in the chamber is 0.2 Pa, and the atmosphere in the chamber is an Ar atmosphere. The sputter power is, for example, 0.3 kW. The Ir film 53 is oriented in the (111) plane in order to take over the orientation of the TiN film 51. Further, instead of the Ir film 53, a film of a metal belonging to the platinum group (Ru, Rh, Pd or the like) may be formed. In order to suppress stress generated in the Ir film 53 itself, the set temperature of the semiconductor substrate 31 is preferably set to 400 ° C. to 450 ° C.

Thereafter, as shown in FIG. 1D, an Ir oxide film 54 (metal oxide film) having a thickness of 5 to 50 nm (for example, 30 nm) is formed on the Ir film 53 by, eg, sputtering. As the Ir oxide film 54, an amorphous film is formed, or a film made of fine equiaxed crystals (microcrystals) is formed. In forming such an Ir oxide film 54, for example, the set temperature of the semiconductor substrate 31 is set to 100 ° C. or lower (eg, 50 ° C. to 60 ° C.), Ar is supplied into the chamber at a flow rate of 100 sccm, and O ₂ is supplied. Supply at a flow rate of 100 sccm. Note that the degree of oxidation of the Ir oxide film 54 is preferably high. This is because if further oxidation of the Ir oxide film 54 proceeds in the subsequent processing, peeling may occur at the top and bottom. In place of the Ir oxide film 54, a Pt oxide film, Ru oxide film, Pd oxide film, Os oxide film, Re oxide film, Rh oxide film, SrRuO ₃ , La _2-x Sr _x CuO ₄ or YBa ₂ Cu ₃ A conductive metal oxide film such as O ₇ may be formed.

  Subsequently, as shown in FIG. 1E, a Pt film 91 (first noble metal film) having a thickness of 5 nm to 20 nm is formed on the Ir oxide film 54 by, eg, sputtering. At this time, the set temperature of the semiconductor substrate 31 is 100 ° C., the pressure in the chamber is 0.2 Pa, and the atmosphere in the chamber is an Ar atmosphere. The sputter power is, for example, 0.3 kW. At this time, since the Ir oxide film 54 is not oriented in any direction, the Pt film 91 is self-oriented and the mirror index of the surface becomes (111). Therefore, the temperature of the semiconductor substrate 31 when forming the Pt film 91 is set lower than the temperature at which the Ir oxide film 54 is crystallized (for example, 100 ° C. or less). Even when another metal oxide film is formed, it is preferable to set the temperature to 200 ° C. or lower in consideration of the roughness of the surface. On the other hand, when the temperature of the semiconductor substrate 31 is less than 20 ° C., film formation may be difficult. Instead of the Pt film 91, a Pd film may be formed, or a noble metal alloy film containing Pt or Pd may be formed.

Next, the crystallinity of the Pt film 91 is improved by performing RTA at 650 ° C. to 750 ° C. for 60 seconds in an atmosphere of an inert gas such as Ar gas or N ₂ gas. That is, the crystal orientation in the Pt film 91 is made more uniform. Further, the adhesion between the TiN film 51, the TiAlN film 52, the Ir film 53, the Ir oxide film 54, and the Pt film 91 is improved by this RTA.

  Thereafter, as shown in FIG. 1E, a Pt film 92 (second noble metal film) having a thickness of 20 nm or more is formed on the Pt film 91 by sputtering, for example. At this time, the set temperature of the semiconductor substrate 31 is set to 200 ° C. to 500 ° C. (for example, 350 ° C.), and Ar is supplied into the chamber at a flow rate of 199 sccm. The sputter power is, for example, 0.3 kW. At this time, since the Pt film 92 takes over the orientation of the Pt film 91, the mirror index of the surface of the Pt film 92 is also (111). The crystal structures of the Pt film 91 and the Pt film 92 can be confirmed using, for example, a cross-sectional TEM. Note that the temperature of the semiconductor substrate 31 when the Pt film 92 is formed is higher than the temperature when the Pt film 91 is formed. This is because the higher the temperature, the larger the crystal grains and the better the orientation. Accordingly, the crystal grains constituting the Pt film 92 are larger than the crystal grains constituting the Pt film. On the other hand, if the temperature of the semiconductor substrate 31 when forming the Pt film 92 is higher than 500 ° C., the tensile stress in the Pt film 92 may become too strong. Accordingly, the temperature of the semiconductor substrate 31 when forming the Pt film 92 is preferably 200 ° C. or higher, and more preferably 500 ° C. or lower. In order to ensure good orientation, the average crystal grain size in the Pt film 92 is preferably 20 nm or more, and the thickness of the Pt film 92 is preferably 20 nm or more. The average crystal grain size in the Pt film 92 is preferably at least twice the average crystal grain size in the Pt film 91. On the other hand, if the thickness of the Pt film 92 exceeds 50 nm, the subsequent processing may take a long time. Therefore, the thickness of the Pt film 92 is, for example, 20 nm to 50 nm. Instead of the Pt film 92, a Pd film may be formed, or a noble metal alloy film containing Pt or Pd may be formed. However, the first noble metal film and the second noble metal film are preferably composed of the same element. This is because crystal lattice mismatch is unlikely to occur.

  Subsequently, the crystallinity of the Pt film 92 is improved by performing RTA at 650 ° C. or more for 60 seconds in an atmosphere of an inert gas such as Ar gas. That is, the orientation of crystals in the Pt film 92 is made more uniform. Further, the RTA further improves the adhesion between the TiN film 51, the TiAlN film 52, the Ir film 53, the Ir oxide film 54, the Pt film 91, and the Pt film 92. The TiN film 51, TiAlN film 52, Ir film 53, Ir oxide film 54, Pt film 91 and Pt film 92 constitute a lower electrode film.

Next, as shown in FIG. 1F, a capacitive insulating film 55 having a thickness of 50 nm to 140 nm (100 nm) is formed on the Pt film 92 by, for example, sputtering. As the capacitor insulating film 55, for example, a ferroelectric film is formed. The material of the ferroelectric film is not particularly limited. For example, an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and at least one selected from rare earth elements, B = Ti , Zr, Nb, Ta, W, Mn, Fe, Co, and Cr) ferroelectric material. More specifically, for example, PZT doped with La, Ca, Sr, and / or Si, PLZT, BLT, SBT, and Bi layered structure (for example, (Bi _1-x R _x ) Ti ₃ O ₁₂ ( R is a rare earth element: 0 <x <1), SrBi ₂ Ta ₂ O ₉ , SrBi ₄ Ti ₄ O ₁₅ ). The crystal structure of these materials corresponds to an ABO ₃ type perovskite structure as a unit. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they do not have to be the same in each unit. The same applies to the B atom. When La, Ca, Sr, Nb, or the like is added, compared to the case where it is not added, the fatigue resistance of the capacitor is improved, the imprint characteristics are improved, the leakage current is reduced, Low voltage operation is possible. However, if the amount of the additive element is too large, the amount of switching charge may decrease. For this reason, it is preferable that the addition amount of each element shall be 0.1 mol%-5 mol%. For example, PZT added with 5 mol% of Ca, 2 mol% of La, and 2 mol% of Sr is used. In place of the ferroelectric material, a high dielectric material such as oxide Zr or Pb-based material may be used.

Thereafter, RTA is performed in an atmosphere containing oxygen (mixed atmosphere of an inert gas and an oxygen gas), so that the entire capacitor insulating film 55 is formed into columnar crystals. Since the columnar crystals constituting the capacitive insulating film 55 take over the orientation of the Pt film 92, the mirror index of the surface thereof also becomes (111). In this RTA, the semiconductor substrate 31 is raised to 550 ° C. to 800 ° C. (for example, 580 ° C.). Further, for example, the flow rate of Ar gas is 2000 sccm, the flow rate of O ₂ gas is 15 sccm to 50 sccm, and the time is 60 seconds to 120 seconds (for example, 90 seconds). The temperature of RTA is preferably adjusted depending on the material. For example, when PZT or PZT containing an additive element is used, the temperature is preferably 600 ° C. or lower. When BLT is used, the temperature is preferably 700 ° C. or lower. When SBT is used, 800 ° C. The following is preferable.

Subsequently, as shown in FIG. 1G, an Ir oxide film 56 that is crystallized at the time of film formation having a thickness of 50 nm is formed on the capacitor insulating film 55 by, eg, sputtering. At this time, the set temperature of the semiconductor substrate 31 is set to 300 ° C., Ar gas is supplied into the chamber at a flow rate of 140 sccm, and O ₂ gas is supplied at a flow rate of 60 sccm. Further, the sputter power is, for example, about 1 kW to 2 kW. Instead of the Ir oxide film 56, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

Next, R2 is performed at 725 ° C. for 60 seconds while O ₂ is supplied into the chamber at a flow rate of 20 sccm and Ar is supplied at a flow rate of 2000 sccm, whereby the entire capacitor insulating film 55 is converted into columnar crystals. . In addition, the plasma damage of the Ir oxide film 56 is recovered by this RTA, and oxygen vacancies in the capacitor insulating film 55 are compensated.

Thereafter, an Ir oxide film 57 having a thickness of 100 nm to 300 nm is formed on the Ir oxide film 56 by, eg, sputtering. When the atmosphere in the chamber is an Ar atmosphere, the pressure in the chamber is 0.8 Pa, and the sputtering power is 1.0 kW, the Ir oxide film 57 has a thickness of about 200 nm in about 79 seconds. The composition of the Ir oxide film 57 is preferably closer to the stoichiometric composition of IrO ₂ than the composition of the Ir oxide film 56. This is because such a composition suppresses the catalytic action against hydrogen, suppresses the problem that the capacitive insulating film 55 is reduced by hydrogen radicals, and improves the hydrogen resistance of the ferroelectric capacitor. . The temperature of the semiconductor substrate 31 when forming the Ir oxide film 57 is preferably 100 ° C. or lower. This is to suppress abnormal growth of the Ir oxide film 57. Further, instead of the Ir oxide film 57, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

  Next, as shown in FIG. 1H, an Ir film 58 having a thickness of 20 nm to 100 nm is formed on the Ir oxide film 57 by sputtering, for example, for the purpose of suppressing hydrogen diffusion and process deterioration. At this time, the atmosphere in the chamber is an Ar atmosphere, the pressure in the chamber is 1 Pa, and the sputtering power is 1.0 kW. In place of the Ir film 58, a noble metal film such as a Pt film, Ru film, Rh film, or Pd film may be formed. Further, an Ir oxide film or Ru oxide film having a low degree of oxidation may be formed. The upper electrode film is composed of the Ir oxide film 56, the Ir oxide film 57 and the Ir film 58.

  Thereafter, backside cleaning is performed in order to remove the material of the PZT film attached to the backside of the semiconductor substrate 31. Subsequently, as shown in FIG. 1I, a titanium nitride film (TiN film) 61 and a silicon oxide film 62 are sequentially formed on the Ir film 58. The TiN film 61 is formed by sputtering, for example. The silicon oxide film 62 is formed by, for example, a CVD method using TEOS gas. Instead of the TiN film 61, a TiAlN film may be formed.

  Next, as shown in FIG. 1J, the silicon oxide film 62 is patterned into an island shape.

  Next, as shown in FIG. 1K, the TiN film 61 is etched using the silicon oxide film 62 as a mask. As a result, a hard mask composed of the island-like TiN film 61 and the silicon oxide film 62 is formed.

Next, using the TiN film 61 and the silicon oxide film 62 as a mask, plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas is performed using an Ir film 58, an Ir oxide film 57, The process is performed on the Ir oxide film 56, the capacitor insulating film 55, the Pt film 92, the Pt film 91, the Ir oxide film 54, and the Ir film 53. As a result, the upper electrode 63 is formed.

  Subsequently, as shown in FIG. 1L, the silicon oxide film 62 is removed by dry etching or wet etching.

  Next, as shown in FIG. 1M, the TiAlN film 52 and the TiN film 51 are patterned by performing dry etching using the Ir film 58 or the like as a mask. In the present embodiment, the lower electrode 60 is composed of the Pt film 92, the Pt film 91, the Ir oxide film 54, the Ir film 53, the TiAlN film 52, and the TiN film 51. Note that the TiAlN film 52 and the TiN film 51 can be regarded as barrier metal films.

  Next, as shown in FIG. 1N, a protective film 65 covering the ferroelectric capacitor is formed on the silicon oxide film 46. As the protective film 65, an aluminum oxide film having a thickness of about 20 nm is formed by sputtering, for example. As the protective film 65, an aluminum oxide film having a thickness of 2 nm to 5 nm may be formed by MOCVD.

  Thereafter, as shown in FIG. 1O, recovery annealing is performed in an oxygen-containing atmosphere in order to recover the damage of the ferroelectric film. The conditions for this recovery annealing are not particularly limited. For example, the set temperature of the semiconductor substrate 31 is set to 550 ° C. to 700 ° C. In particular, when the capacitive insulating film 55 as in this embodiment is formed, recovery annealing is performed in an oxygen atmosphere at 650 ° C. for 60 minutes.

  Thereafter, as shown in FIG. 1P, a new protective film 66 is formed on the protective film 65. As the protective film 66, an aluminum oxide film having a thickness of about 20 nm is formed by, for example, a CVD method.

  Next, as shown in FIG. 1Q, a silicon oxide film 67 having a thickness of about 1500 nm is formed as an interlayer insulating film on the protective film 66 by, for example, plasma TEOSCVD. At this time, for example, a mixed gas composed of TEOS gas, oxygen gas, and helium gas is used as the source gas. Thereafter, the surface of the silicon oxide film 67 is planarized by, eg, CMP. Note that as the interlayer insulating film, for example, an insulating inorganic film or the like may be formed.

Subsequently, heat treatment is performed in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result, moisture in the silicon oxide film 67 is removed, and the film quality of the silicon oxide film 67 changes, so that it is difficult for moisture to enter the silicon oxide film 67.

  Thereafter, a protective film (barrier film) 68 is formed on the silicon oxide film 67 by, for example, sputtering or CVD. As the protective film 68, for example, an aluminum oxide film having a thickness of 20 nm to 100 nm is formed. Since the protective film 68 is formed on the planarized silicon oxide film 67, the protective film 68 also becomes flat.

  Next, a silicon oxide film 69 having a thickness of 300 nm to 500 nm is formed as an interlayer insulating film on the protective film 68 by, for example, plasma TEOSCVD. Thereafter, the surface of the silicon oxide film 69 is planarized by, eg, CMP. Note that a silicon oxynitride film, a silicon nitride film, or the like may be formed as the interlayer insulating film.

  Next, as shown in FIG. 1R, the silicon oxide film 69, the protective film 68, and the silicon oxide film 67 are patterned by photolithography to form a contact hole that exposes the upper electrode 63. Thereafter, heat treatment is performed in an oxygen atmosphere at 550 ° C. to recover oxygen vacancies generated in the capacitor insulating film 55 when the contact holes are formed. Subsequently, a filling material is formed in the contact hole, and a silicon oxide film 69, a protective film 68, a silicon oxide film 67, a protective film 66, a protective film 65, a silicon oxide film 46, and silicon oxynitride are formed by photolithography. By patterning the film 45, a contact hole exposing the contact plug made of the glue film 43 and the W film 44 is formed.

  Next, the embedding material is removed, and a glue film (adhesion film) 70 is formed by sequentially forming a Ti film and a TiN film on the bottom and sides of each contact hole. At this time, for example, a Ti film is formed by sputtering, and a TiN film is formed thereon by MOCVD. However, when the TiN film is formed by the MOCVD method, a treatment in a plasma of a mixed gas of nitrogen and hydrogen is required to remove carbon from the TiN film. In the present embodiment, since the outermost surface of the upper electrode 63 is the Ir film 58, the upper electrode 63 is not reduced even if this plasma treatment is performed. Further, only the TiN film may be formed as the glue film 70.

  Thereafter, a tungsten film (W film) 71 is formed in the contact hole and on the silicon oxide film 69. The thickness of the W film 71 is about 300 nm from the upper surface of the silicon oxide film 69. Subsequently, by performing CMP, the glue film 70 and the W film 71 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 70 and the W film 71 on the silicon oxide film 69 are completely removed by overpolishing.

  Subsequently, as shown in FIG. 1S, a wiring composed of a Ti film 72, a TiN film 73, an AlCu film 74, a TiN film 75, and a Ti film 76 is formed on the silicon oxide film 69 and the contact plug. In forming the wiring, for example, by sputtering, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are used. Films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

  According to the first embodiment, since the Pt film 91 is formed on the amorphous or microcrystalline Ir oxide film 54, the Pt film 91 is self-aligned, and the orientation is easily aligned with (111). . For this reason, the orientation of the Pt film 92 formed thereon is also easily aligned to (111). Further, since the Pt film 92 is formed at a relatively high temperature, the crystal grains become large, and a better orientation than that of the Pt film 91 can be obtained. Therefore, the orientation of the capacitor insulating film 55 can be made extremely good.

  When the Pt film 91 is directly formed on the TiAlN film 52, peeling may occur due to diffusion of elements contained in the capacitor insulating film 55 such as Pb during the heat treatment after the capacitor insulating film 55 is formed. On the other hand, in this embodiment, since the Ir film 53 exists on the TiAlN film 52, such peeling does not easily occur.

  In addition, when the Pt film 91 is directly formed on the Ir film 53, the orientation of the Pt film 91 is affected by the orientation of the Ir film 53, so that preferable crystallinity cannot be obtained. Further, peeling may occur between the Pt film 91 and the Ir film 53 during the heat treatment after the capacitor insulating film 55 is formed. On the other hand, in this embodiment, since the Ir oxide film 54 exists on the Ir film 53, such crystallinity deterioration and peeling are unlikely to occur.

  Note that the Ir oxide film 54 may finally be crystallized. Even in such a case, leakage current is suppressed, and good orientation can be obtained in the capacitor insulating film 55. When the processing as described above is performed, the surface of the crystallized Ir oxide film 54 is easily oriented to (110) and (200). In addition, the crystal is finer than the Ir oxide film crystallized at the time of film formation.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment, a small amount of Ir in the Ir oxide film 54 or Ir film 53 may diffuse to the capacitive insulating film 55. Therefore, in the second embodiment, after the Ir oxide film 54 is formed, a Pt oxide film (diffusion suppression film) having a thickness of about 30 nm is formed, and the Pt film 91 is formed on the Pt oxide film. By thus interposing the Pt oxide film between the Ir oxide film 54 and the capacitive insulating film 55, the diffusion of Ir can be prevented more reliably. As a result, it is possible to suppress a leakage current accompanying the diffusion of Ir. This Pt oxide film is formed by sputtering, for example. At this time, the set temperature of the semiconductor substrate 31 is 350 ° C., Ar gas is supplied into the chamber at a flow rate of 40 sccm, and O ₂ gas is supplied at a flow rate of 160 sccm. That is, the oxygen concentration is 80%. The pressure in the chamber is 0.3 Pa and the sputter power is 1 kW.

  Note that when a Pt oxide film is formed so as to be in contact with the Ir oxide film 54, there is a possibility that peeling occurs between these during the heat treatment for crystallization of the capacitor insulating film 55. Therefore, in the second embodiment, after forming the Ir oxide film 54, a Pt film (third noble metal film) having a thickness of about 10 nm is formed on the Ir oxide film 54, and the above-described Pt film is formed on the Pt film. The Pt oxide film is formed. That is, as compared with the first embodiment, a Pt film and a Pt oxide film are present in order from the bottom between the Ir oxide film 54 and the Pt film 91. This Pt film is formed by sputtering, for example. At this time, the set temperature of the semiconductor substrate 31 is 350 ° C., Ar gas is supplied into the chamber at a flow rate of 199 sccm, and the sputter power is 0.3 kW.

  Note that the lower the temperature of the semiconductor substrate 31 when forming the Pt oxide film, the higher the insulating property. When the temperature is lower than 150 ° C., it becomes difficult to obtain high conductivity even by subsequent annealing or the like. Therefore, the temperature of the semiconductor substrate 31 when forming the Pt oxide film is preferably 150 ° C. or higher. On the other hand, when this temperature is higher than 400 ° C., oxygen is dissociated and a Pt film is formed. Therefore, the temperature of the semiconductor substrate 31 when forming the Pt oxide film is preferably 400 ° C. or lower.

  Further, when the thickness of the Pt oxide film is less than 20 nm, the entire Pt oxide film is reduced to a Pt film during the subsequent heat treatment or the like, and there is a possibility that the diffusion of Ir cannot be sufficiently suppressed. is there. For this reason, the thickness of the Pt oxide film is preferably 20 nm or more. On the other hand, if the thickness of the Pt oxide film exceeds 50 nm, the electrical resistance of the entire lower electrode 60 may increase. For this reason, the thickness of the Pt oxide film is preferably 50 nm or less.

  According to the second embodiment as described above, the leakage current can be reduced by one digit or more as compared with the first embodiment. Even when a part of the Pt oxide film is reduced by the heat treatment, the property of suppressing the diffusion of the element is hardly affected.

  A Pt alloy oxide film may be used instead of the Pt oxide film, and a Pt alloy film may be used instead of the Pt film.

  Here, the outline of the structure of the lower electrode of the ferroelectric capacitor in the first and second embodiments is shown in FIGS. 2A and 2B, respectively. In contrast to the first and second embodiments, the TiN film 51 may be omitted as shown in FIGS. 3A and 3B. Furthermore, as shown in FIGS. 4A and 4B, the TiAlN film 52 may be omitted.

(Third embodiment)
Next, a third embodiment of the present invention will be described. 5A to 5C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention in the order of steps.

In the third embodiment, first, similarly to the first embodiment, the process up to the NH ₃ plasma process is performed on the surface of the silicon oxide film 46. However, in forming a contact plug composed of the glue film 47 and the W film 48, a recess 80 may be formed on the surface of the contact plug as shown in FIG. 5A. The depth of the recess 80 is, for example, about 20 nm to 50 nm.

When processing similar to that of the first embodiment is performed with such a recess 80 present, a recess reflecting the recess 80 is formed on the surface of the TiN film 51 and the like, and the orientation of the capacitive insulating film 55 is lowered. Sometimes. Therefore, in the third embodiment, as shown in FIG. 5B, a Ti film 81 having a thickness of about 100 nm is formed on the silicon oxide film 46 and the contact plug. In forming the Ti film 81, for example, a sputtering apparatus in which a target is provided at a position separated from the semiconductor substrate 31 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 35 seconds in a state where the set temperature of the semiconductor substrate 31 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. Also in this embodiment, since the NH ₃ plasma treatment is performed on the surface of the silicon oxide film 46 before the Ti film 81 is formed, the Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film The surface of 46 can be moved freely. As a result, the Ti film 81 is self-organized and its surface is strongly oriented in the (002) plane.

  Thereafter, the surface of the Ti film 81 is planarized by, eg, CMP. The thickness of the planarized Ti film 81 is, for example, 50 nm to 100 nm from the surface of the silicon oxide film 46. This thickness control is performed by time control, for example.

Subsequently, the surface of the Ti film 81 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 81 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 81. Next, as in the first embodiment, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 5C, the Ti film has a TiN whose surface is strongly oriented in the (111) plane. The film 51 is used.

  Thereafter, similarly to the first or second embodiment, the processes after the formation of the TiAlN film 52 are performed.

  According to the third embodiment, a ferroelectric capacitor having good characteristics can be obtained even when the recess 80 is formed.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. 6A and 6B are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the fourth embodiment of the present invention in the order of steps.

  In the fourth embodiment, first, similarly to the third embodiment, processing up to the formation of the Ti film 81 is performed. Thereafter, as shown in FIG. 6A, the surface of the Ti film 81 is flattened by, for example, a CMP method until the surface of the silicon oxide film 46 is exposed. That is, unlike the third embodiment, the Ti film 81 on the silicon oxide film 46 is completely removed.

Subsequently, similarly to the third embodiment, the surface of the Ti film 81 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 81 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 81. Next, as in the first embodiment, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 6B, the Ti film is TiN whose surface is strongly oriented to the (111) plane. The film 51 is used.

  Thereafter, similarly to the first or second embodiment, the processes after the formation of the TiAlN film 52 are performed.

  According to the fourth embodiment, the same effect as that of the third embodiment can be obtained.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. 7A to 7C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the fifth embodiment of the present invention in the order of steps.

  In the fifth embodiment, first, as shown in FIG. 7A, similarly to the first embodiment, the processes up to the formation of the contact plug composed of the glue film 43 and the W film 44 are performed. However, the contact plug composed of the glue film 43 and the W film 44 is not formed on the silicide layer 40 shared by the two MOS transistors.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 42 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 42. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the semiconductor substrate 31 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the semiconductor substrate 31 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the semiconductor substrate 31 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

  Next, as shown in FIG. 7B, a TiN film 51 is formed on the silicon oxide film 42 and the contact plug. The method for forming the TiN film 51 is the same as in the first embodiment. Thereafter, similarly to the first or second embodiment, the processes from the formation of the TiAlN film 52 to the formation of the protective film 66 are performed.

  Thereafter, as shown in FIG. 7C, the silicon oxide film 67 is formed and planarized in the same manner as in the first embodiment. Next, contact holes reaching the silicide layer 40 shared by the two MOS transistors are formed in the silicon oxide film 67, the protective film 66, the protective film 65, the silicon oxide film 42, and the silicon oxynitride film 41. Then, a contact plug composed of the glue film 70 and the W film 71 is formed in the contact hole. Further, a hole exposing the upper electrode 63 is formed in a state where the contact plug is covered with an antioxidant film (not shown) or the like.

  Subsequently, wirings and pads made of a Ti film 72, a TiN film 73, an AlCu film 74, a TiN film 75, and a Ti film 76 are formed on the silicon oxide film 67, on the contact plug, and in the hole. In forming the wiring and pads, for example, a sputtering method is used to form a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a thickness of 70 nm. TiN films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

  According to the fifth embodiment, the ferroelectric capacitor can be completed with fewer steps than the first embodiment.

  In any of the embodiments, the capacitive insulating film 55 may be formed by a sol-gel method. Further, if the lowermost portion of the capacitor insulating film 55 is formed by a sputtering method or a sol-gel method, the MOCVD method may be combined. The structure of the capacitive insulating film 55 may be a multilayer structure. For example, a ferroelectric film having a thickness of 90 nm may be formed by sputtering, crystallization annealing may be performed, and an amorphous ferroelectric film having a thickness of 10 nm to 30 nm may be further formed. Alternatively, a ferroelectric film having a thickness of 20 nm to 30 nm may be formed by sputtering and crystallization annealing may be performed, and a crystallized ferroelectric film having a thickness of 40 nm to 80 nm may be formed by MOCVD. . Further, an amorphous ferroelectric film having a thickness of 10 nm to 30 nm may be formed thereon.

  Further, the capacitor structure may be a planar type instead of a stack type. In this case, an insulating metal oxide film such as an Al oxide film, a Ti oxide film, a Ta oxide film, or a Zn oxide film may be used instead of the conductive metal oxide film such as the Ir oxide film 54.

Next, the results of experiments actually performed by the present inventors will be described. In this experiment, a plurality of samples (Examples) with different concentrations of O ₂ gas in the atmosphere when forming the Ir oxide film 54 were manufactured according to the first embodiment. Note that the thickness of the Pt film 91 was 20 nm, and the thickness of the Pt film 92 was 30 nm. Further, the temperature of the semiconductor substrate 31 when forming the Pt film 91 was 100 ° C., and the temperature of the semiconductor substrate 31 when forming the Pt film 92 was 350 ° C. In addition, as a comparative example, a sample in which the Pt film 91 and the Pt film 92 were not formed, but instead a Pt film having a thickness of 50 nm with a temperature of the semiconductor substrate of 100 ° C. was produced.

In the embodiment, after the Pt film 92 is formed, the crystal structure is analyzed by an X-ray diffraction method. In the comparative example, the Pt film 91 and the Pt film instead of the Pt film 92 are formed, and then the crystal structure is converted into an X-ray. Analyzed by diffraction method. This analysis was performed at three locations, a central portion, an upper end portion, and a right end portion when the orientation flat of the semiconductor substrate 31 was positioned at the lower end. The results are shown in FIGS. 8A and 8B. FIG. 8A shows the integrated intensity of the orientation to the (111) plane, and FIG. 8B shows the half width of the peak indicating the orientation to the (111) plane. The ratio of O _{2 is} the ratio of the flow rate of O ₂ gas supplied into the chamber to the sum of the flow rate of O ₂ gas and the flow rate of Ar gas.

As shown in FIG. 8A, the integrated intensity higher than that of the comparative example was obtained in the example regardless of the value of the O ₂ ratio. Further, as shown in FIG. 8B, a half value width lower than that of the comparative example was obtained in the example regardless of the value of the O ₂ ratio. These results indicate that the orientation in the example is better than that of the comparative example.

  Further, for each sample of the above-described examples and comparative examples, a PZT film (CSPLZT) in which Ca, Sr and La are added on the Pt film 92 or on the Pt film instead of the Pt film 91 and the Pt film 92. Film) was formed by sputtering, and crystallization annealing was performed. Then, the crystal structure of the CSPLZT film in each sample was analyzed by an X-ray diffraction method. The results are shown in FIGS. 9A to 9E. 9A shows the integrated intensity of orientation to the (100) plane, FIG. 9B shows the integrated intensity of orientation to the (101) plane, and FIG. 9C shows the integrated intensity of orientation to the (111) plane. ing. 9D shows the orientation ratio of the (222) plane, and FIG. 9E shows the half width of the peak indicating the orientation to the (111) plane.

As shown in FIGS. 9A to 9E, the orientation in (100) and (101) is lower in the example than in the comparative example in any example of the ratio of O ₂ . The orientation was strong. In particular, as shown in FIG. 9E, the full width at half maximum of the example is about 0.2 ° lower, and the CSPLZT film is well oriented.

  In the techniques described in Patent Documents 2 to 5, a Pt oxide film exists between two Pt films constituting the lower electrode. That is, there is only one Pt film on the Pt oxide film. The Pt film is formed at 100 ° C. For this reason, the size of the crystal grains is relatively small, and the orientation of the capacitive insulating film cannot be as uniform as in the present invention. If the Pt film on the Pt oxide film is formed to a sufficient thickness at a high temperature, the Pt oxide film is crystallized during the formation, so that the orientation of the Pt film is difficult to align. For this reason, it is difficult to align the orientation of the capacitive insulating film thereon.

  Patent Document 16 describes that two Pt films are stacked. However, since the lower Pt film is formed on the TiN film, its orientation is difficult to align. Further, in the technique of Patent Document 16, there is a description that the upper Pt film is made as independent as possible from the lower Pt film, and the orientation of the upper Pt film becomes more disturbed. Therefore, it is difficult to align the capacitance insulating film.

It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 1st Embodiment of this invention. FIG. 1B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1A. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1B. FIG. 2C is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1C. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1D. FIG. 2E is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1E. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1F. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1G. 1H is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1H. FIG. 11 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1I; FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1J. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1K. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1L. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1M. 1N is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1N; FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 10. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1P. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1Q. FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1R; It is a figure which shows the outline | summary of the lower electrode in the 1st Embodiment of this invention. It is a figure which shows the outline | summary of the lower electrode in the 2nd Embodiment of this invention. It is a figure which shows the outline | summary of the lower electrode in the modification of the 1st Embodiment of this invention. It is a figure which shows the outline | summary of the lower electrode in the modification of the 2nd Embodiment of this invention. It is a figure which shows the outline | summary of the lower electrode in the other modification of the 1st Embodiment of this invention. It is a figure which shows the outline | summary of the lower electrode in the other modification of the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 3rd Embodiment of this invention. FIG. 5B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 5A. FIG. 5B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 5B. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 4th Embodiment of this invention. FIG. 6B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 6A. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 5th Embodiment of this invention. FIG. 7B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 7A. FIG. 7B is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 7B. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane of a Pt film | membrane. It is a graph which shows the half value width of the peak which shows the orientation to the (111) plane of a Pt film. It is a graph which shows the integrated intensity | strength of the orientation to the (100) plane of a CSPLZT film | membrane. It is a graph which shows the integrated intensity | strength of the orientation to the (101) plane of a CSPLZT film | membrane. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane of a CSPLZT film | membrane. It is a graph which shows the orientation rate of the (222) plane of a CSPLZT film | membrane. It is a graph which shows the half value width of the peak which shows the orientation to the (111) plane of a CSPLZT film | membrane.

Explanation of symbols

51: TiN film 52: TiAlN film 53: Ir film 54: Ir oxide film 55: Capacitance insulating film 91: Pt film 92: Pt film

Claims (6)

Forming a lower electrode film above the substrate;
Forming a capacitive insulating film on the lower electrode film;
Forming an upper electrode film on the capacitive insulating film;
Have
The step of forming the lower electrode film includes:
Forming an amorphous or microcrystalline metal oxide film;
Forming a first noble metal film on the metal oxide film at a first temperature;
Forming a second noble metal film on the first noble metal film at a second temperature higher than the first temperature;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the first temperature is lower than a crystallization temperature of the metal oxide film.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second noble metal film is formed thicker than the first noble metal film.   The first noble metal film and the second noble metal film are formed of one film selected from the group consisting of Pt, Pt alloy, Pd and Pd alloy. 4. A method for manufacturing a semiconductor device according to any one of 3 above. As the metal oxide film, Ir oxide film, Pt oxide film, Ru oxide film, Pd oxide film, Os oxide film, Re oxide film, Rh oxide film, SrRuO ₃ , La _2−x Sr _x CuO ₄ and YBa ₂ Cu ₃ 5. The method for manufacturing a semiconductor device according to claim 1, wherein a film made of one selected from the group consisting of O ₇ is formed. 6. A lower electrode formed above the substrate;
A capacitive insulating film formed on the lower electrode;
An upper electrode formed on the capacitive insulating film;
Have
The lower electrode is
A metal oxide film,
A first noble metal film formed on the metal oxide film;
A second noble metal film formed on the first noble metal film and having larger crystal grains than the first noble metal film;
A semiconductor device comprising:

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