JP2009170896A5 - - Google Patents
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- JP2009170896A5 JP2009170896A5 JP2008319214A JP2008319214A JP2009170896A5 JP 2009170896 A5 JP2009170896 A5 JP 2009170896A5 JP 2008319214 A JP2008319214 A JP 2008319214A JP 2008319214 A JP2008319214 A JP 2008319214A JP 2009170896 A5 JP2009170896 A5 JP 2009170896A5
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- film
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- gate electrode
- semiconductor film
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Claims (11)
前記絶縁表面上のゲート電極と、
前記ゲート電極上の、ジルコニウム酸化物の結晶構造を持つ絶縁膜でなるゲート絶縁膜と、
前記ゲート絶縁膜上の、微結晶半導体膜の島状領域と、を有し、
前記微結晶半導体膜の島状領域は、前記ゲート電極と一部又は全部が重畳し、前記微結晶半導体膜の島状領域に、薄膜トランジスタのチャネル形成領域と、一導電型の不純物を含むソース領域及びドレイン領域と、を有することを特徴とする半導体装置。 An insulating surface on the substrate;
A gate electrode on the insulating surface;
A gate insulating film made of an insulating film having a crystal structure of zirconium oxide on the gate electrode;
Before having on Kige over gate insulating film, and the island-shaped region of the microcrystalline semiconductor film, and
The island-shaped region of the microcrystalline semiconductor film partially or entirely overlaps with the gate electrode, and the island-shaped region of the microcrystalline semiconductor film includes a channel formation region of a thin film transistor and a source region containing one conductivity type impurity. And a drain region.
前記ジルコニウム酸化物の結晶構造を持つ絶縁膜は、イットリウム安定化ジルコニアであることを特徴とする半導体装置。 In claim 1,
The semiconductor device, wherein the insulating film having a crystal structure of zirconium oxide is yttrium-stabilized zirconia.
前記ジルコニウム酸化物の結晶構造を持つ絶縁膜は、ジルコニウム酸化物であることを特徴とする半導体装置。 In claim 1 or 2,
The semiconductor device, wherein the insulating film having a crystal structure of zirconium oxide is zirconium oxide.
前記ゲート電極上に接する、酸化珪素、窒化珪素、酸化窒化珪素、窒化酸化珪素の中から選ばれた一からなる絶縁層を有することを特徴とする半導体装置。 In any one of claims 1 to 3,
A semiconductor device comprising an insulating layer made of one selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide in contact with the gate electrode.
前記微結晶半導体膜の島状領域は、ゲルマニウムを含むことを特徴とする半導体装置。 In any one of Claims 1 thru | or 4,
The island-shaped region of the microcrystalline semiconductor film includes germanium.
前記微結晶半導体膜の島状領域に接し、非晶質半導体膜を有することを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 5,
A method for manufacturing a semiconductor device, comprising an amorphous semiconductor film in contact with an island-shaped region of the microcrystalline semiconductor film.
前記ゲート電極上にジルコニウム酸化物の結晶構造を持つ絶縁膜を形成し、
前記ジルコニウム酸化物の結晶構造を持つ絶縁膜上に微結晶半導体膜を化学気相成長法により成膜し、前記ゲート電極と、一部又は全部が重畳するように、前記微結晶半導体膜を選択的にエッチングして、前記ゲート絶縁膜上に微結晶半導体膜の島状領域を形成し、
前記微結晶半導体膜の島状領域に、薄膜トランジスタのチャネル形成領域が含まれるように、一導電型の不純物を含むソース領域及びドレイン領域を形成することを特徴とする半導体装置の作製方法。 Forming a gate electrode over a substrate having an insulating surface;
Forming an insulating film having a crystal structure of zirconium oxide on the gate electrode;
A microcrystalline semiconductor film is formed on the insulating film having a crystal structure of the zirconium oxide by a chemical vapor deposition method, and the microcrystalline semiconductor film is selected so as to partially or entirely overlap with the gate electrode. Etching to form an island region of a microcrystalline semiconductor film over the gate insulating film,
A method for manufacturing a semiconductor device, wherein a source region and a drain region containing an impurity of one conductivity type are formed so that a channel formation region of a thin film transistor is included in an island-shaped region of the microcrystalline semiconductor film.
前記ジルコニウム酸化物の結晶構造を持つ絶縁膜の表面を、H2、O2、Ar、N2、から選ばれた一、あるいはこの組み合わせ、を用いたプラズマ処理をすることを特徴とする半導体装置の作製方法。 In claim 7,
A semiconductor device characterized in that the surface of the insulating film having a crystal structure of the zirconium oxide is subjected to plasma treatment using one selected from H 2 , O 2 , Ar, N 2 , or a combination thereof. Manufacturing method.
前記プラズマ処理は、逆スパッタ処理であることを特徴とする半導体装置の作製方法。 In claim 8,
The method for manufacturing a semiconductor device, wherein the plasma treatment is reverse sputtering treatment.
前記微結晶半導体膜上に、非晶質半導体膜を成膜することを特徴とする半導体装置の作製方法。 In any one of Claims 7 to 9,
A method for manufacturing a semiconductor device, wherein an amorphous semiconductor film is formed over the microcrystalline semiconductor film.
前記ゲート電極上に接し、酸化珪素、窒化珪素、酸化窒化珪素、窒化酸化珪素の中から選ばれた一からなる絶縁層を成膜することを特徴とする半導体装置の作製方法。 In any one of Claims 7 to 10,
A method for manufacturing a semiconductor device, comprising forming an insulating layer formed of one selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide in contact with the gate electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008319214A JP5496500B2 (en) | 2007-12-18 | 2008-12-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007325708 | 2007-12-18 | ||
JP2007325708 | 2007-12-18 | ||
JP2008319214A JP5496500B2 (en) | 2007-12-18 | 2008-12-16 | Method for manufacturing semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009170896A JP2009170896A (en) | 2009-07-30 |
JP2009170896A5 true JP2009170896A5 (en) | 2012-02-02 |
JP5496500B2 JP5496500B2 (en) | 2014-05-21 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008319214A Expired - Fee Related JP5496500B2 (en) | 2007-12-18 | 2008-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
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JP (1) | JP5496500B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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TW202309859A (en) | 2009-09-10 | 2023-03-01 | 日商半導體能源研究所股份有限公司 | Semiconductor device and display device |
JP5683179B2 (en) * | 2009-09-24 | 2015-03-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing display device |
TWI575751B (en) * | 2011-06-16 | 2017-03-21 | 半導體能源研究所股份有限公司 | Semiconductor device and a method for manufacturing the same |
CN103875077B (en) * | 2011-10-07 | 2016-09-28 | 住友电气工业株式会社 | Dielectric film and manufacture method thereof |
JP6046351B2 (en) * | 2012-01-19 | 2016-12-14 | 日新電機株式会社 | Insulating film and manufacturing method thereof |
US8969130B2 (en) * | 2011-11-18 | 2015-03-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulating film, formation method thereof, semiconductor device, and manufacturing method thereof |
CN104409509A (en) * | 2014-10-20 | 2015-03-11 | 深圳市华星光电技术有限公司 | Thin film transistor |
KR20200028451A (en) * | 2017-08-04 | 2020-03-16 | 더 거버먼트 오브 더 유나이트 스테이츠 오브 아메리카 애즈 레프리젠티드 바이 더 씨크리터리 오브 더 네이비 | Monolayer and multilayer silicin prepared by plasma-enhanced chemical vapor deposition |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3006190B2 (en) * | 1991-07-26 | 2000-02-07 | 株式会社島津製作所 | Vacuum deposition method |
JPH10163502A (en) * | 1996-12-03 | 1998-06-19 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
JP2001077112A (en) * | 1999-07-07 | 2001-03-23 | Matsushita Electric Ind Co Ltd | Laminate, manufacture of thereof, and semiconductor element |
JP2001217424A (en) * | 2000-02-03 | 2001-08-10 | Matsushita Electric Ind Co Ltd | Thin film transistor and liquid crystal display using the same |
JP2002319678A (en) * | 2001-04-20 | 2002-10-31 | Hitachi Ltd | Thin film semiconductor device and manufacturing method therefor |
JP2005005509A (en) * | 2003-06-12 | 2005-01-06 | Canon Inc | Thin film transistor and method of manufacturing the same |
JP2005167051A (en) * | 2003-12-04 | 2005-06-23 | Sony Corp | Thin film transistor and manufacturing method thereof |
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2008
- 2008-12-16 JP JP2008319214A patent/JP5496500B2/en not_active Expired - Fee Related
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