JP5683179B2 - Method for manufacturing display device - Google Patents

Description

The present invention relates to a thin film transistor using an oxide semiconductor, a display device using the thin film transistor, and a manufacturing method thereof.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several nanometers to several hundred nanometers or less) formed over a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required. Various metal oxides exist and are used in various applications. For example, indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides exhibit semiconductor properties. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors that use such metal oxides that exhibit semiconductor characteristics as a channel formation region are already known. (Patent Document 1 and Patent Document 2).

A TFT using an oxide semiconductor has a relatively high field effect mobility as an amorphous state. Therefore, a driving circuit such as a display device can be formed using the TFT.

JP 2007-123861 A JP 2007-96055 A

At present, a processing method using a photolithography method in a manufacturing process is often used. When the photolithography method is used, a photomask is also required for each exposure pattern. Therefore, a cost for manufacturing the photomask is required, which is one of the causes of an increase in manufacturing cost. Further, when the photolithography method is used, a large amount of resist material or a large amount of developer is used to improve uniformity, and there is a problem that a large amount of extra material is consumed.

In addition, a display device using a TFT to which an oxide semiconductor is applied has greatly expanded its use to a large display device. Therefore, the screen size is further improved, the aperture ratio is increased, the reliability is increased, and the large size is achieved. There is a growing demand for aging. If the display device is further increased in size in the future, it is disadvantageous in mass production in that the amount of extra material consumed and the amount of waste liquid are large.

An object of one embodiment of the present invention is to provide a thin film transistor which can be manufactured with low yield and high yield, and a manufacturing method thereof. Another object is to provide a method for manufacturing a display device using the thin film transistor.

In one embodiment of the present invention, a light-transmitting first conductive layer is formed over a substrate having an insulating surface, and a first mask is formed over the first conductive layer by a droplet discharge method. Then, the first conductive layer is etched using the first mask to form a first gate electrode layer, a gate insulating layer is formed over the first gate electrode layer, and the gate insulating layer is formed over the gate insulating layer. Forming an oxide semiconductor layer, dehydrating or dehydrogenating the oxide semiconductor layer, forming a second mask on the dehydrated or dehydrogenated oxide semiconductor layer by a droplet discharge method; The island-shaped oxide semiconductor layer is formed by etching the oxide semiconductor layer using the second mask, and the light-transmitting second conductive layer is formed over the island-shaped oxide semiconductor layer Then, a third mask is formed on the second conductive layer by a droplet discharge method, and the third mask is used. By etching the second conductive layer, a first source electrode layer and a first drain electrode layer are formed, and the first gate insulating layer, the island-shaped oxide semiconductor layer, the first source electrode layer, And a protective insulating layer in contact with part of the island-shaped oxide semiconductor layer is formed over the first drain electrode layer and electrically connected to the first source electrode layer or the first drain electrode layer over the protective insulating layer. A display device manufacturing method is characterized in that a light-transmitting pixel electrode layer to be connected is formed by a printing method.

According to one embodiment of the present invention, a first conductive layer is formed over a substrate having an insulating surface, a first mask is formed over the first conductive layer by a droplet discharge method, The first conductive layer is etched using the mask to form a first gate electrode layer, a gate insulating layer is formed over the first gate electrode layer, and an oxide semiconductor layer is formed over the gate insulating layer And the oxide semiconductor layer is dehydrated or dehydrogenated, and a second mask is formed over the dehydrated or dehydrogenated oxide semiconductor layer by a droplet discharge method, and the second mask is formed And etching the oxide semiconductor layer to form an island-shaped oxide semiconductor layer, forming a second conductive layer over the island-shaped oxide semiconductor layer, and over the second conductive layer, A third mask is formed using a droplet discharge method, and the second conductive layer is etched using the third mask. Thus, the first source electrode layer and the first drain electrode layer are formed, and the first gate insulating layer, the island-shaped oxide semiconductor layer, the first source electrode layer, and the first drain electrode layer are formed. A protective insulating layer in contact with part of the island-shaped oxide semiconductor layer is formed on the protective insulating layer, and the pixel having a light-transmitting property is electrically connected to the first source electrode layer or the first drain electrode layer A method for manufacturing a display device is characterized in that an electrode layer is formed by a printing method.

In the above structure, the gate electrode layer, the source electrode layer, and the drain electrode layer are a film containing a metal element as a main component selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, or a film thereof. A laminated film combined with an alloy film is used. Further, the source electrode layer and the drain electrode layer are not limited to a single layer containing any of the above elements, and a stack of two or more layers can be used.

In the above structure, a light-transmitting oxide conductive layer such as indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc oxynitride, or zinc gallium oxide is used as a source. By using the electrode layer, the drain electrode layer, and the gate electrode layer, the light-transmitting property of the pixel portion can be improved and the aperture ratio can be increased.

As one embodiment of the present invention, a thin film transistor having a bottom gate structure is used. In the bottom gate structure, a reverse coplanar type (also referred to as a bottom contact type) having an oxide semiconductor layer overlying a source electrode layer and a drain electrode layer, or a channel in which a source electrode layer and a drain electrode layer overlap with an oxide film semiconductor layer There are an etch type and a channel protection type, both of which can be used.

In the case of the channel etch type, the oxide semiconductor layer may have either a structure in which part of the oxide semiconductor layer is etched in the upper portion of the channel formation region or a structure in which the oxide semiconductor layer is not etched.

Further, the oxide conductive layer is formed between the oxide semiconductor layer and the film containing the metal element as a main component constituting the source electrode layer and the drain electrode layer, and high-speed operation with reduced contact resistance is possible. A thin film transistor can also be formed.

In the above structure, the thin film transistor includes an oxide semiconductor layer, has an oxide insulating layer over the oxide semiconductor layer, and the oxide insulating layer in contact with the channel formation region of the oxide semiconductor layer serves as a protective insulating layer. Function.

In the above structure, the oxide insulating layer functioning as a protective insulating layer of the thin film transistor is formed using an inorganic insulating film formed by a sputtering method, and is typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide film. Aluminum nitride or the like is used.

Note that as the oxide semiconductor layer, a thin film represented by InMO ₃ (ZnO) _m (m> 0) is formed, and a thin film transistor using the thin film as an oxide semiconductor layer is manufactured. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M may be Ga, and may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements. In this specification, among oxide semiconductor layers having a structure represented by InMO ₃ (ZnO) _m (m> 0), an oxide semiconductor having a structure containing Ga as M is represented by In—Ga—Zn—O-based oxidation. It is called a physical semiconductor, and its thin film is also called an In—Ga—Zn—O-based film.

In addition to the above, a metal oxide applied to the oxide semiconductor layer includes an In—Sn—O-based material, an In—Sn—Zn—O-based material, an In—Al—Zn—O-based material, a Sn—Ga—Zn— O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based A ZnO-based metal oxide can be used. Further, silicon oxide may be included in the oxide semiconductor layer formed of the metal oxide.

For the oxide semiconductor layer, a layer which has been subjected to dehydration or dehydrogenation treatment at high temperature and short time by an RTA method or the like is used.

In addition, a driver circuit portion and a pixel portion can be formed over the same substrate using a thin film transistor which is one embodiment of the present invention, and a display device can be manufactured using an EL element, a liquid crystal element, an electrophoretic element, or the like.

In a display device which is one embodiment of the present invention, the pixel portion includes a plurality of thin film transistors, and the gate electrode of the thin film transistor which is also in the pixel portion and a source wiring or drain wiring of another thin film transistor are connected to each other. Yes. In addition, the driver circuit of the display device which is one embodiment of the present invention includes a portion where the gate electrode of the thin film transistor is connected to the source wiring or the drain wiring of the thin film transistor.

In this specification, a film having a light-transmitting property with respect to visible light refers to a film having a film thickness with a visible light transmittance of 75% to 100%. When the film has conductivity, a transparent conductive film is used. Also called a membrane. In addition, as a metal oxide applied to a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, other electrode layers, or other wiring layers, a conductive film that is translucent to visible light is used. Also good. Translucent to visible light means that the visible light transmittance is 50 to 75%.

In addition, since the thin film transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the thin film transistor in the pixel portion over the same substrate with respect to the gate line or the source line. The protective circuit is preferably formed using a non-linear element using an oxide semiconductor layer.

In addition, the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

According to one embodiment of the present invention, in a process of forming a conductor pattern (such as a gate wiring or a source wiring), the exposure process, the development process, and the like can be shortened, and the amount of material used can be reduced, so that a significant cost reduction can be realized. . In addition, a thin film transistor and a display device using the thin film transistor can be provided at low cost without reducing productivity even when the substrate is enlarged.

FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. FIGS. 4A to 4C are cross-sectional process diagrams illustrating one embodiment of the present invention. FIGS. FIGS. 4A to 4C are cross-sectional process diagrams illustrating one embodiment of the present invention. FIGS. FIG. 6 is a plan view illustrating one embodiment of the present invention. 4A and 4B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a droplet discharge device. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. 4A and 4B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. FIG. 10 illustrates a block diagram of a semiconductor device. FIG. 6 illustrates a structure of a signal line driver circuit. FIG. 3 is a circuit diagram illustrating a configuration of a shift register. FIG. 5 is a circuit diagram illustrating a structure of a shift register and a timing chart illustrating an operation. 4A and 4B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. 6A and 6B illustrate a pixel equivalent circuit of a semiconductor device. FIG. 6 is a cross-sectional view illustrating one embodiment of the present invention. 4A and 4B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. 8A and 8B illustrate examples of usage forms of electronic paper. An external view showing an example of an electronic book. FIG. 6 is an external view illustrating an example of a television device and a digital photo frame. An external view showing an example of a gaming machine. The external view which shows an example of a mobile telephone.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a thin film transistor using an oxide semiconductor layer, a display device using the thin film transistor, and a manufacturing method thereof will be described with reference to FIGS.

In the thin film transistor illustrated in FIG. 1, a gate electrode layer 102, a gate insulating layer 105, an oxide semiconductor layer 108, a source electrode layer 112 and a drain electrode layer 113, a protective insulating layer 116, and a pixel electrode layer 121 are provided over a substrate 100. Yes.

FIG. 1A illustrates a structure in which part of the oxide semiconductor layer 108 is etched between the source electrode layer 112 and the drain electrode layer 113 as a normal channel etch thin film transistor. The oxide semiconductor layer 108 may not be etched as shown in FIG.

The gate electrode layer 102 includes a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium, an alloy material containing any of these metal materials as a main component, or any of these metal materials as a component. A single layer or a stacked layer can be formed using nitride. Preferably, formation with a low-resistance metal material such as aluminum or copper is effective, but it may be used in combination with a refractory metal material because of problems of heat resistance and corrosion. As the refractory metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like can be used.

For the purpose of improving the aperture ratio of the pixel portion, the gate electrode layer 102 may be formed of indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc oxynitride, zinc gallium oxide, or the like. A light-transmitting oxide conductive layer can be used. In this embodiment, the case where the gate electrode layer 102 is formed using a light-transmitting oxide conductive layer is described.

As the gate insulating layer 105, a single-layer film or a stacked film of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, tantalum oxide, or the like formed by a CVD method, a sputtering method, or the like can be used.

The oxide semiconductor layer 108 uses an In—Ga—Zn—O-based film containing In, Ga, and Zn and has a structure represented by InMO ₃ (ZnO) _m (m> 0). Note that M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, M may be Ga, and may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements.

The oxide semiconductor layer 108 is formed by a sputtering method. The film thickness is 10 nm to 300 nm, preferably 20 nm to 100 nm. However, as illustrated in FIG. 1, when part of the oxide semiconductor layer 108 is etched between the source electrode layer 112 and the drain electrode layer 113, the thickness of the oxide semiconductor layer 108 is larger than that of a region overlapping with the source electrode layer 112 or the drain electrode layer 113. It has a thin area.

As the oxide semiconductor layer 108, a layer which has been subjected to dehydration or dehydrogenation treatment at high temperature and short time by an RTA method or the like is used. The dehydration or dehydrogenation treatment is performed at a temperature of 500 ° C. or higher and 750 ° C. or lower (or a temperature lower than the strain point of the glass substrate) for 1 minute or longer and 10 minutes or shorter using high-temperature nitrogen, inert gas such as rare gas, or light. RTA (Rapid Thermal Annealing) treatment at about 650 ° C., preferably 3 minutes or more and 6 minutes or less. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed at a temperature exceeding the strain point of the glass substrate.

The oxide semiconductor layer 108 is amorphous having many dangling bonds at the stage of film formation; however, the oxide semiconductor layer 108 is ordered amorphous by performing the heating step of the dehydration or dehydrogenation treatment. It can be a structure. In addition, when ordering develops, a mixture of amorphous and microcrystals in which microcrystals are scattered in an amorphous region, or the entire crystallite group is formed. Here, the particle size of the microcrystal is a so-called nanocrystal of 1 nm or more and 20 nm or less, which is smaller than the microcrystal particle generally called a microcrystal.

The source electrode layer 112 and the drain electrode layer 113 can be formed using a material similar to that of the gate electrode layer 102 described above.

Further, like the gate electrode layer 102, the above light-transmitting oxide conductive layer is used for the source electrode layer 112 and the drain electrode layer 113, whereby the light-transmitting property of the pixel portion is improved and the aperture ratio is increased. Can do. In this embodiment, the case where the source electrode layer 112 and the drain electrode layer 113 are formed using a light-transmitting oxide conductive layer is described.

In addition, the above-described oxide conductive layer is formed between each of the film containing the above-described metal material as a main component and the oxide semiconductor layer 108 to be the source electrode layer 112 and the drain electrode layer 113, so that contact resistance is reduced. You can also.

An oxide insulating layer functioning as the protective insulating layer 116 is provided over the oxide semiconductor layer 108, the source electrode layer 112, and the drain electrode layer 113. An inorganic insulating film formed by a sputtering method is used for the oxide insulating layer, and a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, aluminum oxynitride, or the like is typically used.

In addition, as illustrated in FIG. 1C, the source electrode layer and the drain electrode layer are formed using a light-transmitting oxide conductive layer (a source electrode layer 112 and a drain electrode layer 113) and a film containing a metal material as a main component. It is also possible to have a laminated structure. With a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component, contact resistance can be reduced. Note that FIG. 1C illustrates the case where a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component is used for the source electrode layer 112 and the drain electrode layer 113. The gate electrode layer 102 may have a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component.

With the above structure, a thin film transistor with high reliability and improved electrical characteristics can be provided.

Next, an example of a manufacturing process of a display device including the channel-etched thin film transistor illustrated in FIG. 1 will be described with reference to FIGS. Reference numeral 191 denotes a pixel portion, 192 denotes a storage capacitor portion, 193 denotes a first terminal portion, and 194 denotes a second terminal portion.

First, the substrate 100 is prepared. The substrate 100 is a heat-resistant material that can withstand the processing temperature of this manufacturing process, in addition to an alkali-free glass substrate, a ceramic substrate, or the like manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass. A plastic substrate or the like having the above can be used. Alternatively, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless alloy may be used. Note that a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used instead of the glass substrate. In addition, a crystallized glass substrate or the like can be used.

Further, an insulating film may be formed over the substrate 100 as a base film. As the base film, a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film may be formed by a CVD method, a sputtering method, or the like. In the case where a substrate containing mobile ions such as sodium is used as the substrate 100 such as a glass substrate, the mobile ions are converted into oxide semiconductors by using a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film as a base film. Intrusion into a layer or a semiconductor layer can be prevented.

Next, a conductive film for forming the gate wiring including the gate electrode layer 102, the capacitor wiring 103, and the first terminal 104 is formed over the entire surface of the substrate 100 by a sputtering method or a vacuum evaporation method. Next, after a conductive film is formed over the entire surface of the substrate 100, a mask 101a, a mask 101b, and a mask 101c are formed by an inkjet method or a droplet discharge method, unnecessary portions are removed by etching, and wirings and electrodes (gate electrodes) are formed. A gate wiring including the layer 102, a capacitor wiring 103, and a first terminal 104) are formed (see FIG. 2A). At this time, in order to prevent disconnection, etching is preferably performed so that at least an end portion of the gate electrode layer 102 is tapered.

Here, one mode of a droplet discharge apparatus used in the droplet discharge method is shown in FIG. The individual heads 1405 and 1412 of the droplet discharge means 1403 are connected to the control means 1407, and can be drawn in a pre-programmed pattern by being controlled by the computer 1410. The droplet discharge means is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The drawing position may be determined by recognizing the marker 1411 formed on the substrate 1400 using the imaging unit 1404, the image processing unit 1409, and the computer 1410, and determining the reference point. Alternatively, the reference point may be determined based on the edge of the substrate 1400.

As the imaging unit 1404, an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.

The inside of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. When the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths. A single head can discharge and draw multiple types of materials, etc., and when drawing over a wide area, the same material can be simultaneously discharged from multiple nozzles and drawn to improve throughput. . When a large substrate is used as the object to be processed, the head 1405, the head 1412 and the stage having the object to be processed are scanned relatively in the direction of the arrow, and the drawing area is freely set. A plurality of images can be drawn on a single substrate.

The step of discharging the composition may be performed under reduced pressure. The substrate may be heated at the time of discharge. After discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps. For example, drying is performed at 80 ° C. to 100 ° C. for 3 minutes, and firing is performed at 200 ° C. to 550 ° C. for 15 minutes to 60 minutes. Its purpose, temperature and time are different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. Conditions such as temperature and time for performing the drying and firing steps favorably depend on the material of the substrate and the properties of the composition.

In one embodiment of the present invention, the mask is formed using an ink-jet method or a droplet discharge method, so that the use efficiency of materials is improved, and cost reduction and waste liquid treatment amount can be reduced. In addition, when the region to be removed by etching, such as formation of wiring, is 80% or more, it is preferable to form a mask by a droplet discharge method because wasteful resist solution can be reduced. Further, by forming a mask by a droplet discharge method, the photolithography process can be simplified. That is, photomask formation, exposure, and the like are not necessary, so that the capital investment cost can be reduced and the manufacturing time can be shortened. In the case of forming a mask by a droplet discharge method, plasma treatment may be performed on a surface on which the mask is formed to form a liquid repellent region, and the mask may be formed in the liquid repellent region. In addition, a lyophilic region may be formed by selectively irradiating laser light, and then a mask may be formed in the lyophilic region. Alternatively, a liquid-repellent region or a lyophilic region may be selectively formed on the surface to be processed using a printing method, and then a mask may be formed in the lyophilic region. As a result, the mask formed by the droplet discharge method can be miniaturized.

Inorganic materials (silicon oxide, silicon nitride, silicon oxynitride, etc.) and photosensitive or non-photosensitive organic materials (polyimide, acrylic, polyamide, polyimide amide, polyvinyl alcohol, resist or benzocyclobutene) are used as mask materials. Can do. For example, in the case where a mask is formed using polyimide by an inkjet method, heat treatment may be performed at 150 ° C. or more and 300 ° C. or less in order to calcinate after discharging polyimide to a desired portion by an inkjet method.

The gate wiring and the capacitor wiring 103 including the gate electrode layer 102 and the first terminal 104 in the terminal portion are formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium, or these metal materials It is possible to form a single layer or a stacked layer using an alloy material containing as a main component or a nitride containing these metal materials as components. Preferably, formation with a low-resistance metal material such as aluminum or copper is effective, but it may be used in combination with a refractory metal material because of problems of heat resistance and corrosion. As the refractory metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like can be used.

For example, the stacked structure of the gate electrode layer 102 includes a two-layer structure in which molybdenum is stacked on aluminum, a two-layer structure in which molybdenum is stacked on a copper layer, or titanium nitride or tantalum nitride is stacked on copper. A two-layer structure in which titanium nitride and molybdenum are stacked is preferable. The three-layer structure is a structure in which aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as an intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is stacked as upper and lower layers. It is preferable.

In addition, the aperture ratio can be improved by using a light-transmitting oxide conductive layer for some electrode layers and wiring layers. For example, indium oxide, an indium tin oxide alloy, an indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, zinc gallium oxide, or the like can be used for the oxide conductive layer. 2A to 4B illustrate the case where the gate electrode layer 102, the capacitor wiring 103, and the first terminal 104 are formed using a light-transmitting oxide conductive layer. Note that the gate electrode layer 102, the capacitor wiring 103, and the first terminal 104 have a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component, thereby reducing contact resistance. It can also be made.

Next, a gate insulating layer 105 is formed over the entire surface over the gate wiring and the capacitor wiring 103 including the gate electrode layer 102 and the first terminal 104 in the terminal portion. The gate insulating layer 105 is formed by a CVD method, a sputtering method, or the like with a thickness of 50 nm to 250 nm.

For example, a silicon oxide film is used as the gate insulating layer 105 by a CVD method or a sputtering method, and is formed with a thickness of 100 nm. Needless to say, the gate insulating layer 105 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and a tantalum oxide film are used. Alternatively, it may be formed as a single layer or a laminated structure made of these materials.

As the gate insulating layer 105, a silicon oxide layer can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. It is possible to use a silicon-containing compound such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ). it can.

Alternatively, the gate insulating layer 105 can be formed using an oxide, nitride, oxynitride, or nitride oxide of aluminum, yttrium, or hafnium, or a compound containing at least two of these compounds.

Note that in this specification, oxynitride refers to a substance having a larger number of oxygen atoms than nitrogen atoms as its composition, and a nitrided oxide refers to the number of nitrogen atoms as compared to oxygen atoms. It refers to substances with a lot of content. For example, a silicon oxynitride film has a larger number of oxygen atoms than nitrogen atoms, and uses Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). When measured, oxygen ranges from 50% to 70 atom%, nitrogen from 0.5% to 15 atom%, silicon from 25% to 35 atom%, hydrogen from 0.1% to 10 atom%. Those included in the following ranges. In addition, the composition of the silicon nitride oxide film has a larger number of nitrogen atoms than oxygen atoms, and when measured using RBS and HFS, oxygen has a concentration range of 5% to 30 atomic% and nitrogen has 20%. % To 55 atom%, silicon is contained in the range of 25% to 35 atom%, and hydrogen is contained in the range of 10% to 30 atom%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

Further, before the oxide semiconductor film 106 is formed, reverse sputtering in which an argon gas is introduced to generate plasma is preferably performed to remove dust attached to the surface of the gate insulating layer 105. Reverse sputtering is a method of modifying the surface by forming a plasma on a substrate by applying a voltage using an RF power source on the substrate side in an argon atmosphere without applying a voltage to the target side. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an argon atmosphere may be used in which oxygen, N ₂ O, or the like is added. Alternatively, an atmosphere obtained by adding Cl ₂ , CF _4, or the like to an argon atmosphere may be used. After the reverse sputtering treatment, the oxide semiconductor film 106 is formed without being exposed to the air, whereby dust and moisture can be prevented from attaching to the interface between the gate insulating layer 105 and the oxide semiconductor layer 108.

Next, the oxide semiconductor film 106 with a thickness of 5 nm to 200 nm, preferably 10 nm to 40 nm is formed over the gate insulating layer 105 (see FIG. 2B).

The oxide semiconductor film 106 includes In—Ga—Zn—O, In—Sn—Zn—O, In—Al—Zn—O, Sn—Ga—Zn—O, and Al—Ga—Zn—O. -Based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxides A semiconductor film can be used. The oxide semiconductor film 106 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. . In the case of using a sputtering method, deposition may be performed using a target containing 2 wt% or more and 10 wt% or less of SiO ₂ , and SiO x (X> 0) may be included in the oxide semiconductor film.

Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (molar ratio is In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 0.5, In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 or In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2), the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The film is formed in a direct current (DC) power source of 0.5 kW and in an oxygen (oxygen flow rate 100%) atmosphere. Note that a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. In this embodiment, as the oxide semiconductor film, an In—Ga—Zn—O-based film with a thickness of 30 nm is formed by a sputtering method using an In—Ga—Zn—O-based oxide semiconductor deposition target. .

The filling rate of the oxide semiconductor target for film formation is preferably 80% or higher, preferably 95% or higher, more preferably 99.9% or higher. Accordingly, the impurity concentration in the formed oxide semiconductor film can be reduced, and a thin film transistor with high electrical characteristics or high reliability can be obtained.

Examples of the sputtering method include an RF sputtering method using a high frequency power source as a sputtering power source, a DC sputtering method using a direct current, and a pulsed DC sputtering method that applies a bias in a pulsed manner. The RF sputtering method is mainly used when an insulating film is formed, and the DC sputtering method is mainly used when a metal film is formed.

There is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be installed. The multi-source sputtering apparatus can be formed by stacking different material films in the same chamber, or by simultaneously discharging a plurality of types of materials in the same chamber.

Further, there is a sputtering apparatus using a magnetron sputtering method having a magnet mechanism inside a chamber, and a sputtering apparatus using an ECR sputtering method using plasma generated using microwaves without using glow discharge.

In addition, as a film formation method using a sputtering method, a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or a voltage is applied to the substrate during film formation. There is also a bias sputtering method.

Further, the substrate may be heated to 400 ° C. or higher and 700 ° C. or lower with light or a heater during film formation by sputtering. By heating during film formation, damage caused by sputtering is repaired simultaneously with film formation.

Further, before the oxide semiconductor film 106 is formed, preheating treatment is preferably performed in order to remove moisture or hydrogen remaining on the inner wall of the sputtering apparatus, the target surface, and the target material. As the preheating treatment, there are a method in which the inside of the film forming chamber is heated to 200 ° C. or higher and 600 ° C. or lower under reduced pressure, a method in which introduction and exhaust of nitrogen and inert gas are repeated while heating, and the like. After completion of the preheating treatment, the oxide semiconductor film is formed without being exposed to the air after the substrate or the sputtering apparatus is cooled. In this case, the target coolant may be oil or fat instead of water. Even if the introduction and exhaust of nitrogen are repeated without heating, a certain effect can be obtained.

In addition, before the oxide semiconductor film 106 is formed, during the film formation, or after the film formation, moisture remaining in the sputtering apparatus is preferably removed using a cryopump.

Next, a mask 107 is formed by an inkjet method or a droplet discharge method, and the oxide semiconductor film 106 is etched (see FIG. 2C). For etching, an organic acid such as citric acid or oxalic acid can be used as an etchant. Here, unnecessary portions are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.), the In—Ga—Zn—O-based film is formed into an island shape, and the oxide semiconductor layer 108 is formed. By etching the end portion of the oxide semiconductor layer 108 in a tapered shape, disconnection of a wiring due to a step shape can be prevented. Note that the etching here is not limited to wet etching, and dry etching may be used.

In one embodiment of the present invention, the mask is formed using an ink-jet method or a droplet discharge method, so that the use efficiency of materials is improved, and cost reduction and waste liquid treatment amount can be reduced. In addition, when the region to be removed by etching, such as the formation of an island-shaped oxide semiconductor layer, is 80% or more, a resist solution that is wasted can be reduced by forming a mask by a droplet discharge method. Therefore, it is preferable. Further, by forming a mask by a droplet discharge method, the photolithography process can be simplified. That is, photomask formation, exposure, and the like are not necessary, and the capital investment cost can be reduced, and the manufacturing time can be shortened. In the case of forming a mask by a droplet discharge method, plasma treatment may be performed on a surface on which the mask is formed to form a liquid repellent region, and the mask may be formed in the liquid repellent region. In addition, a lyophilic region may be formed by selectively irradiating laser light, and then a mask may be formed in the lyophilic region. Alternatively, a liquid-repellent region or a lyophilic region may be selectively formed on the surface to be processed using a printing method, and then a mask may be formed in the lyophilic region. As a result, the mask formed by the droplet discharge method can be miniaturized.

Next, the oxide semiconductor layer 108 is dehydrated or dehydrogenated. The first heat treatment for performing dehydration or dehydrogenation is performed at a temperature of 500 ° C. or higher and 750 ° C. or lower (or a temperature below the strain point of the glass substrate) using high-temperature nitrogen, an inert gas such as a rare gas, or light. And RTA (Rapid Thermal Annealing) treatment at about 650 ° C. for about 3 minutes to 6 minutes. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed at a temperature exceeding the strain point of the glass substrate.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 108, the oxide semiconductor layer may be crystallized to be a microcrystalline film or a polycrystalline film. In the case of a microcrystalline film, it is preferable that the ratio of the crystal component to the whole is 80% or more (preferably 90% or more) and that the adjacent microcrystalline grains are in contact with each other. In some cases, the entire oxide semiconductor layer 108 is in an amorphous state.

Note that in this specification, heat treatment in an atmosphere of an inert gas such as nitrogen or a rare gas is referred to as heat treatment for dehydration or dehydrogenation. In this specification, it is not called dehydrogenation only that it is desorbed as H ₂ by this heat treatment, and dehydration or dehydrogenation including desorption of H, OH, etc. It will be called for convenience.

After the oxide semiconductor layer 108 is heated to a heating temperature at which dehydration or dehydrogenation is performed, water or hydrogen is not mixed again without being exposed to the atmosphere in the same furnace where dehydration or dehydrogenation is performed. This is very important. After dehydration or dehydrogenation, the i-type oxide semiconductor layer 108 is changed to n-type (n ⁻ , n ^+, etc.), that is, reduced in resistance, and then converted into i-type to increase resistance again. When a thin film transistor is manufactured using the physical semiconductor layer 108, a threshold voltage value of the thin film transistor can be positive, and a switching element having a so-called normally-off characteristic can be realized. It is desirable for the display device that the channel is formed with a positive threshold voltage as close as possible to 0 V as the gate voltage of the thin film transistor. Note that when the threshold voltage value of the thin film transistor is negative, a so-called normally-on characteristic is easily obtained in which a current flows between the source electrode and the drain electrode even when the gate voltage is 0V. In an active matrix display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and the electrical characteristics affect the performance of the display device. In particular, the threshold voltage (Vth) is important among the electrical characteristics of thin film transistors. Even if the field effect mobility is high, if the threshold voltage value is high or the threshold voltage value is negative, it is difficult to control the circuit. In the case of a thin film transistor having a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as the thin film transistor cannot be achieved in a state where the drive voltage is low, which may cause a load. In the case of an n-channel thin film transistor, a transistor in which a channel is formed and drain current flows only after a positive voltage is applied to the gate voltage is desirable. A transistor in which a channel is not formed unless the driving voltage is increased or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin film transistor used in a circuit.

Further, the gas atmosphere that is lowered from the heating temperature may be switched to a gas atmosphere that is different from the gas atmosphere that is heated up to the heating temperature. For example, without exposing to the atmosphere in the same furnace where dehydration or dehydrogenation is performed, the inside of the furnace is highly purified oxygen gas or N ₂ O gas, ultra-dry air (dew point is −40 ° C. or lower, preferably − 60 ° C. or less) and cooling is performed.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not contained in the atmosphere. Alternatively, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is preferable that

In the case where the heat treatment is performed in an inert gas atmosphere, the i-type oxide semiconductor layer 108 becomes oxygen-deficient due to the heat treatment and becomes n-type, that is, has a low resistance. After that, an oxide insulating layer functioning as a protective insulating layer in contact with the oxide semiconductor layer 108 is formed, so that the oxide semiconductor layer 108 is in an oxygen-excess state, which is i-type, that is, the resistance is increased. It can also be said. Accordingly, a thin film transistor with favorable electric characteristics and high reliability can be manufactured.

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, part of the oxide semiconductor layer 108 may be crystallized. After the first heat treatment, the oxide semiconductor layer 108 becomes an oxygen-deficient type and has low resistance. After the first heat treatment, the carrier concentration is higher than that of the oxide semiconductor film 106 immediately after deposition, and preferably has a carrier concentration of 1 × 10 ¹⁸ / cm ³ or more.

The first heat treatment of the oxide semiconductor layer 108 can be performed on the oxide semiconductor film 106 before being processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus and processed into an island-shaped oxide semiconductor layer.

Next, a photolithography process is performed, a resist mask is formed, unnecessary portions are removed by etching, and a contact hole 109 reaching the wiring and electrode layer of the same material as the gate electrode layer 102 is formed. This contact hole 109 is provided for direct connection to a conductive film to be formed later. For example, a contact hole is formed when a thin film transistor directly in contact with a gate electrode layer and a source electrode layer or a drain electrode layer or a terminal electrically connected to a gate wiring in a terminal portion is formed in a driver circuit portion.

Next, a conductive layer is formed over the oxide semiconductor layer 108 by a sputtering method or a vacuum evaporation method. As a material for the conductive layer, a material similar to that of the gate electrode layer 102 described above can be used.

Next, a mask 110a, a mask 110b, a mask 110c, and a mask 110d are formed by an inkjet method or a droplet discharge method, unnecessary portions are removed by etching, and the source electrode layer 112, the drain electrode layer 113, the connection electrode 114, and the contact are removed. 115 is formed (see FIG. 3A). As an etching method at this time, wet etching or dry etching is used.

In one embodiment of the present invention, the mask is formed using an ink-jet method or a droplet discharge method, so that the use efficiency of materials is improved, and cost reduction and waste liquid treatment amount can be reduced. In addition, when the region to be removed by etching, such as formation of wiring, is 80% or more, it is preferable to form a mask by a droplet discharge method because wasteful resist solution can be reduced. Further, by forming a mask by a droplet discharge method, the photolithography process can be simplified. That is, photomask formation, exposure, and the like are not necessary, and the capital investment cost can be reduced, and the manufacturing time can be shortened. In the case of forming a mask by a droplet discharge method, plasma treatment may be performed on a surface on which the mask is formed to form a liquid repellent region, and the mask may be formed in the liquid repellent region. In addition, a lyophilic region may be formed by selectively irradiating laser light, and then a mask may be formed in the lyophilic region. Alternatively, a liquid-repellent region or a lyophilic region may be selectively formed on the surface to be processed using a printing method, and then a mask may be formed in the lyophilic region. As a result, the mask formed by the droplet discharge method can be miniaturized.

Through the above process, the thin film transistor 150 using the oxide semiconductor layer 108 as a channel formation region can be manufactured.

Here, as in the gate electrode layer 102, the light-transmitting oxide conductive layer is used for the source electrode layer 112 and the drain electrode layer 113, whereby the light-transmitting property of the pixel portion is improved and the aperture ratio is increased. Can do. Further, as with the gate electrode layer 102, contact resistance can be reduced by using a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component. Note that FIGS. 1 to 4 illustrate the case where the conductive layers (the source electrode layer 112, the drain electrode layer 113, and the connection electrode 114) are formed using a light-transmitting conductive layer.

Further, when the source electrode layer 112 and the drain electrode layer 113 are formed, a terminal portion including the second terminal 111 which is the same material as the source electrode layer 112 and the drain electrode layer 113 is formed. Note that the second terminal 111 is electrically connected to a source wiring (a source wiring including the source electrode layer 112 or the drain electrode layer 113).

In the terminal portion, the connection electrode 114 is directly connected to the first terminal 104 in the terminal portion through a contact hole 109 formed in the gate insulating film. Although not shown here, the source wiring or drain wiring of the thin film transistor of the driver circuit and the gate electrode are directly connected through the same process as described above.

Next, the mask 110a, the mask 110b, the mask 110c, and the mask 110d are removed, and the protective insulating layer 116 that covers the thin film transistor 150 is formed. As the protective insulating layer 116, an oxide insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or a tantalum oxide film obtained by a sputtering method or the like can be used.

The protective insulating layer 116 can be formed as appropriate by a method such as sputtering, in which an impurity such as water or hydrogen is not mixed into the protective insulating layer 116. In this embodiment, a silicon oxide film is formed as the protective insulating layer 116 by a sputtering method. The substrate temperature at the time of film formation may be from room temperature to 300 ° C., and is 100 ° C. in this embodiment. Here, as a method for preventing impurities such as water and hydrogen from being mixed at the time of film formation, pre-baking is performed at a temperature of 150 ° C. to 350 ° C. for 2 minutes to 10 minutes under reduced pressure before film formation without touching the atmosphere. It is preferable to form the protective insulating layer 116. The silicon oxide film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Further, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, silicon oxide can be formed by a sputtering method in an atmosphere containing oxygen and a rare gas. The protective insulating layer 116 formed in contact with the low-resistance oxide semiconductor layer 108 does not include impurities such as moisture, hydrogen ions, and OH ^−, and an inorganic insulating film that blocks entry of these from the outside. preferable.

In this embodiment, the purity is 6N, a columnar polycrystalline B-doped silicon target (resistance value 0.01 Ωcm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, and the pressure is 0 The film is formed by pulsed DC sputtering in an atmosphere of 4 Pa, direct current (DC) power supply 6 kW, and oxygen (oxygen flow rate 100%). The film thickness is 300 nm.

Next, second heat treatment (preferably 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C.) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, the second heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere. Alternatively, high temperature and short time RTA treatment may be performed as in the first heat treatment. When the second heat treatment is performed, the oxide semiconductor layer 108 which overlaps with the protective insulating layer 116 is heated. Note that when the second heat treatment is performed, the oxide semiconductor layer 108 whose resistance is reduced by the first heat treatment is in an oxygen-excess state and can be i-type (high resistance).

In this embodiment, the second heat treatment is performed after the protective insulating layer 116 is formed. However, there is no problem as long as the timing of the heat treatment is after the protective insulating layer 116 is formed, and it is limited to immediately after the protective insulating layer 116 is formed. Is not to be done.

In the case where a heat-resistant material is used for the source electrode layer 112 and the drain electrode layer 113, a process using the first heat treatment condition can be performed at the timing of the second heat treatment. In this case, the heat treatment can be performed only once after the protective insulating layer 116 is formed.

Next, a photolithography step is performed to form a resist mask, and a contact hole 118 reaching the drain electrode layer 113 is formed by etching the protective insulating layer 116. Further, a contact hole 117 reaching the second terminal 111 and a contact hole 119 reaching the connection electrode 114 are also formed by the etching here (see FIG. 3B). Note that the contact holes 117, 118, and 119 may be formed by forming a mask pattern by an ink jet method or a droplet discharge method instead of the photolithography process and combining etching.

Next, after removing the resist mask, the pixel electrode layer 121 and the transparent conductive films 120 and 122 are formed. The pixel electrode layer 121 and the transparent conductive films 120 and 122 are formed of indium tin oxide (ITO) or silicon oxide by a printing method such as screen printing or offset printing using a liquid containing a light-transmitting material or paste. A predetermined pattern made of a composition containing indium tin oxide (ITSO) containing zinc, zinc oxide (ZnO), tin oxide (SnO ₂ ), and the like is formed and baked. By using a printing method, a predetermined region can be formed; therefore, there are few regions to be removed by the etching step, and the raw materials can be reduced. As another method, a transparent conductive film or a light reflective conductive film is formed by a sputtering method, a mask pattern is formed by an inkjet method or a droplet discharge method, and etching is combined to form the pixel electrode layer 121 and the transparent conductive film. The films 120 and 121 may be formed.

At this time, a storage capacitor is formed by the capacitor wiring 103 and the pixel electrode layer 121 using the gate insulating layer 105 and the protective insulating layer 116 in the storage capacitor portion 192 as dielectrics.

The transparent conductive films 120 and 122 serve as electrodes or wirings used for connection with the FPC. The transparent conductive film 122 formed over the connection electrode 114 directly connected to the first terminal 104 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive film 120 formed over the second terminal 111 is a connection terminal electrode that functions as an input terminal of the source wiring.

A cross-sectional view at this stage is illustrated in FIG. 3C corresponds to a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG.

5A1 and 5A2 are a cross-sectional view and a plan view of the gate wiring terminal portion at this stage, respectively. FIG. 5A1 corresponds to a cross-sectional view taken along line C1-C2 in FIG. In FIG. 5A1, a transparent conductive film 155 formed over the protective insulating layer 154 is a connection terminal electrode that functions as an input terminal. In FIG. 5A1, in the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode 153 formed of the same material as the source wiring are provided with the gate insulating layer 152 interposed therebetween. Overlap and conduct through the opening. Further, the connection electrode 153 and the transparent conductive film 155 are in direct contact with each other through a contact hole provided in the protective insulating layer 154 to be conducted.

5B1 and 5B2 are a cross-sectional view and a plan view of the source wiring terminal portion, respectively. 5B1 corresponds to a cross-sectional view taken along line D1-D2 in FIG. 5B2. In FIG. 5B1, a transparent conductive film 155 formed over the protective insulating layer 154 is a connection terminal electrode that functions as an input terminal. 5B1, in the terminal portion, an electrode 156 formed of the same material as the gate wiring is provided below the second terminal 180 electrically connected to the source wiring with the gate insulating layer 152 interposed therebetween. Overlap. The electrode 156 is not electrically connected to the second terminal 180. If the electrode 156 is set to a potential different from that of the second terminal 180, for example, floating, GND, 0V, etc. Capacitance for static electricity countermeasures can be formed. In addition, the second terminal 180 is electrically connected to the transparent conductive film 155 through the protective insulating layer 154.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. In the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, and the like are arranged. Any number of terminals may be provided, and the practitioner may determine the number appropriately.

In this manner, the channel etch type thin film transistor 150 and the storage capacitor portion 192 can be completed. These can be arranged in a matrix corresponding to each pixel, and a pixel portion can be formed to form one substrate for manufacturing an active matrix display device. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the case of manufacturing an active matrix liquid crystal display device, a liquid crystal layer is provided between an active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. The fourth terminal is a terminal for setting the common electrode to a fixed potential such as GND or 0V.

In this embodiment, an example in which the capacitor wiring is provided in the pixel structure is described; however, one embodiment of the present invention is not limited thereto, and the capacitor electrode is not provided, and the pixel electrode is protected from the gate wiring of an adjacent pixel. A storage capacitor can be formed so as to overlap with each other with the insulating layer and the gate insulating layer interposed therebetween. In this case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted.

In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is recognized by the observer as a display pattern.

In moving image display of a liquid crystal display device, there is a problem that an afterimage is generated or a moving image is blurred because the response of the liquid crystal molecules themselves is slow. In order to improve the moving image characteristics of a liquid crystal display device, there is a so-called black insertion driving technique in which black display is performed every other frame.

Further, the so-called double speed drive, which improves the response speed by setting the vertical period to 1.5 times, preferably 2 times or more, and selects the gradation to be written for each of a plurality of divided fields in each frame. There is also technology.

In addition, in order to improve the moving image characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as a backlight, and each light source constituting the surface light source is independent. There is also a driving technique that performs intermittent lighting driving within one frame period. As the surface light source, three or more kinds of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be controlled independently, the light emission timings of the LEDs can be synchronized with the optical modulation switching timing of the liquid crystal layer. Since this driving technique can partially turn off the LED, an effect of reducing power consumption can be achieved particularly in the case of video display in which the ratio of the black display area occupying one screen is large.

By combining these driving techniques, the display characteristics such as the moving picture characteristics of the liquid crystal display device can be improved as compared with the related art.

The n-channel transistor obtained in this embodiment uses an In—Ga—Zn—O-based film for a channel formation region and has favorable dynamic characteristics; thus, these driving techniques can be combined.

In the case of manufacturing a light-emitting display device, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential, for example, GND, 0 V, and the like. A fourth terminal is provided for setting to 0V or the like. In the case of manufacturing a light-emitting display device, a power supply line is provided in addition to a source wiring and a gate wiring. Therefore, the terminal portion is provided with a fifth terminal that is electrically connected to the power supply line.

Note that in FIGS. 2 to 4, the gate electrode layer 102, the source electrode layer 112, and the drain electrode layer 113 are formed using a light-transmitting oxide conductive layer; It is not limited. As illustrated in FIG. 7, the gate electrode layer 202, the source electrode layer 222, and the drain electrode layer 223 can be formed using a film containing a metal material as a main component. 2 to 4 illustrate the case where the capacitor wiring 103 and the first terminal 104 are formed using a light-transmitting conductive layer; however, as illustrated in FIG. 7, the light-transmitting conductive layer is used. Instead of the layer, a film containing a metal material as a main component can be used.

The gate electrode layer 202, the capacitor wiring 203, the first terminal 204, the source electrode layer 212, and the drain electrode layer 213 can be formed with a single-layer structure or a stacked structure using a film containing a metal material as a main component. For example, as the gate electrode layer 202, the capacitor wiring 203, and the first terminal 204, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, or a two-layer structure in which a molybdenum layer is stacked over a copper layer, or copper A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over the layer, or a structure in which a titanium nitride layer and a molybdenum layer are stacked can be employed. The three-layer structure can be a structure in which a tungsten layer or a tungsten nitride layer, an aluminum / silicon alloy layer or an aluminum / titanium alloy layer, and a titanium nitride layer or a titanium layer are stacked. When the source electrode layer 212 and the drain electrode layer 213 are formed in a three-layer structure, a titanium layer that is a heat-resistant conductive material is used as the first and third conductive layers, and the second conductive layer is formed. An aluminum alloy layer containing neodymium is used as the layer. With such a configuration, generation of hillocks can be reduced while taking advantage of the low resistance of aluminum.

Although this embodiment mode describes a manufacturing method using a channel-etched thin film transistor as an example, a bottom contact thin film transistor can also be manufactured by changing the order of steps. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along A1-A2 in FIG. 8A.

A thin film transistor 150 illustrated in FIG. 8 includes a gate electrode layer 102, a gate insulating layer 105, a source electrode layer 112 and a drain electrode layer 113, and an oxide semiconductor layer 108 over a substrate 100. The protective insulating layer 116 is provided over the gate insulating layer 105, the source electrode layer 112, the drain electrode layer 113, and the oxide semiconductor layer 108.

Through the above steps, a thin film transistor with favorable electric characteristics and high reliability and a display device using the thin film transistor can be provided.

According to one embodiment of the present invention having the above structure, a highly reliable wiring and conductive layer can be formed while improving throughput and material utilization efficiency. Accordingly, a thin film transistor and a display device using the thin film transistor can be provided at low cost without reducing productivity even when the substrate is enlarged.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, an example of manufacturing an active matrix liquid crystal display device using the active matrix substrate described in Embodiment 1 is described. Note that this embodiment can also be applied to active matrix substrates described in other embodiments.

In this embodiment, when the size of the liquid crystal display panel exceeds 10 inches, 60 inches, or 120 inches, the wiring resistance of the light-transmitting wiring may become a problem. An example of reducing the wiring resistance by using a part of the wiring as a metal wiring will be described.

An example of a cross-sectional structure of the active matrix substrate is shown in FIG. Although the thin film transistor and the storage capacitor portion in the pixel portion are illustrated in Embodiment Mode 1, in this embodiment mode, the thin film transistor 160 in the driver circuit portion is also illustrated and described in addition to the thin film transistor 150 and the storage capacitor portion in the pixel portion. . In addition, the storage capacitor portion, the terminal portion of the gate wiring, and the terminal portion of the source wiring have structures different from those of the first embodiment. In addition, in a portion serving as a display region of the pixel portion, a gate wiring, a source wiring, and a capacitor wiring are formed using a light-transmitting conductive film, thereby realizing a high aperture ratio. Further, a metal wiring can be used for the source wiring layer in a portion other than the display region in order to reduce the wiring resistance.

The capacitor wiring 103 overlaps with the capacitor electrode layer 231 through gate insulating layers 105a and 105b serving as dielectrics to form a storage capacitor portion. Note that the capacitor electrode layer 231 is formed using the same light-transmitting material and the same step as the source electrode layer 112 or the drain electrode layer 113 of the thin film transistor 150. Therefore, in addition to the light-transmitting property of the thin film transistor 150, the storage capacitor portion is also light-transmitting, so that the aperture ratio can be improved. Note that the storage capacitor portion is provided below the pixel electrode layer 121, and the capacitor electrode layer 231 is electrically connected to the pixel electrode layer 121.

The thin film transistor 160 in the driver circuit portion has the same structure as the thin film transistor 150 in the pixel portion except for the source electrode layer, the drain electrode layer, and the conductive layer. The source electrode layer and the drain electrode layer of the thin film transistor 160 in the driver circuit portion are formed using a stacked structure of a light-transmitting oxide conductive layer and a film containing a metal material as a main component.

A conductive layer (hereinafter referred to as a back gate electrode layer 320) is provided over the thin film transistor 160 in the driver circuit portion so as to overlap with the oxide semiconductor layer. When the back gate electrode layer 320 is electrically connected to the gate electrode layer 302 and has the same potential, the gate voltage is applied to the oxide semiconductor layer 308 provided between the gate electrode layer 302 and the back gate electrode layer 320 from above and below. Can be applied. In addition, when the gate electrode layer 302 and the back gate electrode layer 320 are set to different potentials, for example, a fixed potential, GND, or 0 V, the electrical characteristics of the TFT, such as a threshold voltage, can be controlled. Note that in this specification, a conductive layer formed over the oxide semiconductor layer 308 is referred to as a back gate electrode layer 320 regardless of its potential. Therefore, the back gate electrode layer 320 may be in a floating state. Note that a material forming the thin film transistor 160 in the driver circuit portion is not limited to a light-transmitting material.

The gate electrode layer 302 of the thin film transistor 160 in the driver circuit may be electrically connected to the back gate electrode layer 320 provided over the oxide semiconductor layer 308. In that case, the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 150 and the pixel electrode layer 121 is used (see Embodiment Mode 1 (FIG. 3C)) and is flat. The contact insulating layer 234, the protective insulating layers 116a and 116b, and the gate insulating layers 105a and 105b are selectively etched to form contact holes. Through this contact hole, the back gate electrode layer 320 and the gate electrode layer 302 of the thin film transistor 160 of the driver circuit are electrically connected.

In this embodiment, the planarization insulating layer 234 is formed over the protective insulating layer 116b, and then the planarization insulating layer 234 in the terminal portion is selectively removed using a photomask. In the terminal portion, it is preferable that the planarization insulating layer 234 is not present in order to achieve good connection with the FPC.

In the terminal portion, the first terminal electrode having the same potential as that of the gate wiring is formed over the protective insulating layer 116 a and is electrically connected to the second metal wiring layer 237. The wiring routed from the terminal portion is also formed of metal wiring. In FIG. 9A, the gate wiring layer 238 that overlaps part of the second metal wiring layer 237 is shown; however, the gate wiring layer that covers all of the first metal wiring layer 236 and the second metal wiring layer 237 is shown. It is good. That is, the first metal wiring layer 236 and the second metal wiring layer 237 can be called auxiliary wirings for reducing the resistance of the gate wiring layer 238.

In FIG. 9A, the second terminal electrode 235 having the same potential as the source wiring 300 of the driver circuit is formed over the protective insulating layer 116a.

In addition, the gate wiring layer and the capacitor wiring layer in a portion other than the display area use metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 as auxiliary wiring in order to reduce wiring resistance. You can also.

In the case of manufacturing an active matrix liquid crystal display device, a liquid crystal layer is provided between an active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrode electrically connected to the common electrode is provided in the terminal portion. The fourth terminal electrode is a terminal for setting the common electrode to a fixed potential such as GND or 0V. The fourth terminal electrode can be formed using the same light-transmitting material as the pixel electrode layer 121.

FIG. 9B illustrates a cross-sectional structure that is partly different from that in FIG. FIG. 9B is the same as FIG. 9A except that the material of the gate electrode layer of the thin film transistor of the driver circuit is different; therefore, the same portions are denoted by the same reference numerals and detailed description of the same portions is omitted. To do.

FIG. 9B illustrates an example in which the gate electrode layer of the thin film transistor 160 of the driver circuit is a metal wiring. In the driver circuit, the gate electrode layer is not limited to a light-transmitting material.

In FIG. 9B, a thin film transistor 160 in the driver circuit is a gate electrode layer in which a second metal wiring layer 242 is stacked over a first metal wiring layer 241. Note that the first metal wiring layer 241 can be formed using the same material and the same process as the first metal wiring layer 236. The second metal wiring layer 242 can be formed using the same material and the same process as the second metal wiring layer 237.

In addition, when the first metal wiring layer 241 is electrically connected to the back gate electrode layer 320, the second metal wiring layer 242 for preventing oxidation of the first metal wiring layer 241 is a metal nitride film. Is preferred.

Through the above steps, a thin film transistor with favorable electric characteristics and high reliability and a display device using the thin film transistor can be provided.

In one embodiment of the present invention having the above structure, even when metal wiring is partially used to reduce wiring resistance and the size of a liquid crystal display panel exceeds 10 inches, 60 inches, or 120 inches, display is performed. High definition of the image can be achieved and a high aperture ratio can be realized.

According to one embodiment of the present invention having the above structure, a highly reliable wiring and conductive layer can be formed while improving throughput and material utilization efficiency. Accordingly, a thin film transistor and a display device using the thin film transistor can be provided at low cost without reducing productivity even when the substrate is enlarged.

This embodiment can be freely combined with any of the other embodiments.

(Embodiment 3)
In this embodiment, an example in which at least part of a driver circuit and a thin film transistor placed in a pixel portion are formed over the same substrate will be described below.

The thin film transistor to be arranged in the pixel portion is formed in accordance with Embodiment Mode 1 and Embodiment Mode 2. In addition, since the thin film transistor described in any of Embodiments 1 and 2 is an n-channel TFT, a part of the driver circuit that can be formed using the n-channel TFT in the driver circuit is the same as the thin film transistor in the pixel portion. Form on the substrate.

An example of a block diagram of an active matrix display device is illustrated in FIG. A pixel portion 5301, a first scan line driver circuit 5302, a second scan line driver circuit 5303, and a signal line driver circuit 5304 are provided over the substrate 5300 of the display device. In the pixel portion 5301, a plurality of signal lines are extended from the signal line driver circuit 5304, and a plurality of scan lines are extended from the first scan line driver circuit 5302 and the scan line driver circuit 5303. Yes. Note that pixels each having a display element are arranged in a matrix in the intersection region between the scanning line and the signal line. Further, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) through a connection portion such as an FPC (Flexible Printed Circuit).

In FIG. 10A, the first scan line driver circuit 5302, the second scan line driver circuit 5303, and the signal line driver circuit 5304 are formed over the same substrate 5300 as the pixel portion 5301. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. In addition, when the driver circuit is provided outside the substrate 5300, the number of connections in the connection portion by extending the wiring can be reduced, so that the reliability or the yield can be improved.

Note that the timing control circuit 5305 supplies, for example, a first scan line driver circuit start signal (GSP1) and a scan line driver circuit clock signal (GCKL1) to the first scan line driver circuit 5302. For example, the timing control circuit 5305 outputs, to the first scan line driver circuit 5302, a second scan line driver circuit start signal (GSP2) (also referred to as a start pulse), a scan line driver circuit clock signal ( GCLK2) is supplied. The signal line driver circuit 5304 receives a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal (SCLK), video signal data (DATA) (also simply referred to as a video signal), and a latch signal (LAT). Shall be supplied. Each clock signal may be a plurality of clock signals with shifted periods, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that one of the first scan line driver circuit 5302 and the second scan line driver circuit 5303 can be omitted.

In FIG. 10B, circuits with low driving frequencies (for example, the first scan line driver circuit 5302 and the second scan line driver circuit 5303) are formed over the same substrate 5300 as the pixel portion 5301, and the signal line driver circuit 5304 is formed. Is formed on a different substrate from the pixel portion 5301. With this structure, a driver circuit formed over the substrate 5300 can be formed using a thin film transistor whose field-effect mobility is lower than that of a transistor including a single crystal semiconductor. Therefore, an increase in the size of the display device, a reduction in the number of steps, a reduction in cost, an improvement in yield, or the like can be achieved.

The thin film transistors described in Embodiments 1 and 2 are n-channel TFTs. 11A and 11B illustrate an example of a structure and operation of a signal line driver circuit including n-channel TFTs.

The signal line driver circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors called thin film transistors 5603_1 to 5603_k (k is a natural number). An example in which the thin film transistors 5603_1 to 5603_k are n-channel TFTs will be described.

A connection relation of the signal line driver circuit is described by using the switching circuit 5602 1 as an example. First terminals of the thin film transistors 5603_1 to 5603_k are connected to wirings 5604_1 to 5604_k, respectively. Second terminals of the thin film transistors 5603_1 to 5603_k are connected to signal lines S1 to Sk, respectively. The gates of the thin film transistors 5603_1 to 5603_k are connected to the wiring 5605_1.

The shift register 5601 has a function of sequentially outputting H-level signals (also referred to as an H signal and a high power supply potential level) to the wirings 5605_1 to 5605_N and sequentially selecting the switching circuits 5602_1 to 5602_N.

The switching circuit 5602_1 has a function of controlling electrical connection between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk (conduction between the first terminal and the second terminal), that is, the potential of the wirings 5604_1 to 5604_k is changed to the signal lines S1 to S604. It has a function of controlling whether or not to supply to Sk. As described above, the switching circuit 5602 1 has a function as a selector. The thin film transistors 5603_1 to 5603_N each have a function of controlling electrical continuity between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of supplying the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. As described above, the thin film transistors 5603_1 to 5603_N each have a function as a switch.

Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an image signal or an analog signal corresponding to the image signal.

Next, operation of the signal line driver circuit in FIG. 11A is described with reference to a timing chart in FIG. FIG. 11B illustrates an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, and the signals Vdata_1 to Vdata_k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. As an example, one gate selection period is divided into a period T1 to a period TN. The periods T1 to TN are periods for writing video signal data (DATA) to the pixels belonging to the selected row.

Note that signal waveform rounding and the like in each structure illustrated in the drawings and the like in this embodiment are exaggerated for simplicity in some cases. Therefore, it is added that it is not necessarily limited to the scale.

In the periods T1 to TN, the shift register 5601 sequentially outputs H-level signals to the wirings 5605_1 to 5605_N. For example, in the period T1, the shift register 5601 outputs a high-level signal to the wiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k are turned on, so that the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into conduction. At this time, Data (S1) to Data (Sk) are input to the wirings 5604_1 to 5604_k. Data (S1) to Data (Sk) are written to the pixels in the first to kth columns among the pixels belonging to the selected row through the thin film transistors 5603_1 to 5603_k, respectively. Thus, in the periods T1 to TN, video signal data (DATA) is sequentially written to the pixels belonging to the selected row by k columns.

As described above, the number of video signal data (DATA) or the number of wirings can be reduced by writing video signal data (DATA) to pixels by a plurality of columns. Therefore, the number of connections with external circuits can be reduced. In addition, since the video signal is written to the pixels in a plurality of columns, the writing time can be extended and insufficient writing of the video signal can be prevented.

Note that as the shift register 5601 and the switching circuit 5602, a circuit including the thin film transistor described in any of Embodiments 1 and 2 can be used. In this case, the polarity of all the transistors included in the shift register 5601 can be configured with only an n-channel or p-channel polarity.

Note that the structure of the scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. In some cases, a level shifter may be provided. In the scan line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified in the buffer and supplied to the corresponding scanning line. A gate electrode of a transistor of a pixel for one line is connected to the scanning line. Since the transistors of pixels for one line must be turned on all at once, a buffer that can flow a large current is used.

One mode of a shift register used for part of the scan line driver circuit and / or the signal line driver circuit is described with reference to FIGS.

A shift register of the scan line driver circuit and the signal line driver circuit is described with reference to FIGS. The shift register includes the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 12A). In the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register illustrated in FIG. 12A, the first clock signal CK1 from the first wiring 11 and the second pulse output circuit 10_N from the second wiring 12 are connected. The third clock signal CK3 is supplied from the clock signal CK2, the third wiring 13, and the fourth clock signal CK4 is supplied from the fourth wiring 14. In the first pulse output circuit 10_1, the start pulse SP1 (first start pulse) from the fifth wiring 15 is input. In the second and subsequent nth pulse output circuits 10_n (n is a natural number of 2 or more and N or less), a signal (referred to as the previous stage signal OUT (n-1)) from the previous stage pulse output circuit (n is 2). The above natural number) is input. Alternatively, a signal from the (n + 2) th pulse output circuit 10_ (n + 2) in the second stage and the subsequent stage is input to the nth pulse output circuit 10_n in the second and subsequent stages (referred to as a subsequent stage signal OUT (n + 2)). Further, the pulse output circuit at each stage is connected to a first output signal OUT (1) (SR) for input to the preceding stage and / or the subsequent stage pulse output circuit, another wiring, etc. Output signal OUT (1) is output. Note that as shown in FIG. 12A, since the latter stage signal OUT (n + 2) is not input to the last two stages of the shift register, as an example, the second start pulse SP2 and the third stage are separately provided. The start pulse SP3 may be input.

Note that the clock signal (CK) is a signal that repeats an H level and an L level (also referred to as an L signal or a low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by ¼ period. In this embodiment, driving of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4). Note that although the clock signal is sometimes referred to as GCK or SCK depending on the input driving circuit, it is described here as CK.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 12A, in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, and the second input terminal 22 is connected to the second wiring 12. The third input terminal 23 is electrically connected to the third wiring 13. In the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the second pulse output circuit 10_2 is electrically connected to the third wiring 13. 3 input terminals 23 are electrically connected to the fourth wiring 14.

Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth input terminal. An input terminal 25, a first output terminal 26, and a second output terminal 27 are provided (see FIG. 12B). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input terminal 23 is input. The third clock signal CK3 is input, the start pulse is input to the fourth input terminal 24, the post-stage signal OUT (3) is input to the fifth input terminal 25, and the first output terminal 26 The output signal OUT (1) (SR) is output, and the second output signal OUT (1) is output from the second output terminal 27.

Note that each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N uses the four-terminal thin film transistor described in the above embodiment in addition to a three-terminal thin film transistor (also referred to as a thin film transistor). it can. FIG. 12C illustrates a symbol of the thin film transistor 28 having four terminals described in the above embodiment mode. The thin film transistor 28 performs electrical control between the In terminal and the Out terminal by the first control signal G1 input to the first gate electrode and the second control signal G2 input to the second gate electrode. It is an element that can.

In the case where an oxide semiconductor is used for a channel layer of a thin film transistor, the threshold voltage may shift to the negative side or the positive side depending on the manufacturing process. Therefore, a structure in which threshold voltage can be controlled is preferable for a thin film transistor in which an oxide semiconductor is used for a channel layer. The threshold voltage of the thin film transistor 28 illustrated in FIG. 12C is that a gate electrode is provided above and below a channel formation region of the thin film transistor 28 through a gate insulating film, and the potential of the upper and / or lower gate electrode is controlled. Thus, the desired value can be controlled.

Next, an example of a specific circuit configuration of the pulse output circuit illustrated in FIG. 12B will be described with reference to FIG.

The pulse output circuit illustrated in FIG. 12D includes a first transistor 31 to a thirteenth transistor 43. In addition to the first input terminal 21 to the fifth input terminal 25, the first output terminal 26, and the second output terminal 27 described above, the power supply line 51 to which the first high power supply potential VDD is supplied, A signal or power supply potential is supplied to the first transistor 31 to the thirteenth transistor 43 from the power supply line 52 to which the second high power supply potential VCC is supplied and the power supply line 53 to which the low power supply potential VSS is supplied. Here, the magnitude relationship between the power supply potentials of the power supply lines in FIG. 12D is that the first power supply potential VDD is equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is the third power supply potential VSS. Use a higher potential. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and are VDD when the level is H and VSS when the level is the L level. And Note that by making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be kept low without affecting the operation, and the threshold value of the transistor Shift can be reduced and deterioration can be suppressed. Note that among the first transistor 31 to the thirteenth transistor 43, a four-terminal thin film transistor is preferably used for the first transistor 31 and the sixth transistor 36 to the ninth transistor 39. The operation of the first transistor 31 and the sixth transistor 36 to the ninth transistor 39 is a transistor in which the potential of a node to which one of the source and drain electrodes is connected is switched by a control signal of the gate electrode. In this transistor, the response to the control signal input to the gate electrode is fast (the on-state current rises sharply), so that the malfunction of the pulse output circuit can be reduced. Therefore, a threshold voltage can be controlled by using a four-terminal thin film transistor, and a pulse output circuit that can reduce malfunctions can be obtained.

In FIG. 12D, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (first gate electrode and The second gate electrode) is electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the first terminal of the ninth transistor 39, and a gate electrode connected to the fourth transistor 34. It is electrically connected to the gate electrode. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate The electrode is electrically connected to the fourth input terminal 24. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, a second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate The electrodes (first gate electrode and second gate electrode) are electrically connected to the fifth input terminal 25. The seventh transistor 37 has a first terminal electrically connected to the power supply line 52, a second terminal electrically connected to the second terminal of the eighth transistor 38, and a gate electrode (first gate electrode and The second gate electrode) is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode (first gate electrode and second gate electrode). Are electrically connected to the second input terminal 22. The ninth transistor 39 has a first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and a second terminal connected to the gate electrode of the third transistor 33 and The gate electrode (first gate electrode and second gate electrode) of the tenth transistor 40 is electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21, a second terminal electrically connected to the second output terminal 27, and a gate electrode connected to the ninth transistor 39. It is electrically connected to the second terminal. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the second output terminal 27, and a gate electrode connected to the gate electrode of the second transistor 32 and The fourth transistor 34 is electrically connected to the gate electrode. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the second output terminal 27, and a gate electrode of the seventh transistor 37 ( The first gate electrode and the second gate electrode). The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the first output terminal 26, and a gate electrode of the seventh transistor 37 ( The first gate electrode and the second gate electrode).

In FIG. 12D, a connection point between the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is a node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, A connection point of the gate electrode of the eleventh transistor 41 is a node B (see FIG. 13A).

Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and the drain region, the channel region, and the source region. A current can be passed through. Here, since the source and the drain vary depending on the structure and operating conditions of the thin film transistor, it is difficult to limit which is the source or the drain. Thus, a region functioning as a source and a drain may not be referred to as a source or a drain. In that case, as an example, there are cases where they are referred to as a first terminal and a second terminal, respectively.

Note that in FIGS. 12D and 13A, a capacitor for performing a bootstrap operation by bringing the node A into a floating state may be additionally provided. Further, in order to hold the potential of the node B, a capacitor in which one electrode is electrically connected to the node B may be separately provided.

Here, FIG. 13B shows a timing chart of a shift register including a plurality of pulse output circuits shown in FIG. Note that in the case where the shift register is a scan line driver circuit, a period 61 in FIG. 13B corresponds to a vertical blanking period, and a period 62 corresponds to a gate selection period.

As shown in FIG. 13A, by providing the ninth transistor 39 to which the second power supply potential VCC is applied at the gate, the following advantages are obtained before and after the bootstrap operation. .

When there is no ninth transistor 39 to which the second potential VCC is applied to the gate electrode, when the potential of the node A is increased by the bootstrap operation, the potential of the source that is the second terminal of the first transistor 31 is increased. As a result, the potential becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which can cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, the potential of the node A rises by the bootstrap operation, but the second terminal of the first transistor 31 It is possible to prevent the potential from increasing. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced, so that deterioration of the first transistor 31 due to stress is suppressed. be able to.

Note that the ninth transistor 39 is provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Any configuration may be used. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, the ninth transistor 39 may be omitted in a signal line driver circuit having more stages than a scanning line driver circuit, and the number of transistors is reduced. There are advantages.

Note that by using an oxide semiconductor as the semiconductor layers of the first transistor 31 to the thirteenth transistor 43, off-state current of the thin film transistor can be reduced, on-state current and field-effect mobility can be increased, and deterioration can be achieved. Therefore, malfunctions in the circuit can be reduced. In addition, a transistor using an oxide semiconductor is less deteriorated when a high potential is applied to a gate electrode than a transistor using amorphous silicon. Therefore, even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, the same operation can be obtained, and the number of power supply lines routed between the circuits can be reduced. The circuit can be reduced in size.

Note that the clock signal supplied from the third input terminal 23 to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37, and the gate electrode (first gate) of the eighth transistor 38. The clock signal supplied to the second input terminal 22 by the second input terminal 22 is connected to the second input terminal to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37. 22 and the gate signal (first gate electrode and second gate electrode) of the eighth transistor 38 are connected to each other so that the clock signal is supplied from the third input terminal 23. Even if it is replaced, the same effect is obtained. At this time, in the shift register illustrated in FIG. 13A, the seventh transistor 37 and the eighth transistor 38 are turned off, and the seventh transistor 37 and the eighth transistor 38 are turned on. Next, when the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of the node B is lowered by the potential of the second input terminal 22 and the third input terminal 23 being lowered. However, this occurs twice due to a decrease in the potential of the gate electrode of the seventh transistor 37 and a decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. 13A, the seventh transistor 37 is turned on, the seventh transistor 37 is turned on, and the seventh transistor 37 and the eighth transistor 38 are turned on, as in the period of FIG. 13B. 8 transistor 38 is turned off, then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, so that the potentials of the second input terminal 22 and the third input terminal 23 are lowered. Thus, the decrease in the potential of the node B can be reduced at a time due to the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the clock signal is supplied from the third input terminal 23 to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37, and the gate electrode (first gate) of the eighth transistor 38 is supplied. It is preferable that the clock signal is supplied from the second input terminal 22 to the electrode and the second gate electrode). This is because the number of fluctuations in the potential of the node B is reduced and noise can be reduced.

As described above, by setting the signal to be periodically supplied to the node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, the pulse output is performed. A malfunction of the circuit can be suppressed.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 4)
A thin film transistor described in any of Embodiments 1 and 2 is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor in a pixel portion and further in a driver circuit. In addition, the thin film transistor described in any of Embodiments 1 and 2 can be partly or wholly formed over the same substrate as the pixel portion to form a system-on-panel.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

The display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. Further, in the process of manufacturing the display device, the element substrate which corresponds to one embodiment before the display element is completed is provided with a means for supplying current to the display element in each of the plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or after the conductive film to be the pixel electrode is formed, the pixel electrode is formed by etching. The previous state may be used, and all forms are applicable.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, a module with a FPC (Flexible printed circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board at the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.

A liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIGS. 14A1 and 14A2 are top views of the liquid crystal display panel, and FIG 14B corresponds to a cross section taken along line MN in FIGS 14A1 and 14A2. The liquid crystal panel illustrated in FIG. 14 includes the highly reliable thin film transistors 4010 and 4011 (see FIG. 14B) each including the In—Ga—Zn—O-based film described in Embodiments 1 and 2 as an oxide semiconductor layer. doing. 14 has a structure in which the thin film transistors 4010 and 4011 and the liquid crystal element 4013 formed over the first substrate 4001 are sealed with a sealant 4005 between the second substrate 4006 and the liquid crystal panel. is there.

A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. Has been.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. 14A1 illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method, and FIG. 14A2 illustrates an example in which the signal line driver circuit 4003 is mounted by a TAB method.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of thin film transistors. In FIG. 14B, the thin film transistor 4010 included in the pixel portion 4002 and the scan line A thin film transistor 4011 included in the driver circuit 4004 is illustrated. Insulating layers 4020 and 4021 are provided over the thin film transistors 4010 and 4011.

As the thin film transistors 4010 and 4011, the highly reliable thin film transistor described in Embodiments 1 and 2 including an In—Ga—Zn—O-based film as an oxide semiconductor layer can be used. In this embodiment mode, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A conductive layer 4040 is provided over the insulating layer 4021 so as to overlap with a channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driver circuit. By providing the conductive layer 4040 so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. The conductive layer 4040 may have the same potential as or different from the gate electrode layer of the thin film transistor 4011, and can function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0 V, or a floating state.

In addition, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is formed over the second substrate 4006. The liquid crystal element 4013 corresponds to a portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 which function as alignment films, and sandwich the liquid crystal layer 4008 with the insulating layers 4032 and 4033 interposed therebetween. Note that although not illustrated, the color filter may be provided on either the first substrate 4001 or the second substrate 4006 side.

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramic, plastic, or the like can be used. As the plastic, for example, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, and an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can also be used.

The spacer 4035 is obtained by selectively etching the insulating film and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. The counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. Using the common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected to each other through conductive particles disposed between the pair of substrates. Note that the conductive particles are included in the sealant 4005.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, and is optically isotropic, so that alignment treatment is unnecessary and viewing angle dependency is small.

Note that although this embodiment is an example of a transmissive liquid crystal display device, the present invention can be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, a colored layer is provided on the inner side, and an electrode layer used for the display element is provided in this order. May be provided. In addition, the stacked structure of the polarizing plate and the colored layer is not limited to this embodiment mode, and may be set as appropriate depending on the material and manufacturing process conditions of the polarizing plate and the colored layer. Further, a light shielding film functioning as a black matrix may be provided.

In this embodiment mode, the thin film transistor obtained in Embodiment Mode 2 is used as a protective film or a planarization insulating film in order to reduce surface roughness due to the thin film transistor and to improve the reliability of the thin film transistor. The insulating layer 4020 is covered with the insulating layer 4021. Note that the protective film is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and a dense film is preferable. The protective film is formed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film by a sputtering method. What is necessary is just to form by a layer or lamination | stacking. Although an example in which the protective film is formed by a sputtering method is described in this embodiment mode, the method is not particularly limited and may be formed by various methods.

Here, an insulating layer 4020 having a stacked structure is formed as the protective film. Here, as the first layer of the insulating layer 4020, a silicon oxide film is formed by a sputtering method. The use of a silicon oxide film as the protective film is effective in preventing hillocks of the aluminum film used as the source electrode layer and the drain electrode layer.

In addition, an insulating layer is formed as a second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. When a silicon nitride film is used as the protective film, it is possible to prevent mobile ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

Further, after the protective film is formed, the oxide semiconductor layer may be annealed (300 ° C. or higher and 400 ° C. or lower).

In addition, the insulating layer 4021 is formed as the planarization insulating film. As the insulating layer 4021, an organic material having heat resistance such as acrylic, polyimide, benzocyclobutene, polyamide, or epoxy can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), BPSG (phosphorus glass), or the like can be used. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed using these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. Siloxane resins may use organic groups (for example, alkyl groups and aryl groups) and fluoro groups as substituents. The organic group may have a fluoro group.

The formation method of the insulating layer 4021 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dip, spray coating, droplet discharge (inkjet method, screen printing, offset printing, etc.), doctor knife A roll coater, a curtain coater, a knife coater or the like can be used. In the case where the insulating layer 4021 is formed using a material solution, annealing (300 ° C. to 400 ° C.) of the oxide semiconductor layer may be performed at the same time as the baking step. Further, by combining the baking process of the insulating layer 4021 and annealing of the oxide semiconductor layer, a semiconductor device can be efficiently manufactured.

The pixel electrode layer 4030 and the counter electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide ( Hereinafter, it is referred to as ITO), and a light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

In addition, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

In this embodiment, the connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the terminal electrode 4016 is the same conductive film as the source and drain electrode layers of the thin film transistors 4010 and 4011. It is formed with.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

FIG. 14 illustrates an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or only part of the scan line driver circuit may be separately formed and mounted.

Next, a structural example of a liquid crystal display module manufactured by applying the TFT described in any of Embodiments 1 and 2 is described with reference to FIGS.

In the liquid crystal display module illustrated in FIG. 15, a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealant 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, a colored layer 2605, and a polarizing plate 2606 are interposed therebetween. A display area is provided. The colored layer 2605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611. The circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and an external circuit such as a control circuit or a power circuit is incorporated. Yes. Moreover, you may laminate | stack in the state which had the phase difference plate between the polarizing plate and the liquid-crystal layer.

The liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Pattern Attached Pattern) (Axial Symmetrically Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid mode) It can be used.

Through the above process, a highly reliable liquid crystal display panel as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an example of electronic paper is described as a semiconductor device to which the thin film transistor described in any of Embodiments 1 and 2 is applied.

FIG. 16 illustrates an example of active matrix electronic paper. As the thin film transistor 581 used for the semiconductor device, the thin film transistor described in any of Embodiments 1 and 2 can be used.

The electronic paper in FIG. 16 is an example of a display device using a twisting ball display system. The twist ball display method is a method in which spherical particles separately painted in white and black are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and the first electrode layer and the second electrode layer are arranged. In this method, a potential difference is generated in the two electrode layers to control the orientation of the spherical particles.

A thin film transistor 581 sealed between the substrate 580 and the substrate 596 is a bottom-gate thin film transistor, and is in contact with the first electrode layer 587 and an opening formed in the insulating layer 585 with a source electrode layer or a drain electrode layer. Are electrically connected. Between the first electrode layer 587 and the second electrode layer 588, spherical particles 589 including a cavity 594 having a black region 590a and a white region 590b and being filled with a liquid are provided. The periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 16). In this embodiment mode, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581. In addition, with the use of the common connection portion, the second electrode layer 588 and the common potential line can be electrically connected to each other through conductive particles disposed between the pair of substrates.

Further, instead of the twisting ball, an electrophoretic element can be used. A microcapsule having a diameter of about 10 μm or more and 200 μm or less in which transparent liquid, positively charged white fine particles, and negatively charged black fine particles are enclosed is used. In the microcapsule provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white particles and the black particles are opposite to each other. Move in the direction and can display white or black. A display element using this principle is an electrophoretic display element, and is generally called electronic paper. Since the electrophoretic display element has higher reflectance than the liquid crystal display element, an auxiliary light is unnecessary, power consumption is small, and the display portion can be recognized even in a dim place. Further, even when power is not supplied to the display portion, an image once displayed can be held; therefore, a semiconductor device with a display function from a radio wave source (simply a display device or a semiconductor having a display device) Even when the device is also moved away, the displayed image can be stored.

Through the above steps, highly reliable electronic paper as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, an example of a light-emitting display device is described as a semiconductor device to which the thin film transistor described in any of Embodiments 1 and 2 is applied. As a display element included in the display device, a light-emitting element utilizing electroluminescence is used here. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIG. 17 illustrates an example of a pixel structure to which digital time grayscale driving can be applied as an example of a semiconductor device to which the present invention is applied.

A structure and operation of a pixel to which digital time gray scale driving can be applied will be described. Here, two oxide semiconductor layers (In—Ga—Zn—O-based films) described in Embodiments 1 and 2 are used for one pixel as n-channel transistors used for a channel formation region. Show.

The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. The switching transistor 6401 has a gate connected to the scanning line 6406, a first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) connected to the driving transistor. 6402 is connected to the gate. The driving transistor 6402 has a gate connected to the power supply line 6407 through the capacitor 6403, a first electrode connected to the power supply line 6407, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 6404. ing. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed over the same substrate.

Note that a low power supply potential is set for the second electrode (the common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential satisfying the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 6407. For example, GND, 0V, or the like is set as the low power supply potential. May be. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 and a current is caused to flow through the light emitting element 6404 so that the light emitting element 6404 emits light. Each potential is set to be equal to or higher than the forward threshold voltage. Hereinafter, the forward voltage refers to a voltage in a case where desired luminance is obtained.

Further, the capacitor 6403 can be omitted by using the gate capacitance of the driving transistor 6402 instead. As for the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

In the case of the voltage input voltage driving method, a video signal is input to the gate of the driving transistor 6402 so that the driving transistor 6402 is sufficiently turned on or off. That is, the driving transistor 6402 is operated in a linear region. Since the driving transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

Further, in the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel configuration as that in FIG. 17 can be used by changing signal input.

In the case of performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 includes at least a forward threshold voltage. Note that when a video signal that causes the driving transistor 6402 to operate in a saturation region is input, a current can flow through the light-emitting element 6404. In order to operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can be supplied to the light-emitting element 6404 to perform analog gradation driving.

Note that the pixel structure illustrated in FIG. 17 is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

Next, the structure of the light-emitting element is described with reference to FIG. Here, the cross-sectional structure of the pixel will be described with an example in which the driving TFT is an n-type. TFTs 7011, 7021, and 7001 which are driving TFTs used in the semiconductor devices in FIGS. 18A, 18B, and 18C can be manufactured in a manner similar to the thin film transistors described in Embodiments 1 and 2, and In—Ga— It is a highly reliable thin film transistor including a Zn—O-based film as an oxide semiconductor layer.

In order to extract light from the light-emitting element, at least one of the anode and the cathode may be transparent. Then, a thin film transistor and a light emitting element are formed on the substrate, and a top emission that extracts light from the surface opposite to the substrate, a bottom emission that extracts light from the surface on the substrate side, and a surface opposite to the substrate side and the substrate The pixel structure of one embodiment of the present invention can be applied to any light-emitting element having an emission structure.

A light-emitting element having a bottom emission structure will be described with reference to FIG.

A cross-sectional view of a pixel in the case where the driving TFT 7011 is n-type and light emitted from the light-emitting element 7012 is emitted to the first electrode 7013 side is shown. In FIG. 18A, the first electrode 7013 of the light-emitting element 7012 is formed over the light-transmitting conductive film 7017 electrically connected to the drain electrode layer of the driving TFT 7011. An EL layer 7014 and a second electrode 7015 are stacked over the electrode 7013 in this order.

As the light-transmitting conductive film 7017, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, A light-transmitting conductive conductive film such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

In addition, various materials can be used for the first electrode 7013 of the light-emitting element. For example, when the first electrode 7013 is used as a cathode, a material having a low work function, specifically, an alkali metal such as Li or Cs, and an alkaline earth metal such as Mg, Ca, or Sr, and In addition to alloys containing these (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferred. In FIG. 18A, the thickness of the first electrode 7013 is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the first electrode 7013.

Note that after the light-transmitting conductive film and the aluminum film are stacked, the light-transmitting conductive film 7017 and the first electrode 7013 may be formed by selective etching. Since it can etch using a mask, it is preferable.

In addition, the periphery of the first electrode 7013 is covered with a partition wall 7019. A partition 7019 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7019 is formed using an especially photosensitive resin material so that an opening is formed over the first electrode 7013 and the side wall of the opening has an inclined surface formed with a continuous curvature. Is preferred. In the case where a photosensitive resin material is used for the partition 7019, a step of forming a resist mask can be omitted.

In addition, the EL layer 7014 formed over the first electrode 7013 and the partition wall 7019 may include at least a light-emitting layer, and may be formed using a single layer or a plurality of layers. Can be either. In the case where the EL layer 7014 includes a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order over the first electrode 7013 functioning as a cathode. Of these, it is not necessary to provide all layers other than the light emitting layer.

The first electrode 7013 functions as an anode, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer are stacked in this order on the first electrode 7013. Also good. However, when comparing power consumption, the first electrode 7013 functions as a cathode, and the electron injection layer, the electron transport layer, the light-emitting layer, the hole transport layer, and the hole injection layer are stacked in this order on the first electrode 7013. This is preferable because it is possible to suppress an increase in voltage of the drive circuit portion and reduce power consumption.

For the second electrode 7015 formed over the EL layer 7014, various materials can be used. For example, when the second electrode 7015 is used as an anode, a material having a high work function, such as ZrN, Ti, W, Ni, Pt, or Cr, or a transparent conductive material such as ITO, IZO, or ZnO is preferable. Further, a shielding film 7016 such as a metal that blocks light, a metal that reflects light, or the like is used over the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015 and a Ti film is used as the shielding film 7016.

A region where the EL layer 7014 including the light-emitting layer is sandwiched between the first electrode 7013 and the second electrode 7015 corresponds to the light-emitting element 7012. In the case of the element structure illustrated in FIG. 18A, light emitted from the light-emitting element 7012 is emitted to the first electrode 7013 side as indicated by an arrow.

Note that in FIG. 18A, light emitted from the light-emitting element 7012 passes through the color filter layer 7033 and is emitted through the insulating layer 7032, the oxide film insulating layer 7031, the gate insulating layer 7030, and the substrate 7010. .

The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7033 is covered with an overcoat layer 7034 and further covered with a protective insulating layer 7035. Note that although the overcoat layer 7034 is illustrated with a thin film thickness in FIG. 18A, the overcoat layer 7034 uses a resin material such as an acrylic resin and has a function of flattening unevenness caused by the color filter layer 7033. Have.

In addition, the contact hole reaching the drain electrode layer is disposed so as to overlap with the partition wall 7019.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG.

In FIG. 18B, the first electrode 7023 of the light-emitting element 7022 is formed over the light-transmitting conductive film 7027 which is electrically connected to the drain electrode layer of the driver TFT 7021. An EL layer 7024 and a second electrode 7025 are sequentially stacked over the electrode 7023.

As the light-transmitting conductive film 7027, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, A light-transmitting conductive conductive film such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

The first electrode 7023 can be formed using various materials. For example, when the first electrode 7023 is used as a cathode, a material having a low work function, specifically, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, and these are used. In addition to alloys (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and the thickness thereof is set so as to transmit light (preferably, 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode.

Note that after the light-transmitting conductive film and the aluminum film are stacked, the light-transmitting conductive film 7027 and the first electrode 7023 may be selectively etched to form the same. Etching can be performed using a mask, which is preferable.

In addition, the peripheral edge portion of the first electrode 7023 is covered with a partition wall 7029. A partition 7029 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7029 is preferably formed using a photosensitive resin material so that an opening is formed on the electrode 7023 and the side wall of the opening has an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, a step of forming a resist mask can be omitted.

In addition, the EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 may include a light-emitting layer, and may be a single layer or a stack of a plurality of layers. both are fine. In the case where the EL layer 7024 includes a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order over the first electrode 7023 functioning as a cathode. Of these, it is not necessary to provide all layers other than the light emitting layer.

The first electrode 7023 may be used as an anode, and a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer may be stacked in that order on the anode. However, when power consumption is compared, power consumption is lower when the first electrode 7023 is used as the cathode and the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are stacked in this order on the cathode. ,preferable.

For the second electrode 7025 formed over the EL layer 7024, various materials can be used. For example, in the case where the second electrode 7025 is used as an anode, a material having a high work function, for example, a transparent conductive material such as ITO, IZO, or ZnO is preferably used. In this embodiment, an ITO film containing silicon oxide is formed using the second electrode 7025 as an anode.

A region where the EL layer 7024 including the light-emitting layer is sandwiched between the first electrode 7023 and the second electrode 7025 corresponds to the light-emitting element 7022. In the case of the element structure illustrated in FIG. 18B, light emitted from the light-emitting element 7022 is emitted to both the second electrode 7025 side and the first electrode 7023 side as indicated by arrows.

Note that in FIG. 18B, one light emitted from the light-emitting element 7022 to the first electrode 7023 side passes through the color filter layer 7043, and the insulating layer 7042, the oxide film insulating layer 7041, the gate insulating layer 7040, And the substrate 7020 is ejected.

The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7043 is covered with an overcoat layer 7044 and further covered with a protective insulating layer 7045.

In addition, the contact hole reaching the drain electrode layer is disposed so as to overlap with the partition wall 7029.

However, in the case where a light emitting element having a dual emission structure is used and both display surfaces are displayed in full color, light from the second electrode 7025 side does not pass through the color filter layer 7043; A substrate is preferably provided above the second electrode 7025.

Next, a light-emitting element having a top emission structure will be described with reference to FIG.

FIG. 18C is a cross-sectional view of a pixel in the case where the driving TFT 7001 is n-type and light emitted from the light-emitting element 7002 is emitted to the second electrode 7005 side. In FIG. 18C, the first electrode 7003 of the light-emitting element 7002 electrically connected to the drain electrode layer of the driving TFT 7001 is formed, and the EL layer 7004 and the second electrode 7003 are formed over the first electrode 7003. Electrodes 7005 are sequentially stacked.

The first electrode 7003 can be formed using various materials. For example, when the first electrode 7003 is used as a cathode, a material having a low work function, specifically, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, and these are used. In addition to alloys (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferred.

In addition, the periphery of the first electrode 7003 is covered with a partition 7009. A partition 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7009 is formed using an especially photosensitive resin material so that an opening is formed over the first electrode 7003 and the side wall of the opening has an inclined surface formed with a continuous curvature. Is preferred. In the case where a photosensitive resin material is used for the partition 7009, a step of forming a resist mask can be omitted.

In addition, the EL layer 7004 formed over the first electrode 7003 and the partition wall 7009 only needs to include at least a light-emitting layer, and even though it is formed of a single layer, a plurality of layers are stacked. Can be either. In the case where the EL layer 7004 includes a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order over the first electrode 7003 used as the cathode. Of these, it is not necessary to provide all layers other than the light emitting layer.

The order of stacking is not limited, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order over the first electrode 7003 used as the anode.

In FIG. 18C, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked in this order on a stacked film in which a Ti film, an aluminum film, and a Ti film are stacked in this order, and Mg is formed thereon. : A laminate of an Ag alloy thin film and ITO is formed.

However, in the case where the driving TFT 7001 is an n-type, it is more preferable to stack an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer in this order on the first electrode 7003 in order to suppress a voltage increase in the driver circuit. This is preferable because power consumption can be reduced.

The second electrode 7005 is formed using a light-transmitting conductive material, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium oxide containing titanium oxide. Alternatively, a light-transmitting conductive conductive film such as indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide added with silicon oxide may be used.

A region where the EL layer 7004 including the light-emitting layer is sandwiched between the first electrode 7003 and the second electrode 7005 corresponds to the light-emitting element 7002. In the case illustrated in FIG. 18C, light emitted from the light-emitting element 7002 is emitted to the second electrode 7005 side as indicated by an arrow.

In FIG. 18C, the drain electrode layer of the driving TFT 7001 is electrically connected to the first electrode 7003 through contact holes provided in the oxide film insulating layer 7051, the protective insulating layer 7052, and the insulating layer 7055. Connecting. The planarization insulating layer 7053 can be formed using a resin material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the resin material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed using these materials. There is no particular limitation on the formation method of the planarization insulating layer 7053, and a sputtering method, an SOG method, spin coating, dip coating, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, or the like) is used depending on the material. A doctor knife, a roll coater, a curtain coater, a knife coater, or the like can be used.

The partition 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7009 is formed using an especially photosensitive resin material so that an opening is formed over the first electrode 7003 and the side wall of the opening has an inclined surface formed with a continuous curvature. Is preferred. In the case where a photosensitive resin material is used for the partition 7009, a step of forming a resist mask can be omitted.

In the structure of FIG. 18C, when full-color display is performed, for example, the light-emitting element 7002 is a green light-emitting element, one adjacent light-emitting element is a red light-emitting element, and the other light-emitting element is a blue light-emitting element. To do. Alternatively, a light-emitting display device capable of full color display may be manufactured using not only three types of light-emitting elements but also four types of light-emitting elements including white elements.

In the structure of FIG. 18C, a light-emitting display capable of full-color display is provided in which a plurality of light-emitting elements to be arranged are all white light-emitting elements and a sealing substrate having a color filter or the like is provided above the light-emitting elements 7002. A device may be made. A full-color display can be performed by forming a material that emits monochromatic light such as white and combining a color filter and a color conversion layer.

Of course, monochromatic light emission may be displayed. For example, a lighting device may be formed using white light emission, or an area color type light emitting device may be formed using monochromatic light emission.

If necessary, an optical film such as a polarizing film such as a circularly polarizing plate may be provided.

Note that although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that although the thin film transistor (driving TFT 7001) for controlling the driving of the light emitting element is electrically connected to the light emitting element 7002, the current controlling TFT is connected between the driving TFT 7001 and the light emitting element 7002. It may be configured.

Note that the semiconductor device described in this embodiment is not limited to the structure illustrated in FIG. 18 and can be modified in various ways based on the technical idea of the present invention.

Next, an external view and a cross-sectional view of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one mode of a semiconductor device to which the thin film transistor described in any of Embodiments 1 and 2 is applied will be described with reference to FIGS. FIG. 19A is a top view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed with a sealant between the second substrate and FIG. 19B. FIG. 19A corresponds to a cross-sectional view taken along line HI in FIG.

A sealant 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b which are provided over the first substrate 4501. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b provided over the first substrate 4501 include a plurality of thin film transistors. In FIG. A thin film transistor 4510 included in the portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated.

As the thin film transistors 4509 and 4510, the highly reliable thin film transistor described in Embodiments 1 and 2 including an In—Ga—Zn—O-based film as an oxide semiconductor layer can be used. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

A conductive layer 4540 is provided over the insulating layer 4544 so as to overlap with a channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driver circuit. By providing the conductive layer 4540 so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. In addition, the potential of the conductive layer 4540 may be the same as or different from that of the gate electrode layer of the thin film transistor 4509, and can function as a second gate electrode layer. Further, the potential of the conductive layer 4540 may be GND, 0 V, or a floating state.

A first electrode layer 4517 that is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513; however, the structure is not limited to the structure described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4511 or the like.

A partition 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is preferably used so that an opening is formed over the first electrode layer 4517 and the side wall of the opening has an inclined surface formed with a continuous curvature.

The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503a and 4503b, the scan line driver circuits 4504a and 4504b, or the pixel portion 4502 from FPCs 4518a and 4518b.

In this embodiment, the connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511. The terminal electrode 4516 includes source and drain electrode layers included in the thin film transistors 4509 and 4510. It is formed from the same conductive film.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518a through an anisotropic conductive film 4519.

For the substrate positioned in the direction in which light is extracted from the light-emitting element 4511, the second substrate must be light-transmitting. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

In addition to inert gas such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as a filler.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

The signal line driver circuits 4503a and 4503b and the scan line driver circuits 4504a and 4504b may be mounted with a driver circuit formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a separately prepared substrate. Further, only the signal line driver circuit, or a part thereof, or only the scanning line driver circuit or only part thereof may be separately formed and mounted, and this embodiment mode is not limited to the structure in FIG.

Through the above process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 7)
The semiconductor device to which the thin film transistor described in any of Embodiments 1 and 2 is applied can be used as electronic paper. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, the electronic paper can be applied to an electronic book (electronic book), a poster, an advertisement in a vehicle such as a train, and a display on various cards such as a credit card. Examples of electronic devices are illustrated in FIGS.

FIG. 20A illustrates a poster 2631 made of electronic paper. When the advertisement medium is a printed matter of paper, the advertisement is exchanged manually. However, if electronic paper is used, the display of the advertisement can be changed in a short time. In addition, a stable image can be obtained without losing the display. Note that the poster may be configured to transmit and receive information wirelessly.

FIG. 20B illustrates an advertisement 2632 in a vehicle such as a train. When the advertisement medium is a printed matter of paper, the advertisement is exchanged manually. However, if electronic paper is used, the display of the advertisement can be changed in a short time without much labor. In addition, a stable image can be obtained without distorting the display. The in-vehicle advertisement may be configured to transmit and receive information wirelessly.

FIG. 21 illustrates an example of an e-book reader 2700. For example, the electronic book 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated with a shaft portion 2711 and can be opened / closed using the shaft portion 2711 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, a sentence can be displayed on the right display unit (display unit 2705 in FIG. 21) and an image can be displayed on the left display unit (display unit 2707 in FIG. 21). .

FIG. 21 illustrates an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation keys 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the e-book reader 2700 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 2700 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 8)
The semiconductor device including the thin film transistor described in any of Embodiments 1 and 2 can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines.

FIG. 22A illustrates an example of a television device 9600. In the television device 9600, a display portion 9603 is incorporated in a housing 9601. Images can be displayed on the display portion 9603. Here, a structure in which the housing 9601 is supported by a stand 9605 is illustrated.

The television device 9600 can be operated with an operation switch provided in the housing 9601 or a separate remote controller 9610. Channels and volume can be operated with operation keys 9609 provided in the remote controller 9610, and an image displayed on the display portion 9603 can be operated. The remote controller 9610 may be provided with a display portion 9607 for displaying information output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

FIG. 22B illustrates an example of a digital photo frame 9700. For example, a digital photo frame 9700 has a display portion 9703 incorporated in a housing 9701. The display portion 9703 can display various images. For example, by displaying image data captured by a digital camera or the like, the display portion 9703 can function in the same manner as a normal photo frame.

Note that the digital photo frame 9700 includes an operation portion, an external connection terminal (a terminal that can be connected to various types of cables such as a USB terminal and a USB cable), a recording medium insertion portion, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory storing image data captured by a digital camera can be inserted into the recording medium insertion portion of the digital photo frame to capture the image data, and the captured image data can be displayed on the display portion 9703.

Further, the digital photo frame 9700 may be configured to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

FIG. 23A illustrates a portable game machine including two housings, a housing 9881 and a housing 9891, which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine shown in FIG. 23A includes a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (force, displacement, position). , Speed, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 9889) and the like. Needless to say, the structure of the portable game machine is not limited to that described above, and may be any structure as long as it includes at least the semiconductor device according to one embodiment of the present invention, and can be provided with any other appropriate facilities. . The portable game machine shown in FIG. 23A reads out a program or data recorded in a recording medium and displays the program or data on a display unit, or performs wireless communication with another portable game machine to share information. It has a function. Note that the function of the portable game machine illustrated in FIG. 23A is not limited to this, and the portable game machine can have a variety of functions.

FIG. 23B illustrates an example of a slot machine 9900 which is a large-sized game machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 includes operation means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Needless to say, the structure of the slot machine 9900 is not limited to the above structure, and may be any structure as long as it includes at least the semiconductor device according to one embodiment of the present invention, and can have other attached facilities as appropriate.

FIG. 24A illustrates an example of a mobile phone 1000. A cellular phone 1000 includes a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

Information can be input to the cellular phone 1000 illustrated in FIG. 24A by touching the display portion 1002 with a finger or the like. In addition, operations such as making a call or typing an e-mail can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying images. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

For example, when making a phone call or creating an e-mail, the display unit 1002 may be set to a character input mode mainly for inputting characters and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display portion 1002.

Further, by providing a detection device having a sensor for detecting the inclination, such as a gyroscope or an acceleration sensor, in the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 is determined, and the screen display of the display unit 1002 Can be switched automatically.

The screen mode is switched by touching the display portion 1002 or operating the operation button 1003 of the housing 1001. Further, switching can be performed depending on the type of image displayed on the display portion 1002. For example, if the image signal to be displayed on the display unit is moving image data, the mode is switched to the display mode, and if it is text data, the mode is switched to the input mode.

Further, in the input mode, when a signal detected by the optical sensor of the display unit 1002 is detected and there is no input by a touch operation on the display unit 1002, the screen mode is switched from the input mode to the display mode. You may control.

The display portion 1002 can also function as an image sensor. For example, by touching the display unit 1002 with a palm or a finger, a palm print, a fingerprint, or the like can be imaged to perform personal authentication. In addition, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

FIG. 24B is also an example of a mobile phone. A mobile phone in FIG. 24B includes a housing 9411, a display device 9410 including a display portion 9412 and operation buttons 9413, an operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and the like. And a communication device 9400 including a light emitting portion 9406 that emits light when an incoming call is received. A display device 9410 having a display function can be attached to and detached from the communication device 9400 having a telephone function in two directions indicated by arrows. Therefore, the short axes of the display device 9410 and the communication device 9400 can be attached, or the long axes of the display device 9410 and the communication device 9400 can be attached. When only the display function is required, the display device 9410 can be detached from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each have a rechargeable battery.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

DESCRIPTION OF SYMBOLS 10 Pulse output circuit 11 1st wiring 12 2nd wiring 13 3rd wiring 14 4th wiring 15 5th wiring 21 1st input terminal 22 2nd input terminal 23 3rd input terminal 24 4th Input terminal 25 fifth input terminal 26 first output terminal 27 second output terminal 28 thin film transistor 31 first transistor 32 second transistor 33 third transistor 34 fourth transistor 35 fifth transistor 36 6 transistor 37 7th transistor 38 8th transistor 39 9th transistor 40 10th transistor 41 11th transistor 42 12th transistor 43 13th transistor 51 power supply line 52 power supply line 53 power supply line 61 period 62 Period 100 Substrate 101a Mask 101b Mask 101c Mask 102 Gate electrode Layer 103 capacitor wiring 104 first terminal 105 gate insulating layer 105a gate insulating layer 105b gate insulating layer 106 oxide semiconductor film 107 mask 108 oxide semiconductor layer 109 contact hole 110a mask 110b mask 110c mask 110d mask 111 second terminal 112 Source electrode layer 113 Drain electrode layer 114 Connection electrode 115 Contact 116 Protective insulating layer 116a Protective insulating layer 116b Protective insulating layer 117 Contact hole 118 Contact hole 119 Contact hole 120 Transparent conductive film 121 Pixel electrode layer 122 Transparent conductive film 150 Thin film transistor 151 First Terminal 152 gate insulating layer 153 connection electrode 154 protective insulating layer 155 transparent conductive film 156 electrode 160 thin film transistor 180 second terminal 191 pixel portion 192 Capacitor portion 193 First terminal portion 194 Second terminal portion 202 Gate electrode layer 203 Capacitor wiring 204 First terminal 212 Source electrode layer 213 Drain electrode layer 222 Source electrode layer 223 Drain electrode layer 231 Capacitance electrode layer 234 Flattening insulation Layer 235 Second terminal electrode 236 First metal wiring layer 237 Second metal wiring layer 238 Gate wiring layer 241 First metal wiring layer 242 Second metal wiring layer 300 Source wiring 302 Gate electrode layer 308 Oxide semiconductor Layer 320 Back gate electrode layer 580 Substrate 581 Thin film transistor 585 Insulating layer 587 First electrode layer 588 Second electrode layer 589 Spherical particle 590a Black region 590b White region 594 Cavity 595 Filler 596 Substrate 1000 Mobile phone 1001 Housing 1002 Display portion 1003 Operation button 1004 Outside Connection port 1005 Speaker 1006 Microphone 1400 Substrate 1403 Droplet ejection unit 1404 Imaging unit 1405 Head 1406 Dotted line 1407 Control unit 1408 Storage medium 1409 Image processing unit 1410 Computer 1411 Marker 1412 Head 1413 Material supply source 1414 Material supply source 2600 TFT substrate 2601 Counter substrate 2602 Sealing material 2603 Pixel portion 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit portion 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflecting plate 2612 Circuit board 2613 Diffusion plate 2631 Poster 2632 In-car advertisement 2700 Electronic book 2701 Case 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft unit 2721 Power supply 2723 Operation key 2725 Speaker 4 01 first substrate 4002 pixel portion 4003 signal line driver circuit 4004 scanning line driver circuit 4005 sealant 4006 second substrate 4008 liquid crystal layer 4010 thin film transistors 4011 TFT 4013 liquid crystal element 4015 connection terminal electrode 4016 terminal electrodes 4018 FPC
4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4040 Conductive layer 4501 First substrate 4502 Pixel portion 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scan line driver circuit 4504b Scan line driver circuit 4505 Seal material 4506 Second substrate 4507 Filler 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Second electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 First electrode layer 4518a FPC
4518b FPC
4519 Anisotropic conductive film 4520 Partition wall 4540 Conductive layer 4544 Insulating layer 5300 Substrate 5301 Pixel portion 5302 First scan line driver circuit 5303 Second scan line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 6400 Pixel 6401 Switching transistor 6402 Driving transistor 6403 Capacitance element 6404 Light emitting element 6405 Signal line 6406 Scanning line 6407 Power supply line 6408 Common electrode 7001 Driving TFT
7002 Light-emitting element 7003 First electrode 7004 EL layer 7005 Second electrode 7009 Partition 7051 Oxide insulating layer 7052 Protective insulating layer 7053 Planarizing insulating layer 7055 Insulating layer 7010 Substrate 7011 Driving TFT
7012 Light-emitting element 7013 First electrode 7014 EL layer 7015 Second electrode 7016 Shielding film 7017 Conductive film 7019 Partition 7020 Substrate 7021 Driving TFT
7022 Light-emitting element 7023 First electrode 7024 EL layer 7025 Second electrode 7027 Conductive film 7029 Partition wall 7030 Gate insulating layer 7031 Oxide insulating layer 7032 Insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulating layer 7040 Gate insulating layer 7041 Oxide insulating layer 7042 Insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulating layer 9400 Communication device 9401 Case 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting unit 9410 Display unit 9411 Case 9412 Display unit 9413 Operation Button 9600 Television apparatus 9601 Housing 9603 Display portion 9605 Stand 9607 Display portion 9609 Operation key 9610 Remote control operation device 9700 Digital photo Frame 9701 Case 9703 Display unit 9881 Case 9882 Display unit 9883 Display unit 9984 Speaker unit 9886 Operation key 9886 Recording medium insertion unit 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Case 9893 Connection unit 9900 Slot machine 9901 Case 9903 Display section

Claims (3)

Forming a first conductive layer over a substrate having an insulating surface;
Forming a first mask on the first conductive layer using a droplet discharge method;
Etching the first conductive layer using the first mask to form a Gate electrode layer,
Forming a gate insulating layer before Kige over gate electrode layer,
Perform reverse sputtering on the surface of the gate insulating layer,
After the reverse sputtering treatment, an oxide semiconductor layer is formed on the gate insulating layer using a pulsed DC power source ,
Dehydrating or dehydrogenating the oxide semiconductor layer;
A second mask is formed over the dehydrated or dehydrogenated oxide semiconductor layer by a droplet discharge method,
The oxide semiconductor layer is etched using the second mask to form an island-shaped oxide semiconductor layer,
Forming a second conductive layer on the island-shaped oxide semiconductor layer;
Forming a third mask on the second conductive layer by a droplet discharge method;
Etching the second conductive layer using the third mask, to form a source over scan electrode layer及beauty drain electrode layer,
Before Kige over gate insulating layer, said island-shaped oxide semiconductor layer, before Kiso over source electrode layer, and before Kido drain electrode layer, a portion of the island-shaped oxide semiconductor layer Forming a protective insulating layer in contact,
Said protective insulating layer, before Kiso over source electrode layer or before Kido drain electrode layer and is electrically connected to the pixel electrode layer having a light-transmitting property, a display device, and forming by printing Manufacturing method. In claim 1,
After performing the dehydration or the dehydrogenation,
A manufacturing method of a display device, characterized in that the oxide semiconductor layer is cooled in an atmosphere containing oxygen without being exposed to the air. In claim 1 or claim 2,
Having a capacitor on the substrate;
The capacitor section includes a capacitor wiring, and a capacitor electrode having a region overlapping with the capacitor wiring,
For the capacitor wiring, in the step of forming the gate electrode layer, a fourth mask is formed on the first conductive layer by a droplet discharge method, and the first mask is used by using the fourth mask. Formed by etching the conductive layer,
A partial region of the pixel electrode layer formed by the printing method is used as the capacitive electrode,
The capacitor wiring and the capacitor electrode, a method for manufacturing a display device characterized by having a light-transmitting property.

Images