JP2009169111A - Display driving circuit, display, and display driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce signal lines between a display control circuit and a driving circuit, to save thereby a space in an area other than a display panel, and to reduce cost. <P>SOLUTION: This display driving circuit or the like includes a gate driver 30 for driving a gate line 12, and a source driver 20 for driving a source line, the source driver 20 generates a vertical synchronization signal Vsync, based on a horizontal synchronization signal Hsync input into the source driver 20 and an image signal Data serving as a source of a data signal, to be output to the gate driver 30, and the gate driver 30 drives a gate bus line 12, based on the vertical synchronization signal Vsync generated by the source driver 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention includes a scanning signal line, a switching element turned on / off by the scanning signal line, and a pixel electrode connected to one end of the switching element, such as an active matrix liquid crystal display panel. The present invention relates to a display driving circuit and a display driving method for driving a display panel including a plurality of rows to be operated and a data signal line connected to the other end of the switching element of each row.

  Liquid crystal display devices using TFTs (Thin Film Transistors) are widely used in personal computers, mobile phones, and televisions as thin, lightweight, low power consumption display devices that can display high-quality images. Yes. Such a liquid crystal display device is usually formed by sealing liquid crystal between an array substrate on which TFT elements are arranged and a counter substrate on which counter electrodes are arranged. This liquid crystal display device is disclosed in Patent Document 1, for example. Taking the disclosed contents of Patent Document 1 as an example, the configuration of a conventional liquid crystal display device will be described as follows.

  FIG. 8 is a block diagram showing a schematic configuration of a conventional liquid crystal display device. This liquid crystal display device controls a source driver 300 as a data signal line driving circuit, a gate driver 400 as a scanning signal line driving circuit, an active matrix type liquid crystal display panel 100, a source driver 300 and a gate driver 400. Display control circuit 200.

  The liquid crystal display panel 100 in the liquid crystal display device includes a gate line GL as a plurality of scanning signal lines, a source line SL as a plurality of data signal lines intersecting with each of the gate lines GL, and gates thereof. A plurality of pixel formation portions (not shown) provided corresponding to the intersections of the line GL and the source line SL are included.

  These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion has a gate terminal connected to a gate line GL passing through a corresponding intersection and a source line SL passing through the intersection. TFT (not shown) which is a switching element having a source terminal connected to the pixel, a pixel electrode connected to the drain terminal of the TFT, and a common electrode which is an electrode provided in common to the plurality of pixel formation portions And a liquid crystal layer (not shown) provided in common between the plurality of pixel formation portions and disposed between the pixel electrode and the common electrode.

  The display control circuit 200 includes a horizontal scanning clock generation circuit 210 and a vertical scanning clock generation circuit 220. The horizontal scanning clock generation circuit 210 generates a source start pulse HS and a source clock signal HCLK based on a horizontal synchronization signal HSYNC input from the outside, and outputs it to the source driver 300. The vertical scanning clock generation circuit 220 generates a gate start pulse VS and a gate clock signal VCLK based on a vertical synchronization signal VSYNC input from the outside, and outputs it to the gate driver 400.

  The source driver 300 operates a built-in shift register or the like at the rising timing of the source start pulse HS to sample and hold the video signal based on the source clock signal HCLK, and the sample driver at the falling timing of the source start pulse HS. The held video signal is output to each source line SL.

  The gate driver 400 operates a built-in shift register or the like at the rising timing of the gate start pulse VS, and sequentially sets the scanning voltage application standby state to each scanning electrode at the rising timing of the gate clock signal VCLK. The scanning voltage in the application standby state is applied at the falling timing of the source start pulse HS.

As described above, in the conventional liquid crystal display device, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are input from the outside, and the signals corresponding to the synchronization signals (source start pulse HS, source clock signal HCLK, gate start pulse VS). And the gate clock signal VCLK) are input to the source driver and the gate driver, respectively, to drive the liquid crystal display panel.
Japanese Patent Laid-Open No. 6-18843 (published January 28, 1994)

  Here, while recent liquid crystal display devices are required to increase the size of the display panel, the entire device is required to be lighter and thinner, and various components are required to meet these requirements. Improvements are being attempted. In addition, cost reduction must be taken into consideration when making improvements. Under such circumstances, in the present invention, as one method for reducing the weight and thickness of the entire device and further reducing the cost while increasing the size of the display panel, signal lines arranged around the drive circuit are provided. Focused on improving. The number of signal lines arranged around the drive circuit increases with an increase in the size of the display panel, leading to an increase in cost and occupies a large area in the entire apparatus. Therefore, it has been noted that the above requirements can be satisfied by improving the arrangement of the signal lines.

  Therefore, as a result of verifying the signal lines that particularly affect the enlargement of the apparatus among the plurality of signal lines, the display control circuit is connected to the drive circuit via, for example, an FPC (flexible printed circuit board) or a long-distance signal line. When the distance between the display control circuit and the drive circuit is large due to the structure of the liquid crystal display device, the signal lines arranged between the display control circuit and the source driver and gate driver are It has been found that it has a great influence on the enlargement of the device. That is, due to the structure of the liquid crystal display device, in particular, when the distance between the display control circuit and the drive circuit is long, the signal line provided between them becomes long, and the length of the signal line increases in many areas in the entire device. Was found to have occupied.

  The present invention has been made in view of the above problems, and its object is to reduce the number of signal lines between the display control circuit and the drive circuit, thereby saving space in areas other than the display panel and reducing the cost. It is an object of the present invention to provide a display driving circuit and a display driving method that can be reduced.

  In order to solve the above problems, a display drive circuit according to the present invention includes a scan signal line drive circuit that drives a scan signal line and a data signal line drive circuit that drives a data signal line. At least one of the signal line drive circuit and the data signal line drive circuit drives a corresponding signal line using a signal output from the other.

  In the display drive circuit, the data signal line drive circuit generates a signal for driving the scan signal line based on a signal input to the data signal line drive circuit, and the scan signal line drive It is preferable that the scanning signal line driving circuit drive the scanning signal line based on a signal generated in the data signal line driving circuit.

Further, in the display driving circuit, the scanning signal line driving circuit outputs a scanning signal for turning on the switching element of the row in a horizontal scanning period sequentially assigned to each row,
The data signal line driving circuit outputs a data signal corresponding to an image to be displayed based on a horizontal synchronization signal, and the data signal line driving circuit is input to the data signal line driving circuit. A vertical synchronizing signal generating circuit that generates a vertical synchronizing signal based on a signal and a video signal that is a source of the data signal, and the scanning signal line driving circuit includes the vertical synchronizing signal generated by the vertical synchronizing signal generating circuit. It is desirable to output the scanning signal based on the synchronization signal.

  The display panel driven by the display driving circuit has the configuration as described above. A typical arrangement thereof is, for example, a large number of pixel electrodes arranged in a matrix, and scanning signal lines and switching along each row. Elements are arranged, and data signal lines are arranged along each column.

  The vertical synchronization signal and the horizontal synchronization signal are signals that define the scanning timing in each direction. Then, the display driving circuit turns on the switching element of the row in the horizontal scanning period sequentially assigned to each row by the scanning signal, and responds to the data signal with respect to the pixel electrode connected to the turned on switching element. Write the potential. Here, the data signal is a signal obtained by assigning each data signal line to a video signal input to the data signal line driving circuit and performing boosting or the like.

  In this typical arrangement, “row” and “column”, “horizontal” and “vertical” are often arranged in the horizontal direction and vertical direction of the display panel, respectively. No, the vertical and horizontal relationship may be reversed. Therefore, “row”, “column”, “horizontal” and “vertical” in the present invention do not particularly limit directions.

  In the case of such a display drive circuit, usually, as described in the column “Problems to be solved by the invention” above, when the distance between the display control circuit and the drive circuit is large due to the structure of the display device. The display control circuit that controls the drive circuit and the signal line that connects the drive circuit are long and occupy many areas in the display device.

  Therefore, in the display drive circuit, at least one of the scanning signal line drive circuit and the data signal line drive circuit uses a signal output from the other to drive the corresponding signal line. is there. For example, the scanning signal line driving circuit drives the scanning signal line based on a signal generated in the data signal line driving circuit. Specifically, a vertical synchronizing signal that has been input directly from the display control circuit to the scanning signal line driving circuit in the past is converted into a horizontal synchronizing signal and data that are input to the data signal line driving circuit in the data signal line driving circuit. The scanning signal line driving circuit generates a scanning signal based on the generated vertical synchronization signal.

  Accordingly, the scanning signal line driving circuit can directly receive the generated vertical synchronization signal from, for example, the data signal line driving circuit. That is, unlike the prior art, the scanning signal line drive circuit does not need to receive the vertical synchronization signal from the display control circuit. This eliminates the need for a signal line between the display control circuit and the scanning signal line driving circuit for transmitting the vertical synchronization signal. Thereby, as compared with the conventional configuration, there is an effect that the space can be saved in the area other than the display panel and the cost can be reduced.

  Note that a new signal line for transmitting a signal for driving the scanning signal line generated in the data signal line driving circuit from the data signal line driving circuit to the scanning signal line driving circuit is required. Since the circuits can be arranged close to each other, the new signal line hardly affects the area occupied by the signal line in the display device, and the influence on the cost is small. Therefore, the effect described above can be obtained because the effect obtained by reducing the signal lines between the display control circuit and the drive circuit is large.

  In the display driving circuit of the present invention, the data signal line driving circuit may drive the data signal line based on a signal generated in the scanning signal line driving circuit. Further, the display driving circuit may be configured such that each of the scanning signal line driving circuit and the data signal line driving circuit drives a corresponding signal line using a signal output from the other. Even in these configurations, the above-described effects can be obtained.

  In the display drive circuit according to the present invention, in the display drive circuit, the video signal is determined according to an effective data period including video data to be displayed and a potential of a vertical synchronization signal output from a signal source. It is desirable to include a discrimination signal period having any one of binary potentials.

  According to the above configuration, one of the binary potentials corresponding to the potential of the vertical synchronization signal is added to the video signal. For example, when the binary potential is an L level and an H level, a potential (L level or H level) corresponding to the potential of the vertical synchronization signal is added to the video signal. Thus, in the data signal line driving circuit to which the video signal is input, by detecting the potential level of the video signal, it is possible to generate a signal in accordance with the change in the potential of the vertical synchronization signal output from the signal source. it can.

  In the display drive circuit according to the present invention, in the display drive circuit, the vertical synchronization signal generation circuit includes a first input unit that inputs the video signal, a second input unit that inputs the horizontal synchronization signal, An output unit that outputs a signal generated based on the horizontal synchronization signal and the video signal as the vertical synchronization signal, and the potential level of the horizontal synchronization signal input to the second input unit is changed from a low level to a high level. It is desirable that the potential level of the video signal input to the first input unit when the level changes is output as the potential level of the vertical synchronization signal.

  The vertical synchronizing signal generation circuit is preferably composed of a D flip-flop circuit.

  Thereby, since a vertical synchronizing signal can be generated with a simple configuration, the above-described effects of space saving and cost reduction can be achieved.

  The display driving circuit according to the present invention further includes a display control circuit for controlling the scanning signal line driving circuit and the data signal line driving circuit in the display driving circuit, wherein the display control circuit is input from a signal source. Based on the vertical synchronization signal input from the signal source with respect to the signal that is the source of the video signal, the first in one frame of the blanking period in which the video is not displayed located at the boundary between the adjacent horizontal scanning periods The first potential level signal is input during the blanking period immediately before the horizontal scanning period, while the second potential level signal is input during the other blanking period in one frame. It is desirable to output a signal as the video signal.

  According to the above configuration, different potential levels are added to the blanking period immediately before the first horizontal scanning period of one frame and the other blanking periods in the video signal in the display device. be able to. In other words, a potential level corresponding to the potential of the vertical synchronization signal input from the signal source can be added to the video signal. Thus, in the data signal line driving circuit to which the video signal is input, by detecting the potential level of the video signal, it is possible to generate a signal in accordance with the change in the potential of the vertical synchronization signal output from the signal source. it can.

  In the display driving circuit according to the present invention, in the display driving circuit, the scanning signal line driving circuit preferably outputs the scanning signal based on a gate start pulse signal generated based on the vertical synchronization signal. .

  According to the above configuration, the operation of outputting the scanning signal in the scanning signal line driving circuit can be executed based on the gate start pulse signal generated from the vertical synchronization signal.

  In the display driving circuit according to the present invention, in the display driving circuit, the scanning signal line driving circuit generates a gate start pulse signal based on the vertical synchronization signal received from the data signal line driving circuit. It is desirable to further include a control unit.

  According to the above configuration, the scanning signal line driving circuit receives the vertical synchronization signal generated by the data signal line driving circuit, and generates the gate start pulse signal and outputs the scanning signal therein. be able to.

  The display driving circuit according to the present invention is the display driving circuit, wherein the data signal line driving circuit further includes a data signal line driving control unit that generates a gate start pulse signal based on the vertical synchronization signal. It is desirable to output a gate start pulse signal to the scanning signal line driving circuit.

  As described above, the gate start pulse signal is generated in the data signal line driving circuit based on the vertical synchronization signal generated by the data signal line driving circuit, and then input to the data signal line driving circuit. It may be.

  A display device according to the present invention includes any one of the display drive circuits described above and the display panel.

  With the above configuration, it is possible to provide a display device that can save space and reduce costs in a region other than the display panel by the display driving circuit.

  In order to solve the above problems, a display driving method according to the present invention includes a scanning signal line driving process for driving a scanning signal line and a data signal line driving process for driving a data signal line. At least one of the scanning signal line driving process and the data signal line driving process is characterized in that a corresponding signal line is driven using a signal output from the other.

  In the above method, as in the effect described with respect to the display driving circuit, it is possible to achieve an effect of saving space and reducing costs in an area other than the display panel.

  The display device according to the present invention is preferably a liquid crystal display device.

  As described above, in the display driving circuit according to the present invention, at least one of the scanning signal line driving circuit and the data signal line driving circuit uses a signal output from the other to correspond to the signal. It drives the line.

  In the display driving method according to the present invention, as described above, at least one of the scanning signal line driving process and the data signal line driving process uses a signal output from the other to correspond to the signal. It drives the line.

  According to the above configuration and method, signal lines between the display control circuit and the scanning signal line driving circuit can be reduced. Thereby, as compared with the conventional configuration, there is an effect that the space can be saved in the area other than the display panel and the cost can be reduced.

  An embodiment of the present invention will be described below with reference to FIGS.

  First, the configuration of the liquid crystal display device 1 corresponding to the display device of the present invention will be described with reference to FIGS. 1 is a block diagram showing the overall configuration of the liquid crystal display device 1, and FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the pixels of the liquid crystal display device 1.

  The liquid crystal display device 1 includes an active matrix liquid crystal display panel 10 corresponding to a display panel, a data signal line driving circuit, a scanning signal line driving circuit, and a display control circuit of the present invention, a source driver 20, a gate driver 30, and A control circuit 40 is provided.

  The liquid crystal display panel 10 is configured by sandwiching liquid crystal between an active matrix substrate (not shown) and a counter substrate, and has a large number of pixels P arranged in a matrix.

  The liquid crystal display panel 10 includes a source line 11, a gate line 12, a thin film transistor (Thin Film Transistor) corresponding to the data signal line, the scanning signal line, the switching element, and the pixel electrode of the present invention on the active matrix substrate. (Referred to as “TFT”) 13 and a pixel electrode 14 and a counter electrode 19 on a counter substrate. The TFT 13 is shown only in FIG. 2 and is omitted in FIG.

  One source line 11 is formed in each column so as to be parallel to each other in the column direction (vertical direction), and one gate line 12 is provided in each row so as to be parallel to each other in the row direction (lateral direction). It is formed one by one. The TFT 13 and the pixel electrode 14 are formed corresponding to the intersections of the source line 11 and the gate line 12, respectively. The source electrode s of the TFT 13 is on the source line 11, the gate electrode g is on the gate line 12, and the drain electrode is on. d is connected to each pixel electrode 14. In addition, a liquid crystal capacitor 17 is formed between the pixel electrode 14 and the counter electrode 19 via a liquid crystal.

  Thereby, the gate of the TFT 13 is turned on by the scanning signal supplied to the gate line 12, the data signal from the source line 11 is written to the pixel electrode 14, the pixel electrode 14 is set to a potential corresponding to the data signal, and the counter By applying a voltage according to the data signal to the liquid crystal interposed between the electrodes 19, gradation display according to the data signal can be realized.

  The liquid crystal display panel 10 having the above configuration is driven by a source driver 20, a gate driver 30, and a control circuit 40 for controlling them.

  In the present embodiment, in the active period (effective scanning period) in the vertical scanning period that is periodically repeated, the horizontal scanning period of each row is sequentially assigned, and each row is sequentially scanned.

  For this purpose, the gate driver 30 sequentially outputs a scanning signal for turning on the TFT 13 to the gate line 12 of the row in synchronization with the horizontal scanning period of each row based on the vertical synchronization signal.

  The source driver 20 outputs a data signal to each source line 11. For this data signal, a digital video signal (video signal Data described later) supplied from the outside of the liquid crystal display device 1 to the source driver 20 via the control circuit 40 is assigned to each column in the source driver 20 and subjected to boosting or the like. Signal.

  The control circuit 40 outputs a desired signal from each of these drive circuits by controlling the source driver 20 and the gate driver 30 described above. The control circuit 40 is connected away from the source driver 20 and the gate driver 30 via, for example, an FPC (flexible printed circuit board) or a long signal line.

  The present invention is characterized in the control circuit 40, the source driver 20, and the gate driver 30 in the liquid crystal display device 1 constituted by the above-described members, and details thereof will be described below.

  The control circuit 40 receives, from an external signal source, video data Dv representing video to be displayed, a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync corresponding to the video data Dv, and based on the signals Dv, Hsync, and Vsync, A digital video signal Data representing a video to be displayed (a signal corresponding to the video data Dv: hereinafter referred to as “video signal Data”) is generated and output to the source driver 20. Specifically, after the video data Dv output from the signal source is subjected to timing adjustment as necessary in the internal memory and processing for inputting a predetermined signal to the invalid data area in the video data Dv. The video signal Data is output from the control circuit 40 to the source driver 20. A specific configuration in which the control circuit 40 inputs the predetermined signal will be described later.

  Further, the control circuit 40 transfers the horizontal synchronization signal Hsync corresponding to the video data Dv received from the external signal source to the source driver 20 and also displays the video represented by the video data Dv based on the horizontal synchronization signal Hsync. A source clock signal SCK and a gate clock signal GCK are generated as signals to be displayed on the liquid crystal display panel 10 and output to the source driver 20 and the gate driver 30, respectively.

  The source clock signal SCK is a signal that determines the operation timing of the shift register in the source driver 20, and the gate clock signal GCK is a signal that determines the operation timing of vertical scanning.

  In addition to the above signals, the control circuit 40 outputs various control signals (not shown) to the source driver 20 and the gate driver 30.

  Of the signals generated in the control circuit 40 as described above, the video signal Data, the horizontal synchronization signal Hsync, and the source clock signal SCK are input to the source driver 20, and the gate clock signal GCK is input to the gate driver 30. Is done.

  That is, in the control circuit 40 of the present embodiment, at least the vertical synchronization signal VSYNC and the gate start pulse signal GSP (VS in FIG. 8) are omitted as compared with the configuration of the conventional liquid crystal display device shown in FIG. The number of signal lines corresponding to these signals is reduced. In FIG. 8, the configuration of the liquid crystal display device is schematically shown, and various control signals are omitted.

  Thus, according to the configuration of the liquid crystal display device 1 of the present embodiment, the number of signal lines connecting the control circuit 40 and the drive circuit (gate driver 30) is smaller than that of the configuration of the conventional liquid crystal display device. Therefore, it is possible to reduce the space and cost of the area other than the liquid crystal display panel 10 in the entire liquid crystal display device 1.

(Vertical synchronization signal circuit)
Here, the vertical synchronization signal is a signal for defining the scanning timing in the vertical direction, and is an essential signal in the gate driver 30 in order to perform proper video display. Therefore, a specific method for generating the vertical synchronizing signal and inputting it to the gate driver 30 will be described below.

  The source driver 20 of the present embodiment includes a vertical synchronization signal generation circuit 21 therein. FIG. 3 is a block diagram showing a configuration of the vertical synchronization signal generation circuit 21. As shown in FIG.

  Here, the relationship between the horizontal synchronizing signal, the vertical synchronizing signal, and the digital video signal in the conventional liquid crystal display device will be described first. FIG. 4 is a timing chart showing waveforms of various signals in a conventional liquid crystal display device. In FIG. 4, VSYNC is a vertical synchronization signal that defines the timing of vertical scanning, and HSYNC is a horizontal synchronization signal that defines the timing of horizontal scanning. The period from the fall of VSYNC to the next fall is one vertical scanning period (1V period), and the period from the fall of HSYNC to the next fall is one horizontal scanning period (1H period). In the digital video signal (DATA) shown in FIG. 4, the 1H period is composed of an effective data area and an invalid data area, the effective data area is an effective scanning period, and the invalid data area is a horizontal blanking period. Further, the invalid data area when the 1V period ends is a vertical blanking period.

  In the conventional liquid crystal display device, as shown in FIG. 8, the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC are supplied as a horizontal scanning start clock HCLK and a vertical scanning start clock VCLK from the control circuit (display control device 200). Are input to the source driver 300 and the gate driver 400. Therefore, signal lines corresponding to the horizontal synchronization signal (horizontal scanning start clock) and the vertical synchronization signal (vertical scanning start clock) are provided between the control circuit and the drive circuit, respectively.

  In contrast, in the present invention, in the source driver 20, the vertical synchronization signal generation circuit 21 shown in FIG. 3 generates the vertical synchronization signal Vsync based on the horizontal synchronization signal Hsync and the video signal Data, and the generated vertical synchronization signal. In this configuration, Vsync is input to the gate driver 30.

(About the structure of the video signal Data)
Here, a specific configuration of the video signal Data input to the vertical synchronization signal generation circuit 21 will be described. FIG. 5 is a timing chart showing waveforms of various signals inputted to and outputted from the control circuit 40. That is, in the figure, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the video data Dv input from the signal source to the control circuit 40 and the video signal Data output from the control circuit 40 are shown. As shown in FIG. 5, the video data Dv output from the signal source includes an effective data area (effective data period) that is a data area of a video to be displayed and invalid data that is a blanking period in which no video is displayed. Region (discrimination signal period).

  As shown in FIG. 5, the video signal Data in the present embodiment includes different discrimination signals (first signal; * 1, second signal; * 2) in each invalid data area of the video data Dv. Entered and configured.

  This determination signal can be, for example, a signal having a different potential level (low (L) level, high (H) level). Specifically, the invalid data area immediately before (before) the video display for one frame is started in the video data Dv for one frame based on the vertical synchronization signal Vsync input from the signal source by the control circuit 40. (* 1) and other invalid data areas (* 2) are discriminated, and signals of different potential levels (discrimination signal: L level or H level) are input to the respective areas, and the video signal Data is generated. For example, the falling timing of the vertical synchronization signal Vsync defines the timing to start displaying one frame of video, and therefore, an L level signal is input to the corresponding invalid data area (* 1) in accordance with this timing. On the other hand, an H level signal is input to the invalid data area (* 2) until the next falling edge of the vertical synchronization signal Vsync when one vertical scanning period (1V) ends.

  That is, a potential level (H / L level) that changes at the same timing as the vertical scanning timing is added to the video signal Data in the present embodiment. A signal Data1 shown in FIG. 6 indicates a video signal to which the discrimination signal is input, and corresponds to a change in the potential level of the vertical synchronization signal.

  As another method for generating the video signal Data, when the potential level of the vertical synchronizing signal Vsync is L level, the horizontal width of the horizontal synchronizing signal Hsync is different from that of other periods, or the potential of the vertical synchronizing signal Vsync is set. A method of inverting the horizontal synchronization signal Hsync only when the level is L level can be mentioned. Furthermore, since the video data Dv has a plurality of bits, there are a method of using the combination and a method of discriminating only by a specific bit.

(Regarding the generation method of the vertical synchronization signal Vsync)
The video signal Data1 (FIG. 6) generated by the control circuit 40 as described above is input to the vertical synchronization signal generation circuit 21 (FIG. 3) of the source driver 20. As shown in FIG. 3, the vertical synchronization signal generation circuit 21 is configured by a D flip-flop circuit, and the video signal Data1 is input to the terminal D (first input unit), and the clock input (terminal CK; second). The horizontal synchronization signal Hsync is input as an input unit. The output Q (output unit) outputs the input data (video signal Data1) when the horizontal synchronization signal Hsync changes from the L level to the H level, and the previous data output is output during other periods. Retained.

  This will be specifically described below with reference to the timing chart shown in FIG. FIG. 6 is a timing chart showing waveforms of various signals that are input to and output from the vertical synchronization signal generation circuit 21.

  From the control circuit 40, the video signal Data1 is input to the terminal D of the D flip-flop circuit, and the horizontal synchronization signal Hsync is input to the terminal CK. First, a change from the first L level (left end in FIG. 6) of the horizontal synchronization signal Hsync to the H level is input to the terminal CK. From the output Q, the video signal Data1 (H level) input to the terminal D at this time is output. Thereafter, the previous data output (H level) is held until the horizontal synchronization signal Hsync next changes from the L level to the H level.

  Next, the video signal Data1 (L level) input to the terminal D when the horizontal synchronization signal Hsync changes from L level to H level is output. As a result, the output signal OUT is switched from the H level to the L level. Thereafter, the previous data output (L level) is held until the horizontal synchronizing signal Hsync next changes from the L level to the H level. Then, the output signal OUT switches from the L level to the H level again by the change of the next horizontal synchronization signal Hsync from the L level to the H level.

  Thereafter, the output and holding of the video signal Data1 (H level) are repeated until the output of the video signal Data1 of the second frame is started.

  When the video signal Data1 (L level) indicating the start of the next frame is input to the terminal D of the D flip-flop circuit, and the change from the L level to the H level of the horizontal synchronization signal Hsync is input at this time, the output signal OUT switches from the H level to the L level. Thereafter, the above process is repeated. A signal OUT in FIG. 6 indicates a signal generated by the above processing.

  According to the above configuration, in the period from the start of the output of the video signal Data1 of one frame to the start of the output of the video signal Data1 of the next frame, that is, in the output signal OUT output from the D flip-flop circuit A period from the switching point (falling) from the H level to the L level to the switching point (falling) from the next H level to the L level is one vertical scanning period (1 V). That is, the change in the potential level of the signal OUT corresponds to the change in the potential level of the vertical synchronization signal. From the above, the vertical synchronization signal Vsync can be generated based on the horizontal synchronization signal Hsync and the video signal Data1.

  The vertical synchronization signal Vsync generated by the vertical synchronization signal generation circuit 21 is input to the gate driver 30. In the gate driver 30, a gate control unit (scanning signal line drive control unit; not shown) provided in the gate driver 30 is predetermined every one frame period (one vertical scanning period) based on the input vertical synchronization signal Vsync. A gate start pulse signal GSP is generated as a signal that becomes H level only for a period. Note that, as described above, the gate driver 30 receives the gate clock signal GCK generated in the control circuit 40 based on the horizontal synchronization signal Hsync. As a result, processing for outputting a scanning signal for turning on the TFT 13 in the row is executed in the horizontal scanning period sequentially assigned to each row. Note that the input vertical synchronization signal Vsync may be used as it is as the gate start pulse signal GSP.

  As described above, according to the present embodiment, the vertical synchronization signal Vsync is generated based on the horizontal synchronization signal Hsync and the video signal Data in the source driver 20, and then the generated vertical synchronization signal Vsync is supplied to the gate driver 30. Since it can be input, it is not necessary to input the vertical synchronization signal Vsync from the control circuit 40 to the gate driver 30 as in the prior art. This eliminates the need for a signal line between the control circuit 40 and the gate driver 30, and can save space. Although a new signal line is required between the source driver 20 and the gate driver 30, the two drivers 20 and 30 are close to each other, and the ratio of the signal lines in the liquid crystal display device 1 is affected. Absent. Therefore, compared with the conventional configuration, it is possible to save space and reduce costs in the area other than the liquid crystal display panel 10.

  Here, another structure for generating the gate clock signal GCK and the gate start pulse signal GSP is shown in FIG. In this configuration, a source control unit 22 for generating the signal is provided in the source driver 20.

  The gate clock signal GCK may be generated by the source control unit 22 (data signal line drive control unit) in the source driver 20 based on the horizontal synchronization signal Hsync and input to the gate driver 30. A configuration in which the gate control unit (not shown) in the gate driver 30 generates the gate clock signal GCK based on the horizontal synchronization signal Hsync is also applicable. Thereby, the signal lines between the control circuit 40 and the gate driver 30 can be further reduced.

  The gate start pulse signal GSP may be generated by the source control unit 22 in the source driver 20. Specifically, for example, the source control unit 22 generates a gate start pulse signal GSP based on Vsync based on the vertical synchronization signal generated by the vertical synchronization signal generation circuit 21, and outputs this signal GSP to the gate driver 30. A configuration is mentioned.

  The source control unit 22 may be configured to generate the source clock signal SCK. The source control unit 22 can generate the source clock signal SCK based on the horizontal synchronization signal Hsync input from the control circuit 40. Thereby, the signal lines between the control circuit 40 and the source driver 20 can be further reduced.

  Further, the source control unit 22 generates a source start pulse signal SSP that becomes a high level (H level) for a predetermined period every horizontal scanning period and is transferred through the shift register based on the horizontal synchronization signal Hsync. May be. The source start pulse signal SSP may be generated by the control circuit 40.

  As described above, in the liquid crystal display device 1 according to the present embodiment, the source driver 20 generates various signals for driving the gate line 12 based on the various signals input to the source driver 20, and the gate driver The gate driver 30 is configured to drive the gate line 12 based on various signals generated by the source driver 20.

  In the present embodiment, the control circuit 40 is included in the liquid crystal display device 1, but is not limited to this, and the control circuit 40 is not included in the liquid crystal display device 1, and the video signal described above is not included. Data may be input to the source driver 20 of the liquid crystal display device 1 from the outside.

  By the way, since the source driver 20 has a data sampling function, the operation frequency operates according to the data (clock) frequency. On the other hand, since the gate driver 30 does not have a data sampling function, it only needs to operate in accordance with the horizontal synchronization signal Hsync, and the required driving frequency is lower than that of the source driver 20. Therefore, the vertical synchronization signal generation circuit 21 is preferably provided in the source driver 20. Thus, the source driver 20 can be easily operated according to the data (clock) frequency without complicating the circuit configuration. That is, the above configuration can be realized without increasing the cost of the source driver 20.

  In the liquid crystal display device 1, an FPC (flexible printed circuit board) is generally used as means for transmitting an input signal from the outside (not shown in the present embodiment). According to this embodiment, since signal lines can be reduced, the number of connectors of the FPC can also be reduced, and cost can be reduced.

  In the above description, the configuration (configuration 1) in which the gate driver drives the gate line based on the signal (vertical synchronization signal Vsync) generated in the source driver has been described, but other configurations in the liquid crystal display device of the present invention are also described. The configuration (configuration 2) may be a configuration in which the source driver drives the source line based on a signal generated in the gate driver.

  The gate driver is designed to have a higher breakdown voltage than the source driver due to the property of outputting a signal having a high voltage level. Therefore, by adopting the other configuration, for example, a signal obtained by converting a high voltage level signal into a low voltage level signal in the gate driver can be used also in the source driver.

  Here, the high voltage level signal specifically includes, for example, an output signal of a gate driver. Although this signal has a large voltage amplitude and is difficult to receive directly by the source driver, the output state of the gate driver can be monitored by receiving this signal. In addition, although not a high-voltage level signal, other signals that can be generated by the gate driver and used by the source driver include a signal indicating what row the gate driver is scanning. Since the source driver normally performs the same operation for each row, it is not necessary to count what row is being scanned. However, when a certain row is being scanned (for example, at the beginning or end of the retrace period) ), It is effective to use this signal.

  As a method for converting a high voltage level signal into a low voltage level signal, for example, a level shifter circuit inside the gate driver can be realized.

  As described above, the source driver can drive the source line based on the signal obtained by converting the voltage level in the gate driver.

  Note that the liquid crystal display device of the present invention can also be configured by combining the above configurations 1 and 2. Specifically, the gate driver drives the gate line based on a signal (vertical synchronization signal Vsync) generated in the source driver, and the source driver generates a signal (signal converted in voltage level) generated in the gate driver. ), The source line can be driven.

  Finally, operations of the source driver 20 and the gate driver 30 will be briefly described. These operations are general operations in a conventional liquid crystal display device, and a known technique can be used.

  Based on the video signal Data, the source start pulse signal SSP, and the source clock signal SCK, the source driver 20 uses the data signals S (1) to (V) as analog voltages corresponding to pixel values in each horizontal scanning line of the video represented by the video signal Data. S (n) is sequentially generated for each horizontal scanning period, and these data signals S (1) to S (n) are applied to the source lines SL1 to SLn, respectively. Voltages V0 to Vp generated by a gradation voltage source (not shown) are used as gradation reference voltages for selection as analog voltage signals S (1) to S (n). Note that the horizontal synchronization signal may be used as the source start pulse signal SSP.

  Based on the gate start pulse signal GSP and the gate clock signal GCK, the gate driver 30 writes each data signal S (1) to S (n) to each pixel electrode 14 in each frame period (each of the video signals Data). In the vertical scanning period), the gate lines GL1 to GLm are sequentially selected almost every horizontal scanning period. Note that the vertical synchronization signal Vsync may be used as the gate start pulse signal GSP.

  Through the above operation, the liquid crystal display panel 10 is driven, and gradation display according to the potential of the pixel electrode 14 is performed.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be particularly preferably applied to driving an active matrix liquid crystal display device.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of each pixel in the liquid crystal display device of FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a vertical synchronization signal generation circuit in the liquid crystal display device of FIG. It is a timing chart which shows the waveform of various signals in the conventional liquid crystal display device. 2 is a timing chart showing waveforms of various signals input to and output from a control circuit in the liquid crystal display device of FIG. 2 is a timing chart showing waveforms of various signals inputted to and outputted from a vertical synchronizing signal generation circuit in the liquid crystal display device of FIG. FIG. 2 is a block diagram illustrating a schematic configuration of a source driver that generates a gate start pulse signal in the liquid crystal display device of FIG. 1. It is a block diagram which shows schematic structure of the conventional liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal display panel (display panel)
11 Source line (data signal line)
12 Gate line (scanning signal line)
13 TFT (switching element)
14 pixel electrode 17 liquid crystal capacitor 19 counter electrode 20 source driver (data signal line drive circuit)
21 vertical synchronization signal generation circuit 22 source control unit (data signal line drive control unit)
30 Gate driver (scanning signal line drive circuit)
40 Control circuit (display control circuit)

Claims (13)

In a display driving circuit comprising a scanning signal line driving circuit for driving scanning signal lines and a data signal line driving circuit for driving data signal lines,
At least one of the scanning signal line driving circuit and the data signal line driving circuit drives a corresponding signal line by using a signal output from the other. The data signal line driving circuit generates a signal for driving the scanning signal line based on a signal input to the data signal line driving circuit, and outputs the signal to the scanning signal line driving circuit.
The display driving circuit according to claim 1, wherein the scanning signal line driving circuit drives the scanning signal line based on a signal generated in the data signal line driving circuit. The scanning signal line driving circuit outputs a scanning signal for turning on a switching element of the row in a horizontal scanning period sequentially assigned to each row,
The data signal line driving circuit outputs a data signal corresponding to a video to be displayed based on a horizontal synchronization signal,
The data signal line drive circuit includes a vertical synchronization signal generation circuit that generates a vertical synchronization signal based on the horizontal synchronization signal and a video signal that is a source of the data signal input to the data signal line drive circuit. Prepared,
3. The display driving circuit according to claim 2, wherein the scanning signal line driving circuit outputs the scanning signal based on the vertical synchronizing signal generated by the vertical synchronizing signal generating circuit.   The video signal has a valid data period including video data to be displayed and a discrimination signal having one of binary potentials determined according to the potential of the vertical synchronization signal output from the signal source. The display driving circuit according to claim 3, further comprising a period. The vertical synchronization signal generation circuit includes a first input unit that inputs the video signal, a second input unit that inputs the horizontal synchronization signal, and a signal generated based on the horizontal synchronization signal and the video signal. An output unit for outputting as the vertical synchronization signal,
When the potential level of the horizontal synchronization signal input to the second input unit changes from a low level to a high level, the potential level of the video signal input to the first input unit is set to the vertical synchronization. 5. The display driving circuit according to claim 4, wherein the display driving circuit outputs the signal as a potential level.   6. The display driving circuit according to claim 5, wherein the vertical synchronizing signal generation circuit is configured by a D flip-flop circuit. A display control circuit for controlling the scanning signal line driving circuit and the data signal line driving circuit;
The display control circuit is an image located at a boundary between adjacent horizontal scanning periods based on a vertical synchronization signal input from a signal source with respect to a signal that is a source of the image signal input from a signal source. In the blanking period in which no image is displayed, a signal of the first potential level is input in the blanking period immediately before the first horizontal scanning period in one frame, while in the other blanking period in one frame 7. The display driving circuit according to claim 3, wherein a signal generated by inputting a signal having a potential level of 2 is output as the video signal.   The scanning signal line driving circuit outputs the scanning signal based on a gate start pulse signal generated based on the vertical synchronization signal. Display drive circuit.   9. The scanning signal line driving circuit further comprises a scanning signal line driving control unit that generates a gate start pulse signal based on the vertical synchronization signal received from the data signal line driving circuit. A display drive circuit according to 1.   The data signal line driving circuit further includes a data signal line driving control unit that generates a gate start pulse signal based on the vertical synchronization signal, and outputs the generated gate start pulse signal to the scanning signal line driving circuit. The display driving circuit according to claim 8.   A display device comprising: the display drive circuit according to claim 1; and the display panel.   The display device according to claim 11, wherein the display device is a liquid crystal display device. In a display driving method including a scanning signal line driving process for driving a scanning signal line and a data signal line driving process for driving a data signal line,
At least one of the scanning signal line driving process and the data signal line driving process drives a corresponding signal line by using a signal output from the other.

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