JP2009152294A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2009152294A JP2009152294A JP2007327297A JP2007327297A JP2009152294A JP 2009152294 A JP2009152294 A JP 2009152294A JP 2007327297 A JP2007327297 A JP 2007327297A JP 2007327297 A JP2007327297 A JP 2007327297A JP 2009152294 A JP2009152294 A JP 2009152294A
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- electrode pad
- internal circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract
【解決手段】 ウエーハと導電型が逆になるような不純物領域8を裏面に複数作製し、ウエーハ表面に作られる内部回路の接地電極2が保護ダイオードのアノード、裏面電極4、5が前記保護ダイオードのカソードとなるように、チップをパッケージする際に前記内部回路の入力端子1と出力端子3をそれぞれ前記裏面電極4、5に結線する。
【選択図】 図1
Description
2 ボンディングパッド(内部回路の接地端子および保護ダイオードのアノード端子)
3 ボンディングパッド(内部回路の出力端子)
4 裏面電極 (入力保護ダイオードのカソード端子)
5 裏面電極 (出力保護 ダイオードのカソード端子)
6 絶縁保護膜
7 第1導電型高濃度不純物領域
8 第2導電型低濃度不純物領域
9 第1導電型半導体基板
10 内部素子回路の領域
11 第1導電型低濃度不純物領域間の間隔
12 第2導電型高濃度不純物領域
13 ボンディングワイヤー
14 リードフレーム(入力端子)
15 リードフレーム(接地端子)
16 リードフレーム(出力端子)
17 バンプ
100 半導体装置
Claims (4)
- 端子から入るサージから内部回路を保護する保護ダイオードを有する半導体装置であって、
ウエーハと、
前記ウエーハの表面に配置された、接地電極パッドを含む電極パッドを有する内部回路と、
前記ウエーハの裏面に配置された、前記ウエーハと導電型が逆になるような不純物領域と前記不純物領域とオーミック接触する裏面電極パッドと、
前記裏面電極パッドと前記内部回路の接地電極パッド以外の電極パッドとを対として電気的に結線する配線とからなる半導体装置。 - 前記不純物領域と前記裏面電極パッドが間隔を隔て、入力端子、出力端子、入出力端子、テスト端子の数だけ設けられており、前記裏面電極パッドと前記内部回路の接地電極パッド以外の電極パッドが一対ずつ電気的に結線されていることを特徴とする請求項1に記載の半導体装置。
- 前記内部回路の電極パッドがワイヤーボンデイング用の電極パッドであり、前記裏面電極が、機械的にボンディングされない外部電極用パッドであることを特徴とする請求項1または請求項2に記載の半導体装置。
- 端子から入るサージから内部回路を保護する保護ダイオードを有する半導体装置の製造方法であって、
ウエーハ表面に接地電極パッドを含む電極パッドを有する内部回路を形成する工程と、
ウエーハ裏面にウエーハと導電型が逆になるような不純物領域と前記不純物領域とオーミック接触する裏面電極パッドとを設ける工程と、
前記裏面電極パッドと前記内部回路の前記接地電極パッド以外の前記電極パッドを電気的に結線することを含むチップをパッケージする工程とからなる半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007327297A JP5102011B2 (ja) | 2007-12-19 | 2007-12-19 | 半導体装置 |
Applications Claiming Priority (1)
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JP2007327297A JP5102011B2 (ja) | 2007-12-19 | 2007-12-19 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2009152294A true JP2009152294A (ja) | 2009-07-09 |
JP5102011B2 JP5102011B2 (ja) | 2012-12-19 |
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JP2007327297A Expired - Fee Related JP5102011B2 (ja) | 2007-12-19 | 2007-12-19 | 半導体装置 |
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JP (1) | JP5102011B2 (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327976A (ja) * | 2003-04-11 | 2004-11-18 | Fuji Electric Device Technology Co Ltd | 圧接型半導体装置 |
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- 2007-12-19 JP JP2007327297A patent/JP5102011B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327976A (ja) * | 2003-04-11 | 2004-11-18 | Fuji Electric Device Technology Co Ltd | 圧接型半導体装置 |
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JP5102011B2 (ja) | 2012-12-19 |
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