JP2009152279A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, suitably forming a front surface metal layer. <P>SOLUTION: The method of manufacturing the semiconductor device includes: an ohmic metal layer formation process of forming an ohmic metal layer which carries out an ohmic contact with a top face of a semiconductor wafer by avoiding at least a dicing region on the top face of the semiconductor wafer; a lower electrode formation process of forming a lower electrode on a bottom face of the semiconductor wafer by a sputtering; a silicon oxide layer formation process of forming a silicon oxide layer on a front surface of the lower electrode; a front surface metal layer formation process of forming a front surface metal layer containing at least one of nickel and copper on a front surface of the ohmic metal layer by means of a plating method of forming a plated layer on only a front surface of a metal; a silicon oxide layer removal process of removing the silicon oxide layer by an etching; and a dicing process of carrying out a dicing of the semiconductor wafer along the dicing region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having an upper electrode and a lower electrode from a semiconductor wafer. In this specification, “semiconductor wafer” means a semiconductor before dicing, and “semiconductor substrate” means a semiconductor after dicing (that is, after being separated into individual semiconductor devices).

2. Description of the Related Art A large current control semiconductor device used for motor inverter control and the like is known. This type of semiconductor device generates a large amount of heat because it handles a large current. Therefore, a technique for soldering the upper electrode formed on the upper surface of the semiconductor device to an electrode plate or the like is known. When soldered, the thermal conductivity from the semiconductor device to the electrode plate can be increased, and the heat dissipation performance of the semiconductor device can be improved. In order to solder-join the upper electrode, it is necessary to form a metal layer (hereinafter referred to as a surface metal layer) containing nickel or copper having high solder wettability on the surface of the upper electrode.
A plurality of semiconductor devices are usually formed on a semiconductor wafer. The plurality of semiconductor devices formed on the semiconductor wafer are diced and separated into individual semiconductor devices. When the electrode (that is, metal) is diced, defects such as chipping are likely to occur due to the ductility of the metal. Therefore, normally, the upper electrode is formed by patterning so as to avoid a dicing region (a region scraped off during dicing). In addition, in a semiconductor device having a plurality of upper electrodes (for example, an IGBT having an emitter electrode and a gate electrode on the upper surface), each upper electrode is positioned appropriately in each device region (region divided by a dicing region). It is formed by patterning so as to be disposed on the surface. A commonly used upper electrode (aluminum or the like) can be patterned with high accuracy using etching or the like. On the other hand, a surface metal layer such as nickel is difficult to precisely etch and is difficult to form by patterning. Therefore, the surface metal layer is formed by plating (electrolytic plating or electroless plating). That is, a metal layer that is easy to etch is formed on the upper surface of the semiconductor wafer by patterning, and a surface metal layer is formed on the surface of the metal layer by plating. At this time, a plating method in which a plating layer is formed only on the surface of the metal layer is used. According to this method, the upper electrode provided with the surface metal layer can be formed by patterning with high accuracy. Further, according to the plating method, it is easy to form a thick surface metal layer, and there is an advantage that the heat dissipation performance of the upper electrode can be improved.
On the other hand, the lower electrode is usually formed over the entire lower surface of the semiconductor wafer. During dicing, the semiconductor wafer is cut together with the lower electrode. When dicing an electrode (ie, metal), defects such as chipping are likely to occur due to the ductility of the metal. Therefore, it is preferable to form the lower electrode thin in order to suppress problems during dicing. That is, the lower electrode is preferably formed by sputtering capable of forming a thin layer. Since the upper electrode is formed avoiding the dicing area, there is no problem even if it is formed thick by plating.

  As described above, Patent Document 1 discloses a method of manufacturing a semiconductor device in which a surface metal layer is formed by plating and a lower electrode is formed by sputtering. In the technique of Patent Document 1, an ohmic metal layer (aluminum layer) is first formed by patterning on the upper surface of a semiconductor wafer. Thereafter, after polishing the lower surface of the semiconductor wafer, the lower electrode is formed on the lower surface of the semiconductor wafer by sputtering. Next, a masking tape (dicing tape) is bonded to the surface of the formed lower electrode, and the surface of the lower electrode is masked. Next, the semiconductor wafer together with the masking tape is impregnated with an electroless nickel plating solution to form a surface metal layer (nickel layer) on the surface of the ohmic metal layer. Thus, an upper electrode composed of an ohmic metal layer and a surface metal layer is formed. Since the lower electrode is masked with a masking tape during plating, a plating layer (nickel layer) is not formed on the surface of the lower electrode.

Japanese Patent Laid-Open No. 2007-027477

  According to the technique of Patent Document 1, the surface metal layer of the upper electrode can be formed with high accuracy by plating, and the lower electrode can be formed thin by sputtering. However, with this technique, the masking tape adhesive may elute into the plating solution during the plating process. Even if the treatment for improving the resistance to the plating solution is performed, the elution of the adhesive cannot be completely prevented. When the adhesive is eluted in the plating solution, the eluted adhesive may adhere to the surface of the ohmic metal layer. When the adhesive adheres to the surface of the ohmic metal layer, there is a problem that the surface metal layer is not formed at the attachment location, and the upper electrode cannot be suitably formed.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of suitably forming a surface metal layer.

In the semiconductor device manufacturing method of the present invention, a semiconductor device having an upper electrode and a lower electrode is manufactured from a semiconductor wafer. The upper electrode includes an ohmic metal layer and a surface metal layer. This manufacturing method includes an ohmic metal layer forming step, a lower electrode forming step, a silicon oxide layer forming step, a surface metal layer forming step, a silicon oxide layer removing step, and a dicing step. In the ohmic metal layer forming step, an ohmic metal layer that is in ohmic contact with the upper surface of the semiconductor wafer is formed on the upper surface of the semiconductor wafer. The ohmic metal layer is formed avoiding at least the dicing region. In the lower electrode formation step, the lower electrode is formed on the lower surface of the semiconductor wafer by sputtering. In the silicon oxide layer forming step, a silicon oxide layer is formed on the surface of the lower electrode. In the surface metal layer forming step, a surface metal layer containing at least one of nickel and copper is formed on the surface of the ohmic metal layer by a plating method in which a plating layer is formed only on the metal surface. In the silicon oxide layer removal step, the silicon oxide layer is removed by etching. In the dicing process, the semiconductor wafer is diced along the dicing area.
The ohmic metal layer may have a structure in which a plurality of metal layers are stacked. For example, the ohmic metal layer may have a stacked structure of a metal layer that is in ohmic contact with the semiconductor substrate and a titanium layer that prevents diffusion of solder during solder joining. Similarly, the surface metal layer and the lower electrode may have a structure in which a plurality of metals are laminated.
In this method of manufacturing a semiconductor device, plating is performed with the surface of the lower electrode covered with a silicon oxide layer. This prevents a plating layer from being formed on the surface of the lower electrode during plating. Therefore, the surface metal layer can be formed only on the surface of the ohmic metal layer. Further, since the surface of the lower electrode can be covered without using an adhesive, the adhesive is not eluted into the plating solution. A surface metal layer can be suitably formed.

In the silicon oxide layer forming step of the production method of the present invention, it is preferable to form a silicon oxide layer by sputtering.
According to such a configuration, after the lower electrode is formed by sputtering, the silicon oxide layer can be continuously formed using the same sputtering apparatus. A semiconductor device can be manufactured with high manufacturing efficiency.

In order to reduce the resistance of a current path in a semiconductor device, a technique for thinning a semiconductor wafer at the time of manufacturing the semiconductor device is known. In the above-described conventional manufacturing method (a manufacturing method in which plating is performed with a masking tape adhered to the surface of the lower electrode), the semiconductor wafer is thinned. However, in the conventional manufacturing method described above, the entire lower surface of the semiconductor wafer is polished to make the entire semiconductor wafer thinner. This is considered to be because it is necessary to flatten the lower surface of the semiconductor wafer in order to bring the masking tape into close contact with the lower surface of the semiconductor wafer (that is, the surface of the lower electrode). However, there is a problem that the strength of the semiconductor wafer becomes extremely weak if the entire semiconductor wafer is thinned in this way.
The method for manufacturing a semiconductor device of the present invention further includes a thinning step for thinning the central portion of the semiconductor wafer by grinding or etching the central portion of the lower surface of the semiconductor wafer at the latest before the lower electrode forming step. It is preferable.
According to such a configuration, since the central portion of the semiconductor wafer, which is a region where the semiconductor device is formed, is thinned, the characteristics of the manufactured semiconductor device can be improved. Further, since the central portion of the semiconductor wafer is supported by the outer peripheral portion of the semiconductor wafer that maintains the original thickness, the strength of the semiconductor wafer does not decrease so much. Further, in this manufacturing method, since the surface of the lower electrode is covered with the silicon oxide layer, the concave portion on the lower surface of the semiconductor wafer does not get in the way when the silicon oxide layer is formed. Suitably the surface of the lower electrode can be covered with a silicon oxide layer.

In the manufacturing method of the present invention described above, it is preferable to form a plurality of upper electrodes in the device region defined by the dicing region on the upper surface of the semiconductor wafer.
Thus, when a plurality of upper electrodes are formed, the manufacturing method of the present invention capable of forming the surface metal layer with high accuracy is particularly suitable.

The manufacturing method of the present invention described above preferably further includes a diffusion layer forming step and a metal layer forming step. In the diffusion layer forming step, ions are implanted into the lower surface of the semiconductor wafer, and the semiconductor wafer after the ion implantation is heat-treated. In the metal layer forming step, a metal layer containing at least one of gold, platinum, and silver is formed on the surface of the surface metal layer. The metal layer forming step is performed after the diffusion layer forming step at the earliest.
According to such a configuration, since the metal layer containing at least one of gold, platinum, and silver is formed on the surface of the surface metal layer, the surface of the surface metal layer can be prevented from being oxidized. Therefore, it becomes possible to solder the upper electrode more suitably. Further, since the metal layer forming step is performed after the diffusion layer forming step, the formed metal layer (metal layer including at least one of gold, platinum, and silver) diffuses (disappears) by the heat treatment in the diffusion layer forming step. There is nothing.

  According to the present invention, the surface metal layer of the semiconductor device can be suitably formed. A semiconductor device including an upper electrode (an ohmic metal layer and a surface metal layer) and a lower electrode can be preferably manufactured.

The main features of the embodiments described in detail below are listed first.
(Feature 1) The ohmic metal layer is formed of any one of aluminum, an aluminum-silicon alloy, and titanium.
(Feature 2) The surface metal layer is formed by electroless plating.

  The manufacturing method of the Example which applied this invention to the manufacturing method of IGBT is demonstrated. FIG. 1: has shown schematic sectional drawing of IGBT10 manufactured with the manufacturing method of an Example. As shown in FIG. 1, the IGBT 10 includes a semiconductor substrate 12 mainly made of silicon, electrodes formed on the upper surface 12a and the lower surface 12b of the semiconductor substrate 12, an insulating layer, and the like.

  As shown in FIG. 1, a plurality of trenches 30 are regularly formed at intervals on the upper surface 12 a of the semiconductor substrate 12. The wall surface of the trench 30 is covered with a gate insulating film 40. The trench 30 is filled with a gate electrode 42.

  A p-type collector layer 14 is formed in a region facing the lower surface 12 b of the semiconductor substrate 12. An n-type drift layer 16 is formed on the collector layer 14. A p-type body layer 20 is formed in a predetermined region above the drift layer 16. The trench 30 described above extends to a depth that reaches the drift layer 16 through the body layer 20. In a region facing the upper surface 12a of the semiconductor substrate 12, an n-type emitter region 22 and a p-type body contact region 24 are formed. The emitter region 22 is formed in a region in contact with the gate insulating film 40. The body contact region 24 is formed between the two emitter regions 22. The p-type impurity concentration in the body contact region 24 is higher than the p-type impurity concentration in the body layer 20. Of the region facing the upper surface 12 a of the semiconductor substrate 12, a p-type RESURF layer 26 is formed in a region near the edge 12 c of the semiconductor substrate 12. The p-type impurity concentration in the RESURF layer 26 is lower than the p-type impurity concentration in the body layer 20.

  An interlayer insulating film 44 is formed on the upper surface 12 a of the semiconductor substrate 12. The upper surface of the gate electrode 42 and the upper surface of the RESURF layer 26 are covered with an interlayer insulating film 44. Although not shown, gate wiring (metal wiring) is formed on the upper surface 12 a of the semiconductor substrate 12. The gate wiring is electrically connected to each gate electrode 42 at a position not shown. Although not shown, the gate wiring is provided with a pad for electrical connection to the outside. An emitter electrode 46 is formed in a region where the body layer 20 is distributed on the upper surface 12 a of the semiconductor substrate 12. The emitter electrode 46 is in ohmic contact with the emitter region 22 and the body contact region 24. The emitter electrode 46 is insulated from the gate electrode 42 and the gate wiring by the interlayer insulating film 44.

FIG. 2 shows an enlarged cross-sectional view of the emitter electrode 46. As shown in the figure, the emitter electrode 46 has a laminated structure in which four metal layers of an aluminum layer 46a, a titanium layer 46b, a nickel layer 46c, and a gold (Au) layer 46d are laminated. The aluminum layer 46a is in ohmic contact with the semiconductor substrate 12 (that is, the emitter region 22 and the body contact region 24). The aluminum layer 46 a is also in contact with the interlayer insulating film 44. The titanium layer 46b is formed on the surface of the aluminum layer 46a. The titanium layer 46 b prevents the constituent metal of the solder from diffusing into the semiconductor substrate 12 when the emitter electrode 46 is soldered. The nickel layer 46c is formed on the surface of the titanium layer 46b. The nickel layer 46c has high solder wettability and is firmly connected to the solder. The gold layer 46d is formed on the surface of the nickel layer 46c. The gold layer 46d prevents oxidation of the surface of the nickel layer 46c. In FIG. 2, the metal layers 46 a to 46 d are shown with the same thickness in consideration of the visibility of the drawing, but actually, the nickel layer 46 c is a thicker layer than the other metal layers. The gold layer 46d is a very thin layer compared to other metal layers.
Although not shown, the gate wiring pad described above also has a laminated structure similar to that of the emitter electrode 46. In this embodiment, the emitter electrode 46 and the pad of the gate wiring are upper electrodes soldered to the outside.

As shown in FIG. 1, a collector electrode (lower electrode) 48 is formed on the lower surface 12 b of the semiconductor substrate 12. The collector electrode 48 is formed over the entire lower surface 12 b of the semiconductor substrate 12. In FIG. 1, the collector electrode 48 and the emitter electrode 46 are shown with substantially the same thickness. However, the collector electrode 48 is actually much thinner than the emitter electrode 46.
FIG. 3 shows an enlarged cross-sectional view of the collector electrode 48. As shown in the figure, the collector electrode 48 has a laminated structure in which four metal layers of an aluminum layer 48a, a titanium layer 48b, a nickel layer 48c, and a gold (Au) layer 48d are laminated. The aluminum layer 48 a is in ohmic contact with the lower surface 12 b of the semiconductor substrate 12. The titanium layer 48b is formed on the surface of the aluminum layer 48a. The nickel layer 48c is formed on the surface of the titanium layer 48b. The gold layer 48d is formed on the surface of the nickel layer 48c. In FIG. 3, the metal layers 48 a to 48 d are shown with the same thickness in consideration of the visibility of the drawing, but actually, the nickel layer 48 c is a thicker layer than the other metal layers. The gold layer 48d is a very thin layer compared to other metal layers.

The IGBT 10 described above is connected to the outside by solder bonding.
That is, the upper electrode (the emitter electrode 46 and the gate wiring pad) is connected to an external electrode plate by solder bonding. Since the nickel layer 46c has good solder wettability and the gold layer 46d prevents the surface of the nickel layer 46c from being oxidized, the upper electrode can be suitably soldered. Further, during solder joining, the titanium layer 46b prevents the constituent metal (such as tin) of solder from diffusing into the semiconductor substrate 12. By soldering the upper electrode to an external electrode plate, the heat dissipation performance of the IGBT 10 can be improved as compared with the case of using wire bonding or the like.
The collector electrode 48 is also connected to an external electrode plate by solder bonding. Since the collector electrode 48 has the same laminated structure as the upper electrode, it is suitably soldered. By soldering the collector electrode 48 to an external electrode plate, the heat dissipation performance of the IGBT 10 can be improved as compared with the case where a conductive paste or the like is used.

  Next, the manufacturing method of IGBT10 is demonstrated. FIG. 4 is a flowchart showing the manufacturing process of the IGBT 10. The IGBT 10 is manufactured from an n-type semiconductor wafer 100 (a substantially disk-shaped silicon wafer cut out from an ingot). A plurality of IGBTs 10 are manufactured from one semiconductor wafer 100.

  In step S2, the upper IGBT structure (that is, the body layer 20, the emitter region 22, the body contact region 24, the RESURF layer 26, the trench 30, the gate insulating film 40, the gate electrode 42, the gate wiring, and the interlayer is formed on the upper surface of the semiconductor wafer 100. An insulating film 44) is formed. Since the method for forming the upper IGBT structure is a conventionally known method, detailed description thereof is omitted.

  In step S4, an aluminum layer 46a of the upper electrode (that is, the emitter electrode 46 and the gate wiring pad) is formed. That is, first, the aluminum layer 46a is formed over the entire upper surface of the semiconductor wafer 100 by sputtering. Next, the aluminum layer 46a is selectively etched to pattern the aluminum layer 46a into a shape corresponding to the upper electrode. FIG. 5 shows a cross section of the semiconductor wafer 100 after step S4. FIG. 5 shows a cross section of the semiconductor wafer 100 (cross section of the boundary portion of the adjacent IGBTs 10) including the dicing region 102 to be scraped off in a subsequent dicing process. As illustrated, in step S4, the aluminum layer 46a is not formed in the dicing region 102. That is, all the aluminum layer 46a in the dicing region 102 is removed during etching.

  In step S6, the upper electrode titanium layer 46b is formed. That is, first, the titanium layer 46b is formed on the entire upper surface of the semiconductor wafer 100 by sputtering (the titanium layer 46b is formed on the aluminum layer 46a at the place where the aluminum layer 46a exists). Next, the titanium layer 46b is selectively etched to pattern the titanium layer 46b in the same manner as the aluminum layer 46a.

  In step S8, the lower surface of the semiconductor wafer 100 is polished to make the semiconductor wafer 100 thinner. At this time, the central portion (the range in which the IGBT 10 is formed) of the semiconductor wafer 100 is polished, and the outer peripheral portion (the range in which the IGBT 10 is not formed, that is, the range to be discarded after dicing) is not polished. That is, only the central portion of the semiconductor wafer 100 is thinned and the outer peripheral portion is not thinned. Thus, by thickening the outer peripheral portion of the semiconductor wafer 100, the formation range of the IGBT 10 can be reduced while maintaining the strength of the semiconductor wafer 100.

  In step S10, p-type impurities (boron or the like) are implanted into the lower surface of the semiconductor wafer 100, and then the semiconductor wafer 100 is heat-treated. As a result, the p-type impurity implanted into the lower surface of the semiconductor wafer 100 is activated, and the collector layer 14 is formed.

  In step S <b> 12, the collector electrode 48 (that is, the lower electrode) is formed on the lower surface of the semiconductor wafer 100. That is, first, the aluminum layer 48a is formed over the entire lower surface of the semiconductor wafer 100 by sputtering. Next, a titanium layer 48b is formed over the entire surface of the aluminum layer 48a by sputtering. Next, a nickel layer 48c is formed over the entire surface of the titanium layer 48b by sputtering. Next, a gold layer 48d is formed over the entire surface of the nickel layer 48c by sputtering. As a result, a collector electrode 48 composed of an aluminum layer 48a, a titanium layer 48b, a nickel layer 48c, and a gold layer 48d is formed over the entire lower surface of the semiconductor wafer 100.

  In step S14, the silicon oxide layer 50 is formed over the entire surface of the collector electrode 48 by sputtering. The formation (ie, sputtering) of the silicon oxide layer 50 is performed by the same sputtering apparatus following the formation (ie, sputtering) of the collector electrode 48 in step S14. That is, using a sputtering apparatus having a plurality of chambers, the semiconductor wafer 100 is moved in the order of an aluminum chamber, a titanium chamber, a nickel chamber, a gold chamber, and a silicon oxide chamber, and sputtering is performed in each chamber. After step S14, the semiconductor wafer 100 has the structure shown in FIG.

  In step S16, the nickel layer 46c and the gold layer 46d of the upper electrode are formed by plating. FIG. 7 is a flowchart showing details of the plating process in step S16.

First, the plating pretreatment in steps S30 to S36 is performed.
In step S30, the semiconductor wafer 100 in the state shown in FIG. 7 is impregnated with a cleaning liquid, and the semiconductor wafer 100 is cleaned (degreasing).
In step S32, the surface of the titanium layer 46b is etched by impregnating the semiconductor wafer 100 with an etching solution. Thereby, a film such as an oxide film on the surface of the titanium layer 46b is removed, and the surface state of the titanium layer 46b is adjusted.
In step S34, the semiconductor wafer 100 is impregnated with nitric acid (HNO ₃ ) to remove the residue from the previous step (step S32).
In step S36, the surface of the titanium layer 46b is galvanized (substitutional electroless plating). According to substitutional electroless plating, a zinc layer is formed only on the metal surface (that is, the surface of the titanium layer 46b). Note that the zinc plating formed in step S36 is a very thin layer. This galvanization is for suitably forming the nickel layer 46c on the surface of the titanium layer 46b. In step S36, first, the semiconductor wafer 100 is impregnated with a zinc plating solution to form a zinc layer on the surface of the titanium layer 46b. Next, the semiconductor wafer 100 is impregnated with nitric acid (HNO ₃ ), and the formed zinc layer is removed. Next, the semiconductor wafer 100 is again impregnated with a zinc plating solution to form a zinc layer on the titanium layer 46b. Thus, after removing a zinc layer, a suitable zinc layer can be obtained by forming a zinc layer again.

  Next, in step S38, a nickel layer 46c is formed on the surface of the titanium layer 46b after the galvanization by plating (self-catalytic reduction type electroless plating). That is, the semiconductor wafer 100 is impregnated with the nickel plating solution while the nickel plating solution is maintained at about 80 ° C. According to this method, the nickel layer can be grown only on the surface of the metal. Therefore, the nickel layer does not grow on the surface of the semiconductor wafer 100 (region where the semiconductor is exposed) or the surface of the silicon oxide, and the nickel layer 46c can be formed only on the surface of the titanium layer 46b. The nickel layer 46c is formed thicker than other metal layers.

  In step S40, a gold layer 46d is formed on the surface of the nickel layer 46c by plating (substitutional electroless plating). That is, the semiconductor wafer 100 is impregnated in the gold plating solution while the gold plating solution is kept at about 75 ° C. As a result, the gold layer 46d is formed thin on the surface of the nickel layer 46c.

  By performing step S16 described above (ie, steps S30 to S40 in FIG. 7), the upper electrode (ie, emitter electrode 46 and gate) composed of aluminum layer 46a, titanium layer 46b, nickel layer 46c, and gold layer 46d is performed. Wiring pads) are completed. In step S <b> 16, the collector electrode 48 (that is, the lower electrode) is covered with the silicon oxide layer 50, so that no plating layer is formed on the surface of the collector electrode 48.

  In step S18, the silicon oxide layer 50 is removed by spin wet etching using hydrofluoric acid (HF). With hydrofluoric acid, only the silicon oxide layer 50 can be selectively removed. Therefore, a clean surface of the collector electrode 48 is obtained after the silicon oxide layer 50 is removed. When step S18 is completed, the semiconductor wafer 100 has the structure shown in FIG.

  In step S20, the semiconductor wafer 100 is diced to separate the semiconductor wafer 100 into a plurality of IGBTs 10. Thereby, the IGBT 10 is completed. In step S20, the dicing area 102 shown in FIG. As shown in FIG. 8, the upper electrode (that is, the emitter electrode 46 and the gate wiring pad) is not formed in the dicing region 102. Therefore, the upper electrode is not scraped during dicing. Further, since the collector electrode 48 is formed over the entire lower surface of the semiconductor wafer 100, it is scraped off during dicing. However, since the collector electrode 48 is formed thin by sputtering, no chipping occurs during dicing.

As described above, in the method of manufacturing a semiconductor device according to the embodiment, it is possible to prevent a plating layer from being formed on the surface of the collector electrode 48 without using an adhesive. Therefore, the adhesive does not elute into the plating solution when the nickel layer 46c and the gold layer 46d are formed (during plating). The nickel layer 46c and the gold layer 46d can be suitably formed.
Further, since the silicon oxide layer 50 is removed by etching, a clean surface of the collector electrode 48 can be obtained after the silicon oxide layer 50 is removed.
Moreover, since the nickel layer 46c is formed by plating, the upper electrode can be formed thick. The heat dissipation performance of the upper electrode can be further improved.
Moreover, since the collector electrode 48 is formed by sputtering, the collector electrode 48 can be formed thin. Therefore, chipping during dicing can be suppressed.

  Further, in the method for manufacturing a semiconductor device of the embodiment, the silicon oxide layer 50 is formed by sputtering. Therefore, following the formation of the collector electrode 48 (that is, the aluminum layer 48a, the titanium layer 48b, the nickel layer 48c, and the gold layer 48d), the silicon oxide layer 50 can be formed with the same sputtering apparatus. Therefore, the IGBT 10 can be manufactured with high manufacturing efficiency.

  In the semiconductor device manufacturing method of the embodiment, since the surface of the collector electrode 48 is covered with the silicon oxide layer 50, only the central portion of the semiconductor wafer 100 can be thinned when the semiconductor wafer 100 is thinned (collector electrode). In the technique of adhering the masking member to the surface, the masking member cannot be suitably adhered if there is a recess on the lower surface of the semiconductor wafer 100. That is, only the central portion of the semiconductor wafer 100 is thinned, and the outer peripheral portion is not thinned. Therefore, the strength of the semiconductor wafer 100 after thinning is high, and there is no need to use a reinforcing member or the like for reinforcing the semiconductor wafer 100 after thinning. Therefore, the IGBT 10 can be manufactured with high manufacturing efficiency.

  In the method for manufacturing the semiconductor device of the embodiment, the collector layer 14 is formed in steps S10 and S12 before the gold layer 46d and the gold layer 48d are formed. That is, the gold layer 46d and the gold layer 48d are not exposed to high temperatures. Therefore, the gold layer 46d and the gold layer 48d are prevented from diffusing due to high temperatures.

  In the semiconductor device manufacturing method of the example, reduction type electroless plating was used to form the nickel layer 46c. However, the nickel layer 46c may be formed by substitutional electroless plating or electrolytic plating. Also by these platings, the nickel layer 46c can be formed only on the surface of the titanium layer 46b.

  In the semiconductor device manufacturing method of the embodiment, aluminum is used as an ohmic metal that is in ohmic contact with the semiconductor substrate 12 (semiconductor wafer 100), but an aluminum-silicon alloy or titanium may be used. When the ohmic metal layer is formed of titanium, diffusion of solder into the semiconductor substrate 12 can be prevented by the titanium layer.

  In the semiconductor device manufacturing method of the embodiment, nickel is used for the surface metal layer, but copper may be used. An alloy containing at least one of nickel and copper may be used.

  In the semiconductor device manufacturing method of the embodiment, gold (Au) is used for the metal layer that prevents oxidation of nickel, but platinum or silver may be used. Alternatively, an alloy containing at least one of gold (Au), platinum, and silver may be used.

  In the semiconductor device manufacturing method of the embodiment, the manufacturing method of the IGBT 10 has been described. However, the present invention can also be used for manufacturing other semiconductor devices having an upper electrode and a lower electrode. For example, it can be used for manufacturing various semiconductor devices such as a MOS-FET, a PNP transistor, an NPN transistor, and a diode.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

A sectional view of IGBT10. FIG. 3 is an enlarged sectional view of an emitter electrode 46. The expanded sectional view of the collector electrode 48. FIG. The flowchart which shows the manufacturing process of IGBT10. Sectional drawing of the semiconductor wafer 100 after step S4 implementation. Sectional drawing of the semiconductor wafer 100 after step S14 implementation. The flowchart which shows the detail of the plating process of step S16. The flowchart which shows the semiconductor wafer 100 after step S18 implementation.

Explanation of symbols

10: IGBT
12: Semiconductor substrate 14: Collector layer 16: Drift layer 20: Body layer 22: Emitter region 24: Body contact region 26: RESURF layer 30: Trench 40: Gate insulating film 42: Gate electrode 44: Interlayer insulating film 46: Emitter electrode 46a: aluminum layer 46b: titanium layer 46c: nickel layer 46d: gold layer 48: collector electrode 48a: aluminum layer 48b: titanium layer 48c: nickel layer 48d: gold layer 50: silicon oxide layer 100: semiconductor wafer 102: dicing region

Claims (5)

A method of manufacturing a semiconductor device having an upper electrode having an ohmic metal layer and a surface metal layer, and a lower electrode,
An ohmic metal layer forming step for forming an ohmic metal layer in ohmic contact with the upper surface of the semiconductor wafer, avoiding at least a dicing region on the upper surface of the semiconductor wafer;
A lower electrode forming step of forming a lower electrode by sputtering on the lower surface of the semiconductor wafer;
A silicon oxide layer forming step of forming a silicon oxide layer on the surface of the lower electrode;
A surface metal layer forming step of forming a surface metal layer containing at least one of nickel and copper on the surface of the ohmic metal layer by a plating method in which a plating layer is formed only on the metal surface;
A silicon oxide layer removing step of removing the silicon oxide layer by etching;
A dicing process for dicing the semiconductor wafer along the dicing region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the silicon oxide layer forming step, a silicon oxide layer is formed by sputtering.   3. A thinning step for thinning the central portion of the semiconductor wafer by grinding or etching the central portion of the lower surface of the semiconductor wafer at least before the lower electrode forming step. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The method for manufacturing a semiconductor device according to claim 1, wherein a plurality of upper electrodes are formed in a device region defined by a dicing region in an upper surface of the semiconductor wafer. A diffusion layer forming step of implanting ions into the lower surface of the semiconductor wafer and heat-treating the semiconductor wafer after the ion implantation;
2. The metal layer forming step of forming a metal layer containing at least one of gold, platinum, and silver on the surface of the surface metal layer after the diffusion layer forming step at the earliest. The manufacturing method of the semiconductor device as described in any one of -4.

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