JP2009136064A - Circuit and method for controlling switching regulator and switching regulator using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator having an overcurrent protection function. <P>SOLUTION: An error amplifier 10 compares the output voltage Vout of the switching regulator 200 with a predetermined reference voltage Vref1 and generates an error signal Verr based on the difference between the two voltages. A comparator 14 compares a detection signal Vdet' based on a coil current passed through the output inductor L1 of the switching regulator 200 with the error signal Verr from the error amplifier 10 and outputs an off signal Soff that is brought to the high level when the value of the detection signal Vdet' reaches the value of the error signal Verr. A driver circuit 30 turns off a switching transistor M1 when the off signal Soff is brought to the high level and turns on the switching transistor M1 when a clock signal CK transitions to the high level. A clamp circuit 50 clamps the error signal Verr output from the error amplifier 10 at a clamp value based on the output voltage Vout of the switching regulator 200. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a switching regulator, and more particularly to an output voltage control technique.

  Information terminals such as mobile phone terminals and PDAs (Personal Digital Assistance) in recent years include devices that require a voltage higher or lower than the battery output voltage. In this case, an appropriate voltage to be supplied to each device is generated by boosting or lowering the battery voltage using a switching regulator (DC / DC converter).

  The switching regulator includes an output inductor, an output capacitor, a switching transistor, and a control circuit for controlling on / off of the switching transistor. As a method of controlling the switching element by this control circuit, there is known a method of monitoring the coil current (reactor current) flowing through the output inductor (or switching transistor) and controlling the switching element on / off based on the coil current. It has been.

JP-A-9-266664 JP-A-6-006969 JP-A-10-108457

  An inrush current may occur when the switching regulator is started. In addition, a large current may flow through a load connected to the switching regulator. If a large current flows through the coil (inductor) of the switching regulator, the loss may increase or the reliability of the circuit may be impaired.

  The present invention has been made in view of these problems, and a comprehensive object thereof is to provide a switching regulator having an overcurrent protection function.

  One embodiment of the present invention relates to a control circuit for a switching regulator. This control circuit compares the output voltage of the switching regulator with a predetermined reference voltage, generates an error signal according to the error between the two voltages, and a detection signal according to the coil current flowing through the output inductor of the switching regulator Is compared with the error signal from the error amplifier, the comparator that outputs an off signal that becomes a predetermined level when the value of the detection signal reaches the value of the error signal, and the switching transistor is turned off when the off signal becomes the predetermined level, When the clock signal transitions to a predetermined level, a drive unit that turns on the switching transistor and a clamp circuit that clamps the error signal output from the error amplifier with a clamp value corresponding to the output voltage of the switching regulator are provided.

  According to this aspect, when the error between the output voltage and the target value increases, the error signal is clamped, so that the timing for turning off the switching transistor is advanced. As a result, an upper limit is set for the coil current, and overcurrent can be prevented. By changing the clamp value according to the output voltage and increasing the upper limit value of the coil current as the output voltage increases, it is possible to suitably perform overcurrent protection at the time of startup.

  The clamp circuit has a clamp transistor in which the first terminal is grounded, the second terminal is connected to the output terminal of the error amplifier, the output terminal is connected to the control terminal of the clamp transistor, and the clamp value is set to the inverting input terminal And an operational amplifier to which a voltage is applied and whose non-inverting input terminal is connected to the output terminal of the error amplifier. The set voltage may be set according to the output voltage.

  Another aspect of the present invention is a switching regulator. This switching regulator includes a switching regulator output circuit including an output inductor and an output capacitor, a switching transistor connected to the output inductor, and a control circuit according to any one of the above-described aspects for controlling on / off of the switching transistor. .

  Another aspect of the present invention relates to a method for controlling a switching regulator. In this method, the output voltage of the switching regulator is compared with a predetermined reference voltage, and an error signal corresponding to the error between the two voltages is generated. Based on the error signal, the duty is set so that the output voltage matches the reference voltage. A step of generating a pulse signal whose ratio is controlled; a step of controlling on / off of the switching transistor based on the pulse signal; and a step of clamping the error signal with a clamp value corresponding to the output voltage of the switching regulator; .

  It should be noted that any combination of the above-described constituent elements, and those obtained by replacing constituent elements and expressions of the present invention with each other among methods, apparatuses, systems, etc. are also effective as embodiments of the present invention.

  According to the present invention, overcurrent protection can be suitably performed.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 1 is a circuit diagram showing a configuration of a switching regulator 200 according to the embodiment. The switching regulator 200 according to the embodiment is a step-up DC / DC converter including a control circuit 100 and a switching regulator output circuit (hereinafter referred to as an output circuit) 40. The switching regulator 200 includes an input terminal 202 and an output terminal 204, and voltages applied to or appearing at the respective terminals are referred to as an input voltage Vin and an output voltage Vout. The switching regulator 200 boosts the input voltage Vin so that the output voltage Vout matches the target value.

  FIG. 2 is a block diagram illustrating a configuration of an electronic device 300 on which the switching regulator 200 of FIG. 1 is mounted. The electronic device 300 is a battery-driven small information terminal such as a mobile phone terminal, a digital camera, or a mobile game device. Electronic device 300 includes a switching regulator 200, a load 210, and a battery 220. The battery 220 is a lithium ion battery or the like, and outputs a battery voltage Vbat of about 3V to 4V and outputs it to the input terminal 202 of the switching regulator 200.

  The load 210 is an analog or digital circuit including a liquid crystal driver that operates at a power supply voltage higher than the battery voltage. A power supply terminal of the load 210 is connected to the output terminal 204 of the switching regulator 200.

  The switching regulator 200 stabilizes the battery voltage Vbat input to the input terminal 202 to a voltage required by the load 210 and outputs it as an output voltage Vout. Hereinafter, the configuration of the switching regulator 200, particularly the control circuit 100 thereof, will be described in detail.

  Returning to FIG. The output circuit 40 includes an output inductor L1, an output capacitor C1, and a rectifier diode D1. The output capacitor C1 is provided between the output terminal 204 and the ground terminal. The output inductor L1 is provided between the input terminal 202 and the switching terminal 104 of the control circuit 100. In the rectifier diode D1, the cathode is provided between the output terminal 204 and the switching terminal 104 in the direction toward the output terminal 204. The topology of the output circuit may be changed as appropriate according to the step-up, step-down, and step-up / step-down.

  The control circuit 100 includes a switching terminal 104 and a feedback terminal 106. The output voltage Vout of the switching regulator 200 is fed back to the feedback terminal 106. The output voltage Vout is divided by resistors R10 and R11, and a feedback voltage Vfb is generated.

  The control circuit 100 includes a switching transistor M1, an error amplifier 10, a comparator 14, a detection voltage generation unit 16, an RS flip-flop 22, an oscillator 24, a driver circuit 30, a clamp circuit 50, and a clamp voltage setting unit 60.

  The control circuit 100 monitors the current flowing through the output inductor L1 or the switching transistor M1, and controls on / off of the switching transistor M1 based on the detected peak value of the current. This method is called peak current mode.

  The switching transistor M1 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching transistor M1 may be a bipolar transistor. Further, the rectifier diode D1 may be composed of a rectifier transistor. In this case, the rectifying transistor switches in a phase opposite to that of the switching transistor M1. The drain of the switching transistor M1 is connected to the switching terminal 104, and the source is grounded via the detection voltage generation unit 16.

The error amplifier 10 compares the output voltage Vout of the switching regulator 200 with a predetermined reference voltage Vref1, and generates an error signal of two voltages (hereinafter referred to as an error voltage Verr). The error amplifier 10 includes a gm amplifier 12, a second resistor R2, and a second capacitor C2.
The feedback voltage Vfb is input to the inverting input terminal of the gm amplifier 12, and the reference voltage Vref1 is input to the non-inverting input terminal. The feedback voltage Vfb may be the output voltage Vout or a voltage obtained by dividing the output voltage Vout.

  The gm amplifier 12 outputs a current corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref1. The second resistor R2 and the second capacitor C2 are connected in series between the output terminal of the gm amplifier 12 and the ground terminal. The output current of the gm amplifier 12 is converted into a voltage by the second resistor R2 and the second capacitor C2. The converted voltage is output as an error voltage Verr.

  The detection voltage generation unit 16 generates a detection voltage Vdet corresponding to the coil current flowing through the output inductor L1. The control circuit 100 may monitor the peak value of the current on the path from the input terminal 202 to the ground terminal in order to monitor the peak value of the coil current.

  The detection voltage generator 16 in FIG. 1 amplifies the detection resistor R3 provided on the path to the ground through the output inductor L1 and the switching transistor M1, and the voltage drop generated in the detection resistor R3, and outputs the detection voltage Vdet. An amplifier AMP1 is included. The method for generating the detection voltage Vdet is not particularly limited, and other known techniques may be used.

  The oscillator 24 generates a clock signal CK having a predetermined frequency. The oscillator 24 generates a periodic signal Vosc having a sawtooth waveform (ramp waveform) synchronized with the clock signal CK. The amplitude of the periodic signal Vosc is set smaller than the level of the detection voltage Vdet. The adder 26 superimposes the periodic signal Vosc on the detection voltage Vdet. Subharmonic oscillation is suppressed by superimposing the periodic signal Vosc.

  The error voltage Verr from the error amplifier 10 is input to the inverting input terminal of the comparator 14, and the detection voltage Vdet 'on which the periodic signal Vosc is superimposed is input to the non-inverting input terminal. The comparator 14 outputs an off signal Soff that becomes a predetermined level (high level) when the detection voltage Vdet 'reaches the error voltage Verr (Vdet'> Verr).

  The RS flip-flop 22, the oscillator 24, the adder 26, and the driver circuit 30 constitute a drive unit. The driving unit receives the off signal Soff from the comparator 14 and the clock signal CK from the oscillator 24.

  The drive unit turns off the switching transistor M1 when the off signal Soff reaches a predetermined level (high level), and turns on the switching transistor M1 when the clock signal CK transitions to a predetermined level (high level). That is, the period from the timing of the positive edge of the clock signal CK to the timing at which the detection voltage Vdet ′ corresponding to the peak value of the coil current reaches the error voltage Verr is the ON time of the switching transistor M1.

Specifically, the clock signal CK is input to the set terminal of the RS flip-flop 22, and the off signal Soff is input to the reset terminal.
The output signal Q of the RS flip-flop 22 becomes high level at the positive edge timing when the clock signal CK becomes high level, and becomes low level at the positive edge timing when the off signal Soff becomes high level.

  The driver circuit 30 inverts the output signal Q of the RS flip-flop 22 and supplies it to the gate of the switching transistor M1.

  When the output signal Q becomes high level, the switching transistor M1 is turned on, and when the output signal Q becomes low level, the switching transistor M1 is turned off.

  The control circuit 100 according to the present embodiment is characterized in that it includes a clamp circuit 50 and a clamp voltage setting unit 60. In the present embodiment, the clamp circuit 50 functions as a limiter circuit that clamps the error voltage Verr output from the error amplifier 10 below a predetermined clamp value (hereinafter referred to as a clamp voltage Vcl). The clamp voltage Vcl is set according to the output voltage Vout of the switching regulator 200.

  In the present embodiment, the clamp voltage setting unit 60 receives the feedback voltage Vfb corresponding to the output voltage Vout and generates a clamp setting voltage Vs for setting the clamp voltage Vcl.

The clamp voltage setting unit 60 includes an amplifier AMP2, a variable current source 62, and resistors R21, R22, and R23.
The amplifier AMP2 amplifies the feedback voltage Vfb. The variable current source 62 generates a current Ic corresponding to the output of the amplifier AMP2. The resistor R21 has a potential at one end fixed, and the variable current source 62 is connected to the other end. Therefore, a voltage drop corresponding to the feedback voltage Vfb occurs in the resistor R21. The resistors R22 and R23 divide the voltage Vc generated at the other end of the resistor R21 and output it as a clamp setting voltage Vs.

The clamp circuit 50 includes an operational amplifier 52 and a clamp transistor M3. The clamp transistor M3 is an N-channel MOSFET, and the first terminal (source) is grounded, and the second terminal (drain) is connected to the output terminal of the error amplifier 10.
The operational amplifier 52 has an output terminal connected to the control terminal (gate) of the clamp transistor M 3, a clamp setting voltage Vs applied to the inverting input terminal, and a non-inverting input terminal connected to the output terminal of the error amplifier 10. The clamp circuit 50 clamps the error voltage Verr below the clamp setting voltage Vs.

  That is, Verr is input to the inverting input terminal of the comparator 14 when Verr <Vs, and Vs is input when Verr> Vs.

  FIG. 3 is a circuit diagram showing a configuration example of the clamp circuit 50 and the clamp voltage setting unit 60 of FIG. The amplifier AMP2 includes a differential pair including bipolar transistors Q1, Q2, a tail current source 64 that supplies a constant current to the differential pair (Q1, Q2), and a transistor M10 that operates as a load of the differential pair Q1, Q2. Including M11. Transistors M12 and M13 are connected to the bases of the differential pair Q1 and Q2, and the input voltage range is set low. The constant current sources 66 and 68 bias the transistors M12 and M13. The variable current source 62 is an N-channel MOSFET in which the output voltage of the amplifier AMP2 is applied to the gate.

The operational amplifier 52 is a general differential amplifier including a differential pair including MOS transistors M20 and M21, a current mirror load including transistors M22 and M23, and a tail current source 54. The gate of the transistor M21 is a non-inverting input terminal (+), and the gate of the transistor M20 is an inverting input terminal (−).
Note that the configurations of the clamp circuit 50 and the clamp voltage setting unit 60 are not limited to those shown in FIG.

The above is the configuration of the control circuit 100. Next, the operation of the control circuit 100 will be described.
FIG. 4 is a time chart showing the operation of the control circuit 100 of FIG. In addition, IL of the figure shows the coil current which flows into the output inductor L1.

First, in order to clarify the effect of the control circuit 100 according to the present embodiment, an operation when the clamp circuit 50 is not provided will be described. The waveform at this time is indicated by an alternate long and short dash line Verr ′, a broken line Vout ′, and a broken line IL ′.
At time t0, activation of switching regulator 200 is instructed. At this time, since the output voltage Vout = 0V and the difference from the target voltage Vref (= Vref1 × (R10 + R11) / R11) corresponding to the reference voltage Vref1 is large, the error voltage Verr becomes large.

  Since the ON time of the switching transistor M1 continues until the detection voltage Vdet ′ (simply referred to as Vdet) reaches the error voltage Verr ′, the ON time becomes longer and the coil current IL ′ increases as the error voltage Verr increases. . As a result, a large current flows through the output inductor L1 immediately after startup, which becomes a problem as an inrush current.

Next, the operation of the control circuit 100 having the clamp circuit 50 will be described.
When activation is instructed at time t0, the boosting operation starts and the output voltage Vout starts to rise. Immediately after startup, the output voltage Vout is 0 V, so the clamp setting voltage Vs is set to the lowest value determined by the reference voltage Vref4.

The clamp circuit 50 suppresses the error voltage Verr to be equal to or lower than the clamp setting voltage Vs. As the output voltage Vout increases, the clamp setting voltage Vs (clamp voltage Vcl) increases, and the upper limit value of the error voltage Verr increases. The error voltage Verr rises along the clamp setting voltage Vs.
When the detection voltage Vdet ′ proportional to the coil current IL reaches the error voltage Verr, the switching transistor M1 is turned off. Therefore, the error voltage Verr rises gently, and the on-time of the switching transistor M1 gradually increases. . As a result, the coil current IL gradually increases with time. According to the control circuit 100 according to the embodiment, the switching regulator 200 can be soft-started while suppressing the occurrence of inrush current.
This circuit has an advantage that the circuit can be simplified because it is not necessary to change the reference voltage Vref1.

FIG. 5 is a diagram showing voltage-current characteristics of the switching regulator 200 of FIG. The horizontal axis represents the output current Iout, and the vertical axis represents the output voltage Vout. According to the control circuit 100 according to the embodiment, since the coil current can be limited according to the output voltage Vout, a so-called “f” can be realized. That is, in addition to the soft start operation at the start-up, it is possible to realize suitable overcurrent protection at the normal operation.
In addition, when a large current flows through the output inductor L1 during overload, power loss increases. According to the control circuit 100 of FIG. 1, the power loss can be reduced by realizing the U-shaped characteristic.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the first and second embodiments, the case where the gm amplifier 12 is used as the error amplifier 10 has been described, but a voltage output type operational amplifier may be used. Further, although the step-up switching regulator has been described in the embodiment, the present invention can also be applied to a step-down switching regulator. In this case, the topology of the switching transistor M1 and the output circuit 40 may be changed.

  In the embodiment, the peak current mode (current feedback type) switching regulator that feeds back the coil current and stabilizes the output voltage Vout has been described. However, the present invention is not limited to this. The present invention is also applicable to a voltage feedback switching regulator that feeds back only the output voltage Vout. FIG. 6 is a circuit diagram showing the configuration of the control circuit 100a of the voltage feedback switching regulator according to the embodiment.

  The control circuit 100a includes an error amplifier 10, an oscillator 24, a PWM comparator 70, a driver circuit 30, and a switching transistor M1. The error amplifier 10 compares the output voltage Vout of the switching regulator 200 with a predetermined reference voltage Vref1, and generates an error signal Verr corresponding to the error between the two voltages. The PWM comparator 70 compares the level of the error voltage Verr with the periodic signal Vosc, and generates a pulse signal Sp whose level changes at each intersection. The driver circuit 30 switches the switching transistor M1 on and off based on the pulse signal Sp. The clamp voltage setting unit 60 generates a clamp setting voltage Vs corresponding to the feedback voltage Vfb. The clamp circuit 50 clamps the error voltage Verr below the clamp setting voltage Vs.

  According to the control circuit 100a of FIG. 6, overcurrent protection can be realized in the same manner as the control circuit 100 of FIG.

  Although the case where the switching transistor M1 is built in the control circuit 100 has been described in the embodiment, the switching transistor M1 may be provided outside the control circuit 100 using a discrete element.

  In the present embodiment, the setting of the logic value of the high level and low level of the signal is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

It is a circuit diagram which shows the structure of the switching regulator which concerns on embodiment. It is a block diagram which shows the structure of the electronic device carrying the switching regulator of FIG. FIG. 2 is a circuit diagram illustrating a configuration example of a clamp circuit and a clamp voltage setting unit in FIG. 1. It is a time chart which shows operation | movement of the control circuit of FIG. It is a figure which shows the voltage-current characteristic of the switching regulator of FIG. It is a circuit diagram which shows the control circuit structure of the voltage feedback type switching regulator which concerns on embodiment.

Explanation of symbols

C1 ... Output capacitor, D1 ... Rectifier diode, L1 ... Output inductor, 10 ... Error amplifier, 12 ... gm amplifier, 14 ... Comparator, 16 ... Detection voltage generator, 22 ... RS flip-flop, 24 ... Oscillator, 26 ... Adder , 30 ... Driver circuit, 40 ... Output circuit, 50 ... Clamp circuit, 52 ... Operational amplifier, 60 ... Clamp voltage setting unit, 100 ... Control circuit, 104 ... Switching terminal, 106 ... Feedback terminal, 200 ... Switching regulator, 204 ... Output terminal 210 ... Load 202 ... Input terminal R2 ... Second resistor C2 ... Second capacitor M1 ... Switching transistor M3 ... Clamp transistor

Claims (5)

A control circuit for a switching regulator,
An error amplifier that compares an output voltage of the switching regulator with a predetermined reference voltage and generates an error signal according to an error between the two voltages;
The detection signal corresponding to the coil current flowing through the output inductor of the switching regulator is compared with the error signal from the error amplifier, and an off signal that becomes a predetermined level is output when the value of the detection signal reaches the value of the error signal Comparator to
When the off signal reaches a predetermined level, the switching transistor is turned off, and when the clock signal transitions to the predetermined level, a driving unit that turns on the switching transistor;
A clamp circuit for clamping the error signal output from the error amplifier with a clamp value corresponding to an output voltage of the switching regulator;
A control circuit comprising: The clamp circuit is
A clamp transistor having a first terminal grounded and a second terminal connected to the output terminal of the error amplifier;
An operational amplifier in which an output terminal is connected to the control terminal of the clamp transistor, a setting voltage for setting the clamp value is applied to an inverting input terminal, and a non-inverting input terminal is connected to the output terminal of the error amplifier;
Including
The control circuit according to claim 1, wherein the set voltage is set according to the output voltage. A control circuit for a switching regulator,
An error amplifier that compares an output voltage of the switching regulator with a predetermined reference voltage and generates an error signal according to an error between the two voltages;
A pulse modulation comparator that compares the level of the error signal with a periodic signal and generates a pulse signal whose level transitions at each intersection;
A drive unit for switching on and off of the switching transistor based on the pulse signal;
A clamp circuit for clamping the error signal output from the error amplifier with a clamp value corresponding to an output voltage of the switching regulator;
A control circuit comprising: A switching regulator control method comprising:
Comparing the output voltage of the switching regulator with a predetermined reference voltage and generating an error signal corresponding to an error between the two voltages;
Generating a pulse signal based on the error signal, the duty ratio of which is controlled so that the output voltage matches the reference voltage;
Controlling on and off of the switching transistor based on the pulse signal;
Clamping the error signal with a clamp value corresponding to the output voltage of the switching regulator;
A control method comprising: A switching regulator output circuit including an output inductor and an output capacitor;
A switching transistor connected to the output inductor;
The control circuit according to claim 1 or 3, which controls on and off of the switching transistor;
A switching regulator comprising:

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