JP2014150637A - Step-up switching regulator and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a step-up switching regulator that allows preventing malfunction of an overcurrent protection function while suppressing ripple of an output voltage.SOLUTION: A pulse generator 10 generates a pulse signal S10 for turning on and off a switching element Q1. A flip flop 11 outputs a gate control signal S11 becoming a low level when an output voltage Vexceeds a predetermined value or when a current IL exceeds a predetermined value. A mask signal generating unit 20 outputs a mask signal S20 including a low-level period longer than a low-level period of the pulse signal S10 for every predetermined period synchronized with the pulse signal S10. An AND gate 12A supplies a logical product of the pulse signal S10, the gate control signal S11, and the mask signal S20 to the switching element Q1.

Description

  The present invention relates to a step-up switching regulator, and more particularly to a step-up switching regulator having an overcurrent protection function.

  A chopper boost DC-DC converter (boost converter), which is a type of boost switching regulator, subdivides input direct current into pulse currents by a switching element and connects them to obtain a DC output of a necessary voltage. Is. Such a step-up DC-DC converter includes a switching element, an inductor (choke coil), a capacitor, a diode, and a control circuit that controls on / off of the switching element. In such a step-up DC-DC converter, one having an overcurrent protection function is known in order to prevent the current flowing through the inductor and the switching element from becoming excessive.

  For example, in Patent Document 1, an output voltage of a switching regulator is compared with a predetermined reference voltage, an error amplifier that generates an error signal Verr according to an error between two voltages, and a coil current flowing through an output inductor of the switching regulator. The detection signal corresponding to the error signal from the error amplifier is compared, and when the value of the detection signal reaches the value of the error signal, the comparator outputs an off signal that becomes a predetermined level, and when the off signal becomes the predetermined level, the switching element And when the clock signal transitions to a predetermined level, a drive unit that turns on the switching element, a clamp circuit that clamps the error signal output from the error amplifier with a clamp value according to the output voltage of the switching regulator, A switching regulator is described.

JP 2009-136064 A

  A step-up type switching regulator has a fixed duty of a gate signal for driving a switching element, supplies a gate signal when the detected output voltage is smaller than the target voltage, and the detected output voltage is larger than the target voltage. In some cases, there is a control method in which no gate signal is supplied. According to such a control method, for example, the circuit scale can be reduced as compared with a PWM switching regulator that controls the pulse width of the gate signal in accordance with the output voltage. However, in this control method, no consideration has been given to preventing malfunction of the overcurrent protection function while suppressing ripples.

  The present invention has been made in view of the above points, and in the method of controlling the output voltage according to the supply period and non-supply period of the pulse signal, malfunction of the overcurrent protection function is suppressed while suppressing ripple of the output voltage. An object of the present invention is to provide a step-up switching regulator that can be prevented and a semiconductor device used in the step-up switching regulator.

  In order to achieve the above object, a step-up switching regulator according to the present invention is a step-up switching regulator including an inductor, a rectifier element, a switching element, and an output terminal, and a pulse for turning on and off the switching element. A pulse generator for generating a signal, first control means for turning off the switching element when the magnitude of the output voltage output to the output terminal exceeds a predetermined value, and flowing through the inductor and the switching element Second control means for turning off the switching element when the magnitude of the current exceeds a predetermined value, and longer than the off period of the switching element based on the pulse signal for each predetermined period synchronized with the pulse signal And third control means for turning off the switching element over a period of time.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device for a step-up switching regulator to which an external component including an inductor, a rectifying element, and a capacitive element is connected. A first terminal to which the output is input, a second terminal to which one end of the inductor and / or one end of the rectifying element is connected, a switching element having one end connected to the second terminal, and the switching element A pulse generator that generates a pulse signal for turning on and off, a first control unit that turns off the switching element when the magnitude of the voltage generated at the first terminal exceeds a predetermined value, and the flow through the switching element Second control means for turning off the switching element when the magnitude of the current exceeds a predetermined value, and in synchronization with the pulse signal; At predetermined time intervals, including a third control means for turning off said switching element over a longer period than the off period of the switching elements based on the pulse signal.

  According to the step-up switching regulator according to the present invention, it is possible to prevent the malfunction of the overcurrent protection function while suppressing the ripple of the output voltage.

It is a block diagram which shows the structure of the pressure | voltage rise type switching regulator which concerns on the comparative example of this invention. It is a time chart which shows operation | movement of the pressure | voltage rise type switching regulator which concerns on the comparative example of this invention. It is a block diagram which shows the structure of the step-up type switching regulator which concerns on embodiment of this invention. It is a block diagram which shows the structure of the mask signal generation part which concerns on embodiment of this invention. It is a time chart which shows operation | movement of the mask signal generation part which concerns on embodiment of this invention. It is a time chart which shows operation | movement of the pressure | voltage rise type switching regulator which concerns on embodiment of this invention. It is a block diagram which shows the structure of the other mask signal generation part which concerns on embodiment of this invention. It is a time chart which shows operation | movement of the other mask signal generation part which concerns on embodiment of this invention. It is a block diagram which shows the structure of the step-up type switching regulator which concerns on other embodiment of this invention. It is a time chart which shows operation | movement of the pressure | voltage rise type switching regulator which concerns on other embodiment of this invention. It is a block diagram which shows the structure of the step-up type switching regulator which concerns on embodiment of this invention.

  Before describing the step-up switching regulator according to the embodiment of the present invention, a step-up switching regulator according to a comparative example will be described.

  FIG. 1 is a block diagram showing a configuration of a step-up switching regulator 100 (hereinafter also simply referred to as a regulator 100) according to a comparative example of the present invention that employs the above-described control method using a gate signal with a constant duty.

The regulator 100 includes a pulse generator 10, a flip-flop 11, an AND gate 12, a first comparator 13, a second comparator 14, a power input terminal 15, an output terminal 16, a switching element Q1, and an inductor (choke coil) L1. , A diode D1, a capacitor C1, and resistance elements R1 to R3. The step-up switching regulator 100 boosts the input voltage _VIN supplied to the power supply input terminal 15 to a predetermined target voltage V _T and outputs it as an output voltage _VOUT from the output terminal 16.

One terminal of the inductor L1 is connected to the input terminal 15 to which the input voltage _VIN is supplied. The other terminal of the inductor L1 is connected to the drain of the NMOS transistor constituting the switching element Q1 and the anode of the diode D1. The cathode of the diode D1 is connected to the output terminal 16 and one terminal of the capacitor C1, and the other end of the capacitor C1 is connected to the ground line. When the switching element Q1 is turned on, energy is stored in the inductor L1. On the other hand, when the switching element Q1 is turned off, the inductor L1 releases the stored energy and generates an induced current in a direction that prevents a current change. The induced current flows through the capacitor C1 through the diode D1, thereby charging the capacitor C1. That is, during the off period of switching element Q1, the charge stored in inductor L1 is transported to capacitor C1.

The resistance element R1 is a current detection resistor for converting the current IL flowing through the inductor L1 and the switching element Q1 into a voltage, and is provided between the ground line and the source of the switching element Q1. The potential at the connection point between the switching element Q1 and the resistance element R1 (hereinafter referred to as the first detection voltage V _S1 ) is connected to the inverting input terminal of the first comparator 13. The first reference voltage V _ref1 is supplied to the non-inverting input terminal of the first comparator 13. The first comparator 13 outputs a first determination signal S13 that becomes a low level when the level of the first detection voltage V _S1 input to the inverting input terminal exceeds the level of the first reference voltage V _ref1. This is supplied to the reset input terminal RN of the flip-flop 11.

A voltage dividing circuit composed of resistance elements R2 and R3 connected in series is connected between the output terminal 16 and the ground line. The output voltage _VOUT appearing at the output terminal 16 is divided according to the resistance ratio of the resistance elements R2 and R3. A voltage corresponding to the output voltage V _OUT (hereinafter referred to as the second detection voltage V _S2 ) is derived from the connection point of the resistance elements R 2 and R 3 and supplied to the inverting input terminal of the second comparator 14. A second reference voltage V _ref2 is supplied to the non-inverting input terminal of the second comparator 14. The second comparator 14 outputs a second determination signal S14 that becomes a low level when the level of the second detection voltage V _S2 input to the inverting input terminal exceeds the level of the second reference voltage V _ref2. This is supplied to the data input terminal D of the flip-flop 11. The resistance element R2 is a variable resistance, and the target value of the output voltage _VOUT can be adjusted by the resistance value of the resistance element R2.

The pulse generator 10 receives a reference clock signal _SCK supplied from a clock generator (not shown) and generates a pulse signal S10 having a constant duty synchronized with the reference clock signal _SCK . Supply to the first input terminal. The reference clock signal _SCK is also supplied to the clock input terminal C of the flip-flop 11.

The flip-flop 11 is a D flip-flop that operates using the first determination signal S13 as a reset input, the second determination signal S14 as a data input, and the reference clock signal _SCK as a clock input. The flip-flop 11 holds the signal level of the second determination signal S14 input to the data input terminal D at the rising timing of the reference clock signal _SCK , and outputs the held value from the output terminal Q. When the signal level of the first determination signal S13 input to the reset input terminal RN becomes low level, the output value output from the output terminal Q is reset (that is, set to low level). That is, the flip-flop 11 when the output voltage _{V OUT} of the regulator 100 exceeds a predetermined target voltage _{V T,} or, current flowing through the inductor L1 and the switching element Q1 IL predetermined overcurrent protection operation threshold IF (below the threshold A gate control signal S11 that exhibits a low level when it exceeds (also referred to as IF) and exhibits a high level otherwise is output from the output terminal Q. The gate control signal S11 is supplied to the second input terminal of the AND gate 12.

  The AND gate 12 calculates the logical product of the pulse signal S10 from the pulse generator 10 input to the first input terminal and the gate control signal S11 from the flip-flop 11 input to the second input terminal, The calculation result is output as a gate signal S12. The gate signal S12 is supplied to the gate of the switching element Q1.

That is, in a period when the gate control signal S11 of the flip-flop 11 is at a high level (when the output voltage _VOUT is equal to or lower than the predetermined target voltage V _T and the current IL flowing through the inductor L1 and the switching element Q1 is equal to or lower than the threshold IF). A pulse signal S10 from the pulse generator 10 is supplied to the gate of the switching element Q1 as a gate signal S12. In this case, since the switching element Q1 performs an on / off operation according to the signal level of the pulse signal S10, the output voltage _VOUT rises (boosting operation). On the other hand, the period during which the gate control signal S11 of the flip-flop 11 is at a low level (when the output voltage _VOUT exceeds a predetermined target voltage V _T or the current IL flowing through the inductor L1 and the switching element Q1 exceeds the threshold value IF ), The supply of the pulse signal S10 from the pulse generator 10 to the switching element Q1 is cut off. In this case, since the on / off operation of the switching element Q1 is stopped, the output voltage _VOUT decreases (step-down operation). In this way, supply / non-supply of the pulse signal S10 to the switching element Q1 is controlled by the gate control signal S11.

  Hereinafter, the operation of the regulator 100 having the above-described configuration will be described. FIG. 2 is a time chart showing the operation of the regulator 100.

When the reference clock signal _SCK having a constant period is input, the pulse generator 10 generates a pulse signal S10 having a constant duty synchronized with the reference clock signal _SCK . Since the output voltage V _OUT is less time target voltage V _T output from the output terminal S16 the second determination signal S14 is high level output from the second comparator 14, the first comparator 13 Unless an overcurrent is detected, the gate control signal S11 is at a high level, and the pulse signal S10 is supplied to the switching element Q1 as the gate signal S12. As a result, the switching element Q1 is repeatedly turned on and off in accordance with the pulse signal S10, and the inductor L1 repeatedly accumulates and discharges energy accordingly. The induced current discharged from the inductor L1 flows to the capacitor C1 through the diode D1, and charges the capacitor C1. As a result, the output voltage _VOUT increases (step-up operation).

When the output voltage V _OUT reaches the target voltage V _T , the second determination signal S14 output from the second comparator 14 becomes low level, which causes the gate control signal S11 to become low level, so that the pulse signal S10 Supply to the switching element Q1 is cut off. As a result, the switching element Q1 is turned off, energy storage and discharge by the inductor L1 are stopped, and the output voltage _VOUT gradually decreases (step-down operation).

When the output voltage V _OUT falls below the target voltage V _T , the on / off operation of the switching element Q1 is resumed, and the output voltage V _OUT starts to rise. As described above, the regulator 100 controls the supply and non-supply of the pulse signal S10 having a constant duty according to the output voltage V _OUT by the gate control signal S11, thereby converging the output voltage _VOUT to the target value.

  When the current IL flowing through the inductor L1 and the switching element Q1 exceeds a predetermined overcurrent protection operation threshold value IF, the determination signal S13 output from the first comparator 13 becomes low level, and the gate control signal S11 becomes low level. Therefore, the supply of the pulse signal S10 to the switching element Q1 is interrupted. Thereby, since the switching element Q1 is turned off, heat generation and destruction of the switching element Q1 due to overcurrent can be prevented.

However, the above control method may cause the following problems. That is, if the on-duty of the pulse signal S10 is large, the charge transport from the inductor L1 to the capacitor C1 may be insufficient depending on the magnitude of the input voltage _VIN , the gate manufacturing variation of the switching element Q1, and the like. In such a situation, when the on / off operation of the switching element Q1 is repeated according to the pulse signal S10, the amount of charge accumulated in the inductor L1 becomes larger than the amount of charge released from the inductor L1. As a result, the current IL flowing through the inductor L1 and the switching element Q1 is superimposed and becomes excessive, the overcurrent protection function by the first comparator 13 is activated, and the switching element Q1 is turned off. As a result, the charge accumulated in the inductor L1 flows into the capacitor C1 at a stretch, resulting in a ripple in the output voltage _VOUT . In order to avoid such malfunction of the overcurrent protection function, it is conceivable to increase the threshold IF at which the overcurrent protection function operates. However, the ripple generated in the output voltage _VOUT increases as the threshold IF increases. . Thus, in a control method such as the regulator 100 according to the comparative example, it is difficult to prevent malfunction of the overcurrent protection function while suppressing ripples.

  Embodiments of the present invention will be described below with reference to the drawings.

[First embodiment]
FIG. 3 is a block diagram showing a configuration of the step-up switching regulator 1 according to the first embodiment of the present invention. In FIG. 3, the same reference numerals are assigned to the same components and signals as those of the step-up switching regulator 100 according to the comparative example described above.

A step-up switching regulator 1 (hereinafter also simply referred to as regulator 1) includes a pulse generator 10, a flip-flop 11, an AND gate 12A, a first comparator 13, a second comparator 14, a power input terminal 15, and an output. The terminal 16 includes a switching element Q1, an inductor (choke coil) L1, a diode D1, a capacitor C1, resistance elements R1 to R3, and a mask signal generation unit 20. That is, the regulator 1 according to the present embodiment is the comparative example described above in that the mask signal generation unit 20 and the AND gate 12A have three inputs with the pulse signal S10, the gate control signal S11, and the mask signal S20 as inputs. Different from the regulator 100 according to FIG. Like the regulator 100 according to the comparative example, the regulator 1 according to the present embodiment boosts the input voltage _VIN supplied to the power input terminal 15 to a predetermined target voltage V _T and uses this as the output voltage _VOUT as an output terminal. 16 is output.

  The resistance elements R2 and R3, the second comparator 14, the flip-flop 11, and the AND gate 12A correspond to the first control means in the present invention. The resistor element R1, the first comparator 13, the flip-flop 11, and the AND gate 12A correspond to the second control means in the present invention. The mask signal generator 20 and the AND gate 12A correspond to the third control means in the present invention. The flip-flop 11 corresponds to the first control signal generation unit in the present invention. The mask signal generation unit 20 corresponds to the second control signal generation unit in the present invention. The AND gate 12A corresponds to the logical operation unit in the present invention.

One terminal of the inductor L1 is connected to the input terminal 15 to which the input voltage _VIN is supplied. The other terminal of the inductor L1 is connected to the drain of the NMOS transistor constituting the switching element Q1 and the anode of the diode D1. The cathode of the diode D1 is connected to the output terminal 16 and one terminal of the capacitor C1, and the other terminal of the capacitor C1 is connected to the ground line. When the switching element Q1 is turned on, energy is stored in the inductor L1. On the other hand, when the switching element Q1 is turned off, the inductor L1 releases the stored energy and generates an induced current in a direction that prevents a current change. The induced current flows through the capacitor C1 through the diode D1, thereby charging the capacitor C1. That is, during the off period of switching element Q1, the charge stored in inductor L1 is transported to capacitor C1.

The resistance element R1 is a current detection resistor for converting the current IL flowing through the inductor L1 and the switching element Q1 into a voltage, and is provided between the ground line and the source of the switching element Q1. A potential at the connection point between the switching element Q1 and the resistance element R1 (first detection voltage V _S1 ) is connected to the inverting input terminal of the first comparator 13. The first reference voltage V _ref1 is supplied to the non-inverting input terminal of the first comparator 13. The first comparator 13 outputs a first determination signal S13 that becomes a low level when the level of the first detection voltage V _S1 input to the inverting input terminal exceeds the level of the first reference voltage V _ref1. This is supplied to the reset input terminal RN of the flip-flop 11.

A voltage dividing circuit composed of resistance elements R2 and R3 connected in series is connected between the output terminal 16 and the ground line. The output voltage _VOUT appearing at the output terminal 16 is divided according to the resistance ratio of the resistance elements R2 and R3. A voltage (second detection voltage V _S2 ) corresponding to the output voltage V _OUT is derived from the connection point of the resistance elements R 2 and R 3 and supplied to the inverting input terminal of the second comparator 14. A second reference voltage V _ref2 is supplied to the non-inverting input terminal of the second comparator 14. The second comparator 14 outputs a second determination signal S14 that becomes a low level when the level of the second detection voltage V _S2 input to the inverting input terminal exceeds the level of the second reference voltage V _ref2. This is supplied to the data input terminal D of the flip-flop 11. The resistance element R2 is a variable resistance, and the target value of the output voltage _VOUT can be adjusted by the resistance value of the resistance element R2.

Pulse generator 10 receives as input the reference clock signal S _CK fed from a clock generator (not shown), generates a pulse signal S10 having a constant duty synchronized with the reference clock signal S _CK, which of the AND gates 12A This is supplied to the first input terminal and mask signal generation unit 20. The reference clock signal _SCK is also supplied to the clock input terminal C of the flip-flop 11.

The flip-flop 11 is a D flip-flop that operates using the first determination signal S13 as a reset input, the second determination signal S14 as a data input, and the reference clock signal _SCK as a clock input. The flip-flop 11 holds the signal level of the second determination signal S14 input to the data input terminal D at the rising timing of the reference clock signal _SCK , and outputs the held value from the output terminal Q. When the signal level of the first determination signal S13 input to the reset input terminal RN becomes low level, the output value output from the output terminal Q is reset (that is, set to low level). That is, in the flip-flop 11, the output voltage V _OUT of the switching regulator 100 exceeds a predetermined target voltage V _T , or the current IL flowing through the inductor L1 and the switching element Q1 exceeds a predetermined overcurrent protection operation threshold IF. A gate control signal (first control signal) S11 that sometimes exhibits a low level and otherwise exhibits a high level is output from the output terminal Q. The gate control signal S11 is supplied to the second input terminal of the AND gate 12A.

  The mask signal generation unit 20 receives the pulse signal S10 supplied from the pulse generator 10, and receives a mask signal (for masking the pulse train of the pulse signal S10 supplied as the gate signal S12 to the switching element Q1 every predetermined period ( This is a circuit for generating a second control signal (S20). The mask signal S20 is supplied to the third input terminal of the AND gate 12A.

  The AND gate 12A includes a pulse signal S10 from the pulse generator 10 input to the first input terminal, a gate control signal S11 from the flip-flop 11 input to the second input terminal, and a third input terminal. The logical product of the mask signal S20 from the mask signal generation unit 20 input to is calculated, and the calculation result is output as the gate signal S12. The gate signal S12 is supplied to the gate of the switching element Q1.

  FIG. 4 is a block diagram illustrating a configuration of the mask signal generation unit 20. The mask signal generation unit 20 includes a first flip-flop 21, a second flip-flop 22, and a NAND gate 23. The pulse signal S10 from the pulse generator 10 is input to the clock input terminal CN of the first flip-flop 21. The normal output terminal Q of the first flip-flop 21 is connected to the first input terminal of the NAND gate, and the complementary output terminal QN is connected to its own data input terminal D and the clock input terminal CN of the second flip-flop 22. Has been. The normal output terminal Q of the second flip-flop 22 is connected to the second input terminal of the NAND gate, and the complementary output terminal QN is connected to its own data input terminal D. The first flip-flop 21 and the second flip-flop 22 are D flip-flops that operate at the falling edge of the pulse signal S10 input to the clock input terminal CN.

  FIG. 5 is a time chart showing the operation of the mask signal generation unit 20. In FIG. 5, the output signal S21 of the first flip-flop 21 (first input signal of the NAND circuit 23), the output signal S22 of the second flip-flop 22 (second input signal of the NAND circuit 23), and the mask signal S20 (output signal of the NAND circuit 23) is shown. Since the first flip-flop 21 and the second flip-flop 22 have their complementary output terminals QN connected to their data input terminals D, the first and second flip-flops 21 and 22 are clock input terminals. It operates as a T flip-flop that alternately inverts the output value at every falling edge of the input signal input to CN. As a result, the first flip-flop 21 outputs an output signal S21 having a cycle twice that of the pulse signal S10, and the second flip-flop 22 outputs an output signal having a cycle four times that of the pulse signal S20. S22 is output. The NAND gate 23 calculates the negative logical product of these signals S21 and S22 and outputs the result as a mask signal S20.

  That is, the mask signal generation unit 20 generates the mask signal S20 that is at a low level for a time corresponding to one cycle of the pulse signal S10 at a rate of once per four pulses in the pulse train of the pulse signal S10. In other words, the mask signal generation unit 20 generates the mask signal S20 that is at a low level for a time corresponding to one period of the pulse signal S10 at a time interval corresponding to four periods of the pulse signal S10. As described above, the mask signal generation unit 20 operates as a counter that outputs a low level every time the number of pulses of the pulse signal S10 is counted four.

  The operation of the step-up switching regulator 1 according to this embodiment will be described below. FIG. 6 is a time chart showing the operation of the step-up switching regulator 1 according to the present embodiment.

When the reference clock signal _SCK having a constant period is input, the pulse generator 10 generates a pulse signal S10 having a constant duty synchronized with the reference clock signal _SCK . Since the output voltage V _OUT is less time target voltage V _T output from the output terminal S16 the second determination signal S14 is high level output from the second comparator 14, the first comparator 13 Unless an overcurrent is detected, the gate control signal S11 is at a high level, and a boosting operation is performed.

  On the other hand, the mask signal generator 20 generates a mask signal S20 that is at a low level for a period corresponding to one period of the pulse signal S10 at a time interval corresponding to four periods of the pulse signal S10. During the period when the mask signal S20 is at the low level, the AND gate 12A outputs the gate signal S12 at the low level. Thereby, the supply of the pulse signal S10 to the switching element Q1 is cut off during the period when the mask signal S20 is at the low level. That is, in the boosting operation period in which the switching element Q1 is repeatedly turned on and off, the AND gate 12A outputs the gate signal S12 in which the pulse of the pulse signal S10 is partially thinned (missed) according to the signal level of the mask signal S20. .

  The switching element Q1 maintains an off state during a period when the mask signal S20 is at a low level. Since the period in which the mask signal S20 is at the low level is sufficiently longer than the low level period of the pulse signal S10, the switching element Q1 can ensure a relatively long off period within the boosting operation period in which the on / off operation is repeated. By providing a relatively long off-period within the boosting operation period, it is possible to reliably perform charge transport from the inductor L1 to the capacitor C1, and an overcurrent accompanying current superposition in the boosting switching regulator according to the comparative example described above. The malfunction of the protective function can be prevented.

  As described above, according to the step-up switching regulator 1 according to the first embodiment of the present invention, the relatively long forced-off period of the switching element Q1 is inserted at a constant period within the step-up operation period by the mask signal S20. In this forced off period, charge transport from the inductor L1 to the capacitor C1 can be performed reliably. Thereby, it is possible to prevent an increase in current IL flowing through inductor L1 and switching element Q1 during the boosting operation period. As a result, malfunction of the overcurrent protection function can be prevented, and ripple of the output voltage can be prevented even if the overcurrent protection function activation threshold IF is set high.

  In the above-described embodiment, the case where the mask signal S20 that is at a low level is generated at a rate of once every four pulses in the pulse train of the pulse signal S10 is illustrated. The period of forced off of the switching element Q1) can be changed as appropriate.

  FIG. 7 shows a mask signal generation unit that generates a mask signal S20 ′ that becomes a low level at a rate of once every five pulses in the pulse train of the pulse signal S10 (that is, at a time interval corresponding to five cycles of the pulse signal S10). FIG. 8 is a block diagram showing the configuration of 20 ′, and FIG. 8 is a time chart of input / output signals of the mask signal generation unit 20 ′. The mask signal generation unit 20 'receives the normal outputs of the first to third flip-flops 24, 25, and 26 and the first and second flip-flops 24 and 25, respectively, which use the pulse signal S10 as a common clock input. AND gate 27, NOR gate 28 for inputting the normal output of third flip-flop 26 and the output of AND gate 27, respectively, and complementary outputs of first and second flip-flops 24 and 25, respectively. , And a three-input NAND gate 29 for inputting the normal output of the third flip-flop 26. The output of the NOR gate 28 is used as the data input of the first flip-flop 24, the normal output of the first flip-flop 24 is used as the data input of the second flip-flop 25, and the normal input of the second flip-flop 25 is used. The output is the data input of the third flip-flop 26.

  Thus, even when the masking cycle of the pulse signal S10 by the mask signal S20 is changed, the current IL is increased within the boosting operation period as long as the charge accumulation amount in the inductor L1 does not exceed the discharge amount. Can be prevented.

[Second Embodiment]
FIG. 9 is a block diagram showing the configuration of the step-up switching regulator 2 according to the second embodiment of the present invention. In FIG. 9, the same reference numerals are assigned to components and signals that are the same as or correspond to those of the step-up switching regulator 1 according to the first embodiment. In the following, the step-up switching regulator 2 according to the present embodiment will be described with respect to parts different from the first embodiment, and description of common parts will be omitted.

  In the first embodiment, the mask signal generation unit 20 receives the pulse signal S10 and outputs the mask signal S20, and the AND gate 12A calculates the logical product of the pulse signal S10, the mask signal S20, and the gate control signal S11 as inputs. Thus, the calculation result is output as the gate signal S12. On the other hand, in the second embodiment, the AND gate 12B outputs a pre-gate signal S12B that is a logical product of the pulse signal S10 and the gate control signal S11, and the mask signal generation unit 20A receives the pre-gate signal S12B as an input and receives the mask signal S20. The AND gate 12C calculates the logical product of the mask signal S20 and the pre-gate signal S12B and outputs the result as the gate signal S12. Further, the mask signal generation unit 20A according to the present embodiment counts the number of pulses of the input signal and generates the mask signal S20 that becomes a low level for every predetermined period. The mask signal according to the first embodiment described above. The same as the generation unit 20. The mask signal generation unit 20A according to the present embodiment has a reset input terminal RN for receiving the gate control signal S11 output from the flip-flop 11 as a reset input. When the low-level gate control signal S11 is input to the reset input terminal RN, the mask signal generation unit 20A resets the count operation of the input signal (pre-gate signal S12B in the present embodiment), and then the gate control signal S11 is When the level becomes high, the number of pulses of the input signal is counted from the beginning. The AND gate 12B corresponds to the first logical operation unit in the present invention, and the AND gate 12C corresponds to the second logical operation unit in the present invention.

The operation of the step-up switching regulator 2 according to this embodiment will be described below. FIG. 10 is a time chart showing the operation of the step-up switching regulator 2 according to this embodiment. When the reference clock signal _SCK having a constant period is input, the pulse generator 10 generates a pulse signal S10 having a constant duty synchronized with the reference clock signal _SCK . The flip-flop 11 outputs a gate control signal S11 having a high level or a low level according to the output voltage _VOUT . The AND gate 12B calculates the logical product of the pulse signal S10 and the gate control signal S11 and outputs the result as a pre-gate signal S12B. That is, the pulse signal S10 is output as the pre-gate signal S12B during the period when the gate control signal S11 is at the high level, and the pre-gate signal S12B is at the low level during the period when the gate control signal S11 is at the low level. That is, the boosting operation in which the switching element Q1 is repeatedly turned on and off during the period when the gate control signal S11 is at the high level.

  The mask signal generation unit 20A includes the pregate signal S12B (pulse signal S10) at a rate of once every four pulses of the pulse train of the pregate signal S12B (that is, the pulse signal S10 in the high level period of the gate control signal S11) within the boost operation period. The mask signal S20 that is at a low level only during a period corresponding to one cycle of) is generated. In other words, the mask signal generation unit 20A generates a mask signal S20 that is at a low level for a time corresponding to one period of the pulse signal S10 at a time interval corresponding to four periods of the pulse signal S10. In this way, the mask signal generation unit 20A operates as a counter that outputs a low level every time the number of pulses of the pulse signal S10 is counted four.

  Here, the mask signal generation unit 20A resets the count operation when the gate control signal S11 input to the reset input terminal RN becomes a low level (that is, when the boosting operation is stopped). Thereafter, when the gate control signal S11 becomes a high level and the boosting operation is resumed, the mask signal generation unit 20A starts counting the number of pulses of the pre-gate signal S12B (pulse signal S10) from 1 again. That is, the mask signal generation unit 20 sets the first pulse of the pulse train of the pre-gate signal S12B (pulse signal S10) generated after the restart of the boosting operation as the first count. As a result, after the boosting operation is resumed, the period until the mask signal S20 first becomes a low level can always be constant.

  The AND gate 12C outputs a logical product of the pre-gate signal S12B and the mask signal S20 as the gate signal S12.

  As a result, as in the case of the first embodiment, the gate signal S12 in a state where the pulse of the pulse signal S10 is partially thinned out by the mask signal S20 within the boosting operation period is obtained.

  Thus, according to the step-up switching regulator 2 according to the present embodiment, as in the case of the first embodiment, the forced off period of the switching element Q1 that is relatively long within the step-up operation period by the mask signal S20 is a constant cycle. Therefore, charge transport from the inductor L1 to the capacitor C1 can be reliably performed in this forced off period. Thereby, it is possible to prevent an increase in current IL flowing through inductor L1 and switching element Q1 during the boosting operation period. As a result, malfunction of the overcurrent protection function can be prevented, and ripple of the output voltage can be prevented even if the overcurrent protection function activation threshold IF is set high.

  Also, according to the boosting switching regulator 2 according to the present embodiment, the mask signal generation unit 20A resets the count operation according to the signal level of the gate control signal S11. The period until the level becomes low can always be constant. That is, the period from when the boosting operation is restarted until the switching element Q1 is forcibly turned off based on the mask signal S20 can be made constant. Thereby, even when the boosting operation occurs intermittently, the forced off period can be always inserted at the same timing. Therefore, the ripple waveform in the output voltage can always be an approximate waveform. For example, even when a periodic fluctuation load that is asynchronous with the reference clock of the regulator is connected to the regulator, a series of boosting operations according to the fluctuation period of the load can be performed. This is advantageous when the present regulator is used in an application in which there is an original periodic operation like a driving power source of a liquid crystal panel and the power supply fluctuation characteristics are expected to be the same in each cycle.

  In each of the above embodiments, the mask signal generators 20, 20 ′, and 20A generate the mask signal S20 that exhibits a low level over a period corresponding to one cycle of the pulse signal, thereby increasing the boost operation period. The case where a forced off period corresponding to one cycle of the pulse signal S10 is inserted is illustrated, but the present invention is not limited to this. That is, the forced off period may be set to be an integral multiple (2 times, 3 times, 4 times,...) Of the period of the pulse signal.

  4 and 7 illustrate the configurations of the mask signal generation units 20 and 20 ', but the configuration is not limited to these. The circuit configuration of the mask signal generation unit can be modified as appropriate as long as it can realize a function of generating an output signal that exhibits a constant signal level at a constant period in synchronization with the input signal.

  In each of the above embodiments, the mask signal generators 20 and 20A are exemplified as a fixed counter circuit that always counts a fixed number of pulses. However, the control signal is supplied from the outside to control the count number. You may comprise so that it can do. According to such a configuration, the forced off period can be inserted at an arbitrary timing by the control signal.

In each of the above embodiments, the case where the output voltage V _OUT and the current IL are controlled by using a comparator, a flip-flop, an AND gate, etc. is exemplified, but the present invention is not limited to this, and the same function is provided. It is good also as employ | adopting the other structure implement | achieved.

  Further, in each of the above embodiments, the case where the on / off control of the switching element Q1 is performed by the pulse signal S10 having a constant duty has been exemplified, but the present invention is applied to a method of controlling the on / off of the switching element Q1 by the pulse signal whose duty changes. It is also possible to do.

  As shown in FIG. 11, the step-up switching regulator 1 according to the first embodiment can be configured by a combination of a semiconductor device 50 and an external component 60. The external component 60 includes an inductor L1, a diode D1, and a capacitor C1. The semiconductor device 50 is connected to a first terminal 52 connected to the output terminal 16 of the step-up switching regulator 1 (that is, a connection point between the cathode of the diode D1 and the capacitor C1), and a connection point between the inductor L1 and the diode D1. And a second terminal 51. The first terminal 52 is connected to one end of the resistance element R2. The second terminal 51 is connected to the drain of the switching element Q1. The semiconductor device 50 corresponds to the semiconductor device of the present invention. Note that the step-up switching regulator 2 according to the second embodiment can be similarly configured by a combination of a semiconductor device and external components.

1, 2, 100 Step-up switching regulator 10 Pulse generator 11 Flip-flop 12, 12A, 12B, 12C AND gate 13 First comparator 14 Second comparator 15 Power supply input terminal 16 Output terminal 20, 20A Mask signal generation Part S10 Pulse signal S11 Gate control signal S12 Gate signal S12B Pre-gate signal S20 Mask signal Q1 Switching element L1 Inductor C1 Capacitor R1-R3 Resistance element

Claims (11)

A step-up switching regulator comprising an inductor, a rectifying element, a switching element, and an output terminal,
A pulse generator for generating a pulse signal for turning on and off the switching element;
First control means for turning off the switching element when the magnitude of the output voltage output to the output terminal exceeds a predetermined value;
Second control means for turning off the switching element when the magnitude of the current flowing through the inductor and the switching element exceeds a predetermined value;
Third control means for turning off the switching element for a period longer than an off period of the switching element based on the pulse signal for each predetermined period synchronized with the pulse signal;
Boost type switching regulator including The inductor has one end connected to a power input terminal,
The output terminal is connected to the other end of the inductor via the rectifying element,
The step-up switching regulator according to claim 1, wherein the switching element is connected to the other end of the inductor.   3. The step-up switching regulator according to claim 1, wherein each of the first to third control units cuts off supply of the pulse signal to the switching element when the switching element is turned off.   4. The step-up switching regulator according to claim 3, wherein the third control unit cuts off the supply of the pulse signal to the switching element every period corresponding to a period in which a predetermined number of pulses occur in the pulse signal.   5. The step-up switching regulator according to claim 4, wherein the third control unit cuts off the supply of the pulse signal to the switching element for a period corresponding to a period that is an integral multiple of the period of the pulse signal. When the magnitude of the output voltage exceeds a predetermined value, or when the current flowing through the inductor and the switching element exceeds a predetermined value, the first signal level is exhibited; otherwise, the first signal level A first control signal generator for generating a first control signal exhibiting a different second signal level;
A second control signal that exhibits a first signal level every period corresponding to a period in which a predetermined number of pulses occur in the pulse signal, and that exhibits a second signal level different from the first signal level otherwise. A second control signal generator to generate;
Performing a logical operation on the pulse signal, the first control signal, and the second control signal, and during the period in which both the first and second control signals exhibit the second signal level, The step-up switching regulator according to claim 5, further comprising a logic operation unit that outputs a pulse train and supplies the output pulse train to the switching element. When the magnitude of the output voltage exceeds a predetermined value or when the current flowing through the inductor and the switching element exceeds a predetermined value, the first signal level is exhibited. A first control signal generator for generating a first control signal exhibiting a different second signal level;
A first logical operation unit that performs a logical operation of the pulse signal and the first control signal and outputs a pulse train of the pulse signal in a period in which the first control signal exhibits the second signal level; ,
In the pulse train of the pulse signal output from the first logic operation unit, the first signal level is exhibited every period corresponding to a period in which a predetermined number of pulses are generated, and other than that, the first signal level is different. A second control signal generator for generating a second control signal exhibiting a second signal level;
Performing a logical operation of the second control signal and the output signal of the first logical operation unit, the pulse signal during a period in which both the first and second control signals exhibit the second signal level The step-up switching regulator according to claim 5, further comprising: a second logical operation unit that outputs the pulse train of the first and second pulses and supplies the output pulse train to the switching element.   The second control signal generation unit has a constant time from when the first control signal transitions to the second signal level to when the second control signal transitions to the first signal level. The step-up switching regulator according to claim 7, wherein the second control signal is generated as follows.   The second control signal generation unit outputs the first signal level when the count value of the number of pulses of the pulse signal output from the first logic operation unit becomes the predetermined number, and The step-up switching regulator according to claim 8, wherein the count value is reset when one control signal becomes the first signal level.   The step-up switching regulator according to claim 1, wherein the pulse generator generates a pulse signal having a constant duty. A step-up switching regulator semiconductor device to which external components including an inductor, a rectifying element, and a capacitive element are connected,
A first terminal to which the output of the switching regulator is input;
A second terminal to which one end of the inductor or one end of the rectifying element is connected;
A switching element having one end connected to the second terminal;
A pulse generator for generating a pulse signal for turning on and off the switching element;
First control means for turning off the switching element when the magnitude of the voltage generated at the first terminal exceeds a predetermined value;
Second control means for turning off the switching element when the magnitude of the current flowing through the switching element exceeds a predetermined value;
Third control means for turning off the switching element for a period longer than an off period of the switching element based on the pulse signal for each predetermined period synchronized with the pulse signal;
A semiconductor device including: