JP2009135635A - Piezoelectric component - Google Patents

Piezoelectric component Download PDF

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Publication number
JP2009135635A
JP2009135635A JP2007308326A JP2007308326A JP2009135635A JP 2009135635 A JP2009135635 A JP 2009135635A JP 2007308326 A JP2007308326 A JP 2007308326A JP 2007308326 A JP2007308326 A JP 2007308326A JP 2009135635 A JP2009135635 A JP 2009135635A
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piezoelectric
piezoelectric element
saw
substrate
piezoelectric component
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JP5268335B2 (en
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Seiji Abe
誠二 阿部
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Nihon Dempa Kogyo Co Ltd
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Nihon Dempa Kogyo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize package size of a piezoelectric component and to prevent intrusion of sealing resin into a hollow part. <P>SOLUTION: The piezoelectric component includes a substrate 6 consisting of an insulating material; a first piezoelectric element 2 mounted on the substrate 6 by a flip-chip; a second piezoelectric element 3, mounted on the top or the bottom in the perpendicular direction, rather than the first piezoelectric element 2; and the sealing resin 1 which seals and packages the first piezoelectric element 2 and the second piezoelectric element 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、圧電部品、例えば、２つ以上の異なる周波数の弾性表面波（ＳＡＷ）チップを実装基板上にバンプを用いて鉛直方向に積み重ねて搭載した後、積み重ねたＳＡＷチップをシート樹脂によりＳＡＷチップ周辺に気密空間（中空部）を形成するように封止したＳＡＷデバイス、に関する。   In the present invention, piezoelectric components, for example, two or more surface acoustic wave (SAW) chips having different frequencies are stacked on a mounting substrate in the vertical direction using bumps, and then the stacked SAW chips are SAWed by sheet resin. The present invention relates to a SAW device sealed so as to form an airtight space (hollow part) around a chip.

弾性表面波デバイス（ＳＡＷデバイス）は、水晶、タンタル酸リチウム等の圧電基板上に櫛歯状電極（ＩＤＴ電極）、及び接続パッド等の電極パターンを配置した構成を備え、例えばＩＤＴ電極に高周波電界を印加することによって、弾性表面波を励起し、弾性表面波を圧電作用によって高周波電界に変換し、フィルタ特性を得るものとして携帯電話機などに搭載され使用される。   A surface acoustic wave device (SAW device) has a configuration in which electrode patterns such as comb-like electrodes (IDT electrodes) and connection pads are arranged on a piezoelectric substrate such as crystal or lithium tantalate. Is applied to a cellular phone or the like to excite a surface acoustic wave, convert the surface acoustic wave into a high-frequency electric field by a piezoelectric action, and obtain filter characteristics.

ここで、ＳＡＷデバイスを利用するデュアルフィルタやデュプレクサ等の電子機器では、２つ以上の異なる周波数をもつＳＡＷチップを１個のＳＭＤ（表面実装型）製品にパッケージする際、従来は、図２に示すように、パッケージ内に平面状に並べて搭載していた。   Here, when electronic devices such as a dual filter and a duplexer using a SAW device are packaged with two or more SAW chips having different frequencies in one SMD (surface mount type) product, conventionally, as shown in FIG. As shown in the figure, they were mounted side by side in a flat form in the package.

すなわち、図２に示す従来のＩＤＴ電極パターン２８，２９を形成した２つ以上の異なる周波数をもつＳＡＷチップ２２ａ，２２ｂを平面状に並べて、セラミックシート基板２６に配線電極３１ａ，３２ａとバンプ２４ａ，２４ｂを介してフェースダウンでフリップチップ実装し、次いでシート樹脂により樹脂封止して中空部Ｓをそれぞれ形成するようにし、さらに、配線電極３１ａ，３２ａを貫通電極３０ａ，３０ｂを介して端子電極３１ｂ，３２ｂに接続してデュアル型のＳＡＷデバイスＤを構成して使用している。   That is, the SAW chips 22a and 22b having two or more different frequencies on which the conventional IDT electrode patterns 28 and 29 shown in FIG. 2 are formed are arranged in a plane, and the wiring electrodes 31a and 32a and the bumps 24a and 24a are arranged on the ceramic sheet substrate 26. Flip chip mounting is performed face down through 24b, and then the resin is sealed with a sheet resin to form the hollow portions S, and the wiring electrodes 31a and 32a are connected to the terminal electrodes 31b through the through electrodes 30a and 30b. , 32b, a dual SAW device D is configured and used.

しかしながら、この種の従来のＳＡＷデバイスＤでは、異なる周波数をもつ例えば、２個のＳＡＷチップ２２ａ，２２ｂを樹脂封止してパッケージする際、これらのＳＡＷチップ２２ａ，２２ｂをパッケージ内に平面状に並べて搭載していたため、各ＳＡＷチップ２２ａ，２２ｂの縦横の外形寸法に加えて、各チップ２２ａ，２２ｂ間に、図２に示すＳＡＷチップの搭載精度を勘案したクリアランスｇ3が必要であった。そのため、パッケージ（ＳＡＷデバイスＤ）の所要表面積が大きくなり、パッケージ全体の小型化が極めて困難であった。 However, in this type of conventional SAW device D, for example, when two SAW chips 22a and 22b having different frequencies are packaged by resin sealing, these SAW chips 22a and 22b are planarized in the package. because they were mounted side by side, each SAW chip 22a, in addition to the external dimensions of the longitudinal and lateral 22b, each chip 22a, between 22b, were necessary clearance g 3 in consideration of the mounting accuracy of the SAW chip shown in FIG. Therefore, the required surface area of the package (SAW device D) is increased, and it is extremely difficult to reduce the size of the entire package.

また、一個のＳＡＷチップ内に、例えば２つ以上の周波数の異なるＩＤＴ電極パターンを形成すれば、パッケージ全体の小型化が可能となるが、それぞれの周波数によりＳＡＷデバイスの製造条件が異なるため、一方のＩＤＴ電極パターンの周波数特性が良好であっても、他方のＩＤＴ電極パターンの周波数特性が不良となり、ＳＡＷチップ全体として不良となってしまい、ＳＡＷチップの良品歩留りが悪くなる、問題点があった。   Further, if, for example, two or more IDT electrode patterns having different frequencies are formed in one SAW chip, the entire package can be reduced in size. However, since the manufacturing conditions of the SAW device differ depending on the respective frequencies, Even if the frequency characteristic of the IDT electrode pattern is good, the frequency characteristic of the other IDT electrode pattern is poor, and the SAW chip as a whole is defective, and the yield of non-defective products of the SAW chip is deteriorated. .

また、中空部Ｓ内への封止樹脂の流れ込みを阻止するために、図２に示すように、ＳＡＷチップ２２ａ，２２ｂに隣接して樹脂からなる鎖線で示すダム３３を設けていたが、ダムに用いる樹脂自体が高価であるため、ダム３３を設けたＳＡＷデバイスは採算がとれない等の問題点があった。   In order to prevent the sealing resin from flowing into the hollow portion S, a dam 33 indicated by a chain line made of resin is provided adjacent to the SAW chips 22a and 22b as shown in FIG. Since the resin used in the above is expensive, there is a problem that the SAW device provided with the dam 33 cannot be profitable.

本発明が解決しようとする課題は、圧電部品のパッケージサイズの小型化と電極パターン面周辺に形成する中空部形成の容易化である。   The problem to be solved by the present invention is to reduce the package size of the piezoelectric component and facilitate the formation of the hollow portion formed around the electrode pattern surface.

上記した課題を解決するために、本発明の圧電部品は、絶縁材料からなる基板と、該基板にフリップチップ実装された第１の圧電素子と、該第１の圧電素子に対して鉛直方向に上あるいは下に実装された第２の圧電素子と、前記第１の圧電素子及び第２の圧電素子を封止してパッケージ化する封止樹脂と、からなることを特徴とする。   In order to solve the above-described problems, a piezoelectric component of the present invention includes a substrate made of an insulating material, a first piezoelectric element flip-chip mounted on the substrate, and a vertical direction with respect to the first piezoelectric element. It is characterized by comprising a second piezoelectric element mounted above or below, and a sealing resin for sealing the first piezoelectric element and the second piezoelectric element into a package.

圧電部品のパッケージサイズの小型化が達成され、また中空部への封止樹脂の侵入が有効に阻止される。   The package size of the piezoelectric component can be reduced, and the sealing resin can be effectively prevented from entering the hollow portion.

以下、本発明の圧電部品を、表面実装型弾性表面波デバイス（以下、“ＳＡＷデバイス”という）の実施例について詳細に説明する。   Hereinafter, the piezoelectric component of the present invention will be described in detail with respect to an embodiment of a surface-mount type surface acoustic wave device (hereinafter referred to as “SAW device”).

図１は、本発明の圧電部品の実施例であるＳＡＷデバイスＤの縦断面図を示す。   FIG. 1 shows a longitudinal sectional view of a SAW device D which is an embodiment of the piezoelectric component of the present invention.

本実施例のＳＡＷデバイスは、デュアルフィルタやデュプレクサ等の２つ以上の異なった周波数帯域を必要とするＳＭＤ型のＳＡＷフィルタに用いられる。   The SAW device of the present embodiment is used for an SMD type SAW filter that requires two or more different frequency bands, such as a dual filter or a duplexer.

このＳＡＷデバイス（圧電部品）Ｄは、セラミックシート６ａ，６ｂを数枚（例えば、２枚）積層して形成したセラミックシート基板６と、このセラミックシート基板６の上面５に第１のＳＡＷチップ２の四角に位置された金（Ａｕ）バンプ４ａと配線電極１１ａを介してフリップチップ・ボンディング（フェース・ダウン）された第１のＳＡＷチップ２（上段のＳＡＷチップ）と、この第１のＳＡＷチップ２の主面に形成されたＳＡＷチップ電極（ＩＤＴ）パターン９と、セラミックシート基板６のキャビティ底面７に第２のＳＡＷチップ３の四角に位置された金（Ａｕ）バンプ４ｂと配線電極１２ａを介してフリップチップ・ボンディング（フェース・ダウン）された第２のＳＡＷチップ３と、この第２のＳＡＷチップ３の主面に形成されたＳＡＷチップ電極（ＩＤＴ）パターン８と樹脂封止１とからなり、前述した配線電極１１ａ，１２ａは、それぞれ貫通電極１０ａ，１０ｂを介して端子電極１１ｂ，１２ｂに電気的に接続されている。   This SAW device (piezoelectric component) D includes a ceramic sheet substrate 6 formed by laminating several ceramic sheets 6 a and 6 b (for example, two), and a first SAW chip 2 on the upper surface 5 of the ceramic sheet substrate 6. First SAW chip 2 (upper SAW chip) flip-chip bonded (face-down) via gold (Au) bumps 4a and wiring electrodes 11a positioned in the square of the first and second SAW chips 2, the SAW chip electrode (IDT) pattern 9 formed on the main surface, and the gold (Au) bump 4 b and the wiring electrode 12 a positioned on the square of the second SAW chip 3 on the cavity bottom surface 7 of the ceramic sheet substrate 6. And a second SAW chip 3 flip-chip bonded (face down), and formed on the main surface of the second SAW chip 3. Was made SAW chip electrodes (IDT) pattern 8 and the resin sealing 1 Tokyo, wiring electrode 11a described above, 12a, respectively through electrodes 10a, the terminal electrodes 11b through 10b, are electrically connected to 12b.

とくに、本発明の圧電部品の実施例であるＳＡＷデバイスＤでは、セラミックシート基板６ｂの上面５と上段のＳＡＷチップ２の電極パターン面２ａとの間に隙間ｇ1を形成し、その隙間ｇ1の寸法を１０μｍ以下にする。これにより、エポキシ樹脂等からなるシート樹脂をホットプレート等で所定の温度に加熱して軟化させ、型材で押圧して樹脂封止する際、この微少隙間ｇ1により、軟化した封止樹脂が、ＳＡＷチップ２，３の電極パターン面８，９に流れ込むことが阻止され、ＳＡＷチップ電極パターン８，９と封止樹脂１との接触による電気特性不良の発生を回避できる。 In particular, in the SAW device D which is an embodiment of the piezoelectric component of the present invention, a gap g 1 is formed between the upper surface 5 of the ceramic sheet substrate 6b and the electrode pattern surface 2a of the upper SAW chip 2, and the gap g 1 The dimension is set to 10 μm or less. Thus, a sheet resin made of epoxy resin or the like is softened by heating to a predetermined temperature at a hot plate or the like, during the resin sealing by pressing a mold member, by the small gap g 1, it softened sealing resin, It is prevented from flowing into the electrode pattern surfaces 8 and 9 of the SAW chips 2 and 3, and it is possible to avoid the occurrence of defective electrical characteristics due to the contact between the SAW chip electrode patterns 8 and 9 and the sealing resin 1.

また、仮に軟化した樹脂１ａが隙間ｇ1から中空部Ｓ内へ流れ込んでしまった場合でも、下段のＳＡＷチップ３の電極パターン８をセラミックシート基板６ｂの上面５よりも高く配置することにより、セラミックシート基板６ａに形成された凹部（キャビティ）７に流れ込んだ樹脂１ａがこの凹部７に溜まり、ＳＡＷチップ２，３の電極パターン面８，９と接触することがなく、容易に所望の中空部Ｓを電極パターン８の周辺に形成することができるようになる。また、上段のＳＡＷチップ２の電極パターン面９と下段のＳＡＷチップ３の主面（上面）との間には、１０μｍ程度の隙間ｇ2を設け、電極パターン面９とＳＡＷチップ３の上面との接触を回避するようにしてある。 Also, even if tentatively softened resin 1a is had flowed through the gap g 1 into the hollow portion S, by placing higher than the upper surface 5 of the electrode pattern 8 of the lower SAW chip 3 ceramic sheet substrate 6b, ceramic The resin 1a that has flowed into the recess (cavity) 7 formed in the sheet substrate 6a accumulates in the recess 7 and does not come into contact with the electrode pattern surfaces 8 and 9 of the SAW chips 2 and 3, so that the desired hollow portion S can be easily obtained. Can be formed around the electrode pattern 8. Further, a gap g 2 of about 10 μm is provided between the electrode pattern surface 9 of the upper SAW chip 2 and the main surface (upper surface) of the lower SAW chip 3, and the electrode pattern surface 9 and the upper surface of the SAW chip 3 To avoid contact.

通常、多数のＳＡＷデバイスＤをまとめて樹脂封止し、その後、ダイシングマークに沿ってダイシング・ソー等により個々のＳＡＷデバイスＤ（個片）に分割する。   Usually, a large number of SAW devices D are collectively sealed with resin, and then divided into individual SAW devices D (individual pieces) along a dicing mark by a dicing saw or the like.

本発明の圧電部品は、２つ以上の異なる周波数の圧電素子を必要とする、デュアルフィルタ、デュプレクサ、等に利用可能である。   The piezoelectric component of the present invention can be used in dual filters, duplexers, and the like that require two or more different frequency piezoelectric elements.

本発明の圧電部品の実施例である複数のＳＡＷチップを上下に二段に積み重ねたＳＡＷデバイスの縦断面図である。1 is a longitudinal sectional view of a SAW device in which a plurality of SAW chips, which are embodiments of a piezoelectric component of the present invention, are stacked in two stages up and down. 複数のＳＡＷチップを平面状に搭載した従来のＳＡＷデバイスの縦断面図である。It is a longitudinal cross-sectional view of the conventional SAW device which mounted the several SAW chip | tip in planar shape.

符号の説明Explanation of symbols

１ 封止樹脂
２ 上段のＳＡＷチップ
３ 下段のＳＡＷチップ
４ バンプ
５ セラミックシート基板の上面
６ セラミックシート基板
７ 凹部（キャビティ）
８ ＳＡＷチップ電極（ＩＤＴ）パターン
９ ＳＡＷチップ電極（ＩＤＴ）パターン
１０ 貫通電極
１１ａ 配線電極
１１ｂ 端子電極
１２ 配線電極
Ｄ 圧電部品（ＳＡＷデバイス）
Ｓ 中空部（キャビティ） DESCRIPTION OF SYMBOLS 1 Sealing resin 2 Upper SAW chip 3 Lower SAW chip 4 Bump 5 Upper surface of ceramic sheet substrate 6 Ceramic sheet substrate 7 Recess (cavity)
8 SAW chip electrode (IDT) pattern 9 SAW chip electrode (IDT) pattern 10 Through electrode 11a Wiring electrode 11b Terminal electrode 12 Wiring electrode D Piezoelectric component (SAW device)
S Hollow part (cavity)

Claims (8)

絶縁材料からなる基板と、
該基板にフリップチップ実装された第１の圧電素子と、
該第１の圧電素子に対して鉛直方向に上あるいは下に実装された第２の圧電素子と、
前記第１の圧電素子及び第２の圧電素子を封止してパッケージ化する封止樹脂と、
からなることを特徴とする圧電部品。 A substrate made of an insulating material;
A first piezoelectric element flip-chip mounted on the substrate;
A second piezoelectric element mounted vertically or vertically with respect to the first piezoelectric element;
A sealing resin for sealing and packaging the first piezoelectric element and the second piezoelectric element;
A piezoelectric component comprising: 下段に実装された前記第２の圧電素子の電極パターン面よりも前記基板の上面が高くなるよう実装される請求項１に記載の圧電部品。   2. The piezoelectric component according to claim 1, wherein the piezoelectric component is mounted such that an upper surface of the substrate is higher than an electrode pattern surface of the second piezoelectric element mounted on the lower stage. 上段に実装された前記第１の圧電素子の電極パターン面と前記基板の上面の間に微少隙間が形成され、該微少隙間の間隔が１０μｍ未満である請求項１に記載の圧電部品。   2. The piezoelectric component according to claim 1, wherein a minute gap is formed between the electrode pattern surface of the first piezoelectric element mounted on the upper stage and the upper surface of the substrate, and the interval of the minute gap is less than 10 μm. 下段に実装された前記第２の圧電素子に対向する前記基板に凹所が形成され、前記微少隙間から流れ込んだ封止樹脂を溜めるようにした請求項１に記載の圧電部品。   2. The piezoelectric component according to claim 1, wherein a recess is formed in the substrate facing the second piezoelectric element mounted in a lower stage, and the sealing resin flowing from the minute gap is collected. 前記第１の圧電素子の電極パターンの周波数と前記第２の圧電素子の電極パターンの周波数とが、異なる請求項１に記載の圧電部品。   2. The piezoelectric component according to claim 1, wherein a frequency of the electrode pattern of the first piezoelectric element is different from a frequency of the electrode pattern of the second piezoelectric element. 前記基板がセラミックシート基板からなる請求項１に記載の圧電部品。   The piezoelectric component according to claim 1, wherein the substrate is a ceramic sheet substrate. 前記第１の圧電素子及び前記第２の圧電素子がＳＡＷチップからなる請求項１に記載の圧電部品。   The piezoelectric component according to claim 1, wherein the first piezoelectric element and the second piezoelectric element are SAW chips. 前記圧電部品がＳＡＷデバイスである請求項１に記載の圧電部品。   The piezoelectric component according to claim 1, wherein the piezoelectric component is a SAW device.
JP2007308326A 2007-11-29 2007-11-29 Piezoelectric parts Expired - Fee Related JP5268335B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9264016B2 (en) 2012-11-15 2016-02-16 Nihon Dempa Kogyo Co., Ltd. Piezoelectric component having a cover layer including resin that contains translucent filler

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040939A (en) * 1998-07-24 2000-02-08 Mitsubishi Electric Corp Surface acoustic wave device
JP2001156585A (en) * 1999-11-30 2001-06-08 Kyocera Corp Surface acoustic wave device
JP2004064732A (en) * 2002-06-03 2004-02-26 Murata Mfg Co Ltd Surface acoustic wave device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040939A (en) * 1998-07-24 2000-02-08 Mitsubishi Electric Corp Surface acoustic wave device
JP2001156585A (en) * 1999-11-30 2001-06-08 Kyocera Corp Surface acoustic wave device
JP2004064732A (en) * 2002-06-03 2004-02-26 Murata Mfg Co Ltd Surface acoustic wave device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9264016B2 (en) 2012-11-15 2016-02-16 Nihon Dempa Kogyo Co., Ltd. Piezoelectric component having a cover layer including resin that contains translucent filler

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