JP2009135352A - Semiconductor integrated circuit, and voltage-controlled oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS varactor having short transition time from a stand-by state up to an optional capacity stable state. <P>SOLUTION: When a semiconductor integrated circuit is provided a with control circuit for controlling a potential difference obtained by subtracting the potential of a well region from the potential of an electrode to zero and more during the operation stand-by period of a MOS varactor element having an N-well, the transition time from an operation stand-by state to an optional capacity stable state can be shortened. When the semiconductor integrated circuit is provided with a control circuit for controlling the potential difference obtained by subtracting the potential of the well area from the potential of the electrode to zero and less during the operation stand-by period of a MOS varactor element having a P well, transition time from the operation stand-by state to an optional capacity stable state can be shortened. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit (LSI) incorporating a MOS varactor element.

  A varactor, which is a variable capacitor capable of changing a capacitance in accordance with a capacitance control voltage to be applied, is a basic element constituting a semiconductor integrated circuit. For example, an LC resonance type voltage controlled oscillator is combined with an inductor. It is used to form a circuit such as (LC-VCO). The oscillation frequency is given by Equation 1 where L is the inductance of the inductor and C is the capacitance of the variable capacitor.

When a varactor is formed on a silicon substrate, a MOS type (Metal Oxide Semiconductor) structure is widely known.
FIG. 1 is a sectional view of a varactor (MOS varactor element) 10 having a MOS structure.
In FIG. 1, an N well (N-well) 12 is formed on the surface of a P type silicon substrate (P-sub) 11, and N type diffusion regions (N +) 13 and 14 are formed on the surface of the N well 12. Formed in isolation. A gate insulating film 15 is formed immediately above the region between one N-type diffusion region 13 and the other N-type diffusion region 14 on the N well 12. Is provided with a gate electrode 16. The two isolated N-type diffusion regions 13 and 14 are connected to the well terminal 17. The potential of the well terminal 17 is set to a well potential Vw. The gate electrode 16 is connected to the gate terminal 18. The potential of the gate terminal 18 is set to the gate potential Vg. With this connection, in the MOS varactor element 10, a capacitor is formed between the gate electrode 16 and the N well 12.

When the capacitance control voltage (Vg−Vw) applied between the gate terminal 18 and the well terminal 17 of the MOS varactor element 10 of FIG. 1 is sufficiently increased, electrons as carriers are collected immediately below the gate electrode 16 on the surface of the N well 12. Since this region becomes conductive, the thickness of the substantial insulating region under the gate electrode 16 becomes equal to the thickness of the gate insulating film 15, and the capacitance value between the gate electrode 16 and the N well 12 is the maximum. Value. Even if the capacitance control voltage (Vg−Vw) is further increased, the substantial thickness of the insulating region under the gate electrode 16 does not change, so that the capacitance value does not change.
When the capacitance control voltage (Vg−Vw) is lowered from this state, a depletion layer grows in a region immediately below the gate insulating film 15 on the surface of the N well 12, and the thickness of the substantial insulating region under the gate electrode 16 is increased. However, the capacitance value is reduced because the thickness of the gate insulating film 15 is added to the thickness of the depletion layer. When the capacitance control voltage (Vg−Vw) is sufficiently low, the depth of the depletion layer is maximized and the capacitance value is stabilized. The maximum depth of this depletion layer is determined by the impurity dopant concentration on the substrate surface.

When the capacitance control voltage (Vg−Vw) is further lowered, an inversion layer is formed on the surface of the N well 12 by holes that are minority carriers. However, even if an inversion layer is formed by holes, the depth of the depletion layer immediately below the inversion layer does not change, so the capacitance value does not change.
In this way, by changing the capacitance control voltage (Vg−Vw) applied to the MOS varactor element 10, a variable capacitance can be realized (see, for example, Patent Document 1).

FIG. 2 is a sectional view of a varactor (MOS varactor element) 20 having a MOS structure.
In FIG. 2, a P-well 22 is formed on the surface of an N-type silicon substrate (N-sub) 21, and P-type diffusion regions (P +) 23 and 24 are formed on the surface of the P-well 22. Formed in isolation. A gate insulating film 25 is formed immediately above the region between one P-type diffusion region 23 and the other P-type diffusion region 24 on the P well 22. Is provided with a gate electrode 26. The two isolated P-type diffusion regions 23 and 24 are connected to the well terminal 27. The potential of the well terminal 27 is set to a well potential Vw. The gate electrode 26 is connected to the gate terminal 28. The potential of the gate terminal 28 is set to the gate potential Vg. With this connection, in the MOS varactor element 20, a capacitor is formed between the gate electrode 26 and the P well 22.

When the capacitance control voltage (Vg−Vw) applied between the gate terminal 28 and the well terminal 27 of the MOS varactor element 20 of FIG. 2 is sufficiently lowered, holes as carriers are gathered immediately below the gate electrode 26 on the surface of the P well 22. Since this region becomes conductive, the thickness of the substantial insulating region under the gate electrode 26 is equal to the thickness of the gate insulating film 25, and the capacitance value between the gate electrode 26 and the P well 22 is maximum. Value. Note that even if the capacitance control voltage (Vg−Vw) is further reduced, the thickness of the substantial insulating region under the gate electrode 26 does not change, so the capacitance value does not change.
When the capacitance control voltage (Vg−Vw) is increased from this state, a depletion layer grows in a region immediately below the gate insulating film 25 on the surface of the P well 22, and the thickness of the substantial insulating region under the gate electrode 26 is increased. However, the capacitance value decreases because the thickness of the gate insulating film 25 is added to the thickness of the depletion layer. When the capacity control voltage (Vg−Vw) becomes sufficiently high, the depth of the depletion layer is maximized and the capacity value is stabilized. The maximum depth of this depletion layer is determined by the impurity dopant concentration on the substrate surface.

When the capacitance control voltage (Vg−Vw) is further increased, an inversion layer composed of electrons which are minority carriers is formed on the surface of the P well 22. However, even if an inversion layer is formed by electrons, the depth of the depletion layer immediately below the inversion layer does not change, so the capacitance value does not change.
Thus, by changing the capacitance control voltage (Vg−Vw) applied to the MOS varactor element 20, a variable capacitance can be realized.

In FIG. 3, the horizontal axis represents the capacitance control voltage (Vg−Vw) applied to the MOS varactor element 10 shown in FIG. 1, and the vertical axis represents the capacitance value C of the MOS varactor element 10. It is the graph which showed.
The first region in FIG. 3 is a region where the capacitance control voltage (Vg−Vw) is positive, the second region is a region where the capacitance control voltage (Vg−Vw) is negative, and no inversion layer is formed. Is a region where the capacitance control voltage (Vg−Vw) is negative and an inversion layer is formed. In FIG. 3, the capacitance control voltage (Vg−Vw) of 0 corresponds to the boundary line between the first region and the second region.
The conventional MOS varactor element achieves a desired capacitance by controlling the capacitance control voltage (Vg−Vw) in the first and second regions of FIG. 3 during normal operation. The third region is a region where the capacitance value does not change with the capacitance control voltage (Vg−Vw) and is not used.
However, in the operation standby state such as in the sleep mode, the applied capacity control voltage (Vg−Vw) is not related to the power consumption, so it is not intentionally controlled and may eventually enter the state of the third region. There is.

4, the horizontal axis represents the capacitance control voltage (Vg−Vw) applied to the MOS varactor element 20 of FIG. 2, and the vertical axis represents the capacitance value C of the MOS varactor element 20. It is the graph which showed.
The first region in FIG. 4 is a region where the capacitance control voltage (Vg−Vw) is negative, the second region is a region where the capacitance control voltage (Vg−Vw) is positive, and no inversion layer is formed. Is a region where the capacitance control voltage (Vg−Vw) is positive and an inversion layer is formed. In FIG. 4, the capacitance control voltage (Vg−Vw) of 0 corresponds to the boundary line between the first region and the second region.
The conventional MOS varactor element realizes a desired capacitance by controlling the capacitance control voltage (Vg−Vw) in the first and second regions of FIG. 4 during normal operation. The third region is a region where the capacitance value does not change with the capacitance control voltage (Vg−Vw) and is not used.
However, in a standby state such as a sleep mode, the applied capacity control voltage (Vg−Vw) is not related to the power consumption, so it is not intentionally controlled and may eventually enter the state of the third region. is there.
JP 2005-269310 A

However, in the conventional MOS varactor element shown in FIGS. 1 and 2, the transition time from the standby state to an arbitrary stable capacitance state varies depending on the capacity control voltage (Vg−Vw) in the standby state, and (Vg -Vw) There is a problem that the potential becomes slower when the potential is in the third region of FIGS.
This is because the potential of the capacity control voltage (Vg−Vw) in the standby state is not controlled as described above. For example, when a potential of the capacitance control voltage (Vg−Vw) in the third region is applied, an inversion layer is formed on the well surface immediately below the gate electrode of the MOS varactor element. In order to diffuse the formed inversion layer by applying the potential of the capacitance control voltage (Vg−Vw) of the first region or the second region to be a depth at which the depletion layer realizes an arbitrary capacitance value, Compared with the case where the inversion layer is not present, the transient time is increased by the amount of diffusion of the inversion layer.

  The present invention has been made in view of such problems, and an object thereof is to provide a MOS varactor having a short transition time from a standby state to an arbitrary capacitance stable state.

  In order to solve the above problems and achieve the object of the present invention, a semiconductor integrated circuit according to the present invention includes an N well region formed on the surface of a silicon substrate, an insulating film provided on the N well region, A semiconductor integrated circuit including a MOS varactor element having an electrode provided on a film, wherein a potential difference obtained by subtracting a potential of the well region from a potential of the electrode is set to 0 or more during standby of the operation of the MOS varactor element The control circuit is provided.

The control circuit sets the potential of the N-well region to a predetermined value during normal operation of the MOS varactor element, controls the capacitance value of the MOS varactor element, and waits for operation of the MOS varactor element. The potential of the N well region is a ground potential.
The control circuit sets the potential of the electrode to a predetermined value during normal operation of the MOS varactor element to control the capacitance value of the MOS varactor element. The electrode potential is a positive power supply potential.

  A semiconductor integrated circuit according to the present invention includes a MOS varactor having a P well region formed on the surface of a silicon substrate, an insulating film provided on the P well region, and an electrode provided on the insulating film. A semiconductor integrated circuit comprising an element, comprising a control circuit for reducing a potential difference obtained by subtracting the potential of the well region from the potential of the electrode to 0 or less when the MOS varactor element is on standby.

The control circuit sets the potential of the electrode to a predetermined value during normal operation of the MOS varactor element to control the capacitance value of the MOS varactor element. The electrode potential is a ground potential.
The control circuit sets the potential of the P-well region to a predetermined value during normal operation of the MOS varactor element, controls the capacitance value of the MOS varactor element, and waits for operation of the MOS varactor element. The potential of the P well region is a positive power supply potential.
Furthermore, a voltage controlled oscillator according to the present invention includes any one of the semiconductor integrated circuits described above as a variable capacitance element.
Furthermore, a PLL circuit according to the present invention includes the voltage controlled oscillator described above.

The semiconductor integrated circuit according to the present invention includes a control circuit that sets a potential difference obtained by subtracting the potential of the well region from the potential of the electrode at the time of operation standby of the MOS varactor element having the N well to 0 or more. It is possible to shorten the transition time to the stable state.
In addition, by providing a control circuit that reduces the potential difference obtained by subtracting the potential of the well region from the potential of the electrode when the MOS varactor element having the P-well is in operation standby, the transition time from the operation standby to an arbitrary capacitance stable state is provided. Can be shortened.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 5 shows a specific example of an LC resonance type voltage controlled oscillator (LC-VCO) 50 to which the present invention is applied. The LC-VCO 50 in FIG. 5 includes inductors L1 and L2, fixed capacitors C1 and C2, variable capacitors M1 and M2 using MOS varactor elements, a tank circuit 51 including resistors R1 and R2 for applying a bias potential, and positive feedback at the resonance frequency. Bipolar transistors Q1 and Q2 to be amplified, current source I1, fixed capacitors C3 and C4 for cutting off DC potential, resistors R3 and R4 for applying DC potential to bipolar transistors Q1 and Q2, and DC potential are generated. And a control circuit 52 that sets the input potential and the output potential to the same potential during normal operation of the LC-VCO 50 and sets the output potential to the ground potential during standby.

Here, the variable capacitors M1 and M2 have the same cross-sectional structure as the MOS varactor element 10 of FIG. The gate electrode (gate terminal 18) of the variable capacitor M1 is connected to the fixed capacitor C1 and the resistor R1, and the well region (well terminal 17) is connected to the control circuit 52 via the VCNT ′ node 53. The gate electrode (gate terminal 18) of the variable capacitor M2 is connected to the fixed capacitor C2 and the resistor R2, and the well region (well terminal 17) is connected to the control circuit 52 via the VCNT 'node 53.
The control circuit 52 receives a control signal VCNT from a VCNT terminal (potential control terminal) 54, and transmits a control signal VCNT ′ controlled based on the control signal S 0 input from the control terminal 55 via a VCNT ′ node 53. The data is output to the well regions (well terminals 17) of the variable capacitors M1 and M2.

The bias potential V1 from the bias terminal 56 is applied to the connection point between the variable capacitor M1 and the fixed capacitor C1, and the connection point between the variable capacitor M2 and the fixed capacitor C2 via the resistors R1 and R2, and the bias potential V1 and the control point are controlled. The variable capacitors M1 and M2 are determined by the difference from the potential of the signal VCNT ′.
The other terminals of the fixed capacitors C1 and C2 are connected to one terminals of the inductors L1 and L2, respectively, and the other terminals of the inductors L1 and L2 are connected to the power supply VDD.

The collectors of the bipolar transistors Q1 and Q2 have a so-called cross coupling configuration in which they are input to the bases of each other via fixed capacitors C3 and C4 for DC cut. The emitters of the bipolar transistors Q1 and Q2 are commonly connected to each other and receive a current supply from the current source I1 at the connection point. A DC potential V3 is generated by the current source I2 and the resistor R5 and supplied to the bases of the bipolar transistors Q1 and Q2 via the resistors R3 and R4, respectively.
The collectors of the bipolar transistors Q1 and Q2 are also connected to the tank circuit 51 at the common connection point of the inductor L1 and the fixed capacitor C1, and the common connection point of the inductor L2 and the fixed capacitor C2, respectively, thereby generating a negative resistance. The stable LC oscillation is continued, and the output signals OUT and OUTB are output from the output terminals 57 and 58 connected to the common connection point.

FIG. 6 shows a specific example of the control circuit 52 shown in FIG.
The control circuit 52 in FIG. 6 has N channel MOS transistors (NMOS) QN0 and QN1, a P channel MOS transistor (PMOS) QP1, and an inverter INV1, and a terminal VCNT is the source of the N channel MOS transistor QN1 and the P channel MOS transistor QP1. The terminals VCNT ′ are connected to the drains of the N channel MOS transistor QN1 and the P channel MOS transistor QP1, respectively.

Terminal S0 is connected to the gate of N-channel MOS transistor QN1, and is connected to the gate of P-channel MOS transistor QP1 and the gate of N-channel MOS transistor (NMOS) QN0 via inverter INV1. The source of the N channel MOS transistor (NMOS) QN0 is grounded and the drain is connected to the terminal VCNT ′. The terminal VCNT, the terminal VCNT ′, and the terminal S0 are connected to the VCNT terminal 54, the VCNT ′ node 53, and the control terminal 55 in FIG.
When the potential of the control signal S0 input from the terminal S0 is equal to the power supply potential, that is, when the potential of the control signal S1 is equal to the ground potential, the potential of the terminal VCNT and the potential of the terminal VCNT ′ are equal. When the potential of the control signal S0 is equal to the ground potential, that is, when the potential of the control signal S1 is equal to the power supply potential, the potential of the terminal VCNT ′ is equal to the ground potential.

  In the normal operation of the LC-VCO 50 of FIG. 5, the potential VCNT of the control signal VCNT and the potential VCNT ′ of the control signal VCNT ′ are equalized by making the potential of the control signal S0 of the control circuit 52 equal to the power supply potential. A potential difference (V1−VCNT ′) is applied to the MOS varactor elements M1 and M2, and the capacitance value corresponds to this potential difference. The bias potential V1 at this time is a positive fixed potential, and the LC-VCO 50 oscillates at the resonance frequency of the tank circuit 51. Therefore, the potential of the control signal VCNT is adjusted to control the capacitance values of the MOS varactor elements M1 and M2. Thus, a desired oscillation frequency can be obtained.

When the operation of the LC-VCO 50 in FIG. 5 is on standby, the potential of the control signal VCNT ′ applied to the MOS varactor elements M1 and M2 is set to the ground potential by making the potential of the control signal S0 of the control circuit 52 equal to the ground potential. To do. The bias potential V1 during operation standby can be ground potential or a positive fixed potential, and the capacity control voltages (V1−VCNT ′) of the MOS varactor elements M1 and M2 are 0 or positive. This is equivalent to that the potential difference obtained by subtracting the potential of the well region from the potential of the electrodes of the MOS varactor elements M1 and M2 is 0 or more.
Therefore, the inversion layer is not formed at the time of operation standby, and it is possible to quickly transition to an arbitrary capacitance stable state.

  Even in a circuit other than the specific example of the control circuit of FIG. 6, the potential of the control signal VCNT ′ during operation standby is controlled to be equal to or less than the bias potential V1, and the capacitance control voltage (V1−VCNT ′) of the MOS varactor element during operation standby is negative. If it is avoided, the same effect can be obtained.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 7 shows a specific example of an LC resonance type voltage controlled oscillator (LC-VCO) 70 to which the present invention is applied. The LC-VCO 70 of FIG. 7 includes a tank circuit 71 including inductors L1 and L2, fixed capacitors C1 and C2, variable capacitors M1 and M2 using MOS varactor elements, resistors R1 and R2 for applying a bias potential, and positive feedback at the resonance frequency. Bipolar transistors Q1 and Q2 to be amplified, current source I1, fixed capacitors C3 and C4 for cutting off DC potential, resistors R3 and R4 for applying DC potential to bipolar transistors Q1 and Q2, and DC potential are generated. The control circuit 72 has the same input potential and output potential during normal operation of the LC-VCO 70 and the output potential as a power supply potential during standby.

Here, the variable capacitors M1 and M2 have the same cross-sectional structure as the MOS varactor element 10 of FIG. The gate electrode (gate terminal 18) of the variable capacitor M1 is connected to the fixed capacitor C1 and the resistor R1, and the well region (well terminal 17) is connected to the VCNT terminal 74. The gate electrode (gate terminal 18) of the variable capacitor M2 is connected to the fixed capacitor C2 and the resistor R2, and the well region (well terminal 17) is connected to the VCNT terminal 74.
The control circuit 72 receives the control signal V 1 from the V 1 terminal (bias voltage control terminal) 76, and receives the bias signal V 1 ′ controlled based on the control signal S 0 input from the control terminal 75 via the V 1 ′ node 73. Are output to the resistors R1 and R2.

A bias potential V1 ′ of the bias signal V1 ′ output from the control circuit 72 is applied to the connection point between the variable capacitor M1 and the fixed capacitor C1, and the connection point between the variable capacitor M2 and the fixed capacitor C2 via the resistors R1 and R2. The variable capacitance is determined by the difference between the bias potential V1 ′ and the potential of the control signal VCNT.
The other terminals of the fixed capacitors C1 and C2 are connected to one terminals of the inductors L1 and L2, respectively, and the other terminals of the inductors L1 and L2 are connected to the power supply VDD.
The collectors of the bipolar transistors Q1 and Q2 have a so-called cross coupling configuration in which they are input to the bases of each other via fixed capacitors C3 and C4 for DC cut. The emitters of the bipolar transistors Q1 and Q2 are commonly connected to each other and receive a current supply from the current source I1 at the connection point. A DC potential V3 is generated by the current source I2 and the resistor R5 and supplied to the bases of the bipolar transistors Q1 and Q2 via the resistors R3 and R4, respectively.

  The collectors of the bipolar transistors Q1 and Q2 are also connected to the tank circuit 71 at the common connection point of the inductor L1 and the fixed capacitor C1, and the common connection point of the inductor L2 and the fixed capacitor C2, respectively, thereby generating a negative resistance. And stable LC oscillation is continued, and output signals OUT and OUTB are output from output terminals 77 and 78 connected to a common connection point.

FIG. 8 shows a specific example of the control circuit 72 shown in FIG.
The control circuit 72 of FIG. 8 has an N channel MOS transistor (NMOS) QN1, P channel MOS transistors (PMOS) QP0 and QP1, and an inverter INV1, and a terminal V1 is the source of the N channel MOS transistor QN1 and P channel MOS transistor QP1. And the terminal V1 ′ is connected to the drains of the N-channel MOS transistor QN1 and the P-channel MOS transistor QP1, respectively.

  Terminal S0 is connected to the gate of N channel MOS transistor QN1 and the gate of P channel MOS transistor QP0, and is connected to the gate of P channel MOS transistor QP1 through inverter INV1. The source of the P-channel MOS transistor QP0 is connected to the power supply VDD, and the drain is connected to the terminal V1 '. Terminal V1, terminal V1 'and terminal S0 are connected to V1 terminal 76, V1' node 73 and control terminal 75 of FIG.

When the potential of the control signal S0 input from the terminal S0 is equal to the power supply potential, that is, when the potential of the control signal S1 is equal to the ground potential, the potential of the terminal V1 is equal to the potential of the terminal V1 ′. Further, when the potential of the control signal S0 is equal to the ground potential, that is, when the potential of the control signal S1 is equal to the power supply potential, the potential of the terminal V1 ′ becomes equal to the power supply potential. During normal operation of the LC-VCO 70 in FIG. By making the potential of the control signal S0 of the control circuit 72 equal to the power supply potential, the potential V1 of the control signal V1 and the potential V1 ′ of the control signal V1 ′ become equal, and the potential difference (V1′−VCNT) is applied to the MOS varactor elements M1 and M2. ), And the MOS varactor elements M1 and M2 have capacitance values corresponding to the potential difference (V1′−VCNT). The bias potential V1 at this time is a positive fixed potential, and the LC-VCO 70 oscillates at the resonance frequency of the tank circuit 71. Therefore, the potential of the control signal VCNT is adjusted to control the capacitance values of the MOS varactor elements M1 and M2. Thus, a desired oscillation frequency can be obtained.

When the operation of the LC-VCO 70 in FIG. 7 is on standby, the potential of the control signal V1 ′ applied to the MOS varactor elements M1 and M2 is set to the power supply potential by making the potential of the control signal S0 of the control circuit 72 equal to the ground potential. To do. The potential of the control signal VCNT during standby is considered to be an arbitrary potential between the ground potential and the power supply potential, and the capacity control voltage (V1′−VCNT) of the MOS varactor elements M1 and M2 becomes 0 or positive. . This is equivalent to that the potential difference obtained by subtracting the potential of the well region from the potential of the electrodes of the MOS varactor elements M1 and M2 is 0 or more.
Therefore, the inversion layer is not formed at the time of operation standby, and it is possible to quickly transition to an arbitrary capacitance stable state.

  Even in a circuit other than the specific example of the control circuit of FIG. 8, the potential of the control signal V1 ′ during operation standby is controlled to be equal to or higher than the potential of the control signal VCNT, and the capacity control voltage (V1′−VCNT) of the MOS varactor element during operation standby. A similar effect can be obtained by avoiding negative.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
FIG. 9 shows a specific example of an LC resonance type voltage controlled oscillator (LC-VCO) 90 to which the present invention is applied. The LC-VCO 90 shown in FIG. 9 includes inductors L1 and L2, fixed capacitors C1 and C2, variable capacitors M1 and M2 using MOS varactor elements, a tank circuit 91 including resistors R1 and R2 for applying a bias potential, and positive feedback at the resonance frequency. Bipolar transistors Q1 and Q2 to be amplified, current source I1, fixed capacitors C3 and C4 for cutting off DC potential, resistors R3 and R4 for applying DC potential to bipolar transistors Q1 and Q2, and DC potential are generated. The control circuit 92 has the same input potential and output potential during normal operation of the LC-VCO 90 and the output potential as a ground potential during standby.

The variable capacitors M1 and M2 have the same cross-sectional structure as the MOS varactor element 20 shown in FIG. The well region (well terminal 27) of the variable capacitor M1 is connected to the fixed capacitor C1 and the resistor R1, and the gate electrode (gate terminal 28) is connected to the control circuit 92 via the VCNT 'node 93. The well region (well terminal 27) of the variable capacitor M2 is connected to the fixed capacitor C2 and the resistor R2, and the gate electrode (gate terminal 28) is connected to the control circuit 92 via the VCNT ′ node 93.
The control circuit 92 receives a control signal VCNT from a VCNT terminal (potential control terminal) 94, and transmits a control signal VCNT ′ controlled based on the control signal S 0 input from the control terminal 95 via a VCNT ′ node 93. This is output to the gate electrodes (gate terminals 28) of the variable capacitors M1 and M2.

A bias potential V1 from the bias terminal 96 is applied to the connection point between the variable capacitor M1 and the fixed capacitor C1, and the connection point between the variable capacitor M2 and the fixed capacitor C2 via the resistors R1 and R2, and the bias potential V1 and the control point are controlled. The variable capacitance is determined by the difference in potential of the signal VCNT ′.
The other terminals of the fixed capacitors C1 and C2 are connected to one terminals of the inductors L1 and L2, respectively, and the other terminals of the inductors L1 and L2 are connected to the power supply VDD.
The collectors of the bipolar transistors Q1 and Q2 have a so-called cross coupling configuration in which they are input to the bases of each other via fixed capacitors C3 and C4 for DC cut. The emitters of the bipolar transistors Q1 and Q2 are commonly connected to each other and receive a current supply from the current source I1 at the connection point. A DC potential V3 is generated by the current source I2 and the resistor R5 and supplied to the bases of the bipolar transistors Q1 and Q2 via the resistors R3 and R4, respectively.

The collectors of the bipolar transistors Q1 and Q2 are also connected to the tank circuit 91 at the common connection point of the inductor L1 and the fixed capacitor C1, and the common connection point of the inductor L2 and the fixed capacitor C2, respectively, thereby generating a negative resistance. Stable LC oscillation is continued, and output signals OUT and OUTB are output from output terminals 97 and 98 connected to a common connection point.
The above-described FIG. 6 is given as a specific example of the control circuit 92 shown in FIG. Although the detailed description of the internal circuit and its operation is omitted as described above, the terminal VCNT, the terminal VCNT ′, and the terminal S0 are connected to the VCNT terminal 94, the VCNT ′ node 93, and the control terminal 95 of FIG.

  During normal operation of the LC-VCO 90 of FIG. 9, by making the control signal S0 potential of the control circuit 92 equal to the power supply potential, the potential VCNT of the control signal VCNT and the potential VCNT ′ of the control signal VCNT ′ become equal, A potential difference (V1−VCNT ′) is applied to the MOS varactor elements M1 and M2, and the capacitance value corresponds to this potential difference. The bias potential V1 at this time is a positive fixed potential, and the LC-VCO 90 oscillates at the resonance frequency of the tank circuit 91. Therefore, the potential of the control signal VCNT is adjusted to control the capacitance values of the MOS varactor elements M1 and M2. Thus, a desired oscillation frequency can be obtained.

When the operation of the LC-VCO 90 in FIG. 9 is on standby, the potential of the control signal VCNT ′ applied to the MOS varactor elements M1 and M2 is set to the ground potential by making the potential of the control signal S0 of the control circuit 92 equal to the ground potential. To do. The bias potential V1 during operation standby can be ground potential or positive fixed potential, and the capacity control voltage (V1-VCNT ′) of the MOS varactor elements M1 and M2 can be 0 or positive and negative. Absent. This is equivalent to that the potential difference obtained by subtracting the potential of the well region from the potential of the electrodes of the MOS varactor elements M1 and M2 is 0 or less.
Therefore, the inversion layer is not formed at the time of operation standby, and it is possible to quickly transition to an arbitrary capacitance stable state.

  Even in a circuit other than the specific example of the control circuit of FIG. 6, the potential of the control signal VCNT ′ during operation standby is controlled to be equal to or less than the bias potential V1, and the capacitance control voltage (V1−VCNT ′) of the MOS varactor element during operation standby is negative. If it is avoided, the same effect can be obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.
FIG. 10 shows a specific example of an LC resonance type voltage controlled oscillator (LC-VCO) 100 to which the present invention is applied. The LC-VCO 100 in FIG. 10 includes inductors L1 and L2, fixed capacitors C1 and C2, variable capacitors M1 and M2 using MOS varactor elements, resistors R1 and R2 that provide bias potentials, and positive feedback at the resonance frequency. Bipolar transistors Q1 and Q2 to be amplified, current source I1, fixed capacitors C3 and C4 for cutting off DC potential, resistors R3 and R4 for applying DC potential to bipolar transistors Q1 and Q2, and DC potential are generated. The control circuit 102 has an input potential and an output potential that are the same during normal operation of the LC-VCO 100 and an output potential that is a power supply potential during standby.

The variable capacitors M1 and M2 have the same cross-sectional structure as the MOS varactor element 20 shown in FIG. The well region (well terminal 27) of the variable capacitor M1 is connected to the fixed capacitor C1 and the resistor R1, and the gate electrode (gate terminal 28) is connected to the VCNT terminal 104. The well region (well terminal 27) of the variable capacitor M2 is connected to the fixed capacitor C2 and the resistor R2, and the gate electrode (gate terminal 28) is connected to the VCNT terminal 104.
The control circuit 102 receives the control signal V 1 from the V 1 terminal (bias voltage control terminal) 106, and receives the bias signal V 1 ′ controlled based on the control signal S 0 input from the control terminal 105 via the V 1 ′ node 103. Are output to the resistors R1 and R2.

A bias potential V1 ′ of the bias signal V1 ′ output from the control circuit 102 is applied to the connection point between the variable capacitor M1 and the fixed capacitor C1, and the connection point between the variable capacitor M2 and the fixed capacitor C2 via the resistors R1 and R2. The variable capacitance is determined by the difference between the bias potential V1 ′ and the potential of the control signal VCNT.
The other terminals of the fixed capacitors C1 and C2 are connected to one terminals of the inductors L1 and L2, respectively, and the other terminals of the inductors L1 and L2 are connected to the power supply VDD.
The collectors of the bipolar transistors Q1 and Q2 have a so-called cross coupling configuration in which they are input to the bases of each other via fixed capacitors C3 and C4 for DC cut. The emitters of the bipolar transistors Q1 and Q2 are commonly connected to each other and receive a current supply from the current source I1 at the connection point. A DC potential V3 is generated by the current source I2 and the resistor R5 and supplied to the bases of the bipolar transistors Q1 and Q2 via the resistors R3 and R4, respectively.

  The collectors of the bipolar transistors Q1 and Q2 are also connected to the tank circuit 101 at the common connection point of the inductor L1 and the fixed capacitor C1, and the common connection point of the inductor L2 and the fixed capacitor C2, respectively, thereby generating a negative resistance. The stable LC oscillation is continued, and the output signals OUT and OUTB are output from the output terminals 107 and 108 connected to the common connection point.

As a specific example of the control circuit 102 shown in FIG. Although the detailed description of the internal circuit and its operation is omitted as described above, the terminal V1, the terminal V1 ′, and the terminal S0 are connected to the V1 terminal 106, the V1 ′ node 103, and the control terminal 105 in FIG.
In the normal operation of the LC-VCO 100 of FIG. 10, by making the potential of the control signal S0 of the control circuit 102 equal to the power supply potential, the potential V1 of the control signal V1 and the potential V1 ′ of the control signal V1 ′ become equal. A potential difference (V1′−VCNT) is applied to the varactor elements M1 and M2, and the MOS varactor elements M1 and M2 have capacitance values corresponding to the potential difference (V1′−VCNT). The bias potential V1 at this time is a positive fixed potential, and the LC-VCO 100 oscillates at the resonance frequency of the tank circuit 101. Therefore, the potential of the control signal VCNT is adjusted to control the capacitance values of the MOS varactor elements M1 and M2. Thus, a desired oscillation frequency can be obtained.

When the LC-VCO 100 in FIG. 10 is on standby, the potential of the control signal V1 ′ applied to the MOS varactor elements M1 and M2 is set to the power supply potential by making the potential of the control signal S0 of the control circuit 102 equal to the ground potential. To do. The potential of the control signal VCNT during standby is considered to be an arbitrary potential between the ground potential and the power supply potential, and the capacity control voltage (V1′−VCNT) of the MOS varactor elements M1 and M2 becomes 0 or positive. . This is equivalent to that the potential difference obtained by subtracting the potential of the well region from the potential of the electrodes of the MOS varactor elements M1 and M2 is 0 or less.
Therefore, the inversion layer is not formed at the time of operation standby, and it is possible to quickly transition to an arbitrary capacitance stable state.

  Even in a circuit other than the specific example of the control circuit of FIG. 8, the potential of the control signal V1 ′ during operation standby is controlled to be equal to or higher than the potential of the control signal VCNT, and the capacity control voltage (V1′−VCNT) of the MOS varactor element during operation standby. A similar effect can be obtained by avoiding negative.

(Fifth embodiment)
Next, a PLL circuit 110 will be described as an example of an application system that can provide the LC-VCO according to the first to fourth embodiments of the present invention described above.
FIG. 11 shows a configuration of a general PLL circuit 110, which includes a phase comparator (PFD) and a charge pump (CP) 111, a loop filter (LPF) 112, a voltage controlled oscillator (VCO) 113, and a reference potential generation circuit (VREF). 114 and a feedback frequency divider (DIV) 115. In this example, PFD and CP are shown as one block.

  When the LC-VCO of FIG. 5, FIG. 7, FIG. 9, or FIG. 10 is applied to the VCO 113 of FIG. 11, the VCNT terminal (potential control terminal) of the LC-VCO of FIG. Are connected to the output of the LPF 112, the V1 terminal is connected to the output of the VREF 114, the output terminals of the differential output signals OUT and OUTB of the LC-VCO are connected to the output terminals 116 and 117, and are further connected to the input of the DIV 115. The

  In the normal operation state, the PLL circuit divides the differential output signals OUT and OUTB of the VCO 113 by the DIV 115 and further performs differential-single conversion, and a reference signal input from the REFIN terminal 118 separately. The PFD 111 compares the phase with the other clock signal, generates a pulse signal having a pulse width depending on the comparison result, and outputs a current depending on the pulse width from the CP 111. Next, the current is converted into a potential by the LPF 112 and the converted output is supplied as the control signal VCNT of the VCO 113. At this time, the control signal V1 of the LC-VCO in FIG. 5, FIG. 7, FIG. 9 or FIG. 10 is a positive fixed potential supplied from the VREF 114.

  Such a PLL circuit 110 can be realized using the LC-VCO in the embodiment of the present invention. In the LC-VCO according to the embodiment of the present invention, by controlling the capacitance control voltage applied to the MOS varactor element during operation standby, an inversion layer due to minority carriers is not formed on the well surface immediately below the electrode of the MOS varactor element. Thus, it is possible to provide a PLL circuit that can quickly transition from the standby state to the stable capacity state, and thus has a fast transient response from the standby state to the stable frequency state.

It is sectional drawing of the varactor element which has a MOS type structure. It is sectional drawing of the varactor element which has a MOS type structure. It is a figure which shows the relationship between the capacity | capacitance control voltage applied to the MOS varactor element of FIG. 1, and the capacitance value of a MOS varactor element. It is a figure which shows the relationship between the capacity | capacitance control voltage applied to the MOS varactor element of FIG. 2, and the capacitance value of a MOS varactor element. 1 is a diagram illustrating an LC resonance type voltage controlled oscillator according to a first embodiment of the present invention. It is a figure which shows an example of the control circuit of FIG. 5, FIG. It is a figure which shows the LC resonance type voltage controlled oscillator of the 2nd Embodiment of this invention. It is a figure which shows an example of the control circuit of FIG. 7, FIG. It is a figure which shows the LC resonance type voltage controlled oscillator of the 3rd Embodiment of this invention. It is a figure which shows the LC resonance type voltage controlled oscillator of the 4th Embodiment of this invention. It is a figure which shows the PLL circuit using the LC resonance type voltage control oscillator of the 1st to 4th embodiment of this invention.

Explanation of symbols

10, 20, M1, M2 MOS varactor element 12 N well 22 P well 16, 26 Gate electrode 50, 70, 90, 100 LC resonant voltage controlled oscillator 52, 72, 92, 102 Control circuit 53, 93 VCNT 'node 54 , 74, 94, 104 VCNT terminal 55, 75, 95, 105 Control terminal 56, 76, 96, 106 Bias terminal 73, 103 V1 ′ node 110 PLL circuit 111 Phase comparator and charge pump 112 Loop filter 113 Voltage controlled oscillator 114 Reference potential generation circuit 115 Feedback divider

Claims (8)

A semiconductor integrated circuit comprising a MOS varactor element having an N-type well region formed on the surface of a silicon substrate, an insulating film provided on the N-type well region, and an electrode provided on the insulating film. And
A semiconductor integrated circuit, comprising: a control circuit for setting a potential difference obtained by subtracting a potential of the N-type well region from a potential of the electrode to 0 or more during standby of the operation of the MOS varactor element.   The control circuit sets the potential of the N-type well region to a predetermined value during normal operation of the MOS varactor element, controls the capacitance value of the MOS varactor element, and waits for operation of the MOS varactor element 2. The semiconductor integrated circuit according to claim 1, wherein the potential of the N-type well region is a ground potential.   The control circuit sets the potential of the electrode to a predetermined value during normal operation of the MOS varactor element to control the capacitance value of the MOS varactor element. 2. The semiconductor integrated circuit according to claim 1, wherein the potential of the electrode is a positive power supply potential. A semiconductor integrated circuit including a MOS varactor element having a P-type well region formed on the surface of a silicon substrate, an insulating film provided on the P-type well region, and an electrode provided on the insulating film. And
A semiconductor integrated circuit, comprising: a control circuit that sets a potential difference obtained by subtracting the potential of the P-type well region from the potential of the electrode to 0 or less during standby of the operation of the MOS varactor element.   The control circuit sets the potential of the electrode to a predetermined value during normal operation of the MOS varactor element to control the capacitance value of the MOS varactor element. 5. The semiconductor integrated circuit according to claim 4, wherein the potential of the electrode is a ground potential.   The control circuit sets the potential of the P-type well region to a predetermined value during normal operation of the MOS varactor element, controls the capacitance value of the MOS varactor element, and waits for operation of the MOS varactor element 5. The semiconductor integrated circuit according to claim 4, wherein the potential of the P-type well region is a positive power supply potential.   A voltage-controlled oscillator comprising the semiconductor integrated circuit according to claim 1 as a variable capacitance element.   A PLL circuit comprising the voltage controlled oscillator according to claim 7.