JP2009135187A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of short circuit between a first p-type region and a second p-type region, even if a first n-type region and the first p-type region are laminated and formed on the second p-type region in a semiconductor device with a thyristor structure. <P>SOLUTION: In the semiconductor device 1, a thyristor T1 in which a p-type first p-type region p1 (a first region), an n-type first n-type region n1 (a second region), a p-type second p-type region p2 (a third region), and an n-type second n-type region n2 (a fourth region) are sequentially connected is isolated by an element isolation region 13. The second p-type region p2 is formed on a semiconductor substrate 11 isolated by the element isolation region 13. The first n-type region n1 is formed on a portion of the second p-type region p2. One end of an interface between the first n-type region n1 and the second p-type region p2 is connected to a sidewall of the element isolation region 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a thyristor and a method for manufacturing the same.

  There has been proposed a memory (in particular, for SRAM) in which a thyristor is used and the turn-on and turn-off characteristics of the thyristor are controlled by a gate electrode realized on the thyristor and connected in series with an access transistor (hereinafter referred to as T-RAM). In this case, the memory operation is performed by setting the off region of the thyristor to “0” and the on region to “1”.

A thyristor is basically a first p-type region p1, a first n-type region n1, a second p-type region p2, and a second n-type region n2, which are sequentially joined. For example, n-type silicon and p-type silicon are arranged in four layers. It is configured.
Hereinafter, this basic structure is referred to as p1 / n1 / p2 / n2. Two types of structures have been proposed by T-RAM.
One is a p1 / n1 / p2 / n2 structure formed vertically on a silicon substrate.
The other is an SOI substrate in which a p1 / n1 / p2 / n2 structure is horizontally formed on a silicon layer.
In any configuration, high-speed operation is enabled by providing a gate electrode having a MOS structure on p1 / n2 / p2 / n2 (see, for example, Non-Patent Documents 1, 2, 3, and Patent Document 1).

When a thyristor is manufactured using a planar type bulk silicon substrate, when a p1 / n1 / p2 / n2 structure is formed by ion implantation, for example, as shown in FIG. 16, a first p-type region p1 and a first n-type region n1 are formed. It must be formed with a double diffusion layer.
However, in the configuration using the double diffusion layer, the process margin of the first p-type region p1 and the first n-type region n1 cannot be increased from the viewpoint of element isolation, and the device characteristics are limited.

  Further, a manufacturing method using a selective epitaxial growth technique has been proposed by the applicant of the present invention and T-RAM (see, for example, Patent Document 2).

For example, as shown in FIG. 17, in order to secure a large process margin between the first p-type region p1 and the first n-type region n1, a method of forming the first p-type region p1 and the first n-type region n1 by selective epitaxial growth is proposed. Has been.
In order to form the first p-type region p1 and the first n-type region n1 by selective epitaxial growth, it is required to suppress a short circuit between the first p-type region p1 and the second p-type region p2.

  However, as shown in FIG. 18, when the first n-type region n1 is formed on the second p-type region p2 by selective epitaxial growth, the growth may not proceed to the outside of the underlying silicon substrate region, that is, the element isolation region 13. .

In this state, selective epitaxial growth for further forming the first p-type region p1 is performed to form the first p-type region p1 on the first n-type region n1, as shown in FIG. 19, so that the facet region of the first n-type region n1 is obtained. Therefore, the first p-type region p1 and the second p-type region p2 come into contact with each other at the skirt portion of the first n-type region n1, and a short circuit occurs.
When a short circuit occurs between the first p-type region p1 and the second p-type region p2, the p1 / n1 / p2 / n2 junction becomes equivalent to a simple pn junction, so that thyristor characteristics cannot be obtained and the memory is used. It becomes impossible to operate.
Accordingly, it is necessary to prevent the short by physically separating the distance between the first p-type region p1 and the second p-type region p2.

US Pat. No. 6,462,359 (B1) US Pat. No. 6,888,176 (B1) Farid Nemati and James D. Plummer "A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device" 1998 IEEE, VLSI Technology Tech.Dig. P.66 1998 Farid Nemati and James D. Plummer `` A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories '' 1999 IEEE IEDM Tech., P.283 1999 Farid Nemati, Hyun-Jin Cho, Scott Robins, Rajesh Gupta, Marc Tarabbia, Kevin J. Yang, Dennis Hayes, Vasudevan Gopalakrishnan, `` Fully Planar 0.562μm2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High- Performance SRAMs '' 2004 IEEE IEDM Tech., P.273 2004

  The problem to be solved is that, when the first n-type region and the first p-type region are formed on the second p-type region p2 by epitaxial growth, the first p-type region and the second p-type region are formed at the bottom of the first n-type region. This is a point where a short circuit occurs due to contact.

  The present invention provides a semiconductor device having a thyristor in which a first p-type region, a first n-type region, a second p-type region, and a second n-type region are sequentially joined, and the first n-type region, the first p-type region on the second p-type region. Even when the regions are stacked, the first p-type region and the second p-type region can be prevented from being short-circuited.

  The semiconductor device (first semiconductor device) of the present invention includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type third region. A semiconductor device having a thyristor in which a region and a fourth region of the second conductivity type are sequentially joined, wherein the third region is formed on a semiconductor substrate separated by an element isolation region; The region is formed on a part of the third region, and is formed so that one end portion of the interface between the second region and the third region is joined to the side wall portion of the element isolation region. It is characterized by that.

  In the first semiconductor device of the present invention, the second region is formed on a part of the third region, and one end portion of the interface between the second region and the third region is a side wall portion of the element isolation region. Thus, the first region and the third region are separated by the second region and the element isolation region.

  A semiconductor device (second semiconductor device) according to the present invention includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type third region. A semiconductor device having a thyristor in which a region and a fourth region of the second conductivity type are sequentially joined, wherein the third region is formed on a semiconductor substrate separated by an element isolation region; The region is formed on a part of the third region, the first region is formed on the second region, and the first region is formed on the second region surface where the first region is formed. The second region is formed around the side.

  In the second semiconductor device of the present invention, the first region is formed on the second region, and the second region exists around the side of the first region on the second region surface where the first region is formed. Since it is formed, the first region and the third region are separated by the second region.

  A method for manufacturing a semiconductor device of the present invention (first manufacturing method) includes a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and a first conductivity type. A method of manufacturing a semiconductor device in which a thyristor in which the third region and the fourth region of the second conductivity type are sequentially joined is formed, the step of forming an element isolation region on a semiconductor substrate, and the element isolation region Forming the third region on the semiconductor substrate separated by the step, forming a gate electrode on the third region through a gate insulating film, and forming a sidewall on the side wall of the gate electrode. A step of forming a non-doped epitaxial growth layer on the third region on one side of the gate electrode, and a surface of the epitaxial growth layer on the epitaxial growth layer and the third region below the epitaxial growth layer. Forming a second region by ion-implanting a second conductivity type impurity so that one end is joined to the sidewall of the element isolation region at a predetermined distance, and the epitaxially grown layer and its lower part Forming a first region above the second region by ion-implanting a first conductivity type impurity so that one end of the third region is joined to a side wall of the element isolation region; Forming the fourth region so as to be joined to the third region on the other side of the electrode.

  In the first manufacturing method of the present invention, the second conductivity type is formed such that one end of the epitaxial growth layer and the third region under the epitaxial growth layer are joined to the side wall portion of the element isolation region at a predetermined distance from the surface of the epitaxial growth layer. Impurities are ion-implanted into the epitaxial growth layer and the third region below the epitaxial growth layer so that one end of the impurity is ion-implanted to the sidewall portion of the element isolation region. And the step of forming the first region above the second region by implantation, the first region and the third region are formed to be separated by the second region and the element isolation region.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method (second manufacturing method) including a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type. A method of manufacturing a semiconductor device in which a thyristor in which the third region and the fourth region of the second conductivity type are sequentially joined is formed, the step of forming an element isolation region on a semiconductor substrate, and the element isolation region Forming the third region on the semiconductor substrate separated by the step, forming a gate electrode on the third region through a gate insulating film, and forming a sidewall on the side wall of the gate electrode. A step of forming a non-doped epitaxial growth layer on the third region on one side of the gate electrode, the non-doped epitaxial growth layer and the third region under the non-doped epitaxial growth layer, Forming the second region by ion implantation of a second conductivity type impurity so that one end is joined to the side wall of the child isolation region, and forming the first region on the second region by selective epitaxial growth And a step of forming the fourth region so as to be joined to the third region on the other side of the gate electrode.

  In the second manufacturing method of the present invention, a step of forming a non-doped epitaxial growth layer on the third region on one side of the gate electrode, and a non-doped epitaxial growth layer and a third region under the non-doped epitaxial growth layer Forming a second region by ion-implanting a second conductivity type impurity so that one end is joined to the side wall of the isolation region; and forming the first region on the second region by selective epitaxial growth; Therefore, the first region and the third region are formed so as to be separated by the second region or the second region and the element isolation region.

  A method for manufacturing a semiconductor device according to the present invention (third manufacturing method) includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type. A method of manufacturing a semiconductor device in which a thyristor in which the third region and the fourth region of the second conductivity type are sequentially joined is formed, the step of forming an element isolation region on a semiconductor substrate, and the element isolation region Forming the third region on the semiconductor substrate separated by the step, forming a gate electrode on the third region through a gate insulating film, and forming a sidewall on the side wall of the gate electrode. And forming an epitaxial growth layer doped with an impurity of a second conductivity type on the third region on one side of the gate electrode so as to cover the boundary between the element isolation region and the third region, and the epitaxial growth On the surface side of the layer Forming a first region by ion-implanting an impurity of one conductivity type, and forming a fourth region so as to be joined to a third region on the other side of the gate electrode, The implantation is performed so that the second region exists between the first region and the third region, and the second region covering the boundary between the third region and the element isolation region is maintained. It is characterized by performing.

  In the third manufacturing method of the present invention, an epitaxial growth layer doped with an impurity of the second conductivity type is formed on the third region on one side of the gate electrode so as to cover the boundary between the element isolation region and the third region; A step of forming a first region by ion implantation of a first conductivity type impurity on the surface side of the epitaxial growth layer, and a step of forming a fourth region so as to be joined to the third region on the other side of the gate electrode. The ion implantation is performed so that the second region exists between the first region and the third region, and the second region covering the boundary between the third region and the element isolation region is maintained. Therefore, the first region and the third region are separated by the second region and the element isolation region.

  A method for manufacturing a semiconductor device according to the present invention (fourth manufacturing method) includes a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and a first conductivity type. A method of manufacturing a semiconductor device in which a thyristor in which the third region and the fourth region of the second conductivity type are sequentially joined is formed, the step of forming an element isolation region on a semiconductor substrate, and the element isolation region Forming the third region on the semiconductor substrate separated by the step, forming a gate electrode on the third region through a gate insulating film, and forming a sidewall on the side wall of the gate electrode. And forming the second region on the third region on one side of the gate electrode, forming an insulating film covering the second region, and then forming the insulating film on the second region. Forming an opening so as to fit inside the second region; , Forming the first region on the second region of the opening by selective epitaxial growth, and forming the fourth region so as to be joined to the third region on the other side of the gate electrode. It is characterized by that.

  In the fourth manufacturing method of the present invention, the step of forming the second region on the third region on one side of the gate electrode, the insulating film covering the second region being formed, and then the insulating film on the second region And forming a first region on the second region of the opening by selective epitaxial growth, so that the first region and the third region are formed. Are separated by a second region.

  In the semiconductor device of the present invention, the first region and the third region are separated from each other by the second region and the element isolation region, or separated from each other by the second region. There is no short circuit with the area. Therefore, the junction between the first region and the second region and the junction between the second region and the third region in the thyristor in which the first region, the second region, the third region, and the fourth region are joined in order function. Therefore, a semiconductor device capable of obtaining normal thyristor characteristics can be obtained.

  In the method of manufacturing a semiconductor device according to the present invention, the first region and the third region are formed so as to be separated by the second region and the element isolation region or by the second region. Will never short. Therefore, the junction between the first region and the second region and the junction between the second region and the third region in the thyristor in which the first region, the second region, the third region, and the fourth region are joined in order function. Therefore, a semiconductor device capable of obtaining normal thyristor characteristics can be manufactured.

  An embodiment (first example) according to a semiconductor device (first semiconductor device) of the present invention will be described with reference to a schematic sectional view of FIG.

  As shown in FIG. 1, an element isolation region 13 for isolating an element formation region 12 for forming a thyristor T1 is formed in a semiconductor substrate 11. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation).

A first conductivity type (p-type) first p-type region p1 (first region) and a second conductivity type (n-type) opposite to the first conductivity type are formed in the element formation region 12 and the upper portion thereof. The first n-type region n1 (second region), the first conductivity type (p-type) second p-type region p2 (third region), and the second conductivity-type (n-type) second n-type region n2 (fourth) A semiconductor device 1 is formed which is composed of a thyristor T1 that is joined in order to the region.
Here, the first conductivity type is described as p-type and the second conductivity type is described as n-type, but conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Details will be described below.
For example, an n-well region (not shown) may be formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation region 12 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 is formed by doping with boron (B), and the concentration thereof is, for example, 5 × 10 ¹⁸ cm ^−3, which is about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. desirable. Basically, it must be lower than the dopant concentration of the first n-type region n1 of the second conductivity type (n-type) described later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm.
The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A thyristor gate electrode 22 can be formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the thyristor gate electrode 22 as a hard mask.

Sidewalls 23 and 24 are formed on the side wall of the thyristor gate electrode 22. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

On one side of the thyristor gate electrode 22, a first n-type region n1 (second region) of the second conductivity type (n-type) is formed. The first n-type region n1 is formed on the surface of the element isolation region 13 (13-2) on a part of the second p-type region p2 (third region) and a part of the second p-type region p2 below it. One end is joined to the side wall of the element isolation region 13 (13-2) at a deeper position. The first n-type region n1 above the second p-type region p2 is formed of, for example, an epitaxially grown layer formed by epitaxial growth.
The first n-type region n1 is formed of, for example, a non-doped epitaxial growth layer together with the first p-type region p1, and a lower layer portion of the non-doped epitaxial growth layer and a part of the second p-type region p2 are formed in the film by ion implantation. The phosphorus (P) concentration is set to 1.5 × 10 ¹⁹ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2, and the first p-type region described below It is necessary to be lower than p1 (first region).
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The film thickness of the first n-type region n1 is desirably about 50 nm to 300 nm, for example, as the film thickness of the epitaxial growth layer portion.
The first n-type region n1 (second region) is joined to the sidewall of the sidewall 24. Specifically, the end of the first n-type region n1 where one end of the interface between the first n-type region n1 and the second p-type region p2 is not joined to the side wall of the element isolation region 13 (13-2). The part is joined to the side wall of the side wall 24.
Furthermore, the main part of the first n-type region n1 (the part formed on the main surface of the semiconductor substrate 11) is formed on the surface of the semiconductor substrate 11. Alternatively, it may be formed on the surface of the semiconductor substrate 11 and a position deeper than the surface of the semiconductor substrate 11.

A first p-type region p1 (first region) of the first conductivity type (p-type) is formed on the first n-type region n1.
The first p-type region p1 is formed on the first n-type region n1 and part of the second p-type region p2, and at least one end is joined to the side wall of the element isolation region 13 (13-2). Is formed. That is, the first n-type region n1 is formed on a part of the second p-type region p2, and one end portion of the interface between the first n-type region n1 and the second p-type region p2 is the element isolation. What is necessary is just to be formed so that it may join to the side wall part of the area | region 13 (13-2).
The first p-type region p1 is formed of, for example, a non-doped epitaxial growth layer together with the first n-type region n1, and the boron (B) concentration in the film is, for example, 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .
The film thickness of the epitaxial growth layer portion is preferably about 50 nm to 300 nm, for example, as long as the first p-type region p1 can function as an anode electrode.
The first p-type region p <b> 1 is joined to the side wall of the sidewall 24.

  Therefore, the junction position of the first p-type region p1 and the first n-type region n1 in the side wall portion of the element isolation region 13 (13-2) is, for example, a position having a depth of 50 nm to 200 nm from the surface of the semiconductor substrate 11; For example, it is formed so as to be at a depth of 100 nm.

On the semiconductor substrate 11 on the other side of the thyristor gate electrode 22, a second n-type region n2 (fourth region) made of an epitaxial growth layer obtained by introducing an n-type dopant is formed.
In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p 2, and the film thickness is the surface of the semiconductor substrate 11. However, it is important that the second n-type region n2 has a film thickness that functions as a cathode electrode.
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The second n-type region n2 may be formed in the semiconductor substrate 11 by ion implantation.

  In addition, a metal silicide layer (not shown) may be formed on the surface of the first p-type region p1, the surface of the second n-type region n2, and the thyristor gate electrode 22 to reduce the resistance. As the metal silicide, a metal silicide used in a normal MOS device or the like, such as titanium silicide, cobalt silicide, nickel silicide, or the like can be used.

In the semiconductor device 1, the first n-type region n1 includes the element growth region 13 (the epitaxial growth layer epitaxially grown on a part of the second p-type region p2 and the part of the second p-type region p2 below the epitaxial growth layer. 13-2) is formed so that one end thereof is joined to the side wall portion. Therefore, the first p-type region p1 and the second p-type region p2 are defined by the first n-type region n1 and the element isolation region 13 (13-2). Will be separated. Therefore, the first p-type region p1 and the second p-type region p2 are not short-circuited.
In addition, since the first n-type region n1 having a sufficient thickness is provided between the first p-type region p1 and the second p-type region p2, for example, the depletion layer in which the first n-type region n1 is generated at the front-side interface and the back-side interface. As a result, the occurrence of punch-through between the first p-type region p1 and the second p-type region p2 can be eliminated.
Therefore, the junction of the first p-type region p1 and the first n-type region n1 in the thyristor in which the first p-type region p1, the first n-type region n1, the second p-type region p2, and the second n-type region n2 are sequentially joined, the first n Since the junction between the type region n1 and the second p-type region p2 can function, normal thyristor characteristics can be obtained.

  Next, an embodiment (second example) according to the semiconductor device (first semiconductor device) of the present invention will be described with reference to the schematic sectional view of FIG.

  As shown in FIG. 2, an element isolation region 13 for isolating the element formation region 12 for forming the thyristor T2 is formed in the semiconductor substrate 11. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation).

A first conductivity type (p-type) first p-type region p1 (first region) and a second conductivity type (n-type) opposite to the first conductivity type are formed in the element formation region 12 and the upper portion thereof. The first n-type region n1 (second region), the first conductivity type (p-type) second p-type region p2 (third region), and the second conductivity-type (n-type) second n-type region n2 (fourth) A semiconductor device 2 is formed which is composed of a thyristor T <b> 2 that is joined in order to the region.
Here, the first conductivity type is described as p-type and the second conductivity type is described as n-type, but conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Details will be described below.
For example, an n-well region (not shown) may be formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation region 12 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 is formed by doping with boron (B), and the concentration thereof is, for example, 5 × 10 ¹⁸ cm ^−3, which is about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. desirable. Basically, it must be lower than the dopant concentration of the first n-type region n1 of the second conductivity type (n-type) described later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm.
The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A thyristor gate electrode 22 can be formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the thyristor gate electrode 22 as a hard mask.

Sidewalls 23 and 24 are formed on the side wall of the thyristor gate electrode 22. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

On one side of the thyristor gate electrode 22, a first n-type region n1 (second region) of the second conductivity type (n-type) is formed. The first n-type region n1 is formed in the element isolation region 13 (on the part of the second p-type region p2 above the second p-type region p2 (third region) and below the first n-type region n1. 13-2) is formed so that one end is joined to the side wall portion of the element isolation region 13 (13-2) at a position deeper than the surface of 13-2). The first n-type region n1 above the second p-type region p2 is formed of, for example, an epitaxially grown layer formed by epitaxial growth. This epitaxial growth layer is, for example, a non-doped epitaxial growth layer. The first n-type region n1 is formed by performing ion implantation on the non-doped epitaxial growth layer and part of the second p-type region p2.
The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2, and the first p-type region described below It is necessary to be lower than p1 (first region). Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The film thickness of the first n-type region n1 is desirably about 50 nm to 300 nm, for example, as the film thickness of the epitaxial growth layer portion.
The first n-type region n1 (second region) is joined to the sidewall of the sidewall 24.

A first p-type region p1 (first region) of the first conductivity type (p-type) is formed on the first n-type region n1.
The first p-type region p1 is formed on the second region of the epitaxial growth layer and a part of the third region below the epitaxial growth layer, and at least on the surface of the element isolation region 13 (13-2). One end is formed to be joined.
The first p-type region p1 is formed, for example, by selective epitaxial growth, and the boron (B) concentration in the film is, for example, 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .
The film thickness of the epitaxial growth layer portion is preferably about 50 nm to 300 nm, for example, as long as the first p-type region p1 can function as an anode electrode.
The first p-type region p <b> 1 is joined to the side wall of the sidewall 24.

  Therefore, the junction position of the first p-type region p1 and the first n-type region n1 in the side wall portion of the element isolation region 13 is, for example, a position having a depth of 50 nm to 200 nm from the surface of the semiconductor substrate 11, for example, a depth of 100 nm. It is formed to be in the position.

On the semiconductor substrate 11 on the other side of the thyristor gate electrode 22, a second n-type region n2 (fourth region) made of an epitaxial growth layer obtained by introducing an n-type dopant is formed.
In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p 2, and the film thickness is the surface of the semiconductor substrate 11. However, it is important that the second n-type region n2 has a film thickness that functions as a cathode electrode.
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The second n-type region n2 may be formed in the semiconductor substrate 11 by ion implantation.

  In addition, a metal silicide layer (not shown) may be formed on the surface of the first p-type region p1, the surface of the second n-type region n2, and the thyristor gate electrode 22 to reduce the resistance. As the metal silicide, a metal silicide used in a normal MOS device or the like, such as titanium silicide, cobalt silicide, nickel silicide, or the like can be used.

In the semiconductor device 2, the first n-type region n 1 includes the element isolation region 13 (on the epitaxial growth layer epitaxially grown on a part of the second p-type region p 2 and a part of the second p-type region p 2 below the epitaxial growth layer. 13-2) is formed so that one end thereof is joined to the side wall portion. Therefore, the first p-type region p1 and the second p-type region p2 are defined by the first n-type region n1 and the element isolation region 13 (13-2). Will be separated. Therefore, the first p-type region p1 and the second p-type region p2 are not short-circuited.
In addition, since the first n-type region n1 having a sufficient thickness is provided between the first p-type region p1 and the second p-type region p2, for example, the depletion layer in which the first n-type region n1 is generated at the front-side interface and the back-side interface. As a result, the occurrence of punch-through between the first p-type region p1 and the second p-type region p2 can be eliminated.
Therefore, the junction of the first p-type region p1 and the first n-type region n1 in the thyristor in which the first p-type region p1, the first n-type region n1, the second p-type region p2, and the second n-type region n2 are sequentially joined, the first n Since the junction between the type region n1 and the second p-type region p2 can function, normal thyristor characteristics can be obtained.

  Next, an embodiment (example) according to the semiconductor device (second semiconductor device) of the present invention will be described with reference to the schematic configuration cross-sectional view of FIG.

  As shown in FIG. 3, an element isolation region 13 for isolating the element formation region 12 for forming the thyristor T3 is formed in the semiconductor substrate 11. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation).

A first conductivity type (p-type) first p-type region p1 (first region) and a second conductivity type (n-type) opposite to the first conductivity type are formed in the element formation region 12 and the upper portion thereof. The first n-type region n1 (second region), the first conductivity type (p-type) second p-type region p2 (third region), and the second conductivity-type (n-type) second n-type region n2 (fourth) A semiconductor device 3 is formed which is composed of a thyristor T4 that is sequentially joined to the region.
Here, the first conductivity type is described as p-type and the second conductivity type is described as n-type, but conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Details will be described below.
For example, an n-well region (not shown) may be formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation region 12 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 is formed by doping with boron (B), and the concentration thereof is, for example, 5 × 10 ¹⁸ cm ^−3, which is about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. desirable. Basically, it must be lower than the dopant concentration of the first n-type region n1 of the second conductivity type (n-type) described later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm.
The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A thyristor gate electrode 22 can be formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the thyristor gate electrode 22 as a hard mask.

Sidewalls 23 and 24 are formed on the side wall of the thyristor gate electrode 22. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

On one side of the thyristor gate electrode 22, a first n-type region n1 (second region) of the second conductivity type (n-type) is formed. The first n-type region n1 is formed of an epitaxial growth layer epitaxially grown on a part of the second p-type region p2 (third region).
The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2, and the first p-type region described below It is necessary to be lower than p1 (first region). Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The film thickness of the first n-type region n1 is desirably about 50 nm to 300 nm, for example, as the film thickness of the epitaxial growth layer portion.
The first n-type region n1 (second region) is joined to the sidewall of the sidewall 24.

A first p-type region p1 (first region) of the first conductivity type (p-type) is formed on the first n-type region n1.
The first p-type region p1 is formed on the first n-type region n1 and the first n-type region n1 surface on which the first p-type region p1 is formed has a first p-type region p1 around the side of the first p-type region p1. The 1n-type region n1 is formed.
The first p-type region p1 is formed, for example, by selective epitaxial growth, and the boron (B) concentration in the film is, for example, 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .
The film thickness of the epitaxial growth layer portion is preferably about 50 nm to 300 nm, for example, as long as the first p-type region p1 can function as an anode electrode.
Therefore, the first p-type region p1 is not joined to the sidewall of the sidewall 24. If the first n-type region n1 is bonded to the sidewall of the sidewall 24, the first p-type region p1 may be bonded to the sidewall of the sidewall 24.

On the semiconductor substrate 11 on the other side of the thyristor gate electrode 22, a second n-type region n2 (fourth region) made of an epitaxial growth layer obtained by introducing an n-type dopant is formed.
In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p 2, and the film thickness is the surface of the semiconductor substrate 11. However, it is important that the second n-type region n2 has a film thickness that functions as a cathode electrode.
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
The second n-type region n2 may be formed in the semiconductor substrate 11 by ion implantation.

  In addition, a metal silicide layer (not shown) may be formed on the surface of the first p-type region p1, the surface of the second n-type region n2, and the thyristor gate electrode 22 to reduce the resistance. As the metal silicide, a metal silicide used in a normal MOS device or the like, such as titanium silicide, cobalt silicide, nickel silicide, or the like can be used.

In the semiconductor device 4, the first p-type region p1 is formed on the first n-type region n1 and around the first p-type region p1 on the surface of the first n-type region n1 where the first p-type region p1 is formed. Since the first n-type region n1 is formed, the first p-type region p1 and the second p-type region p2 are separated by the first n-type region n1. Therefore, the first p-type region p1 and the second p-type region p2 are not short-circuited.
In addition, since the first n-type region n1 having a sufficient thickness is provided between the first p-type region p1 and the second p-type region p2, for example, the depletion layer in which the first n-type region n1 is generated at the front-side interface and the back-side interface. As a result, the occurrence of punch-through between the first p-type region p1 and the second p-type region p2 can be eliminated.
Therefore, the junction of the first p-type region p1 and the first n-type region n1 in the thyristor in which the first p-type region p1, the first n-type region n1, the second p-type region p2, and the second n-type region n2 are sequentially joined, the first n Since the junction between the type region n1 and the second p-type region p2 can function, normal thyristor characteristics can be obtained.

  Further, in the semiconductor device 2, since the facet regions of the first p-type region p1 and the first n-type region n1 that are likely to cause defects due to epitaxial growth do not contact each other, the first p-type region p1 and the first n-type region n1 are not in contact with each other. Junction leakage current can be reduced. As a result, variations in thyristor electrical characteristics and an increase in off current can be suppressed.

  Next, an embodiment (example) according to the method for manufacturing a semiconductor device (first manufacturing method) of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS. This first manufacturing method is an example of a method for manufacturing the semiconductor device 1 of the first embodiment of the first semiconductor device.

  As shown in FIG. 4A, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 13 for isolating the element formation region 12 is formed in the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region (not shown) may be formed below the element formation region 12.

Thereafter, the upper portion of the element formation region 12 of the semiconductor substrate 11 is formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of this ion implantation condition, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 5 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later.
The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

Next, as shown in FIG. 4B, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, a thyristor gate electrode 22 is formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

The thyristor gate electrode 22 is formed by, for example, forming a gate electrode forming film on the gate insulating film 21, then applying a normal resist, forming an etching mask by a lithography technique, and etching technique using the etching mask. The gate electrode formation film is formed by etching. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, sidewalls 23 and 24 are formed on the sidewalls of the thyristor gate electrode 22. For example, after forming a sidewall formation film so as to cover the thyristor gate electrode 22, the sidewall formation film is etched back to form the sidewalls 23 and 24 on the sidewall of the thyristor gate electrode 22. Can do. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.
Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example.

Next, as shown in FIG. 4 (3), a first epitaxial growth mask 31 having an opening 32 is formed on the second p-type region p 2 on one side of the thyristor gate electrode 22.
In order to form the first epitaxial growth mask 31, for example, a mask formation film is formed so as to cover the thyristor gate electrode 22, the sidewalls 23 and 24, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.
Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on one side of the thyristor gate electrode 22 by a normal resist coating and lithography technique, and this is used as an etching mask. By using this, the first epitaxial growth mask 31 is formed. As a result, the second p-type region p2 in the region where the first n-type region is formed is exposed.
As the first epitaxial growth mask 31, a silicon nitride film is used as an example. However, any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as selectivity can be maintained during epitaxial growth. It may be.

Next, as shown in FIG. 5 (4), a non-doped epitaxial growth layer 33 is formed on the semiconductor substrate 11 (second p-type region p 2) in the opening 32 by a selective epitaxial growth technique using the first epitaxial growth mask 31. Form.
The epitaxial growth layer 33 is formed to have a film thickness including the first n-type region n1 and the first p-type region p1 formed thereon. For example, when it is desired to set the thickness of the first p-type region p1 to 100 nm and the thickness of the first n-type region n1 to 100 nm, the thickness of the epitaxial growth layer 33 is set to 200 nm. The film thickness of the epitaxial growth layer 33 is desirably 100 nm to 600 nm.
Further, in order to prevent the first p-type region p1 and the second p-type region p2 from being connected at the time of ion implantation for forming the first p-type region p1 described later, this selective epitaxial growth is performed along the side wall of the sidewall 24. Do as follows.

Next, as shown in FIG. 5 (5), the second p-type region p2 (epitaxial growth layer 33) between the thyristor gate electrode 22 and the element formation region 13 (13-2) is formed by ordinary resist coating and lithography techniques. ) An ion implantation mask (not shown) having an upper opening is formed.
Next, by an ion implantation technique using the ion implantation mask, a second distance is formed so that one end is bonded to the side wall portion of the element isolation region 13 (13-2) at a predetermined distance from the surface of the epitaxial growth layer 33. The first n-type region n1 (second region) is formed by ion implantation of a conductivity type (n-type) impurity. The other end of the first n-type region n1 is joined to the sidewall of the sidewall 24.

The ion implantation conditions are set so that, for example, phosphorus (P) is used as a dopant and the concentration is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . In order to implant ions at such a concentration, for example, when phosphorus is used, the implantation energy is set to 100 keV and the implantation amount is set to 5 × 10 ¹³ cm ⁻² . This concentration is desirably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^{−3 and} needs to be lower than the dopant concentration of the first p-type region p1 to be formed next. Further, it is preferably higher than the dopant concentration of the second p-type region p2.
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

Next, as shown in FIG. 6 (6), by the ion implantation technique using the ion implantation mask (not shown), the epitaxial growth layer 33 and the second p-type region p 2 below the epitaxial growth layer 33 are formed. A first conductivity type (p-type) impurity is ion-implanted so that one end is joined to the side wall of the element isolation region 13 (13-2), and the first p-type region p1 is formed above the first n-type region n1. (First region) is formed.
As for the ion implantation conditions, for example, a p-type impurity such as boron or indium is used as a dopant, and the concentration is desirably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . For example, in the case of ion implantation using boron, for example, the implantation energy is set to 5 keV and the implantation amount is set to 1 × 10 ¹⁵ cm ⁻² .
The junction between the first p-type region p1 and the first n-type region n1 is, for example, an ion of the first p-type region p1 and the first n-type region n1 so as to be formed at a position of 100 nm from the surface of the epitaxial growth layer 33. Adjust injection energy. The junction depth is designed so that the distance from the semiconductor substrate 11 to the junction position is larger than the depletion layer width of the first n-type region n1, and is preferably about 50 to 200 nm from the surface of the semiconductor substrate 11.
Thereafter, the ion implantation mask is removed.

Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example. The conditions at this time may be within a range where the dopant can be activated.
Moreover, whichever may be the first ion implantation order of the first p-type region p1 and the first n-type region n1.

Next, as shown in FIG. 6 (7), a second epitaxial growth mask 34 having an opening 35 is formed on the second p-type region p 2 on the other side of the thyristor gate electrode 22.
For the second epitaxial growth mask 34, for example, a mask formation film is formed so as to cover the first epitaxial growth mask 31, the first p-type region p1, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.

Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on the other side of the thyristor gate electrode 22 by ordinary resist coating and lithography techniques, and this is used as an etching mask. By using this, the second epitaxial growth mask 34 is formed. The opening 35 formed in the second epitaxial growth mask 34 is also formed in the first epitaxial growth mask 31 below it. As a result, the second p-type region p2 in the region where the second n-type region is formed is exposed.
As the second epitaxial growth mask 34, a silicon nitride film is used as an example. However, any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as selectivity can be maintained during epitaxial growth. It may be.

Next, an epitaxial growth layer in which an n-type impurity (for example, phosphorus, arsenic, etc.) is doped on the semiconductor substrate 11 (second p-type region p2) of the opening 35 by a selective epitaxial growth technique using the second epitaxial growth mask 34. A second n-type region n2 (fourth region) is formed. As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example. Further, the film thickness of the second n-type region n2 is preferably 50 nm to 300 nm, and may be a film thickness within a range where the second n-type region n2 can function as a cathode electrode.

The second n-type region n2 can be performed before the first epitaxial growth mask 34 and the first epitaxial growth layer 33 are formed. In this case, the second epitaxial growth mask 34 is formed first to form the second n-type region n2, and then the first epitaxial growth mask 31 and the first epitaxial growth layer 33 are formed, and the first n-type region n1 and the first n-type region n1 are formed by ion implantation. The 1p type region p1 may be formed.
Either the first n-type region n1 or the first p-type region p1 may be formed first.

Moreover, in the said Example, although produced in order of the 1st p-type area | region p1 and the 2nd n-type area | region n2, you may form in order of the 2nd n-type area | region n2 and the 1st p-type area | region p1.
Further, if necessary, activation annealing may be performed in one or both of the first p-type region p1 and the second n-type region n2. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  Next, although not shown, in order to expose each thyristor gate electrode 22, each first p-type region p1, and second n-type region n2, the first epitaxial growth mask 31 and the second epitaxial growth mask 34 on each region are removed. . Then, before forming an interlayer insulating film (not shown), a metal silicide layer is formed on each exposed first p-type region p1, second n-type region n2, and sidewall gate electrode 22 by a salicide process. This metal silicide layer is formed of, for example, titanium silicide, cobalt silicide, or nickel silicide. Thereafter, an interlayer insulating film is formed, and a wiring process similar to a normal CMOS process is performed.

In the semiconductor device manufacturing method (first manufacturing method), the first n-type region n1 includes the first epitaxial growth layer 33 epitaxially grown on a part of the second p-type region p2, and the first epitaxial growth layer 33 below the first epitaxial growth layer 33. Since the first p-type region p1 and the second p-type region p2 are formed in a part of the 2p-type region p2 so that one end is joined to the side wall portion of the element isolation region 13, the first n-type region n1 and the first p-type region p1 It is formed so as to be isolated by the element isolation region 13.
For this reason, a short circuit between the first p-type region p1 and the second p-type region p2 can be prevented. Furthermore, the occurrence of punch-through can be prevented.
Therefore, the first p-type region p1 (first region), the first n-type region n1 (second region), the second p-type region p2 (third region), and the second n-type region n2 (fourth region) are sequentially joined. Since the junction between the first p-type region p1 and the first n-type region n1 and the junction between the first n-type region n1 and the second p-type region p2 in the thyristor can function, normal thyristor characteristics can be obtained.

  Next, an embodiment (Example) according to the method for manufacturing a semiconductor device (second manufacturing method) of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS. This second manufacturing method is an example of a method for manufacturing the semiconductor device 2 of the second embodiment of the first semiconductor device.

  As shown in FIG. 7A, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 13 for isolating the element formation region 12 is formed in the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region (not shown) may be formed below the element formation region 12.

Thereafter, the upper portion of the element formation region 12 of the semiconductor substrate 11 is formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of this ion implantation condition, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 5 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later.
The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

Next, as shown in FIG. 7B, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, a thyristor gate electrode 22 is formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

The thyristor gate electrode 22 is formed by, for example, forming a gate electrode forming film on the gate insulating film 21, then applying a normal resist, forming an etching mask by a lithography technique, and etching technique using the etching mask. The gate electrode formation film is formed by etching. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, sidewalls 23 and 24 are formed on the sidewalls of the thyristor gate electrode 22. For example, after forming a sidewall formation film so as to cover the thyristor gate electrode 22, the sidewall formation film is etched back to form the sidewalls 23 and 24 on the sidewall of the thyristor gate electrode 22. Can do. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

  Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example.

Next, as shown in FIG. 7 (3), a first epitaxial growth mask 36 having an opening 37 is formed on the second p-type region p 2 on one side of the thyristor gate electrode 22. Here, the element isolation region 13 (13-2) side of the opening 37 is formed so as to expose the boundary between the second p-type region p2 and the element isolation region 13 (13-2).
In order to form the first epitaxial growth mask 36, for example, a mask forming film is formed of an insulating film so as to cover the thyristor gate electrode 22, the side walls 23, 24, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.
Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on one side of the thyristor gate electrode 22 by a normal resist coating and lithography technique, and this is used as an etching mask. The first epitaxial growth mask 37 having the opening 37 is used. As a result, the second p-type region p2 in the region where the first n-type region is formed is exposed.
As the first epitaxial growth mask 36, a silicon nitride film is used as an example. However, a film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

Next, as shown in FIG. 8D, a non-doped epitaxial growth layer 38 is formed on the semiconductor substrate 11 (second p-type region p2) in the opening 37 by a selective epitaxial growth technique using the first epitaxial growth mask 36. Form.
The epitaxial growth layer 38 is formed to have a thickness of the first n-type region formed thereon. For example, when it is desired to set the thickness of the first p-type region p1 to 100 nm, the thickness of the epitaxial growth layer 38 is set to 100 nm. The film thickness of the epitaxial growth layer 38 is desirably 50 nm to 300 nm.
Further, this selective epitaxial growth is performed so as to grow along the side wall of the sidewall 24 so that the first p-type region and the second p-type region p2 are not connected when the first p-type region described later is formed.

Next, as shown in FIG. 8 (5), the second p-type region p2 (epitaxial growth layer 38) between the thyristor gate electrode 22 and the element isolation region 13 (13-2) is formed by ordinary resist coating and lithography techniques. ) An ion implantation mask (not shown) having an upper opening is formed.
Next, by the ion implantation technique using the ion implantation mask, the epitaxial growth layer 38 and a part of the second p-type region p2 below the epitaxial growth layer 38 are formed on the side wall portion of the element isolation region 13 (13-2). The first n-type region n1 (second region) is formed by ion-implanting a second conductivity type (n-type) impurity so that one end is joined. The other end of the first n-type region n1 is joined to the sidewall of the sidewall 24.

The ion implantation conditions are set so that, for example, phosphorus (P) is used as a dopant and the concentration is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . In order to perform ion implantation at such a concentration, for example, when phosphorus is used, the implantation energy is set to 20 keV and the implantation amount is set to 1 × 10 ¹³ cm ⁻² . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^{−3, and} needs to be lower than the dopant concentration of the first p-type region p1 to be formed next. Further, it is preferably higher than the dopant concentration of the second p-type region p2.
Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.
Thus, the junction position between the first n-type region n1 and the second p-type region p2 on the side wall of the element isolation region 13 (13-2) is closer to the semiconductor substrate 11 than the boundary between the semiconductor substrate 11 and the epitaxial growth layer 38. The ion implantation energy for forming the first n-type region n1 is adjusted so as to be formed at the intrusion position.
Thereafter, the ion implantation mask is removed.

  Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example. The conditions at this time may be within a range where the dopant can be activated.

Next, as shown in FIG. 9 (6), a first conductivity type (p-type) first p-type region p1 (first region) is formed in the opening 37 on the first n-type region n1. At this time, one end of the first p-type region p1 may be formed to be bonded to the surface of the element isolation region 13 (13-2).
The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 200 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode.
The gas used for the dopant may be any gas containing p-type impurities, and an organic source containing p-type impurities can also be used.
At this time, if necessary, the epitaxially grown surface may be cleaned using a chemical solution such as hydrofluoric acid (HF) or hydrogen (H ₂ ) gas.
Further, if necessary, subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to, for example, 900 ° C., and then, for example, heating to 900 ° C. and entering the cooling process in less than 1 second. The conditions at this time may be within a range where the dopant can be activated.

Next, as shown in FIG. 9 (7), a second epitaxial growth mask 39 having an opening 40 is formed on the second p-type region p 2 on the other side of the thyristor gate electrode 22.
For the second epitaxial growth mask 39, for example, a mask formation film is formed so as to cover the first epitaxial growth mask 36, the first p-type region p1, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.

Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on the other side of the thyristor gate electrode 22 by ordinary resist coating and lithography techniques, and this is used as an etching mask. The second epitaxial growth mask 39 having the opening 40 is used. In this etching, an opening 40 is also formed in the first epitaxial growth mask 36. As a result, the second p-type region p2 in the region where the second n-type region n2 is formed is exposed.
As the second epitaxial growth mask 39, a silicon nitride film is used as an example. However, a film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

Next, an epitaxial growth layer in which an n-type impurity (for example, phosphorus, arsenic, etc.) is doped on the semiconductor substrate 11 (second p-type region p2) of the opening 40 by a selective epitaxial growth technique using the second epitaxial growth mask 39. A second n-type region n2 (fourth region) is formed. As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example. Further, the film thickness of the second n-type region n2 is preferably 50 nm to 300 nm, and may be a film thickness within a range where the second n-type region n2 can function as a cathode electrode.

  The second n-type region n2 can be performed before forming the first epitaxial growth mask 36, the first n-type region n1, and the first p-type region p1. In this case, the second epitaxial growth mask 39 is formed first to form the second n-type region n2, and then the first epitaxial growth mask 36, the first n-type region n1, and the first p-type region p1 are formed.

  Further, if necessary, activation annealing may be performed in one or both of the first p-type region p1 and the second n-type region n2. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  Next, although not shown, in order to expose the thyristor gate electrode 22, the first p-type region p1, and the second n-type region n2, the first epitaxial growth mask 36 and the second epitaxial growth mask 39 on the respective regions are removed. Then, before forming an interlayer insulating film (not shown), a metal silicide layer is formed on each exposed first p-type region p1, second n-type region n2, and sidewall gate electrode 22 by a salicide process. This metal silicide layer is formed of, for example, titanium silicide, cobalt silicide, or nickel silicide. Thereafter, an interlayer insulating film is formed, and a wiring process similar to a normal CMOS process is performed.

In the semiconductor device manufacturing method (second manufacturing method), a non-doped first epitaxial growth layer 38 is formed on a part of the second p-type region p2 on one side of the thyristor gate electrode 22, and this non-doped first epitaxial growth is performed. An n-type impurity is ion-implanted into the layer 38 and a part of the second p-type region p2 below the first epitaxial growth layer 38 so that one end is joined to the side wall portion of the element isolation region 13. n1 is formed. Further, since the first p-type region p1 is formed on the first n-type region n1 by selective epitaxial growth, the first p-type region p1 and the second p-type region p2 are separated by the first n-type region n1 and the element isolation region 13. It is formed so that.
For this reason, a short circuit between the first p-type region p1 and the second p-type region p2 can be prevented. Furthermore, the occurrence of punch-through can be prevented.
Therefore, the first p-type region p1 (first region), the first n-type region n1 (second region), the second p-type region p2 (third region), and the second n-type region n2 (fourth region) are sequentially joined. Since the junction between the first p-type region p1 and the first n-type region n1 and the junction between the first n-type region n1 and the second p-type region p2 in the thyristor can function, normal thyristor characteristics can be obtained.

  Next, an embodiment (Example) according to the method for manufacturing a semiconductor device (third manufacturing method) of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS.

As shown in FIG. 10A, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 13 for isolating the element formation region 12 is formed in the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region (not shown) may be formed below the element formation region 12.
Thereafter, the upper portion of the element formation region 12 of the semiconductor substrate 11 is formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of this ion implantation condition, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 5 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later.
The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

Next, as shown in FIG. 10B, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, a thyristor gate electrode 22 is formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

The thyristor gate electrode 22 is formed by, for example, forming a gate electrode forming film on the gate insulating film 21, then applying a normal resist, forming an etching mask by a lithography technique, and etching technique using the etching mask. The gate electrode formation film is formed by etching. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, sidewalls 23 and 24 are formed on the sidewalls of the thyristor gate electrode 22. For example, after forming a sidewall formation film so as to cover the thyristor gate electrode 22, the sidewall formation film is etched back to form the sidewalls 23 and 24 on the sidewall of the thyristor gate electrode 22. Can do. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

  Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example.

Next, as shown in FIG. 10 (3), a first epitaxial growth mask 41 having an opening 42 is formed on the second p-type region p 2 on one side of the thyristor gate electrode 22.
In order to form the first epitaxial growth mask 41, for example, a mask formation film is formed so as to cover the thyristor gate electrode 22, the sidewalls 23 and 24, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.
Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on one side of the thyristor gate electrode 22 by a normal resist coating and lithography technique, and this is used as an etching mask. By using this, the first epitaxial growth mask 41 is formed. As a result, the second p-type region p2 in the region where the first n-type region is formed is exposed.
As the first epitaxial growth mask 41, a silicon nitride film is used as an example. However, any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as selectivity can be maintained during epitaxial growth. It may be.

Next, as shown in FIG. 11 (4), an n-type impurity (for example, on the semiconductor substrate 11 (second p-type region p2) in the opening 42 is formed by a selective epitaxial growth technique using the first epitaxial growth mask 41. An epitaxial growth layer 43 doped with phosphorus, arsenic, or the like is formed so as to cover the boundary between the element isolation region 13 and the second p-type region p2.
The epitaxial growth layer 43 is formed to have a film thickness that includes the first n-type region and the first p-type region formed thereon. For example, when it is desired to set the thickness of the first p-type region to 100 nm and the thickness of the first n-type region to 100 nm, the thickness of the epitaxial growth layer 43 is set to 200 nm. The film thickness of this epitaxial growth layer 43 is desirably 100 nm to 600 nm.
Further, this selective epitaxial growth is performed so as to grow along the side wall of the sidewall 24 so that the first p-type region and the second p-type region p2 are not connected when the first p-type region described later is formed.

As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example.

Next, as shown in FIG. 11 (5), the second p-type region p2 (epitaxial growth layer 43) between the thyristor gate electrode 22 and the element formation region 13 (13-2) is formed by ordinary resist coating and lithography techniques. ) An ion implantation mask (not shown) having an upper opening is formed.
Next, by the ion implantation technique using the ion implantation mask, the first conductivity type (p-type) is formed so that one end is bonded to the surface of the element isolation region 13 (13-2) on the surface side of the epitaxial growth layer 43. The first p-type region p1 (first region) is formed by ion implantation of the impurity. At this time, the other end of the first p-type region p <b> 1 is ion-implanted so as to be joined to the sidewall of the sidewall 24. Further, the first n-type region n1 is left so that the first n-type region n1 covers the boundary between the second p-type region p2 and the element formation region 13 (13-2).
Therefore, in the ion implantation, the first p-type region p1 and the second p-type region p2 are formed so as to be separated by the first n-type region n1 and the element isolation region 13.

The junction depth between the first p-type region p1 and the first n-type region n1 is designed so that the distance from the surface of the epitaxial growth layer 43 to the junction position is larger than the depletion layer width of the first n-type region n1. Depending on the film thickness of the epitaxially grown layer 43, it is desirable that the position be about 50 nm to 200 nm from the surface.
The dopant concentration at this time is, for example, boron, and the concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ⁻³ . The dopant may be a p-type impurity such as indium.
For example, when the film thickness of the epitaxial growth layer 43 is 200 nm, the ion implantation is such that the junction position between the first p-type region p1 and the first n-type region n1 is formed at a position of 100 nm from the surface of the epitaxial growth layer 43. Adjust the ion implantation energy. For example, when boron is used, the implantation energy is set to 5 keV and the implantation amount is set to 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 11 (6), a second epitaxial growth mask 44 having an opening 45 is formed on the second p-type region p 2 on the other side of the thyristor gate electrode 22.
In order to form the second epitaxial growth mask 44, for example, a mask formation film is formed so as to cover the first epitaxial growth mask 41, the first p-type region p1, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.

Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on the other side of the thyristor gate electrode 22 by ordinary resist coating and lithography techniques, and this is used as an etching mask. The second epitaxial growth mask 44 having the opening 45 is used. The opening 45 is also formed in the first epitaxial growth mask 41. As a result, the second p-type region p2 in the region where the second n-type region n2 is formed is exposed.
As the second epitaxial growth mask 44, a silicon nitride film is used as an example. However, a film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

Next, an epitaxial growth layer in which an n-type impurity (for example, phosphorus, arsenic, etc.) is doped on the semiconductor substrate 11 (second p-type region p2) of the opening 45 by a selective epitaxial growth technique using the second epitaxial growth mask 44. A second n-type region n2 (fourth region) is formed. As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example. Further, the film thickness of the second n-type region n2 is preferably 50 nm to 300 nm, and may be a film thickness within a range where the second n-type region n2 can function as a cathode electrode.

  The second n-type region n2 may be performed before the first epitaxial growth mask 41, the first n-type region n1, and the first p-type region p1 are formed. In this case, the second epitaxial growth mask 44 is formed first to form the second n-type region n2, and then the first epitaxial growth mask 41, the first n-type region n1, and the first p-type region p1 are formed.

  Further, if necessary, activation annealing may be performed in one or both of the first p-type region p1 and the second n-type region n2. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  Next, although not shown, in order to expose the thyristor gate electrode 22, the first p-type region p1, and the second n-type region n2, the first epitaxial growth mask 41 and the second epitaxial growth mask 44 on each region are removed. Then, before forming an interlayer insulating film (not shown), a metal silicide layer is formed on each exposed first p-type region p1, second n-type region n2, and sidewall gate electrode 22 by a salicide process. This metal silicide layer is formed of, for example, titanium silicide, cobalt silicide, or nickel silicide. Thereafter, an interlayer insulating film is formed, and a wiring process similar to a normal CMOS process is performed.

In the semiconductor device manufacturing method (third manufacturing method), the epitaxial growth layer 43 doped with the second conductivity type impurity is formed on the second p-type region p2 on one side of the thyristor gate electrode 22 with the element isolation region 13 and the second p-type. When the first p-type region p1 is formed by ion-implanting a p-type impurity on the surface side of the epitaxial growth layer 43 so as to cover the boundary with the region p2, the ion implantation is performed in the first p-type region p1. The first n-type region n1 exists between the first p-type region p2 and the second p-type region p2, and the first n-type region n1 covering the boundary between the second p-type region p2 and the element isolation region 13 is maintained. The first p-type region p1 and the second p-type region p2 are formed so as to be separated by the first n-type region n1 and the element isolation region 13.
For this reason, a short circuit between the first p-type region p1 and the second p-type region p2 can be prevented. Furthermore, the occurrence of punch-through can be prevented.
Therefore, the first p-type region p1 (first region), the first n-type region n1 (second region), the second p-type region p2 (third region), and the second n-type region n2 (fourth region) are sequentially joined. Since the junction between the first p-type region p1 and the first n-type region n1 and the junction between the first n-type region n1 and the second p-type region p2 in the thyristor can function, normal thyristor characteristics can be obtained.

  Next, an embodiment (Example) according to the method for manufacturing a semiconductor device (fourth manufacturing method) of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS. This fourth manufacturing method is an example of a method for manufacturing the semiconductor device 3 of the embodiment of the second semiconductor device.

As shown in FIG. 12A, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 13 for isolating the element formation region 12 is formed in the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region (not shown) may be formed below the element formation region 12.
Thereafter, the upper portion of the element formation region 12 of the semiconductor substrate 11 is formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of this ion implantation condition, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 5 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later.
The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

Next, as shown in FIG. 12B, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, a thyristor gate electrode 22 is formed on the gate insulating film 21. The thyristor gate electrode 22 is usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

The thyristor gate electrode 22 is formed by, for example, forming a gate electrode forming film on the gate insulating film 21, then applying a normal resist, forming an etching mask by a lithography technique, and etching technique using the etching mask. The gate electrode formation film is formed by etching. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, sidewalls 23 and 24 are formed on the sidewalls of the thyristor gate electrode 22. For example, after forming a sidewall formation film so as to cover the thyristor gate electrode 22, the sidewall formation film is etched back to form the sidewalls 23 and 24 on the sidewall of the thyristor gate electrode 22. Can do. The sidewalls 23 and 24 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

  Subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to 900 ° C., for example, spike annealing is performed in which the cooling process is started in less than 1 second after heating to 900 ° C., for example.

Next, as shown in FIG. 12 (3), a first epitaxial growth mask 46 having an opening 47 is formed on the second p-type region p 2 on one side of the thyristor gate electrode 22.
For the first epitaxial growth mask 46, for example, a mask forming film is formed so as to cover the thyristor gate electrode 22, the side walls 23, 24, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.
Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on one side of the thyristor gate electrode 22 by a normal resist coating and lithography technique, and this is used as an etching mask. The first epitaxial growth mask 46 having the opening 47 is used. As a result, the second p-type region p2 in the region where the first n-type region is formed is exposed.
As the first epitaxial growth mask 46, a silicon nitride film is used as an example, but any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

  Next, as shown in FIG. 13 (4), an n-type impurity (for example, on the semiconductor substrate 11 (second p-type region p2) of the opening 47 is formed by a selective epitaxial growth technique using the first epitaxial growth mask 46. A first n-type region n1 composed of an epitaxial growth layer doped with phosphorus, arsenic, or the like is formed. For example, the thickness of the first n-type region n1 is 100 nm. The film thickness of the first n-type region n1 made of this epitaxial growth layer is desirably 50 nm to 300 nm.

As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example.

Next, as shown in FIG. 13 (5), a second epitaxial growth mask 48 having an opening 49 on the first n-type region n1 is formed of an insulating film.
For the second epitaxial growth mask 48, for example, a mask formation film is formed so as to cover the first epitaxial growth mask 46, the first n-type region n1, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.
Thereafter, a mask (not shown) made of a resist having an opening is formed on the first n-type region n1 by ordinary resist coating and lithography techniques, and is used as an etching mask to form the first n-type region n1. The second epitaxial growth mask 48 in which the opening 49 is formed so as to fit inside is formed. As a result, the first n-type region n1 is exposed.
As the second epitaxial growth mask 48, a silicon nitride film is used as an example, but any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

Next, as shown in FIG. 14 (6), a first p-type region p1 (first region) of the first conductivity type (p-type) is formed in the opening 49 on the first n-type region n1. At this time, the first p-type region p1 is formed on the first n-type region n1 and on the first n-type region n1 surface where the first p-type region p1 is formed, around the first p-type region p1 side. The 1n-type region n1 is formed.
The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 100 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode.
The gas used for the dopant may be any gas containing p-type impurities, and an organic source containing p-type impurities can also be used.
At this time, if necessary, the epitaxially grown surface may be cleaned using a chemical solution such as hydrofluoric acid (HF) or hydrogen (H ₂ ) gas.
Further, if necessary, subsequently, as annealing for activation, for example, spike annealing is performed immediately after heating to, for example, 900 ° C., and then, for example, heating to 900 ° C. and entering the cooling process in less than 1 second. The conditions at this time may be within a range where the dopant can be activated.

Next, as shown in FIG. 14 (7), a third epitaxial growth mask 51 having an opening 52 is formed on the second p-type region p 2 on the other side of the thyristor gate electrode 22.
In order to form the third epitaxial growth mask 51, for example, a mask formation film is formed so as to cover the second epitaxial growth mask 48, the first p-type region p1, and the like. This mask formation film is formed, for example, by depositing a silicon nitride film to a thickness of 20 nm.

Thereafter, a resist mask (not shown) having an opening is formed on the second p-type region p2 on the other side of the thyristor gate electrode 22 by ordinary resist coating and lithography techniques, and this is used as an etching mask. The third epitaxial growth mask 51 having the opening 52 is used. The opening 52 is also formed in the first epitaxial growth mask 46 and the second epitaxial growth mask 48. As a result, the second p-type region p2 in the region where the second n-type region n2 is formed is exposed.
As the fifth epitaxial growth mask 51, a silicon nitride film is used as an example, but any film type other than silicon nitride, for example, an insulating film such as silicon oxide or silicon oxynitride, can be used as long as the film type can maintain selectivity during epitaxial growth. It may be.

Next, an epitaxial growth layer in which an n-type impurity (for example, phosphorus, arsenic, etc.) is doped on the semiconductor substrate 11 (second p-type region p2) of the opening 52 by a selective epitaxial growth technique using the third epitaxial growth mask 51. A second n-type region n2 (fourth region) is formed. As a doping gas in this epitaxial growth, a gas containing an n-type impurity such as phosphine (PH ₃ ), arsine (AsH ₃ ), or an organic source can be used.
Further, the dopant concentration at this time is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example. Further, the film thickness of the second n-type region n2 is preferably 50 nm to 300 nm, and may be a film thickness within a range where the second n-type region n2 can function as a cathode electrode.

  The second n-type region n2 can be performed before the first n-type region n1 and the first p-type region p1 are formed.

  Further, if necessary, activation annealing may be performed in one or both of the first p-type region p1 and the second n-type region n2. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  Next, although not shown, in order to expose the thyristor gate electrode 22, the first p-type region p1, and the second n-type region n2, the first epitaxial growth mask 46, the second epitaxial growth mask 48, and the third epitaxial growth mask on each region are exposed. 51 is removed. Then, before forming an interlayer insulating film (not shown), a metal silicide layer is formed on each exposed first p-type region p1, second n-type region n2, and sidewall gate electrode 22 by a salicide process. This metal silicide layer is formed of, for example, titanium silicide, cobalt silicide, or nickel silicide. Thereafter, an interlayer insulating film is formed, and a wiring process similar to a normal CMOS process is performed.

In the semiconductor device manufacturing method (fourth manufacturing method), the step of forming the first n-type region n1 on the second p-type region p2 on one side of the thyristor gate electrode 22 and the step of covering the first n-type region n1 After forming the second epitaxial growth mask 48, a step of forming the opening 49 in the second epitaxial growth mask 48 on the first n-type region n1 so as to be inside the first n-type region n1, and the inside of the opening 49 by selective epitaxial growth Forming the first p-type region p1 on the first n-type region n1, the first p-type region p1 and the second p-type region p2 are separated from each other by the first n-type region n1.
For this reason, a short circuit between the first p-type region p1 and the second p-type region p2 can be prevented. Furthermore, the occurrence of punch-through can be prevented.
Therefore, the first p-type region p1 (first region), the first n-type region n1 (second region), the second p-type region p2 (third region), and the second n-type region n2 (fourth region) are sequentially joined. Since the junction between the first p-type region p1 and the first n-type region n1 and the junction between the first n-type region n1 and the second p-type region p2 in the thyristor can function, normal thyristor characteristics can be obtained.

  Further, in the fourth manufacturing method, since the facet regions of the first p-type region p1 and the first n-type region n1 that are likely to cause defects do not contact each other, the first p-type region p1 and the first n-type region n1 are not in contact. Junction leakage current can be reduced, and as a result, variation in thyristor electrical characteristics and increase in off current can be suppressed.

  Next, an example in which a selection transistor is mounted on the semiconductor device will be described with reference to a schematic sectional view of FIG. FIG. 15 shows an example in which a selection transistor is mounted on the first semiconductor device as an example.

  As shown in FIG. 15, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 13 for isolating the element formation region 12 for forming the thyristor T1 and the element formation region 14 for forming the selection transistor Tr are formed in the semiconductor substrate 11. The element isolation region 13 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12.

  A first conductivity type (p-type) first p-type region p1 (first region) and a second conductivity type (n-type) opposite to the first conductivity type are formed in the element formation region 12 and the upper portion thereof. The first n-type region n1 (second region), the first conductivity type (p-type) second p-type region p2 (third region), and the second conductivity-type (n-type) second n-type region n2 (fourth) The semiconductor device 1 is formed of the thyristor T1 that is joined in order to the region. The details are as described with reference to FIG.

  On the other hand, a p-type well region 60 is formed in the element formation region 14. This p-type well region 60 can be formed in the same manner as a p-type well region formed by a known MOS process.

On the element formation region 14, a gate insulating film 61 similar to that on the element formation region 12 in which the thyristor T1 is formed is formed. The gate insulating film 61 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A gate electrode 62 is formed on the gate insulating film 61. The gate electrode 62 is usually made of polycrystalline silicon, like the thyristor gate electrode 22. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Side walls 63 and 64 are formed on the side wall of the gate electrode 62. The side walls 63 and 64 can be formed simultaneously with the side walls 23 and 24 formed on the side wall of the thyristor gate electrode 22. The sidewalls 23 and 24 and the sidewalls 63 and 64 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof. .

Source / drain regions 73 and 74 are formed in the element formation region 14 on both sides of the gate electrode 62.
Before forming the side walls 63 and 64, extension regions (or LDD regions) 71 and 72 are preferably formed in the element formation region 14 on both sides of the gate electrode 62.

  A silicide layer (not shown) is formed on the surface of the thyristor gate electrode 22, the first p-type region p1, the second n-type region n2, the source / drain regions 73, 74, etc. by a salicide process, for example, titanium silicide, cobalt silicide. Alternatively, it may be formed of nickel silicide.

  The anode sensor A is connected to the first p-type region p1, the cathode side is connected to the second n-type region n2, and is connected to one source / drain region 74 of the selection transistor Tr. A bit line B is connected to the other source / drain region 73 of the selection transistor Tr.

By arranging such memory elements including the thyristor T1 and the selection transistor Tr, a main part of the memory part of the thyristor RAM is configured.
The above example is merely an example, and the semiconductor device 2, 3, 4 or the like may be employed as the thyristor T1.

1 is a schematic cross-sectional view showing an embodiment (first example) according to a semiconductor device (first semiconductor device) of the present invention. 1 is a schematic cross-sectional view showing an embodiment (second embodiment) according to a semiconductor device (first semiconductor device) of the present invention. It is a schematic structure sectional view showing one embodiment (example) concerning a semiconductor device (second semiconductor device) of the present invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (1st manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (1st manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (1st manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (2nd manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (2nd manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (2nd manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (3rd manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (3rd manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (4th manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (4th manufacturing method) of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method (4th manufacturing method) of the semiconductor device of this invention. 1 is a schematic cross-sectional view illustrating an example in which a selection transistor is mounted on a semiconductor device of the present invention. It is general | schematic structure sectional drawing explaining a prior art and its problem. It is schematic structure sectional drawing explaining a prior art. It is schematic structure sectional drawing explaining a prior art. It is a schematic structure sectional view explaining a problem of conventional technology.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Semiconductor substrate, 13 ... Element isolation region, p1 ... 1st p-type area | region (1st area | region), n1 ... 1st n-type area | region (2nd area | region), p2 ... 1st p-type area | region (3rd area | region) ), N2 ... second n-type region (fourth region), T1 ... thyristor

Claims (9)

A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A semiconductor device in which a thyristor bonded in order is formed,
The third region is formed on a semiconductor substrate separated by an element isolation region,
The second region is formed on a part of the third region, and is formed so that one end portion of an interface between the second region and the third region is joined to a side wall portion of the element isolation region. A semiconductor device characterized by that. A gate electrode formed on the third region via a gate insulating film;
Having a sidewall formed on the sidewall of the gate electrode;
The second region is formed on the third region on one side of the gate electrode, and one end of the interface between the second region and the third region is bonded to the side wall of the element isolation region. 2. The semiconductor device according to claim 1, wherein an end portion of the second region that is not bonded to the element isolation region is bonded to a side wall portion of one side wall of the gate electrode. The second region is formed in a lower layer of the epitaxial growth layer epitaxially grown on a part of the third region and a part of the third region below the epitaxial growth layer at a position deeper than the surface of the element isolation region. One end is formed to be joined to the side wall of the separation region,
The first region is formed in a part of the epitaxial growth layer and the third region on the second region, and is formed so that one end is joined to at least a side wall portion of the element isolation region. The semiconductor device according to claim 1. The second region has an epitaxial growth layer epitaxially grown on a part of the third region and a part of the third region below the epitaxial growth layer so that one end is joined to a side wall portion of the element isolation region. Formed,
The first region is formed by the epitaxial growth layer epitaxially grown on the second region, and is formed so that at least one end is bonded to the surface of the element isolation region. Semiconductor device. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A semiconductor device in which a thyristor bonded in order is formed,
The third region is formed on a semiconductor substrate separated by an element isolation region,
The second region is formed on a part of the third region,
The first region is formed on the second region, and is formed such that the second region exists around the side of the first region on the second region surface where the first region is formed. A semiconductor device characterized by comprising: A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A method of manufacturing a semiconductor device in which thyristors bonded in order are formed,
Forming an element isolation region in a semiconductor substrate;
Forming the third region in the semiconductor substrate separated by the element isolation region;
Forming a gate electrode on the third region through a gate insulating film;
Forming a sidewall on the sidewall of the gate electrode;
Forming a non-doped epitaxial growth layer on the third region on one side of the gate electrode;
Impurities of the second conductivity type are added to the epitaxial growth layer and the third region below the epitaxial growth layer at a predetermined distance from the surface of the epitaxial growth layer and so that one end is joined to the side wall portion of the element isolation region. Forming a second region by ion implantation;
An impurity of a first conductivity type is ion-implanted into the epitaxial growth layer and the third region below the first region so that one end is joined to a side wall portion of the element isolation region, and the first region is formed above the second region. Forming, and
And a step of forming the fourth region so as to be joined to the third region on the other side of the gate electrode. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A method of manufacturing a semiconductor device in which thyristors bonded in order are formed,
Forming an element isolation region in a semiconductor substrate;
Forming the third region in the semiconductor substrate separated by the element isolation region;
Forming a gate electrode on the third region through a gate insulating film;
Forming a sidewall on the sidewall of the gate electrode;
Forming a non-doped epitaxial growth layer on the third region on one side of the gate electrode;
Impurities of the second conductivity type are ion-implanted into the non-doped epitaxial growth layer and the third region below the non-doped epitaxial growth layer so that one end is joined to the side wall portion of the element isolation region. Forming, and
Forming the first region on the second region by selective epitaxial growth;
And a step of forming the fourth region so as to be joined to the third region on the other side of the gate electrode. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A method of manufacturing a semiconductor device in which thyristors bonded in order are formed,
Forming an element isolation region in a semiconductor substrate;
Forming the third region in the semiconductor substrate separated by the element isolation region;
Forming a gate electrode on the third region through a gate insulating film;
Forming a sidewall on the sidewall of the gate electrode;
Forming an epitaxial growth layer doped with a second conductivity type impurity on the third region on one side of the gate electrode so as to cover a boundary between the element isolation region and the third region;
Forming a first region by ion-implanting a first conductivity type impurity on the surface side of the epitaxial growth layer;
Forming the fourth region so as to be joined to the third region on the other side of the gate electrode,
In the ion implantation, the second region exists between the first region and the third region, and the second region covering the boundary between the third region and the element isolation region is maintained. A method for manufacturing a semiconductor device, comprising: A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A method of manufacturing a semiconductor device in which thyristors bonded in order are formed,
Forming an element isolation region in a semiconductor substrate;
Forming the third region in the semiconductor substrate separated by the element isolation region;
Forming a gate electrode on the third region through a gate insulating film;
Forming a sidewall on the sidewall of the gate electrode;
Forming the second region on the third region on one side of the gate electrode;
After forming an insulating film covering the second region, forming an opening in the insulating film on the second region so as to fit inside the second region;
Forming the first region on the second region of the opening by selective epitaxial growth;
And a step of forming the fourth region so as to be joined to the third region on the other side of the gate electrode.

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