JP2009094381A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the influence of a facet generated at epitaxial growth by enlarging an effective epitaxial growth area. <P>SOLUTION: A semiconductor device 1 is so formed that a first thyristor T1 and a second thyristor T2 formed by bonding a first p-type region p1, a first n-type region n1, a second p-type region p2 and a second n-type region n2 in sequence are isolated by an element isolation region 14. The first n-type regions n1 of the first and second thyristors T1 and T2 are provided while sandwiching the element isolation region 14. Each of the first p-type regions p1 of the first and second thyristors T1 and T2 formed on each of the first n-type regions n1 by selective epitaxial growth is formed in a state where they are continued on the element isolation region 14 between the first n-type regions n1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a thyristor as a memory element and a method for manufacturing the same.

  There has been proposed a memory (in particular, for SRAM) in which a thyristor is used and the turn-on and turn-off characteristics of the thyristor are controlled by a gate electrode realized on the thyristor and connected in series with an access transistor (hereinafter referred to as T-RAM). In this case, the memory operation is performed by setting the off region of the thyristor to “0” and the on region to “1”.

  A thyristor is basically a p-type region p1, an n-type region n1, a p-type region p2, and an n-type region n2, which are sequentially joined. For example, n-type silicon and p-type silicon are formed in four layers. It is. Hereinafter, this basic structure is referred to as p1 / n1 / p2 / n2. Two types of structures have been proposed by T-RAM. One is a p1 / n1 / p2 / n2 structure formed vertically on a silicon substrate. The other is an SOI substrate in which a p1 / n1 / p2 / n2 structure is horizontally formed on a silicon layer. In any configuration, high-speed operation is enabled by providing a gate electrode having a MOS structure on p1 / n2 / p2 / n2 (for example, see Non-Patent Documents 1-3 and Patent Document 1).

  Further, a manufacturing method using a selective epitaxial growth technique has been proposed by the applicant of the present invention and T-RAM (see, for example, Patent Document 2).

  After forming the p1 / n1 / p2 / n2 structure, which is the main functional part of the thyristor, T-RAM uses the selective epi technology and the elevated source / drain applied in CMOS manufacturing technology (Elevated Source / Drain) The same selective epitaxial manufacturing technique is used. On the other hand, the applicant of the present invention is to form one or a plurality (for example, p1, n2) of the p1 / n1 / p2 / n2 structure, which is the main functional part of the thyristor, by a selective epitaxial growth technique.

  As the device scales (especially after the 90 nm node generation), the active region for selective epitaxial growth becomes smaller. Further, for example, as shown in FIGS. 34 and 35, either the p1 / n1 / p2 / n2 structure which is the main functional part of the thyristor, for example, the p1 region shown in FIG. 34 or the n2 region shown in FIG. 35 is selectively epitaxially grown. Since the facet is generated (the side of the epitaxial growth layer is formed with an inclined surface), the shape of the selective epitaxial growth film grows into a quadrangular pyramid or a trapezoid. For these reasons, the film formed by selective epi deposition has a sharp tip (shown shape) or a very flat upper area. As a result, the effective thickness of the epi film at the edge of the active region is reduced. When the silicide process is performed on this epitaxial growth layer, in the worst case, the silicide layer penetrates the epitaxial growth layer and reaches the silicon substrate. The problem of short circuiting. Further, there arises a problem such as a contact failure in the subsequent upper layer wiring process and a characteristic variation due to a variation in distance between the wiring contact of the selective epi layer and the silicon substrate.

US Pat. No. 6,462,359 (B1) US Pat. No. 6,888,176 (B1) Farid Nemati and James D. Plummer "A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device" 1998 IEEE, VLSI Technology Tech.Dig. P.66 1998 Farid Nemati and James D. Plummer `` A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories '' 1999 IEEE IEDM Tech., P.283 1999 Farid Nemati, Hyun-Jin Cho, Scott Robins, Rajesh Gupta, Marc Tarabbia, Kevin J. Yang, Dennis Hayes, Vasudevan Gopalakrishnan, `` Fully Planar 0.562μm2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High- Performance SRAMs '' 2004 IEEE IEDM Tech., P.273 2004

  The problem to be solved is that when a thyristor component is formed by selective epitaxial growth technology, facets are generated and the shape of the epitaxial growth layer grows to a quadrangular pyramid or trapezoid. In this case, it is difficult to prevent the silicide layer formed by the silicide reaction from penetrating the epitaxial growth layer. In addition, there is a possibility of causing a problem such as a contact failure in the subsequent upper layer wiring process and a characteristic variation due to a variation in the distance between the wiring contact of the selective epi layer and the silicon substrate.

  The present invention expands the effective epitaxial growth area and suppresses the influence of facets generated during epitaxial growth.

  A first semiconductor device of the present invention includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, A semiconductor device in which a first thyristor and a second thyristor, which are sequentially joined to a second region of a second conductivity type, are separated in an element isolation region, wherein the second region of the first thyristor and the second region are A second region of the second thyristor is provided across the element isolation region, and the first region of the first thyristor formed by selective epitaxial growth on the second region of the first thyristor, and the second region of the second thyristor. The first region of the second thyristor formed by selective epitaxial growth on two regions is continuous on the element isolation region between the second region of the first thyristor and the second region of the second thyristor. Formed into a state And wherein the Rukoto.

  In the first semiconductor device of the present invention, the epitaxial growth is performed from the second region of the first thyristor and the second region of the second thyristor separated through the element isolation region by utilizing the selective epitaxial growth in the lateral direction. By doing so, the area of the region where selective epitaxial growth starts effectively can be expanded, so that the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer has a trapezoidal shape and one plane portion on the upper surface. It is formed wider than the case where selective epitaxial growth is performed from the second region.

The second semiconductor device of the present invention includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, A semiconductor device in which a first thyristor and a second thyristor, which are sequentially joined to a second region of a second conductivity type, are separated in an element isolation region, wherein the second region of the first thyristor and the second region are A second region of the second thyristor is provided across the element isolation region, and a plurality of the first thyristors are arranged via the element isolation region in a direction orthogonal to the arrangement direction of the first thyristor and the second thyristor. And
A plurality of the second thyristors are arranged through an element isolation region in a direction orthogonal to the arrangement direction of the first thyristor and the second thyristor, and a gate insulating film is provided in a third region of each first thyristor. The first gate electrode formed through the first thyristor is formed by a common first gate wiring disposed in the direction in which each first thyristor is disposed, and a third region of each second thyristor is interposed through a gate insulating film. The formed second gate electrode is formed by a common second gate wiring arranged in the arrangement direction of each of the second thyristors, and the first region of each of the first thyristors is the second of the first thyristor. The first region of each of the second thyristors is formed on the second region of each of the second thyristors and between them. On separation area And characterized in that it is continuously formed along the second gate line.

  In the second semiconductor device of the present invention, the second regions of the first thyristors and the second regions of the second thyristors separated through the element isolation region are utilized by utilizing the selective epitaxial growth in the lateral direction. Since the area of the region where selective epitaxial growth starts effectively can be expanded, the influence of facets generated during epitaxial growth is reduced, the selective epitaxial growth layer has a trapezoidal shape, and the planar portion of the upper surface is It is formed wider than the case where selective epitaxial growth is performed from one second region.

  A third semiconductor device of the present invention includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, A semiconductor device in which a thyristor and a MIS transistor, which are sequentially joined to a second region of a two-conductivity type, are separated in an element isolation region, wherein one of the second region and the MIS transistor is provided. A source / drain region is provided across the element isolation region, the first region formed by selective epitaxial growth on the second region, and a stacked source formed by selective epitaxial growth on the one source / drain region The drain region is formed in a continuous state on the element isolation region between the second region and the one source / drain region.

  In the third semiconductor device of the present invention, by utilizing the selective epitaxial growth in the lateral direction, the second region of the thyristor separated via the element isolation region and one source / drain region of the MIS transistor are used. Epitaxial growth effectively increases the area of the region where selective epitaxial growth begins, so that the effect of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer has a trapezoidal shape with a flat top portion. It is formed wider than the case where selective epitaxial growth is performed from the two second regions.

  According to a first method of manufacturing a semiconductor device of the present invention, a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and a first conductivity type on a semiconductor substrate. A first thyristor and a second thyristor in which the third region of the second conductive type and the fourth region of the second conductivity type are sequentially joined, and are separated in the element isolation region. The second region of the first thyristor and the second region of the second thyristor are formed on the semiconductor substrate with the element isolation region interposed therebetween, and then epitaxially grown from the second region of the first thyristor by selective epitaxial growth. At the same time as forming the first region of the first thyristor, the first region of the second thyristor is formed by epitaxial growth from the second region of the second thyristor, and the first thyristor is formed on the element isolation region. And forming a first region of the data between the first region of the second thyristor in a state of being bonded.

  In the first manufacturing method of the semiconductor device of the present invention, the second region of the first thyristor and the second region of the second thyristor separated through the element isolation region by utilizing the selective epitaxial growth in the lateral direction. Therefore, the area of the region where selective epitaxial growth begins can be effectively expanded, so that the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer has a trapezoidal shape and a planar portion on the upper surface. Is formed wider than that obtained by selective epitaxial growth from one second region.

  According to a second method of manufacturing a semiconductor device of the present invention, a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type third region are provided. The second thyristor and the second thyristor, which are sequentially joined to the fourth region of the second conductivity type, are separated in the element isolation region, and the second region of the first thyristor and the second thyristor are formed. A plurality of the first thyristors are arranged via the element isolation regions in a direction perpendicular to the arrangement direction of the first thyristors and the second thyristors, A plurality of second thyristors are arranged via element isolation regions in a direction perpendicular to the direction in which the first thyristor and the second thyristor are arranged, and a gate insulating film is interposed in the third region of each first thyristor. The first gate electrode formed A second gate electrode formed by a common first gate wiring arranged in the arrangement direction of each first thyristor and formed in a third region of each second thyristor via a gate insulating film is provided in each of the first thyristors. A method of manufacturing a semiconductor device formed of a common second gate wiring arranged in a direction in which two thyristors are arranged, wherein the first region of each first thyristor is defined as the second region of each first thyristor. Forming the first region of each of the second thyristors on and between the second regions of each of the second thyristors; It is characterized by being formed continuously on the isolation region and along the second gate wiring.

  In the second manufacturing method of the semiconductor device of the present invention, the second regions of the first thyristors and the second thyristors of the second thyristors separated by the element isolation region are utilized by utilizing the selective epitaxial growth in the lateral direction. By epitaxially growing the two regions, the area of the region where selective epitaxial growth starts effectively can be expanded, so that the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer is trapezoidal and has a top surface. The planar portion is formed wider than the case where selective epitaxial growth is performed from one second region.

  According to a third method of manufacturing a semiconductor device of the present invention, a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, and a first conductivity type third region are provided. And a MIS type transistor in which the second conductivity type fourth region is sequentially joined and the MIS transistor are separated in the element isolation region, wherein the element is formed on the semiconductor substrate. After forming the second region and the source / drain region of the MIS transistor across the isolation region, the first region is formed by epitaxial growth from the second region by selective epitaxial growth. The stacked source / drain regions are formed by epitaxial growth from the source / drain regions formed with the element isolation region interposed therebetween, and the first region is formed on the element isolation region. And forming the stacked state of being bonded to the source and drain regions.

  In the third manufacturing method of the semiconductor device of the present invention, by utilizing the selective epitaxial growth in the lateral direction, the second region isolated via the element isolation region and one source / drain region of the MIS transistor are provided. Since the area of the region where selective epitaxial growth begins can be effectively expanded, the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer has a trapezoidal shape and the plane portion on the upper surface is reduced. When the selective epitaxial growth is performed from one second region, it is formed wider.

  Since the first semiconductor device and the second semiconductor device of the present invention can effectively expand the area of the region where selective epitaxial growth begins, the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer is The shape of the upper surface and the planar portion of the upper surface are wider than those obtained by selective epitaxial growth from one second region. As a result, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

  According to the first and second manufacturing methods of the semiconductor device of the present invention, the area of a region where selective epitaxial growth can be effectively started can be increased, so that the influence of facets generated during epitaxial growth is reduced, and selective epitaxial growth is performed. The layer can be formed in a trapezoidal shape, and the planar portion of the upper surface can be formed wider than the case where selective epitaxial growth is performed from one second region. As a result, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

  An embodiment (first example) according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 1, an element isolation region 14 for separating an element formation region 12 for forming a first thyristor T1 and an element formation region 13 for forming a second thyristor T2 are formed in a semiconductor substrate 11. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation regions 12 and 13 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 (third region) is formed by doping boron (B), and its concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^19. About cm ⁻³ is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate is formed on the gate insulating film 21 formed in the element forming region 13. An electrode 22B can be formed. The first and second gate electrodes 22A and 22B are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed as a hard mask on the first and second gate electrodes 22A and 22B.

Side walls 24 and 25 are formed on the side walls of the first and second gate electrodes 22A and 22B. The sidewalls 24 and 25 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

A first n-type region n1 (second region) into which an n-type dopant is introduced is formed in the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B. The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

A second n-type region n2 (fourth region) formed by introducing an n-type dopant is formed in the semiconductor substrate 11 on the other side of the first and second gate electrodes 22A and 22B. In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2 and it is important to operate as a cathode electrode. It is. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

A first conductivity type (p-type) first p-type region p1 (first region) is formed on each first n-type region n1 and on the element isolation region 14 therebetween. The first p-type region p1 is formed by selective epitaxial growth, for example, and the boron (B) concentration in the film is 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode.

  Accordingly, the semiconductor device 1 includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a first n of the second conductivity type (for example, n-type) opposite to the first conductivity type. Type region n1 (second region), first conductivity type (p-type) second p-type region p2 (third region), second conductivity type (n-type) second n-type region n2 (fourth region) in this order. The first thyristor T1 and the second thyristor T2 are joined, and the first n-type regions n1 of the first and second thyristors T1 and T2 are formed to face each other with the element isolation region 14 interposed therebetween. Each first p-type region p1 is formed so as to be joined on the element isolation region 14 by selective epitaxial growth from the element formation regions 12 and 13 (each first n-type region n1).

  In the semiconductor device 1, the first n-type region n1 of the first thyristor T1 and the first n-type region of the second thyristor T2 that are separated via the element isolation region 14 by utilizing the selective epitaxial growth in the lateral direction. By epitaxially growing the first p-type region p1 from n1, it is possible to increase the area of the region where the selective epitaxial growth starts effectively, so that the influence of facets generated during epitaxial growth is reduced, and the selective epitaxial growth layer is The shape of the upper surface and the planar portion of the upper surface are wider than those obtained by selective epitaxial growth from one first n-type region n1. Further, the sidewall of the first p-type region p1 which is an epitaxial growth layer is suppressed by the sidewalls 24 and 25, and from the first n-type region n1 of the first thyristor T1 and the first n-type region n1 of the second thyristor T2. Even when the first p-type regions p1 grown epitaxially are joined to each other on the element isolation region 14, the upper surface of the first p-type region p1 is easily formed in a planar shape. Therefore, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

  Next, an embodiment (first example) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS. 2 to 6 show, as an example, a manufacturing method in which two thyristors are formed across an element isolation region. This manufacturing method can be applied to a method for manufacturing a thyristor RAM, for example.

As shown in FIG. 2, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. Then, an element isolation region 14 for separating the element formation regions 12 and 13 is formed in the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Thereafter, upper portions of the element formation regions 12 and 13 of the semiconductor substrate 11 are formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of the ion implantation conditions, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

Next, as shown in FIG. 3, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, a first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate electrode 22B is formed on the gate insulating film 21 formed in the element forming region 13. . The first and second gate electrodes 22A and 22B are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

For each of the first and second gate electrodes 22A and 22B, for example, after forming a gate electrode forming film on the gate insulating film 21, a normal resist coating, an etching mask is formed by a lithography technique, and the etching mask is used. The gate electrode forming film is formed by etching using the conventional etching technique. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, as shown in FIG. 4, sidewalls 24 and 25 are formed on the sidewalls of the first and second gate electrodes 22A and 22B. For example, after forming a sidewall formation film so as to cover the first and second gate electrodes 22A and 22B, the sidewall formation film is etched back, whereby each of the first and second gate electrodes 22A and 22B. The side walls 24 and 25 can be formed on the side walls. The sidewalls 24 and 25 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

Next, an ion implantation mask (not shown) having openings on the element formation regions 12 and 13 between the first and second gate electrodes 22A and 22B is formed by ordinary resist coating and lithography techniques. Next, an n-type dopant is introduced into the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B by an ion implantation technique using the ion implantation mask, and the element formation regions 12 and 13 are introduced. A first n-type region n1 (second region) is formed. The ion implantation conditions are set so that, for example, phosphorus (P) is used as a dopant, and the concentration is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used. Thereafter, the ion implantation mask is removed.

  Subsequently, as annealing for activation, for example, heating is performed to reach 1050 ° C., and then spike annealing that immediately enters a cooling step is performed. The conditions at this time may be within a range where the dopant can be activated.

  The sidewalls 24 and 25 may be formed after ion implantation for forming the first n-type region n1.

Next, an ion implantation mask (not shown) having an opening on the other side of each of the first and second gate electrodes 22A and 22B, that is, the region where the second n-type region is formed, is formed by ordinary resist coating and lithography techniques. Form. Next, an n-type dopant is introduced into the semiconductor substrate 11 on the other side of each of the first and second gate electrodes 22A and 22B by an ion implantation technique using this ion implantation mask, and the second n-type region n2 (first 4 regions). The ion implantation conditions are set so that, for example, phosphorus (P) is used as a dopant, and the concentration is, for example, 5 × 10 ²⁰ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2 and it is important to operate as a cathode electrode. It is. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used. Thereafter, the ion implantation mask is removed.

  Subsequently, as annealing for activation, for example, heating is performed to reach 1050 ° C., and then spike annealing that immediately enters a cooling step is performed. The conditions at this time may be within a range where the dopant can be activated.

  Further, the order of forming the first n-type region n1 and the second n-type region n2 may be different from the procedure described above. The second n-type region n2 may be formed first, and the first n-type region n1 may be formed later. The annealing may be performed once after both the first n-type region n1 and the second n-type region n2 are formed, or may be a step of source / drain activation annealing of the selection transistor.

  Next, as shown in FIG. 5, an insulating film 41 that covers the first and second gate electrodes 22A and 22B, the sidewalls 24 and 25, and the like is formed. The insulating film 41 serves as a mask for selective epitaxial growth performed in a later process, and is formed of, for example, a silicon nitride film and has a thickness of, for example, 20 nm. Next, an etching mask (not shown) that opens on the element formation regions 12 and 13 between the first and second gate electrodes 22A and 22B and the element isolation region 14 therebetween is formed by ordinary resist coating and lithography techniques. To do. Thereafter, an opening 42 is formed in the insulating film 41 on each first n-type region n1 and on the element isolation region 14 therebetween by etching using this etching mask. By this etching process, the surface of the semiconductor substrate 11 (first n-type region n1) can be exposed only in the selective epitaxial growth portion. Here, as an example, a silicon nitride film is used as the insulating film 41, but this is for obtaining selectivity during epitaxial growth. Therefore, other types of insulating films can be used as long as the selectivity can be maintained. Thereafter, the etching mask is removed. Further, this step may be performed simultaneously with the formation of the sidewalls 24 and 25. The film thickness is set to be thinner than the epitaxial film of the first p-type region p1 to be grown next.

  In the step of exposing the surface of the semiconductor substrate 11 (first n-type region n1), the shape of the opening 42 will be described in detail later.

Next, as shown in FIG. 6, a first conductivity type (p-type) first p-type region p1 (first region) is formed in the opening 42 on each first n-type region n1. The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 200 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. Here, the first p-type region p1 starts to grow epitaxially from each first n-type region n1, joins on the element isolation region 14, and is further grown. At this time, if necessary, the surface of the semiconductor substrate 11 may be cleaned using a chemical solution such as HF, hydrogen (H ₂ ) gas, or the like.

  In the first embodiment, the second n-type region n2 is formed by the ion implantation method, but may be performed by a selective epitaxial method. In that case, following the above, a silicon nitride film is again deposited, for example, by 20 nm, and then a region to be the second n-type region n2 is patterned and opened with a resist, and then the silicon nitride film is etched.

  In this example, a silicon nitride film is used as an example. However, since this is for selectivity during epitaxial growth, other film types and film thicknesses may be used as long as the selectivity can be maintained.

Next, the second n-type region n2 is formed by selective epitaxial growth. The conditions at this time are, for example, using an arsine (AsH ₃ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to, for example, 200 nm by adjusting the pressure and the like. The dopant (arsenic) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example, and is set to 1 × 10 ²⁰ cm ⁻³ as an example. The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the second n-type region n2 can function as a cathode electrode. Of course, any gas may be used as long as it is doped with n-type impurities, such as phosphine (PH ₃ ) or an organic source.

Moreover, in the said Example, although produced in order of the 1st p-type area | region p1 and the 2nd n-type area | region n2, you may form in order of the 2nd n-type area | region n2 and the 1st p-type area | region p1. At this time, if necessary, the surface of the silicon (Si) substrate may be cleaned using a chemical solution such as hydrofluoric acid (HF), hydrogen (H ₂ ) gas, or the like. Further, if necessary, after the first p-type region p1 or the second n-type region n2 is formed, activation annealing may be performed on either or both. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  Next, although not shown, in order to expose the first and second gate electrodes 22A and 22B, the first p-type region p1 and the second n-type region n2, the insulating film 41 on each region (see FIG. 6). ) Is removed. Then, before forming an interlayer insulating film (not shown), a silicide layer is formed on each exposed first p-type region p1, second n-type region n2, first and second gate electrodes 22A and 22B by a salicide process. Are formed of, for example, titanium silicide, cobalt silicide, or nickel silicide. Thereafter, an interlayer insulating film is formed, and a wiring process similar to a normal CMOS process is performed.

  The semiconductor device 1 of the present invention formed by the above manufacturing method includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a second conductivity type opposite to the first conductivity type. (For example, n-type) first n-type region n1 (second region), first conductivity-type (p-type) second p-type region p2 (third region), second conductivity-type (n-type) second n-type region The first thyristor T1 and the second thyristor T2 are formed by sequentially joining n2 (fourth region), and the first n-type regions n1 of the first and second thyristors T1 and T2 are opposed to each other with the element isolation region 14 interposed therebetween. The element isolation regions are formed by selective epitaxial growth from the element formation regions 12 and 13 (each first n-type region n1) in the opening 42 in which each first p-type region p1 is formed in the insulating film 41. 14 is formed so as to be bonded on top of each other.

  In the method for manufacturing the semiconductor device 1, the first epitaxial region n1 of the first thyristor T1 and the second thyristor T2 of the first thyristor T2 separated through the element isolation region 14 are utilized by utilizing the selective epitaxial growth in the lateral direction. By epitaxially growing the first p-type region p1 from the 1n-type region n1, it is possible to increase the area of the region where effective selective epitaxial growth starts, so that the influence of facets generated during epitaxial growth is reduced, and selective epitaxial growth is achieved. The layer is formed in a trapezoidal shape, and the plane portion of the upper surface is formed wider than the case where selective epitaxial growth is performed from one first n-type region n1. Further, the sidewalls of the first p-type region p1 which is an epitaxial growth layer are suppressed by the sidewalls 24 and 25, and from the first n-type region n1 of the first thyristor T1 and the first n-type region n1 of the second thyristor T2. Even when the first p-type regions p1 grown epitaxially are joined to each other on the element isolation region 14, the upper surface of the first p-type region p1 is easily formed in a planar shape. Therefore, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

  Next, an example of the shape of the first p-type region p1 (first region) serving as the opening 42 and the anode electrode in the step of exposing the surface of the semiconductor substrate 11 (first n-type region n1) will be described.

  As shown in FIG. 7, the first thyristor T1 and the second thyristor T2 are divided into a first n-type region n1 (second region) of the first thyristor T1 and a first n-type region of the second thyristor T2 across the element isolation region 14. The first gate electrode 22A is formed on the second p-type region p2 (third region) of the first thyristor T1 via a gate insulating film (not shown), so as to be opposed to n1, and the second thyristor A second gate electrode 22B is formed on the second p-type region p2 of T2 via a gate insulating film (not shown). A plurality of such first thyristors T1 and second thyristors T2 are arranged in the arrangement direction of the first gate electrode 22A and the second gate electrode 22B, and each first thyristor T1 has one first gate electrode 22A. One thyristor word line TW1 is formed, and the second gate electrode 22B of each second thyristor T2 is formed by one second thyristor word line TW2.

  An opening 42 of the insulating film 41 is formed between the first thyristor word line TW1 and the second thyristor word line TW2 including the first n-type region n1 and the element isolation region 14 therebetween. Then, the first p-type region p1 (first region) is selectively epitaxially grown from above each first n-type region n1 in the opening 42 and between the first thyristor word line TW1 and the second thyristor word line TW2. ) Is formed.

  An example of wiring in the semiconductor device 1 (1A) having the above configuration will be described with reference to a plan layout diagram of FIG. 8 and a circuit diagram of FIG.

  As shown in FIGS. 8 and 9, for example, the semiconductor device 1 (1A) includes a second selection transistor Tr2, a first selection transistor Tr1, a first thyristor T1, and a second thyristor in one direction (for example, the X direction). They are repeatedly arranged in the order of T2. In the repetitive arrangement direction, an element isolation region 14 is formed between the selection transistor and the thyristor and between the thyristors. On the other hand, the second selection transistor Tr2, the first selection transistor Tr1, the first thyristor T1, and the second thyristor T2 are repeated through the element isolation region 14 in a direction orthogonal to the one direction (for example, the Y direction). Has been placed. The first thyristor word line TW1 of each first thyristor T1 and the second thyristor word line TW2 of each second thyristor T2 are arranged in the Y direction, and the first word line W1 of each first select transistor Tr1 and each The second word line W2 of the second selection transistor Tr2 is arranged in the Y direction.

  The first p-type region p1 (first region) selectively epitaxially grown on each first n-type region n1 (second region) between the first thyristor word line TW1 and the second thyristor word line TW2 is an anode. An anode line A is connected to the first thyristor word line TW1 and the second thyristor word line TW2 in parallel with each other via an anode contact 64. Further, the source / drain 51 on the thyristor side of each first selection transistor Tr1 (and the second selection transistor Tr2) and the second n-type region n2 (fourth region) of the thyristor are respectively wired via bridge contacts 61 and 62 ( (Not shown). Further, on the uppermost layer, a bit line B connected to a source / drain region 52 between the second selection transistor Tr2 and the first selection transistor Tr1 via a bit contact 63 is connected to the first and second word lines. It is arranged in a direction orthogonal to W1 and W2.

  In the above configuration, one memory element is configured by one selection transistor and one thyristor. For example, the memory element M1 (or M2) is configured by the first thyristor T1 and the first selection transistor Tr1 (or the second thyristor T2 and the second selection transistor Tr2) surrounded by a two-dot chain line.

  Next, an example of the shape of the opening 42 will be described in the step of exposing the surface of the semiconductor substrate 11 (first n-type region n1).

  As shown in FIG. 10, a first n-type region n1 (second region) of the first thyristor T1 and a first n-type region of the second thyristor T2 with the element isolation region 14 sandwiched between the first thyristor T1 and the second thyristor T2. The first gate electrode 22A is formed on the second p-type region p2 (third region) of the first thyristor T1 via a gate insulating film (not shown), so as to be opposed to n1, and the second thyristor A second gate electrode 22B is formed on the second p-type region p2 of T1 via a gate insulating film (not shown). A plurality of such first thyristors T1 and second thyristors T2 are arranged in the arrangement direction of the first gate electrode 22A and the second gate electrode 22B, and each first thyristor T1 has one first gate electrode 22A. One thyristor word line TW1 is formed, and the second gate electrode 22B of each second thyristor T2 is formed by one second thyristor word line TW2.

  The opening of the insulating film 41 is formed on the first n-type region n1 of the first thyristor T1 and on the first n-type region n1 of the second thyristor T1 adjacent to the first thyristor T1 via the element isolation region 14 and on the element isolation region 14. A portion 42 is formed. Therefore, the opening 42 is formed on each first n-type region n1 in a direction orthogonal to the first thyristor word line TW1 and the second thyristor word line TW2. Then, the first thyristor T1 and the second thyristor T2 are selectively epitaxially grown on each first n-type region n1 in the opening 42 and between the first thyristor word line TW1 and the second thyristor word line TW2. The first p-type region p1 (first region) used in common is formed. In this configuration, an anode contact 64 is provided in the first p-type region p1 above each first n-type region n1.

  Next, an example of wiring in the semiconductor device 1 (1B) having the above configuration will be described with reference to a plan layout diagram of FIG. 11 and a circuit diagram of FIG.

  As shown in FIGS. 11 and 12, as an example, the semiconductor device 1 (1B) includes a second selection transistor Tr2, a first selection transistor Tr1, a first thyristor T1, and a second thyristor in one direction (for example, the X direction). They are repeatedly arranged in the order of T2. In the repetitive arrangement direction, an element isolation region 14 is formed between the selection transistor and the thyristor and between the thyristors. On the other hand, the second selection transistor Tr2, the first selection transistor Tr1, the first thyristor T1, and the second thyristor T2 are repeated through the element isolation region 14 in a direction orthogonal to the one direction (for example, the Y direction). Has been placed. The first thyristor word line 22A of each first thyristor T1 and the second thyristor word line 22B of each second thyristor T2 are arranged in the Y direction, and the first word line W1 of each first select transistor Tr1 and each first thyristor word line 22B. The second word line W2 of the two selection transistors Tr2 is arranged in the Y direction.

  Each first p-type region p1 (first region) selectively epitaxially grown on each first n-type region n1 (second region) between the first thyristor word line TW1 and the second thyristor word line TW2 is provided. An anode line A which becomes an anode electrode and is connected to each anode electrode via an anode contact 64 is arranged in a direction orthogonal to the first thyristor word line TW1 and the second thyristor word line TW2. Further, the source / drain 51 on the thyristor side of each first selection transistor Tr1 (and the second selection transistor Tr2) and the second n-type region n2 (fourth region) of the thyristor are respectively wired via bridge contacts 61 and 62 ( (Not shown). Further, on the uppermost layer, a bit line B connected to the source / drain region 52 between the second selection transistor Tr2 and the first selection transistor Tr1 via a bit contact 63 is connected to the first thyristor word line TW1. They are arranged in a direction parallel to the second thyristor word line TW2.

  In the above configuration, one memory element is configured by one selection transistor and one thyristor. For example, the memory element M1 is configured by the first thyristor T1 and the first selection transistor Tr1 surrounded by a two-dot chain line.

  The above-described semiconductor devices 1A and 1B have the advantages that the effects described with reference to FIG. 1 can be obtained, and the semiconductor device 1A has an advantage that the anode contact 64 can be easily taken because the first p-type region p1 can be widened. In the semiconductor device 1B, since the anode line A can be connected to the memory cell here, it is possible to control each memory cell.

  Next, an embodiment (second to fourth examples) according to the semiconductor device of the present invention will be described with reference to schematic sectional views of FIGS.

In the second embodiment, as shown in FIG. 13, an element isolation region 14 for separating an element formation region 12 for forming the first thyristor T1 and an element formation region 13 for forming the second thyristor T2 is formed in the semiconductor substrate 11. Has been. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation regions 12 and 13 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 (third region) is formed by doping boron (B), and its concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^19. About cm ⁻³ is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate is formed on the gate insulating film 21 formed in the element forming region 13. An electrode 22B can be formed. The first and second gate electrodes 22A and 22B are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed as a hard mask on the first and second gate electrodes 22A and 22B.

Side walls 24 and 25 are formed on the side walls of the first and second gate electrodes 22A and 22B. The sidewalls 24 and 25 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

A first n-type region n1 (second region) into which an n-type dopant is introduced is formed in the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B. The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

A second n-type region n2 (fourth region) formed by introducing an n-type dopant is formed in the semiconductor substrate 11 on the other side of the first and second gate electrodes 22A and 22B. In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2 and it is important to operate as a cathode electrode. It is. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

  Further, an interlayer insulating film 43 having an opening 44 formed on the first n-type region n1 (second region) and on the element isolation region 14 therebetween is formed on the semiconductor substrate 11. The upper surface of the interlayer insulating film 43 may be planarized, for example.

Within the opening 44 of the interlayer insulating film 43, a first p-type region p1 (first region) of the first conductivity type (p-type) is formed on each first n-type region n1 and on the element isolation region 14 therebetween. Is formed. The first p-type region p1 is formed by selective epitaxial growth, for example, and the boron (B) concentration in the film is 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm. However, the first p-type region p <b> 1 may be in a range that can function as an anode electrode, and is formed thinner than the film thickness of the interlayer insulating film 43.

  Accordingly, the semiconductor device 1 includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a first n of the second conductivity type (for example, n-type) opposite to the first conductivity type. Type region n1 (second region), first conductivity type (p-type) second p-type region p2 (third region), second conductivity type (n-type) second n-type region n2 (fourth region) in this order. The first thyristor T1 and the second thyristor T2 are joined, and the first n-type regions n1 of the first and second thyristors T1 and T2 are formed to face each other with the element isolation region 14 interposed therebetween. Each first p-type region p1 is formed so as to be joined on the element isolation region 14 by selective epitaxial growth from the element formation regions 12 and 13 (each first n-type region n1).

In the third embodiment, as shown in FIG. 14, an element isolation region 14 for separating an element formation region 12 for forming the first thyristor T1 and an element formation region 13 for forming the second thyristor T2 is formed in the semiconductor substrate 11. ing. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation regions 12 and 13 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 (third region) is formed by doping boron (B), and its concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^19. About cm ⁻³ is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate is formed on the gate insulating film 21 formed in the element forming region 13. An electrode 22B can be formed. The first and second gate electrodes 22A and 22B are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed as a hard mask on the first and second gate electrodes 22A and 22B.

Side walls 24 and 25 are formed on the side walls of the first and second gate electrodes 22A and 22B. The sidewalls 24 and 25 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

A first n-type region n1 (second region) into which an n-type dopant is introduced is formed in the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B. The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

A second n-type region n2 (fourth region) formed by introducing an n-type dopant is formed in the semiconductor substrate 11 on the other side of the first and second gate electrodes 22A and 22B. In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2 and it is important to operate as a cathode electrode. It is. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

  Further, an interlayer insulating film 43 having an opening 44 formed on the first n-type region n1 (second region) and on the element isolation region 14 therebetween is formed on the semiconductor substrate 11. The upper surface of the interlayer insulating film 43 may be planarized, for example.

Within the opening 44 of the interlayer insulating film 43, a first p-type region p1 (first region) of the first conductivity type (p-type) is formed on each first n-type region n1 and on the element isolation region 14 therebetween. Is formed. The first p-type region p1 is formed by selective epitaxial growth, for example, and the boron (B) concentration in the film is 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . Further, the film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. For example, the film is formed thicker than the interlayer insulating film 43.

  Accordingly, the semiconductor device 1 includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a first n of the second conductivity type (for example, n-type) opposite to the first conductivity type. Type region n1 (second region), first conductivity type (p-type) second p-type region p2 (third region), second conductivity type (n-type) second n-type region n2 (fourth region) in this order. The first thyristor T1 and the second thyristor T2 are joined, and the first n-type regions n1 of the first and second thyristors T1 and 3 are formed so as to face each other with the element isolation region 14 interposed therebetween. Each first p-type region p1 is formed so as to be joined on the element isolation region 14 by selective epitaxial growth from the element formation regions 12 and 13 (each first n-type region n1).

In the fourth embodiment, as shown in FIG. 15, an element isolation region 14 for separating an element formation region 12 for forming the first thyristor T1 and an element formation region 13 for forming the second thyristor T2 is formed in the semiconductor substrate 11. ing. For example, a silicon substrate is used as the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Further, a first conductivity type (p-type) region is formed above the element formation regions 12 and 13 of the semiconductor substrate 11. This p-type region is the second p-type region p2 (third region) of the thyristor. The second p-type region p2 (third region) is formed by doping boron (B), and its concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^19. About cm ⁻³ is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

A gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and has a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  A first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate is formed on the gate insulating film 21 formed in the element forming region 13. An electrode 22B can be formed. The first and second gate electrodes 22A and 22B are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed as a hard mask on the first and second gate electrodes 22A and 22B.

Side walls 24 and 25 are formed on the side walls of the first and second gate electrodes 22A and 22B. The sidewalls 24 and 25 may be formed of either silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

A first n-type region n1 (second region) into which an n-type dopant is introduced is formed in the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B. The concentration of the first n-type region n1 is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

A second n-type region n2 (fourth region) formed by introducing an n-type dopant is formed in the semiconductor substrate 11 on the other side of the first and second gate electrodes 22A and 22B. In the second n-type region n2, for example, phosphorus (P) is used as a dopant, and the concentration is set to 5 × 10 ²⁰ cm ⁻³ , for example. This concentration is preferably about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2 and it is important to operate as a cathode electrode. It is. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used.

  Further, an interlayer insulating film 43 having an opening 44 formed on the first n-type region n1 (second region) and on the element isolation region 14 therebetween is formed on the semiconductor substrate 11. The upper surface of the interlayer insulating film 43 may be planarized, for example.

Within the opening 44 of the interlayer insulating film 43, a first p-type region p1 (first region) of the first conductivity type (p-type) is formed on each first n-type region n1 and on the element isolation region 14 therebetween. Is formed. The first p-type region p1 is formed by selective epitaxial growth, for example, and the boron (B) concentration in the film is 1 × 10 ²⁰ cm ⁻³ . The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. For example, the first p-type region p1 is formed to have the same thickness as the interlayer insulating film 43.

  Accordingly, the semiconductor device 1 includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a first n of the second conductivity type (for example, n-type) opposite to the first conductivity type. Type region n1 (second region), first conductivity type (p-type) second p-type region p2 (third region), second conductivity type (n-type) second n-type region n2 (fourth region) in this order. The first thyristor T1 and the second thyristor T2 are joined, and the first n-type regions n1 of the first and second thyristors T1 and 3 are formed so as to face each other with the element isolation region 14 interposed therebetween. Each first p-type region p1 is formed so as to be joined on the element isolation region 14 by selective epitaxial growth from the element formation regions 12 and 13 (each first n-type region n1).

  An example of a method for manufacturing the configurations of the second to fourth embodiments of the semiconductor device will be described as a second embodiment of the manufacturing method of the semiconductor device with reference to the manufacturing process sectional views of FIGS.

  As shown in FIG. 16, a semiconductor substrate 11 is prepared. In the same manner as described with reference to FIGS. 2 to 4, the element isolation region 14 for isolating the element formation regions 12 and 13 is formed in the semiconductor substrate 11. For example, an n-well region 18 is formed below the element formation region 12. Thereafter, the upper portions of the element formation regions 12 and 13 of the semiconductor substrate 11 are formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor.

  Next, a gate insulating film 21 is formed on the semiconductor substrate 11. Next, a first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and a second gate electrode 22B is formed on the gate insulating film 21 formed in the element forming region 13. . Next, sidewalls 24 and 25 are formed on the sidewalls of the first and second gate electrodes 22A and 22B.

  Next, an ion implantation mask (not shown) having openings on the element formation regions 12 and 13 between the first and second gate electrodes 22A and 22B is formed by ordinary resist coating and lithography techniques. Next, an n-type dopant is introduced into the semiconductor substrate 11 between the first and second gate electrodes 22A and 22B by an ion implantation technique using the ion implantation mask, and the element formation regions 12 and 13 are introduced. A first n-type region n1 (second region) is formed. Thereafter, the ion implantation mask is removed.

  Subsequently, as annealing for activation, for example, heating is performed to reach 1050 ° C., and then spike annealing that immediately enters a cooling step is performed. The conditions at this time may be within a range where the dopant can be activated.

  The sidewalls 24 and 25 may be formed after ion implantation for forming the first n-type region n1.

  Next, an ion implantation mask (not shown) having an opening on the other side of each of the first and second gate electrodes 22A and 22B, that is, on the region where the second n-type region is formed, is formed by ordinary resist coating and lithography techniques. Form. Next, by an ion implantation technique using this ion implantation mask, an n-type dopant is introduced into the semiconductor substrate 11 on the other side of the first and second gate electrodes 22A and 22B, and the second n-type region n2 (first 4 regions). Thereafter, the ion implantation mask is removed.

  Subsequently, as annealing for activation, for example, heating is performed to reach 1050 ° C., and then spike annealing that immediately enters a cooling step is performed. The conditions at this time may be within a range where the dopant can be activated.

  Further, the order of forming the first n-type region n1 and the second n-type region n2 may be different from the procedure described above. The second n-type region n2 may be formed first, and the first n-type region n1 may be formed later. The annealing may be performed once after both the first n-type region n1 and the second n-type region n2 are formed, or may be a step of source / drain activation annealing of the selection transistor.

Next, as shown in FIG. 17, an interlayer insulating film 43 that covers the first and second gate electrodes 22A and 22B, the sidewalls 24 and 25, and the like is formed. The interlayer insulating film 43 is formed, for example, by depositing a silicon oxide (HDP-SiO ₂ ) film having a thickness of, for example, 300 nm by high-density plasma CVD. The film thickness at this time is preferably about 1 μm or less and not less than the height of the first and second gate electrodes 22A and 22B. Further, the interlayer insulating film 43 used at this time is not limited to HDP-SiO ₂ , but is an interlayer insulating film used in a normal CMOS process such as P-SiO ₂ or a low dielectric constant (Low-k) film. Any insulating film may be used as long as it is a film type and can maintain selectivity during epitaxial growth. Here, if necessary, the surface of the interlayer insulating film 43 may be planarized by performing chemical mechanical polishing (CMP).

  Next, an etching mask (not shown) that opens on the element formation regions 12 and 13 between the first and second gate electrodes 22A and 22B and the element isolation region 14 therebetween is formed by ordinary resist coating and lithography techniques. To do. Thereafter, an opening 44 is formed in the interlayer insulating film 43 on each first n-type region n1 and the element isolation region 14 therebetween by etching using this etching mask. By this etching process, the surface of the semiconductor substrate 11 (first n-type region n1) can be exposed only in the selective epitaxial growth portion. Since the interlayer insulating film 43 is for selectivity during epitaxial growth, a single film of a silicon oxide film or a silicon nitride film can be used. If the selectivity can be maintained, other types of insulating films can be used. You can also. Thereafter, the etching mask is removed.

  There are mainly three shapes of the opening 44 of the interlayer insulating film 43 as will be described later. One is to connect and open adjacent anode regions in a direction perpendicular to the thyristor word line (described later with reference to FIG. 19). One is opened by connecting one row in parallel to the thyristor word line (described later with reference to FIGS. 21 to 26). One is to open all anode regions sandwiched between thyristor word lines (described later with reference to FIG. 20).

Next, as shown in FIG. 18, a first conductivity type (p-type) first p-type region p1 (first region) is formed in the opening 44 on each first n-type region n1. The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 200 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. At this time, if necessary, the surface of the semiconductor substrate 11 may be cleaned using a chemical solution such as HF, hydrogen (H ₂ ) gas, or the like.

  In the above embodiment, the second n-type region n2 is formed by the ion implantation method, but may be performed by a selective epitaxial method. In that case, following the above, a silicon nitride film is again deposited, for example, by 20 nm, and then a region to be the second n-type region n2 is patterned and opened with a resist, and then the silicon nitride film is etched.

  In this example, a silicon nitride film is used as an example. However, since this is for selectivity during epitaxial growth, other film types and film thicknesses may be used as long as the selectivity can be maintained.

Next, the second n-type region n2 is formed by selective epitaxial growth. The conditions at this time are, for example, using an arsine (AsH ₃ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to, for example, 200 nm by adjusting the pressure and the like. The dopant (arsenic) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example, and is set to 1 × 10 ²⁰ cm ⁻³ as an example. The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the second n-type region n2 can function as a cathode electrode. Of course, any gas may be used as long as it is doped with n-type impurities, such as phosphine (PH ₃ ) or an organic source.

Moreover, in the said Example, although produced in order of the 1st p-type area | region p1 and the 2nd n-type area | region n2, you may form in order of the 2nd n-type area | region n2 and the 1st p-type area | region p1. At this time, if necessary, the surface of the silicon (Si) substrate may be cleaned using a chemical solution such as hydrofluoric acid (HF), hydrogen (H ₂ ) gas, or the like. Further, if necessary, after the first p-type region p1 or the second n-type region n2 is formed, activation annealing may be performed on either or both. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated.

  The semiconductor device 1 of the present invention formed by the manufacturing method of the second embodiment is a first p-type region p1 (first region) of the first conductivity type (for example, p-type), which is a reverse conductivity type from the first conductivity type. Second conductivity type (for example, n-type) first n-type region n1 (second region), first conductivity type (p-type) second p-type region p2 (third region), second conductivity type (n-type) Each of the first n-type regions n1 of the first and second thyristors T1 and T2 is an element isolation region. The first thyristor T1 and the second thyristor T2 are formed by sequentially joining the second n-type regions n2 (fourth region). 14 is formed so as to be opposed to each other, and each first p-type region p1 is selectively epitaxially grown from the element formation regions 12 and 13 (each first n-type region n1) in the opening 44 formed in the insulating film 43. Is formed so as to be bonded on the element isolation region 14. That.

  In the manufacturing method of the second embodiment, the selective epitaxial growth is performed in the lateral direction, and the first n-type region n1 and the second thyristor T2 of the first thyristor T1 separated through the element isolation region 14 are used. By epitaxially growing the first p-type region p1 from the first n-type region n1, it is possible to increase the area of the region where selective epitaxial growth starts effectively, so that the influence of facets generated during epitaxial growth is reduced, and the selection is made. The epitaxial growth layer has a trapezoidal shape, and the planar portion of the upper surface is formed wider than the case where selective epitaxial growth is performed from one first n-type region n1. Furthermore, the first p-type region p1 which is an epitaxial growth layer is suppressed by the side wall of the opening 44 of the interlayer insulating film 43, and the first n-type region n1 of the first thyristor T1 and the first n-type region of the second thyristor T2 The first p-type regions p1 epitaxially grown from n1 are also joined to each other on the element isolation region 14, so that the upper surface of the first p-type region p1 is easily formed in a planar shape. Therefore, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

  The shape of the opening 44 of the interlayer insulating film 43 and the anode electrode will be described with reference to the plan layout diagrams of FIGS.

  As shown in FIG. 19, the first thyristor T1 and the second thyristor T2 are arranged such that the first n-type region n1 (second region) of the first thyristor T1 and the first n-type region of the second thyristor T2 across the element isolation region 14. The first gate electrode 22A is formed on the second p-type region p2 (third region) of the first thyristor T1 via a gate insulating film (not shown). A second gate electrode 22B is formed on the second p-type region p2 of the second thyristor T1 via a gate insulating film (not shown). A plurality of such first thyristors T1 and second thyristors T2 are arranged in the arrangement direction of the first gate electrode 22A and the second gate electrode 22B, and each first thyristor T1 has one first gate electrode 22A. One thyristor word line TW1 is formed, and the second gate electrode 22B of each second thyristor T2 is formed by one second thyristor word line TW2.

  Then, on the first n-type region n1 (second region) of the first thyristor T1, the first n-type region n1 of the second thyristor T1 adjacent to the first thyristor T1 via the element isolation region 14, and the element isolation region 14 described above. An opening 44 of the interlayer insulating film 43 is formed. Therefore, the opening 44 is formed on each first n-type region n1 in a direction orthogonal to the first thyristor word line 22A and the second thyristor word line 22B. Then, the first thyristor T1 and the second thyristor T2 are selectively epitaxially grown on each first n-type region n1 in the opening 44 and between the first thyristor word line 22A and the second thyristor word line 22B. The first p-type region p1 (first region) used in common is formed. In this configuration, an anode contact 64 is provided in the first p-type region p1 above each first n-type region n1.

  Next, as shown in FIG. 20, the first thyristor T1 and the second thyristor T2 are connected to the first n-type region n1 (second region) of the first thyristor T1 and the second thyristor T2 across the element isolation region 14. A first gate electrode 22A is formed on the second p-type region p2 (third region) of the first thyristor T1 via a gate insulating film (not shown); A second gate electrode 22B is formed on the second p-type region p2 of the second thyristor T1 via a gate insulating film (not shown). A plurality of such first thyristors T1 and second thyristors T2 are arranged in the arrangement direction of the first gate electrode 22A and the second gate electrode 22B, and each first thyristor T1 has one first gate electrode 22A. One thyristor word line TW1 is formed, and the second gate electrode 22B of each second thyristor T2 is formed by one second thyristor word line TW2.

  An opening 44 of the interlayer insulating film 43 is formed between the first thyristor word line TW1 and the second thyristor word line TW2 including the first n-type region n1 and the element isolation region 14 therebetween. . Then, the first p-type region p1 (first region) is selectively epitaxially grown from above each first n-type region n1 in the opening 44 and between the first thyristor word line TW1 and the second thyristor word line TW2. ) Is formed.

  A configuration in which an opening 44 of the interlayer insulating film 43 is formed between the first thyristor word line TW1 and the second thyristor word line TW2 including the first n-type region n1 and the element isolation region 14 therebetween. , In the arrangement direction of the first thyristor word line 22A and the second thyristor word line 22B, the first n-type region n1 of two or more first thyristors T1 and two or more second adjacent ones. The opening 44 may be formed on the first n-type region n1 of the thyristor T2 and the element isolation region 14 therebetween. Accordingly, the first p-type region p1 formed in the opening 44 includes the first n-type region n1 of the two or more first thyristors T1 and the two or more second thyristors T2 adjacent thereto. It may be formed on the first n-type region n1 and the element isolation region 14 therebetween.

  Next, an embodiment of the second semiconductor device and a manufacturing method thereof will be described with reference to FIGS. In FIGS. 21 to 26, the first p-type region p1 (on the first n-type region n1 (second region) of the plurality of first thyristors T1 and the element isolation region 14 therebetween along the first thyristor word line TW1. The first p-type region p1 (first region) is formed on the first n-type region n1 (second region) of the plurality of second thyristors T2 along the second thyristor word line TW2 and on the element isolation region 14 therebetween. A configuration in which the first region) is formed will be described.

First, the steps described with reference to FIGS. 2 to 4 are performed. Further, as described with reference to FIG. 17, the first thyristor word line TW1 (first gate electrode 22A), the second, as shown in FIG. An interlayer insulating film 43 that covers the thyristor word line TW2 (second gate electrode 22B), the sidewalls 24, 25, and the like is formed. The interlayer insulating film 43 is formed, for example, by depositing a silicon oxide (HDP-SiO ₂ ) film having a thickness of, for example, 300 nm by high-density plasma CVD. The film thickness at this time is preferably about 1 μm or less and not less than the height of the first and second gate electrodes 22A and 22B. Further, the interlayer insulating film 43 used at this time is not limited to HDP-SiO ₂ , but is an interlayer insulating film used in a normal CMOS process such as P-SiO ₂ or a low dielectric constant (Low-k) film. Any insulating film may be used as long as it is a film type and can maintain selectivity during epitaxial growth. Here, if necessary, the surface of the interlayer insulating film 43 may be planarized by performing chemical mechanical polishing (CMP).

  Next, by a normal resist coating and lithography technique, the first n-type region n1 (second region) of the plurality of first thyristors T1 along the first thyristor word line TW1, the element isolation region 14 therebetween, and the second An etching mask (not shown) having openings on the first n-type region n1 (second region) of the plurality of second thyristors T2 and the element isolation region 14 therebetween is formed along the thyristor word line TW2. Thereafter, by etching using this etching mask, the first n-type region n1 (second region) of the plurality of first thyristors T1 along the first thyristor word line TW1, and the element isolation region 14 between them and the second Openings 45 and 46 are formed in the interlayer insulating film 43 on the first n-type region n1 (second region) of the plurality of second thyristors T2 and the element isolation region 14 therebetween along the thyristor word line TW2. By this etching process, the surface of the semiconductor substrate 11 (first n-type region n1) can be exposed only in the selective epitaxial growth portion. Since the interlayer insulating film 43 is for selectivity during epitaxial growth, a single film of a silicon oxide film or a silicon nitride film can be used. If the selectivity can be maintained, other types of insulating films can be used. You can also. Thereafter, the etching mask is removed.

Next, as shown in the cross-sectional view of FIG. 22 and the planar layout diagram of FIG. 23, the above-mentioned over the first n-type region n1 (second region) of the plurality of first thyristors T1 along each first thyristor word line TW1. A first p-type region p1 (first region) of the first conductivity type (p-type) is formed in the opening 45, and at the same time, first n-type regions n1 of the plurality of second thyristors T2 along each second thyristor word line TW2. A first conductivity type (p-type) first p-type region p1 (first region) is formed in the opening 46 on the (second region). The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 200 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. At this time, if necessary, the surface of the semiconductor substrate 11 may be cleaned using a chemical solution such as HF, hydrogen (H ₂ ) gas, or the like. An anode contact 64 is provided on the first p-type region p1.

  Next, an example of the wiring in the second semiconductor device 2 configured as described above will be described with reference to the plan layout diagram of FIG. 24 and the circuit diagrams of FIGS.

  As shown in FIGS. 24, 25, and 26, for example, the semiconductor device 2 includes a second selection transistor Tr2, a first selection transistor Tr1, a first thyristor T1, and a second thyristor in one direction (for example, the X direction). They are repeatedly arranged in the order of T2. In the repetitive arrangement direction, an element isolation region 14 is formed between the selection transistor and the thyristor and between the thyristors. On the other hand, the second selection transistor Tr2, the first selection transistor Tr1, the first thyristor T1, and the second thyristor T2 are repeated through the element isolation region 14 in a direction orthogonal to the one direction (for example, the Y direction). Has been placed. The first thyristor word line 22A of each first thyristor T1 and the second thyristor word line 22B of each second thyristor T2 are arranged in the Y direction, and the first word line W1 of each first select transistor Tr1 and each first thyristor word line 22B. The second word line W2 of the two selection transistors Tr2 is arranged in the Y direction.

  The first p-type regions p1 (first regions) selectively epitaxially grown from the first n-type regions n1 (second regions) along the first thyristor word lines TW1 serve as anode electrodes. An anode line A1 connected via an anode contact 64 is arranged in a direction parallel to the first thyristor word line TW1. Similarly, the first p-type regions p1 (first regions) selectively epitaxially grown from the first n-type regions n1 (second regions) along the second thyristor word lines TW2 serve as anode electrodes. An anode line A2 connected to each anode electrode via an anode contact 64 is arranged in a direction parallel to the first thyristor word line TW2. The source / drain 51 on the thyristor side of each first selection transistor Tr1 (and the second selection transistor Tr2) and the second n-type region n2 (fourth region) of the thyristor are respectively connected via bridge contacts 61 and 62 (not shown). Connected). Further, on the uppermost layer, a bit line B connected to the source / drain region 52 between the second selection transistor Tr2 and the first selection transistor Tr1 via a bit contact 63 is connected to the first thyristor word line TW1. They are arranged in a direction orthogonal to the second thyristor word line TW2.

  In the above configuration, one memory element is configured by one selection transistor and one thyristor. For example, the memory element M1 is configured by the first thyristor T1 and the first selection transistor Tr1 surrounded by a two-dot chain line.

  The semiconductor device 2 has the same effect as the semiconductor devices 1A, 1B and the like, and the semiconductor device 2 has an advantage that the anode contact 64 can be easily taken because the first p-type region p1 can be widened.

  Next, an embodiment of the third semiconductor device and a method for manufacturing the same will be described with reference to FIGS. 27 to 33, on the second p-type region p2 (third region) on the first selection transistor Tr1 side of the first thyristor T1 and on the source / drain region 52 on the first thyristor T1 side of the first selection transistor Tr1. And a configuration in which a second n-type region n2 (fourth region) is formed on the element isolation region 14 therebetween.

First, as shown in FIG. 27, a semiconductor substrate 11 is prepared. For example, a silicon substrate is used as the semiconductor substrate 11. An element isolation region 14 for isolating the element formation regions 12 and 15 is formed in the semiconductor substrate 11. The element isolation region 14 is formed by a technique such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or DTI (Deep Trench Isolation). For example, an n-well region 18 is formed below the element formation region 12. Thereafter, the upper portion of the element formation region 12 of the semiconductor substrate 11 is formed in a first conductivity type (p-type) region. This p-type region becomes the second p-type region p2 (third region) of the thyristor. As an example of the ion implantation conditions, boron (B) which is a p-type dopant is used as a dopant, and the concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ , and 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm. ^{About -3} is desirable. Basically, it must be lower than the dopant concentration of the first n-type region of the second conductivity type (n-type) to be formed later. The p-type dopant may be a p-type dopant such as indium (In) in addition to boron (B). The concentration when using indium is the same as when using boron.

  A p-type well region 55 is formed in the element formation region 15. This p-type well region 55 can be formed in the same manner as a p-type well region formed by a known MOS process.

Next, a gate insulating film 21 is formed on the semiconductor substrate 11. The gate insulating film 21 is formed of, for example, a silicon oxide (SiO ₂ ) film and is formed to a thickness of about 1 nm to 10 nm. The gate insulating film 21 is not limited to silicon oxide (SiO ₂ ), but also silicon nitride oxide (SiON), hafnium oxide (HfO ₂ ), nitrided hafnium oxide (HfON), and aluminum oxide (Al ₂ O). ₃ ), a gate insulating film material that has been studied in a normal CMOS, such as hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), or lanthanum oxide (La ₂ O ₃ ) can also be used.

  Next, the first gate electrode 22A is formed on the gate insulating film 21 formed in the element forming region 12, and the gate electrode 56 is formed on the gate insulating film 21 formed in the element forming region 15. The first gate electrode 22A and the gate electrode 56 are usually made of polycrystalline silicon. Alternatively, it can be a metal gate electrode, or can be formed of silicon germanium (SiGe) or the like.

For each of the first gate electrode 22A and the gate electrode 56, for example, after forming a gate electrode forming film on the gate insulating film 21, a normal resist coating, formation of an etching mask by a lithography technique, and the etching mask were used. The gate electrode formation film is formed by etching using an etching technique. For this etching technique, a normal dry etching technique can be used. Alternatively, it can be formed by wet etching. Further, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or the like may be formed on the gate electrode formation film as a hard mask.

Next, side walls 24 and 25 are formed on the side walls of the first gate electrode 22 </ b> A, and at the same time, side walls 57 and 58 are formed on the side walls of the gate electrode 56. For example, a sidewall formation film is formed so as to cover the first gate electrode 22A and the gate electrode 56, and then the sidewall formation film is etched back so that the sidewalls of the first gate electrode 22A and the gate electrode 56 are etched. The side walls 24 and 25 and the side walls 57 and 58 can be formed. The side walls 24 and 25 and the side walls 57 and 58 may be formed of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or may be formed of a laminated film thereof.

Next, an ion implantation mask (not shown) having an opening on the element formation region 12 on one side (the side opposite to the gate electrode 56) of the first gate electrode 22A is formed by ordinary resist coating and lithography techniques. . Next, an n-type dopant is introduced into the semiconductor substrate 11 by an ion implantation technique using the ion implantation mask to form a first n-type region n1 (second region) in the element formation region 12. The ion implantation conditions are set so that, for example, phosphorus (P) is used as a dopant, and the concentration is, for example, 1.5 × 10 ¹⁹ cm ⁻³ . This concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, but it needs to be higher than the dopant concentration of the second p-type region p2. Further, n-type dopants such as arsenic and antimony can be used instead of phosphorus. The concentration when n-type dopants such as arsenic and antimony are used is equivalent to that when phosphorus is used. Thereafter, the ion implantation mask is removed.

  Next, an ion implantation mask (not shown) having an opening on the element formation region 15 is formed by ordinary resist coating and lithography techniques. Next, an n-type dopant is introduced into the semiconductor substrate 11 by ion implantation using the ion implantation mask to form source / drain regions 51 and 52 in the element formation region 15 on both sides of the gate electrode 56. . As the ion implantation conditions, the conditions for forming the source / drain regions of a normal nMOS transistor can be used. Thereafter, the ion implantation mask is removed.

  Before forming the side walls 57 and 58, extension regions (or LDD regions) 59 and 60 are preferably formed in the element formation region 15 on both sides of the gate electrode 56.

  Subsequently, as annealing for activation, for example, heating is performed to reach 1050 ° C., and then spike annealing that immediately enters a cooling step is performed. The conditions at this time may be within a range where the dopant can be activated.

  Next, as shown in FIG. 28, an insulating film 41 is formed to cover each first gate electrode 22A, gate electrode 56, sidewalls 24 and 25, sidewalls 57 and 58, and the like. The insulating film 41 serves as a mask for selective epitaxial growth performed in a later process, and is formed of, for example, a silicon nitride film and has a thickness of, for example, 20 nm. Next, on the first n-type region n1 of another thyristor (not shown) adjacent to the first n-type region n1 with the element isolation region 14 sandwiched between the first n-type region n1 and the first n-type region n1 by ordinary resist coating and lithography techniques. Then, an etching mask (not shown) having an opening on the element isolation region 14 therebetween is formed. Thereafter, an opening 42 is formed in the insulating film 41 on each first n-type region n1 and on the element isolation region 14 therebetween by etching using this etching mask. By this etching process, the surface of the semiconductor substrate 11 (first n-type region n1) can be exposed only in the selective epitaxial growth portion. Here, as an example, a silicon nitride film is used as the insulating film 41, but this is for obtaining selectivity during epitaxial growth. Therefore, other types of insulating films can be used as long as the selectivity can be maintained. Thereafter, the etching mask is removed.

  In the step of exposing the surface of the semiconductor substrate 11 (first n-type region n1), the shape of the opening 42 is the above-described shape (for example, FIG. 7, FIG. 10, FIG. 19, FIG. 20, FIG. 23). Etc.).

Next, as shown in FIG. 29, a first conductivity type (p-type) first p-type region p1 (first region) is formed in the opening 42 on each first n-type region n1. The first p-type region p1 was formed by selective epitaxial growth, for example, so that the boron (B) concentration in the film was 1 × 10 ²⁰ cm ⁻³ . The selective epitaxial growth conditions at this time are, for example, using diborane (B ₂ H ₆ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to 200 nm, for example, by adjusting the pressure of the film forming atmosphere. The dopant (boron) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the first p-type region p1 can function as an anode electrode. At this time, if necessary, the surface of the semiconductor substrate 11 may be cleaned using a chemical solution such as HF, hydrogen (H ₂ ) gas, or the like.

  Here, as an example, a silicon nitride film is used as the insulating film 41, but this is for the purpose of selectivity during epitaxial growth, and therefore other film types and film thicknesses may be used as long as the selectivity can be maintained.

Next, as shown in FIG. 30, an interlayer insulating film 43 that covers each first gate electrode 22A, gate electrode 56, sidewalls 24 and 25, sidewalls 57 and 58, insulating film 41, and the like is formed. The interlayer insulating film 43 is formed, for example, by depositing a silicon oxide (HDP-SiO ₂ ) film having a thickness of, for example, 300 nm by high-density plasma CVD. The film thickness at this time is preferably about 1 μm or less and above the height of the first gate electrode 22A and the gate electrode 56. Further, the interlayer insulating film 43 used at this time is not limited to HDP-SiO ₂ , but is an interlayer insulating film used in a normal CMOS process such as P-SiO ₂ or a low dielectric constant (Low-k) film. Any insulating film may be used as long as it is a film type and can maintain selectivity during epitaxial growth. Here, if necessary, the surface of the interlayer insulating film 43 may be planarized by performing chemical mechanical polishing (CMP).

  Next, an etching mask (not shown) that opens on the first gate electrode 22A, the element formation regions 12 and 15 between the gate electrodes 56 and the element isolation region 14 therebetween is formed by ordinary resist coating and lithography techniques. . After that, by etching using this etching mask, the source on the second p-type region p2 (third region) on the first selection transistor Tr1 side of the first thyristor T1 and on the first thyristor T1 side of the first selection transistor Tr1. An opening 44 is formed in the interlayer insulating film 43 on the drain region 51 and on the element isolation region 14 therebetween. By this etching process, the surface of the semiconductor substrate 11 (the second p-type region p2 and the source / drain region 51) can be exposed only in the selective epitaxial growth portion. Since the interlayer insulating film 43 is for selectivity during epitaxial growth, a single film of a silicon oxide film or a silicon nitride film can be used. If the selectivity can be maintained, other types of insulating films can be used. You can also. Thereafter, the etching mask is removed.

Next, as shown in the sectional view of FIG. 31 and the plan layout diagram of FIG. 32, the second p-type region p2 and the opening 44 on the source / drain region 51 have a second conductivity type (n-type) second n-type. Region n2 (fourth region) is formed. The second n-type region n2 is formed by selective epitaxial growth, for example. The conditions at this time are, for example, using an arsine (AsH ₃ ) gas as a dopant source gas together with a silane-based gas, setting the substrate temperature at the time of film formation to 750 ° C., for example, The film thickness was set to, for example, 200 nm by adjusting the pressure and the like. The dopant (arsenic) concentration is preferably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example, and is set to 1 × 10 ²⁰ cm ⁻³ as an example. The film thickness is preferably about 50 nm to 300 nm, but may be in a range where the second n-type region n2 can function as a cathode electrode. Of course, any gas may be used as long as it is doped with n-type impurities, such as phosphine (PH ₃ ) or an organic source.

Moreover, in the said Example, although produced in order of the 1st p-type area | region p1 and the 2nd n-type area | region n2, you may form in order of the 2nd n-type area | region n2 and the 1st p-type area | region p1. At this time, if necessary, the surface of the silicon (Si) substrate may be cleaned using a chemical solution such as hydrofluoric acid (HF), hydrogen (H ₂ ) gas, or the like. Further, if necessary, after the first p-type region p1 or the second n-type region n2 is formed, activation annealing may be performed on either or both. As the activation annealing, for example, after heating up to 1050 ° C., spike annealing that immediately enters the cooling step is performed. The annealing conditions at this time may be within a range where the dopant can be activated. Further, as illustrated, the surface of the interlayer insulating film 43 and the surface of the second n-type region n2 may be planarized by, for example, chemical mechanical polishing so that the surface is the same height.

  Next, although not shown, the first thyristor word line TW1 (first gate electrode 22A), the gate electrode 56, the first p-type region p1, the second n-type region n2, the source / drain regions 51, 52, and the like are exposed. Then, the interlayer insulating film 43 and the insulating film 41 (see FIG. 6) on each region are removed. Then, a salicide process is performed on the surface of each exposed first thyristor word line TW1 (first gate electrode 22A), gate electrode 56, first p-type region p1 and second n-type region n2, source / drain regions 51, 52, and the like. For example, the silicide layer may be formed of titanium silicide, cobalt silicide, or nickel silicide. Thereafter, a wiring process similar to a normal CMOS process is performed.

  The semiconductor device 3 of the present invention formed by the above manufacturing method includes a first p-type region p1 (first region) of the first conductivity type (for example, p-type), and a second conductivity type opposite to the first conductivity type. (For example, n-type) first n-type region n1 (second region), first conductivity-type (p-type) second p-type region p2 (third region), second conductivity-type (n-type) second n-type region The first thyristor T1 is formed by sequentially joining n2 (fourth region), and the first selection transistor Tr1 is an nMOS transistor. The second p-type region p2 of each first thyristor T1 has a first isolation region 14 in between. The selection transistor Tr1 is formed so as to face the source / drain region 51, and is joined to the second p-type region p2 in the opening 44 and the source / drain region 51 on the element isolation region 14 by selective epitaxial growth. Second Wherein the type region n2 (fourth region) is formed.

  In the manufacturing method of the semiconductor device 3, the selective epitaxial growth is performed in the lateral direction, and the second p-type region p2 of the first thyristor T1 and the first selection transistor Tr1 separated by the element isolation region 14 are used. By epitaxially growing the second n-type region n2 from the source / drain region 52, the area of the region where selective epitaxial growth can be effectively started can be increased, so that the influence of facets generated during epitaxial growth is reduced, and selection is made. The epitaxial growth layer has a trapezoidal shape, and the planar portion of the upper surface is formed wider than the case where selective epitaxial growth is performed from one second n-type region n2. Further, the sidewall of the second n-type region n2 which is an epitaxial growth layer is suppressed by the sidewalls 24 and 58, and the second p-type region p2 of the first thyristor T1 and the source / drain region 5 of the first selection transistor Tr1 When the second n-type regions n2 epitaxially grown from each other are joined together on the element isolation region 14, the upper surface of the second n-type region n2 is easily formed in a planar shape. Therefore, the salicide process margin and the contact formation process margin can be increased, and there is an advantage that a device with stable and less variation can be manufactured.

In the manufacturing method of the semiconductor device 3, the case where the first n-type region n <b> 1 is formed by the ion implantation method has been described, but it can also be formed by a selective epitaxial method. The conditions at this time are, for example, an arsine (AsH ₃ ) gas, a film formation atmosphere temperature of 750 ° C., an n-type impurity arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ , and a film thickness of 100 nm. In this manner, film formation may be performed. The concentration of the n-type impurity is desirably about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example. The film thickness is preferably about 50 nm to 300 nm. The gas used may be an n-type impurity such as phosphine (PH ₃ ) or an organic source. Therefore, arsenic (As), phosphorus (P), antimony (Sb), or the like can be used as the n-type impurity. If necessary, the surface of the semiconductor substrate 11 may be cleaned using a chemical solution such as hydrofluoric acid (HF) or hydrogen (H ₂ ) gas.

  Next, a modified example of the semiconductor device 3 will be described with reference to a schematic sectional view of FIG.

  As shown in FIG. 33, in the configuration in which the first n-type region n1 or the second n-type region n2 is formed by selective epitaxial growth, as in the case of the first select transistor Tr1, the normal thyristor T1 is formed on both sides of the gate electrode 22A. In the CMOS process, diffusion layer regions 27 and 28 that are called shallower than the normal CMOS source and drain, called LDD (Lightly Doped Drain) or extension, may be formed. In this configuration, since the first n-type region n1 or the second n-type region n2 is formed by selective epitaxial growth, impurities having the same type as the first n-type region n1 or the second n-type region n2 are not doped immediately below the sidewalls 24 and 25. .

  Further, in the third semiconductor device 3, the first n-type region n1 can be formed by epitaxial growth so as to have a thickness of about 10 nm to 50 nm before the first p-type region p1 is formed. Thereby, it is possible to suppress diffusion of impurities in the first p-type region p1 into the semiconductor substrate 11.

  Further, in the third semiconductor device 3, the second p-type region p2 can be formed by epitaxial growth so as to have a thickness of about 10 nm to 50 nm before the second n-type region n2 is formed. Thereby, it is possible to prevent the impurities in the second n-type region n2 from diffusing into the semiconductor substrate 11.

  In each of the above embodiments, the selective epitaxial growth was performed while doping an n-type impurity or a p-type impurity. For example, all or a part of the epitaxial growth layer may be epitaxially grown without doping, and then a predetermined impurity may be doped by an ion implantation method or a solid layer diffusion method.

  In each of the above embodiments, it is assumed that a bulk silicon substrate is used as the semiconductor substrate 11, but the semiconductor substrate 11 can also be manufactured using an SOI (Silicon on insulator) substrate.

  In each of the above embodiments, the first conductivity type impurity is a p-type impurity and the second conductivity type impurity is an n-type impurity. However, the first conductivity type impurity is an n-type impurity, and the second conductivity type impurity is an n-type impurity. The type impurity can also be produced as a p-type impurity.

1 is a schematic cross-sectional view showing an embodiment (first embodiment) of a semiconductor device according to the present invention. It is manufacturing process sectional drawing which showed the 1st Example of one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the 1st Example of one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the 1st Example of one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the 1st Example of one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the 1st Example of one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is the plane layout figure which showed an example of the shape of the opening part and anode electrode in the process of exposing a semiconductor substrate surface. It is the plane layout figure which showed an example of the wiring in the semiconductor device 1 (1A). It is a circuit diagram showing an example of wiring in semiconductor device 1 (1A). It is the plane layout figure which showed an example of the shape of the opening part and anode electrode in the process of exposing a semiconductor substrate surface. It is the plane layout figure which showed an example of the wiring in the semiconductor device 1 (1B). It is the circuit diagram which showed an example of the wiring in the semiconductor device 1 (1B). It is a schematic structure sectional view showing one embodiment (the 2nd example) concerning a semiconductor device of the present invention. FIG. 3 is a schematic cross-sectional view showing an embodiment (third embodiment) according to the semiconductor device of the present invention. FIG. 6 is a schematic cross-sectional view showing an embodiment (fourth example) according to the semiconductor device of the present invention. It is manufacturing process sectional drawing which showed 2nd Example of the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example of the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example of the manufacturing method of the semiconductor device of this invention. FIG. 6 is a plan layout diagram showing the shape of an opening of an interlayer insulating film and an anode electrode. FIG. 6 is a plan layout diagram showing the shape of an opening of an interlayer insulating film and an anode electrode. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the 2nd semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the 2nd semiconductor device of this invention. It is the plane layout figure shown about the opening of an interlayer insulation film concerning the manufacturing method of the 2nd semiconductor device of the present invention, and the shape of an anode electrode. 4 is a plan layout view showing an example of wiring in the semiconductor device 2. FIG. 4 is a circuit diagram showing an example of wiring in the semiconductor device 2. FIG. 4 is a circuit diagram showing an example of wiring in the semiconductor device 2. FIG. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. It is the plane layout figure which showed one Embodiment (Example) which concerns on the 3rd semiconductor device of this invention, and its manufacturing method. FIG. 10 is a schematic cross-sectional view showing a modification of the embodiment according to the third semiconductor device. It is schematic structure sectional drawing which showed the subject. It is schematic structure sectional drawing which showed the subject.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 14 ... Element isolation region, p1 ... 1st p-type area | region (1st area | region), p2 ... 2nd p-type area | region (3rd area | region), n1 ... 1st n-type area | region (2nd area | region), n2 ... 1st 2n-type region (fourth region), T1... First thyristor, T2.

Claims (12)

A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A semiconductor device in which a first thyristor and a second thyristor joined in order are separated in an element isolation region,
A second region of the first thyristor and a second region of the second thyristor are provided across the element isolation region;
The first region of the first thyristor formed by selective epitaxial growth on the second region of the first thyristor, and the first region of the second thyristor formed by selective epitaxial growth on the second region of the second thyristor. Is formed in a continuous state on the element isolation region between the second region of the first thyristor and the second region of the second thyristor. A first gate electrode formed in a third region of the first thyristor via a gate insulating film;
A second gate electrode formed in a third region of the second thyristor via a gate insulating film;
The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are arranged in parallel. A plurality of the first thyristors are arranged through an element isolation region in a direction orthogonal to a direction in which the first thyristor and the second thyristor are disposed,
A plurality of the second thyristors are arranged through an element isolation region in a direction perpendicular to a direction in which the first thyristor and the second thyristor are disposed;
An anode line connected to the first region between the first gate electrode and the second gate electrode and disposed in parallel with the first gate electrode and the second gate electrode;
The first gate electrode and the second gate are connected to one source / drain of a first selection transistor that selects the first thyristor and one source / drain of a second selection transistor that selects the second thyristor. The semiconductor device according to claim 2, further comprising: a bit line disposed in a direction orthogonal to the gate electrode. An anode line connected to the first region between the first gate electrode and the second gate electrode and disposed in a direction orthogonal to the first gate electrode and the second gate electrode;
The first gate electrode and the second gate are connected to one source / drain of a first selection transistor that selects the first thyristor and one source / drain of a second selection transistor that selects the second thyristor. The semiconductor device according to claim 2, further comprising: a bit line disposed in a direction parallel to the first gate electrode and the second gate electrode between the gate electrode and the gate electrode. A row in which a plurality of the first thyristors are arranged and a row in which the plurality of second thyristors are arranged are arranged in parallel,
A first gate electrode formed in a third region of each first thyristor via a gate insulating film;
A second gate electrode formed in a third region of each second thyristor via a gate insulating film;
The first gate electrodes of the first thyristors are formed of the same first gate wiring, and the second gate electrodes of the second thyristors are formed of the same second gate wiring,
The first region of each first thyristor is continuously formed along the first gate wiring, and the first region of each second thyristor is continuously formed along the second gate wiring. The semiconductor device according to claim 1. An anode line connected to the first region between the first gate electrode and the second gate electrode and disposed in parallel with the first gate electrode and the second gate electrode;
The first gate electrode and the second gate are connected to one source / drain of a first selection transistor that selects the first thyristor and one source / drain of a second selection transistor that selects the second thyristor. 6. The semiconductor device according to claim 5, further comprising a bit line disposed in a direction orthogonal to the gate electrode. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A semiconductor device in which a first thyristor and a second thyristor joined in order are separated in an element isolation region,
A second region of the first thyristor and a second region of the second thyristor are provided across the element isolation region;
A plurality of the first thyristors are arranged through an element isolation region in a direction orthogonal to a direction in which the first thyristor and the second thyristor are disposed,
A plurality of the second thyristors are arranged through an element isolation region in a direction perpendicular to a direction in which the first thyristor and the second thyristor are disposed;
A first gate electrode formed in a third region of each first thyristor via a gate insulating film is formed by a common first gate wiring arranged in the arrangement direction of each first thyristor;
A second gate electrode formed in a third region of each second thyristor via a gate insulating film is formed by a common second gate wiring arranged in the arrangement direction of each second thyristor;
A first region of each of the first thyristors is continuously formed on the second region of each of the first thyristors and on an element isolation region therebetween and along the first gate wiring;
The first region of each of the second thyristors is formed continuously on the second region of each of the second thyristors and on the element isolation region therebetween and along the second gate wiring. Semiconductor device. A first anode line connected to the first region of the first thyristor and disposed in parallel with the first gate wiring;
A second anode line connected to the first region of the second thyristor and disposed in parallel with the second gate wiring;
One source / drain of a first selection transistor for selecting the first thyristor and one source / drain of a second selection transistor for selecting the second thyristor are connected to the first gate line and the second The semiconductor device according to claim 7, further comprising a bit line disposed in a direction orthogonal to the gate wiring. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A semiconductor device in which a thyristor and a MIS transistor that are sequentially joined are separated in an element isolation region,
The second region and one source / drain region of the MIS transistor are provided across the element isolation region,
The first region formed by selective epitaxial growth on the second region and the stacked source / drain region formed by selective epitaxial growth on the one source / drain region are the second region and the one source. The semiconductor device is formed in a continuous state on the element isolation region between the drain region. A semiconductor substrate includes a first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type first region. A method of manufacturing a semiconductor device in which a first thyristor and a second thyristor, which are sequentially joined to four regions, are formed in a state of being separated in an element isolation region,
After forming the second region of the first thyristor and the second region of the second thyristor across the element isolation region on the semiconductor substrate,
By selective epitaxial growth, the first region of the first thyristor is epitaxially grown from the second region of the first thyristor, and at the same time, the first region of the second thyristor is epitaxially grown from the second region of the second thyristor. Forming a first region of the first thyristor and a first region of the second thyristor on the element isolation region; and manufacturing the semiconductor device. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. The first thyristor and the second thyristor that are sequentially joined are formed in a state of being separated in the element isolation region,
A second region of the first thyristor and a second region of the second thyristor are provided across the element isolation region;
A plurality of the first thyristors are arranged through an element isolation region in a direction orthogonal to a direction in which the first thyristor and the second thyristor are disposed,
A plurality of the second thyristors are arranged through an element isolation region in a direction perpendicular to a direction in which the first thyristor and the second thyristor are disposed;
A first gate electrode formed in a third region of each first thyristor via a gate insulating film is formed by a common first gate wiring arranged in the arrangement direction of each first thyristor;
A semiconductor device in which a second gate electrode formed in a third region of each second thyristor via a gate insulating film is formed by a common second gate wiring arranged in the arrangement direction of each second thyristor A manufacturing method of
Forming a first region of each of the first thyristors on the second region of each of the first thyristors and on an element isolation region therebetween and continuously along the first gate wiring;
The first region of each second thyristor is formed continuously on the second region of each second thyristor and on the element isolation region therebetween, and along the second gate wiring. Device manufacturing method. A first conductivity type first region, a second conductivity type second region opposite to the first conductivity type, a first conductivity type third region, and a second conductivity type fourth region. A method of manufacturing a semiconductor device in which a thyristor and an MIS transistor that are sequentially joined are separated in an element isolation region,
After forming the second region and the source / drain region of the MIS transistor across the element isolation region on the semiconductor substrate,
By selective epitaxial growth, the first region is formed by epitaxial growth from the second region, and at the same time, the source / drain region is formed by epitaxial growth from the source / drain region formed by sandwiching the element isolation region in the second region. Forming a region, and forming the first region and the stacked source / drain region in a bonded state on the element isolation region.

Images