JP2009135130A - Apparatus and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and method for manufacturing a semiconductor device that enhances the quality of a semiconductor device by making the chip coordinate correspondent accurately to the time of measuring the electrical characteristics and when picking, and ranking the chips simply. <P>SOLUTION: An apparatus for manufacturing a semiconductor device provided with a probe reference chip and a picking reference chip includes a memory for storing the electrical characteristics of a probe reference coordinate and a prove reference chip, the picking reference coordinate, the pattern of a picking reference chip, and the electrical characteristics of a plurality of chips and the coordinates of the chips in correspondence with each other, a first chip specification section for specifying a chip having electrical characteristics matching the electrical characteristics of the prove reference chip, a coordinate correction section for converting a first coordinate into a probe reference coordinate and converting the coordinates other than the first coordinate based on the coordinate conversion when a specified first coordinate is different from a probe reference coordinate, a second chip specification section for specifying a chip having a pattern matching the pattern of the picking reference chip, and a picking reference setting section for setting the coordinate of a specified chip as a picking reference coordinate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for recognizing the position of a chip formed on a wafer in a semiconductor device manufacturing process.

  Conventionally, chips diced in the manufacturing process of a semiconductor device are picked up in order only to chips that are determined to be non-defective, and are directly incorporated into a package, or are rearranged in a tray or the like classified by rank. Chips determined to be defective are marked, and only non-defective products that are not marked by image recognition are picked and used.

  In Patent Document 1, a control unit is provided that reads, by data compression, wafer identifier data and characteristic data of all chips from a wafer test apparatus that has tested all chips on the wafer. Further, the control unit decodes the position data of each chip having the specified characteristic data from the compressed data and outputs it. There has been a proposal of die bonding only the chips of the ranks instructed by the picking unit picking the chips and die bonding based on the position data from the control unit.

  In Patent Document 2, a pad for pad alignment of a probe card needle tip and an alignment chip having an alignment mark for marking are provided on a wafer. In the prober, a proposal has been made to prevent positional deviation of the chip address at the time of measurement and marking by performing the needle alignment of the pad and the probe card and the initial alignment of the marking with the alignment chip.

  In Patent Document 3, a recognizable identification mark is provided on a chip that is arranged at the periphery of a wafer and cannot be a good product. When information on each chip is recognized, information on the positional relationship of each chip with respect to the chip provided with the identification mark is also recognized and stored in the information medium, and then the wafer is diced and picked. In this way, by accurately recognizing information for each chip and sending it to the subsequent process, defective products can be sent to the subsequent process, or different ranks can be classified as the same rank Proposals have been made to prevent this.

  However, in Patent Document 1, chip coordinates at the time of wafer probe and chip coordinates at the time of picking must be the same, but a method of recognizing the coordinates is not described. In general, these apparatuses incorporate a processing routine for determining an effective chip area. However, when the chip is small, there is a possibility that coordinates may be misidentified due to misalignment of pattern printing onto the wafer. In addition, there is a method in which an operator designates a reference chip on a wafer and determines coordinates, but the reference may be mistaken due to an operator's mistake.

In Patent Document 2, since the alignment chip is used for the initial alignment of the marking, the alignment chip must be searched for.
Also in Patent Document 3, it is necessary to search for a reference chip first. The identification by the mark must be performed by image recognition. In particular, if the marked chip is near the outer periphery of the chip area, the identification is likely to be erroneous.

In addition, there is a problem that the correspondence between the coordinates when the electrical characteristics are measured by the prober device and the coordinates at the time of picking of the picking device after dicing cannot be accurately taken. As a result, the ranking may be wrong.
JP-A-4-262543 Japanese Patent Laid-Open No. 5-109842 Japanese Patent Laid-Open No. 9-50945

  The present invention has been made in view of the above-described circumstances, and can accurately correspond to the chip coordinates at the time of electrical characteristic measurement and picking, and can easily rank and improve the quality of the semiconductor device. It is an object of the present invention to provide a semiconductor device manufacturing apparatus and manufacturing method that are improved.

  One aspect of the present invention relates to an apparatus for manufacturing a semiconductor device in which electrical characteristics of a plurality of chips formed on a wafer are measured, and then the wafer is diced to pick the chips. A probe reference chip having electrical characteristics different from those of other chips among the plurality of chips and a picking reference chip having a pattern different from the other chips among the plurality of chips are provided on the wafer. A prober for measuring electrical characteristics of the plurality of chips; electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating a position of the probe reference chip in the wafer; A first memory for storing a pattern of the picking reference chip stored in association with a picking reference coordinate indicating a position of the picking reference chip in the wafer; and the plurality of the plurality of measurements measured by the prober unit A second memory in which electrical characteristics of the chip and coordinates indicating positions of the plurality of chips in the wafer are associated and stored; and electrical characteristics of the plurality of chips stored in the second memory A first chip specifying unit that specifies an electrical characteristic that matches the electrical characteristic of the probe reference chip, and the first chip specifying unit. If the first coordinates, which are the coordinates stored in the second memory in association with the electrical characteristics specified in the above, are different from the probe reference coordinates, the first coordinates are converted into the probe reference coordinates. A coordinate correction unit that converts coordinates other than the first coordinate among the coordinates stored in the second memory based on the coordinate conversion; and a pattern of the picking reference chip among the plurality of chips. A second chip specifying unit that specifies a chip having a pattern to be picked, and a picking reference setting in which the coordinates indicating the position of the chip specified by the second chip specifying unit are the picking reference coordinates stored in the first memory It consists of parts.

  In addition, the semiconductor device manufacturing apparatus for dicing the wafer and picking the chip after measuring the electrical characteristics of the plurality of chips formed on the wafer may include another chip among the plurality of chips on the wafer. A probe reference chip having different electrical characteristics and a picking reference chip having a pattern different from other chips among the plurality of chips, a prober unit for measuring electrical characteristics of the plurality of chips, and the plurality An image recognition unit for measuring the pattern of the chip, electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating the position of the probe reference chip in the wafer, and the picking reference in the wafer The picking reference chip stored in association with the picking reference coordinates indicating the position of the chip. A plurality of chips measured by the prober unit, and a plurality of chip patterns measured by the image recognition unit. Of the electrical characteristics of the plurality of chips stored in the second memory and the second memory stored in association with the coordinates indicating the positions of the plurality of chips in the memory, the electrical characteristics of the probe reference chip A first chip specifying unit that specifies an electrical characteristic that matches the characteristic; a second chip specifying unit that specifies a chip having a pattern that matches the pattern of the picking reference chip among the plurality of chips; and the first chip When the first coordinates which are the coordinates stored in the second memory in association with the electrical characteristics specified by the specifying unit are different from the probe reference coordinates, The first coordinate is transformed into the probe reference coordinate, the coordinates other than the first coordinate among the coordinates stored in the second memory are transformed based on the coordinate transformation, and the second When the second coordinate, which is the coordinate stored in the second memory in association with the pattern specified by the chip specifying unit, is different from the picking reference coordinate, the second coordinate is converted into the picking reference coordinate. In addition, the coordinate correction device is configured to perform coordinate conversion of coordinates other than the second coordinate among the coordinates stored in the second memory based on the coordinate conversion.

  By doing as described above, the correspondence between the chip coordinates at the time of electrical characteristic measurement and picking can be accurately taken. Furthermore, the quality of the semiconductor device can be improved by simply ranking.

  The probe reference chip and the picking reference chip may be the same chip.

  According to the present invention, it is possible to accurately take correspondence between chip coordinates at the time of electrical characteristic measurement and picking, and it is possible to easily rank and improve the quality of the semiconductor device.

Example 1
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Constitution)
FIG. 1 is a diagram showing a configuration of a wafer used in the present invention. A normal chip 2, a probe reference chip 3, and a picking reference chip 4 are formed on the wafer 1. The probe reference chip 3 and the picking reference chip 4 are formed in at least one place in the range where the chips in the wafer surface are formed.

  Usually, circuit wiring is provided on the chip 2. For example, in the enlarged view shown in FIG. 1, a MOSFET 5 is used, and wiring is made from each terminal of the MOSFET 5 to a pad 6 (drain pad), a pad 7 (source pad), and a pad 8 (gate pad).

  The probe reference chip 3 has pads formed at the same position as the normal chip 2 as shown in FIG. This is because the electrical characteristics are measured in the same way as with the chip 2.

  Further, the probe reference chip 3 is configured so that the circuit formed on the chip is different from that of the normal chip 2. That is, the probe reference chip 3 has different electrical characteristics from the normal chip 2. For example, in the case of FIG. 1, in the probe reference chip 3, both terminals of the resistance element 9 are wired to the pad 11 and the pad 12, and the resistance element 9 is not wired to the pad 12.

A special pattern is formed on the picking reference chip 4. For example, a figure or the like may be formed instead of a circuit.
FIG. 2 is a diagram showing the configuration of the semiconductor device manufacturing apparatus according to the present invention. The manufacturing apparatus manufactures a semiconductor device using the prober unit 21, the picking unit 22, the coordinate correction unit 23, and the like.

  The prober unit 21 performs a characteristic inspection of the chip formed on the wafer, and includes a tester unit that is an apparatus that generates an electrical signal and a position specifying device that specifies a chip to be inspected. The measurement electrode (probe card) of the prober is connected from the tester to the measurement cable.

  The position specifying device performs positioning for specifying the position of each chip on the wafer. For example, positioning is performed by a height sensor and a prober stage (having an XY mechanism), and an edge portion of the prober stage is detected by moving the prober stage in the X-axis and Y-axis directions. The XY coordinates of the detected edge part are recognized, and the center of the prober stage is calculated based on the recognized coordinates.

  Then, the wafer is placed on the prober stage and moved in the X-axis and Y-axis directions to obtain the height of the surface of the prober stage and the height of the wafer surface, and the edge portion of the wafer is detected from the difference. The wafer center and diameter coordinates are calculated using the edge portion of the wafer.

Further, in order to define the coordinates of the chip position on the wafer, the center of the probe card and the prober stage are aligned.
After calculating the center coordinates of the prober stage and the wafer, the distance (correction distance) between the center of the prober stage and the center of the wafer is calculated on the same coordinate plane.

  Based on the calculated prober stage center, wafer center, correction distance, wafer diameter, and chip size inputted in advance, the center coordinates of each chip arranged in the X-axis and Y-axis directions are determined.

Note that there is no limitation as long as the coordinates of each chip can be determined by methods other than those described above.
Next, in the final test (electrical characteristic measurement) using the prober unit 21, before dicing the chip with a dicer, the electrodes of the probe card and the terminals (pads) provided on the chip are matched, Measurement of physical characteristics. At this time, the electrical characteristics of each chip are sequentially measured based on the coordinates of each chip. Electrical characteristic data (electric characteristic information) as a measurement result is transferred to the coordinate correction unit 23 together with the coordinates of the corresponding chip, and processing for converting the measurement coordinates of each chip based on probe reference coordinates described later, Based on the characteristic measurement, classification is performed for each rank, and the processing result is recorded. In addition, since it is before performing fragmentation by a dicer, at the time of measuring the electrical characteristics of the chips, the coordinate position relationship between the chips is kept as designed.

  After the measurement, before cutting the wafer 1 into chips, mounting the wafer on a wafer sheet (adhesive plastic tape, etc.) and attaching it to the wafer ring, to make the wafer 1 into smaller chips Dicing (dividing into small pieces) with a dicer.

Next, the wafer 1 that is stuck to the wafer sheet and held by the wafer ring is set in the picking unit 22.
The picking unit 22 determines the wafer reference coordinates of the picking unit of the wafer 1 diced like the prober unit 21.

The picking reference chip 4 of the wafer 1 is detected by image recognition by the image recognition unit 24.
The image recognition unit 24 searches for picking reference data, which is a unique pattern at the picking reference coordinates of the picking reference chip 4 input in advance, by a method such as pattern matching. If it is not in the picking reference coordinates, the vicinity of the coordinates is searched, and if it is found in the vicinity, the coordinates detected by pattern matching described later are coordinate-converted to the picking reference coordinates.

  Next, a chip of a desired rank is picked from each chip held on the wafer ring. The picked chips are directly incorporated into a package, classified into ranks and rearranged on a tray or the like, or rearranged into different wafer shapes and picked and fixed on another wafer ring.

The coordinate correction unit 23 includes an input unit 25, an output unit 26, a control unit 27, and a storage unit 28.
The input unit 25 acquires chip information from the prober unit 21. The chip information includes coordinate information of chips formed on the wafer 1 measured by the prober unit 21 and electrical characteristic information obtained by measurement for each chip.

The output unit 26 acquires the calculation result of the control unit 27 and transfers it to the picking unit 22.
The control unit 27 performs processing based on the chip information acquired from the input unit 25. Further, a coordinate conversion process for converting the measurement coordinates of each chip measured by the prober unit 21 based on probe reference coordinates, which will be described later, and a classification process for classifying each rank based on electrical characteristic measurement are performed in the storage unit 28. Record.

The storage unit 28 includes a first memory and a second memory.
The first memory is associated with the electrical characteristics of the probe reference chip stored in association with the probe reference coordinates indicating the position of the probe reference chip in the wafer, and the picking reference coordinates indicating the position of the picking chip in the wafer. The picking reference chip pattern to be stored is stored.

The second memory stores the electrical characteristics of the plurality of chips measured by the prober and the coordinates indicating the positions of the plurality of chips in the wafer in association with each other.
In addition, the control unit 27 includes a first chip specifying unit that specifies an electric characteristic that matches the electric characteristic of the probe reference chip among the electric characteristics of the plurality of chips stored in the second memory, and among the plurality of chips. A second chip specifying unit that specifies a chip having a pattern that matches the pattern of the picking reference chip is provided.

  In addition, when the first coordinate which is the coordinate stored in the second memory and associated with the electrical characteristic specified by the first chip specifying unit is different from the probe reference coordinate, the control unit 27 determines the first coordinate. A coordinate correction unit is provided that converts the coordinates to the probe reference coordinates and converts the coordinates other than the first coordinates among the coordinates stored in the second memory based on the coordinate conversion. In addition, a picking reference setting unit is provided that uses coordinates indicating the position of the chip specified by the second chip specifying unit as picking reference coordinates stored in the first memory.

  Although not shown, the prober unit 21 can be controlled by connecting the prober unit 21 and the coordinate correction unit 23 with a control line. For example, the prober unit 21 is notified of the chip information capture timing.

(Process description)
FIG. 3 is a diagram illustrating a manufacturing process of a semiconductor device.
In step S1, the normal chip 2, the probe reference chip 3, and the picking reference chip 4 are formed on the wafer 1 by the previous process.

In step S <b> 2, the electrical characteristics of each chip are measured based on the measurement coordinates of each chip measured by the prober unit 21, and the chip information is transferred to the coordinate correction unit 23.
Here, it does not matter if the picking reference chip is not measured. However, bringing the probe card measurement pin into contact with a position where there is no pad causes the probe card to hurt, so a dummy pad is provided for measurement.

The coordinate correction unit 23 executes the following steps S3 to S5 to correct the coordinates.
In step S3, it is determined whether the electrical characteristic data of the measurement coordinates of the probe reference chip 3 measured by the prober unit 21 is within the range indicated by the probe reference data (electrical characteristics) preset in the first memory of the storage unit 28. judge. As a result of the determination, if the electrical characteristic data of the measurement coordinates of the probe reference chip 3 is within the range indicated by the probe reference data, the process proceeds to step S6. If it is not within the range, the process proceeds to step S4 to execute coordinate conversion. If the first coordinates, which are the coordinates associated with the electrical characteristics specified by the first chip specifying unit and stored in the second memory, are different from the probe reference coordinates, the first coordinates are converted into probe reference coordinates. . In addition, coordinates other than the first coordinate among the coordinates stored in the second memory are converted based on the coordinate conversion.

Here, in the chip information acquired from the prober unit 21, the electrical characteristic measurement result is associated with the measurement coordinates measured by the prober unit 21.
FIG. 4A shows the data structure of chip information. In the case of FIG. 4A, (1, 3) (1, 4)... (10, 8) are assigned as measurement coordinates to each chip formed on the wafer 1 by the prober unit 21. Moreover, the electrical characteristic measurement result (electrical characteristic data: measurement items 1) of the chip measured by the prober unit 21 is associated with each measurement coordinate.

FIG. 4B shows the measurement coordinates of each chip of the wafer 1.
If the electrical characteristic data corresponding to the measurement coordinates (2, 8) is within the range indicated by the probe reference data, the process proceeds to step S6. That is, if the actual position of the probe reference chip 3 on the wafer 1 matches the position indicated by the measurement coordinates of the measured probe chip, coordinate conversion is not executed.

  When the electrical characteristic data corresponding to the measurement coordinates (2, 8) is not within the range indicated by the probe reference data, the process proceeds to step S4. That is, if the actual position of the probe reference chip 3 on the wafer 1 does not match the position indicated by the measurement coordinates of the measured probe chip, coordinate conversion is executed.

In step S4, an electrical characteristic data in the chip information is searched for within the probe reference data range.
In step S5, the deviation between the wafer reference coordinates and the measurement coordinates is corrected.

  Search for measurement coordinates within the probe reference data range from the measurement coordinates. FIG. 5 shows a case where the measurement range of the measurement coordinates of the prober unit 21 is the measurement range 51 (broken line) and the measurement range 52 (solid line thick). Further, (2, 9) indicates the coordinates where the probe reference data of the measurement range 52 should be, and (3, 7) indicate the coordinates where the probe reference data of the measurement range 51 should be.

6A and 6B are tables comparing the measurement coordinates of the measurement ranges 51 and 52 with the wafer reference coordinates.
In the case of the measurement range 51, since the start coordinates are shifted from the start coordinates (1, 3) of the actual wafer coordinates (wafer reference coordinates) recorded in advance, the wafer reference coordinates (2, 2) are sequentially measured. As a result, the coordinates of the probe reference chip become (3, 7) in the wafer reference coordinates. However, since there is no probe reference data at the coordinates (3, 7) and the wafer reference coordinates (2, 8) with the probe reference chip are not measured, the measurement is executed again.

  In the case of the measurement range 52, since the start coordinates (1, 3) of the actual wafer coordinates (wafer reference coordinates) recorded in advance are shifted from the start coordinates (1, 4), the measurement is sequentially performed. As a result, the coordinates of the probe reference chip become (2, 9) in the wafer reference coordinates. However, there is no probe reference data at the coordinates (2, 9) corresponding to the measurement coordinates (2, 8). The wafer reference coordinates (2, 8) where the probe reference chip is located are (2, 7) in the measurement coordinates, so that it is determined that the coordinates are shifted, and the coordinates are corrected.

  In the coordinate correction, coordinates having data within the range of probe reference data of measurement coordinates are moved to coordinates of probe reference chips of wafer reference coordinates. At this time, other measurement coordinates are also moved in the same direction.

  In the measurement coordinates, when (mx-2, my + 1) of the wafer reference coordinates is recognized as the probe reference chip at the time of measurement, (mx-2, my + 1) is the coordinates (mx, my) of the probe reference chip of the wafer reference coordinates. Will be converted to

  At this time, if the effective chip range is (1 ≦ x ≦ nx, 1 ≦ y ≦ ny), the measurement coordinates (1, 1) are converted to (3, 0). Since the y coordinate is 0, it is out of the effective chip range, so the measurement result is invalidated. On the other hand, when it is (0, ny + 1), it becomes (2, ny) and is within the effective chip range, so that the measurement result is valid.

When the difference between the probe reference coordinates of the wafer reference coordinates and the probe reference coordinates of the measurement coordinates is large, the electrical characteristic measurement is performed again.
In step S6, the wafer 1 is diced by a dicer. For example, a wafer having thousands of chips is cut into small pieces. Thereafter, the diced wafer 1 is set in the picking unit 22.

  In step S7, like the prober unit 21, after determining the wafer reference coordinates of the picking unit 22 of the diced wafer 1, the image recognition unit 24 detects the picking reference chip 4 of the wafer 1 by image recognition.

  The image recognition unit 24 searches for coordinates where a special pattern is formed. First, the image recognition unit 24 performs pattern matching on the coordinates corresponding to the picking reference coordinates stored in the first memory and the patterns of the first memory corresponding to the picking reference coordinates of the picking reference chip 4 input in advance. Search by the method of. If it is not in the picking reference coordinates, the vicinity of the coordinates is searched, and if it is found in the vicinity, the detected coordinates are converted into coordinates.

In the case of the wafer 1 in FIG. 4, since it is formed at the wafer coordinates (5, 6), the vicinity of the coordinates (5, 6) is searched.
Coordinate transformation is executed when the picking reference chip is found. For example, as shown in FIG. 8, when it is recognized that there is a picking reference coordinate at (4,5) of the wafer reference coordinate, coordinate conversion is performed to change the coordinate from (4,5) to (5,6). In addition to conversion, coordinate conversion is performed by adding 1 in the x-axis direction and adding 1 in the y-axis direction in the same manner as the conversion from (4, 5) to (5, 6). Coordinate transformation is performed on the reference in the same manner as the coordinate transformation shown in step S5.

In step S8, rank determination is performed on the database. Note that rank determination may be performed in a process prior to S8.
In the diagram shown in FIG. 7A, corresponding electrical measurement data is associated with converted measurement coordinates or conversion coordinates that do not require conversion. In FIG. 7B, a table for determining a rank is prepared, and a rank is assigned to each conversion coordinate based on this table. In FIG. 7B, an electrical characteristic range is set in the storage unit 28 for each measurement item. In measurement item 1 of rank A, H1 to H2 are set as the electric characteristic range, H3 to H4 are set in measurement item 2, and H5 to H6 are set in measurement item 3. Similarly, ranks B and C are set.

A special rank is given to the electrical characteristics of the probe reference chip.
When searching for a reference chip, this dedicated rank may be searched if a rank is assigned in advance.

  In step S9, picking is performed for each rank corresponding to the transformed coordinates, and the process proceeds to the next process (wire bonding, packaging, visual inspection, packaging, product characteristic inspection, etc.).

In this way, the ranking quality can be easily improved without adding a new mechanism.
In addition, the probe reference chip may include any circuit as long as it outputs a characteristic that cannot occur due to a characteristic defect with respect to the normal chip.

The probe reference chip and the picking reference chip may be used in common. In that case, imposition loss is reduced.
The two types of reference chips may be used in common with a process confirmation dummy chip. In that case, there is no imposition loss.

A plurality of the two types of reference chips may be arranged. In that case, the probability that a recognition chip remains is high for a wafer defect, and the reliability increases.
The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

It is a figure which shows the structure of the wafer of this invention. It is a block diagram which shows the structure of this invention. It is a flowchart which shows the process of this invention. (A) It is a figure which shows the structure of the chip | tip information which the prober part measured. (B) It is a figure which shows a wafer coordinate. It is a figure which shows the relationship between a wafer coordinate and a measurement coordinate. (A) It is a table | surface which shows the measurement coordinate of the measurement coordinate 51, and an electrical property. (B) It is a table | surface which shows the measurement coordinate of the measurement coordinate 52, and an electrical property. (A) It is a table | surface which shows the relationship between a conversion coordinate and a rank. (B) It is a table which shows the conditions of the measurement item of a rank and an electrical property. It is the figure which showed the relationship at the time of converting a measurement coordinate into a wafer reference coordinate.

Explanation of symbols

1 wafer, 2 normal chip, 3 probe reference chip, 4 picking reference chip,
5 MOSFET,
6, 7, 8 pads,
9 resistance elements,
10, 11, 12 pads,
21 prober section, 22 picking section, 23 coordinate correction section,
24 image recognition unit,
25 input unit, 26 output unit, 27 control unit, 28 storage unit, 29 recording medium,

Claims (5)

A semiconductor device manufacturing apparatus that performs electrical property measurement of a plurality of chips formed on a wafer, and then dices the wafer and picks the chips.
The wafer is provided with a probe reference chip having electrical characteristics different from other chips among the plurality of chips and a picking reference chip having a pattern different from other chips among the plurality of chips,
A prober unit for measuring electrical characteristics of the plurality of chips;
The electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating the position of the probe reference chip in the wafer and the picking reference coordinates indicating the position of the picking reference chip in the wafer A first memory in which a pattern of the picking reference chip to be stored is stored;
A second memory in which electrical characteristics of the plurality of chips measured by the prober and coordinates indicating positions of the plurality of chips in the wafer are stored in association with each other;
A first chip specifying unit that specifies an electric characteristic that matches an electric characteristic of the probe reference chip among the electric characteristics of the plurality of chips stored in the second memory;
When the first coordinate which is the coordinate stored in the second memory and associated with the electrical characteristic specified by the first chip specifying unit is different from the probe reference coordinate, the first coordinate is set as the probe reference. A coordinate correction unit that converts the coordinates other than the first coordinate among the coordinates stored in the second memory, based on the coordinate conversion,
A second chip specifying unit for specifying a chip having a pattern that matches the pattern of the picking reference chip among the plurality of chips;
A picking reference setting unit that uses the coordinates indicating the position of the chip specified by the second chip specifying unit as the picking reference coordinates stored in the first memory;
An apparatus for manufacturing a semiconductor device. A semiconductor device manufacturing apparatus that performs electrical property measurement of a plurality of chips formed on a wafer, and then dices the wafer and picks the chips.
The wafer is provided with a probe reference chip having electrical characteristics different from other chips among the plurality of chips and a picking reference chip having a pattern different from other chips among the plurality of chips,
A prober unit for measuring electrical characteristics of the plurality of chips;
An image recognition unit for measuring a pattern of the plurality of chips;
The electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating the position of the probe reference chip in the wafer and the picking reference coordinates indicating the position of the picking reference chip in the wafer A first memory in which a pattern of the picking reference chip to be stored is stored;
The electrical characteristics of the plurality of chips measured by the prober unit and the patterns of the plurality of chips measured by the image recognition unit correspond to coordinates indicating the positions of the plurality of chips in the wafer. A second memory attached and stored;
A first chip specifying unit that specifies an electric characteristic that matches an electric characteristic of the probe reference chip among the electric characteristics of the plurality of chips stored in the second memory;
A second chip specifying unit for specifying a chip having a pattern that matches the pattern of the picking reference chip among the plurality of chips;
When the first coordinate which is the coordinate stored in the second memory and associated with the electrical characteristic specified by the first chip specifying unit is different from the probe reference coordinate, the first coordinate is set as the probe reference. Converting the coordinates into coordinates, converting coordinates other than the first coordinates among the coordinates stored in the second memory based on the coordinate conversion, and
When the second coordinate which is the coordinate stored in the second memory in association with the pattern specified by the second chip specifying unit is different from the picking reference coordinate, the second coordinate is changed to the picking reference coordinate. A coordinate correction device that converts the coordinates other than the second coordinates among the coordinates stored in the second memory based on the coordinate conversion;
An apparatus for manufacturing a semiconductor device.   3. The semiconductor device manufacturing apparatus according to claim 1, wherein the probe reference chip and the picking reference chip are the same chip. After measuring electrical characteristics of a plurality of chips formed on a wafer, the method for manufacturing a semiconductor device, wherein the wafer is diced to pick the chips,
Providing the wafer with a probe reference chip having electrical characteristics different from other chips among the plurality of chips and a picking reference chip having a pattern different from other chips among the plurality of chips;
The electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating the position of the probe reference chip in the wafer and the picking reference coordinates indicating the position of the picking reference chip in the wafer Storing the pattern of the picking reference chip stored in a first memory;
Measuring the electrical characteristics of the plurality of chips, and storing the electrical characteristics of the plurality of chips in association with coordinates indicating the positions of the plurality of chips in a second memory;
Identifying electrical characteristics that match electrical characteristics of the probe reference chip among electrical characteristics of the plurality of chips stored in the second memory; and
When the first coordinates, which are the coordinates associated with the specified electrical characteristics and stored in the second memory, are different from the probe reference coordinates, the first coordinates are converted to the probe reference coordinates. Converting the coordinates stored in the second memory other than the first coordinates based on the coordinate conversion;
Dicing the wafer;
A step of designating a desired chip;
Identifying a chip having a pattern that matches the pattern of the picking reference chip among the plurality of chips;
Setting the coordinates indicating the position of the identified chip as the picking reference coordinates stored in the first memory;
Picking a desired chip based on coordinates indicating the position of the identified chip;
A semiconductor device manufacturing apparatus comprising: After measuring electrical characteristics of a plurality of chips formed on a wafer, the method for manufacturing a semiconductor device, wherein the wafer is diced to pick the chips,
Providing the wafer with a probe reference chip having electrical characteristics different from other chips among the plurality of chips and a picking reference chip having a pattern different from other chips among the plurality of chips;
The electrical characteristics of the probe reference chip stored in association with probe reference coordinates indicating the position of the probe reference chip in the wafer and the picking reference coordinates indicating the position of the picking reference chip in the wafer Storing the pattern of the picking reference chip stored in a first memory;
Measuring the electrical characteristics of the plurality of chips, and storing the electrical characteristics of the plurality of chips in association with coordinates indicating the positions of the plurality of chips in a second memory;
Identifying electrical characteristics that match electrical characteristics of the probe reference chip among electrical characteristics of the plurality of chips stored in the second memory; and
When the first coordinates, which are the coordinates associated with the specified electrical characteristics and stored in the second memory, are different from the probe reference coordinates, the first coordinates are converted to the probe reference coordinates. Converting the coordinates stored in the second memory other than the first coordinates based on the coordinate conversion;
Dicing the wafer;
A step of designating a desired chip;
The patterns of the plurality of chips are measured, and the patterns of the plurality of chips, the electrical characteristics of the plurality of chips, and coordinates indicating the positions of the plurality of chips are associated and stored in a second memory. Process,
Identifying a pattern that matches the pattern of the picking reference chip among the patterns of the plurality of chips stored in the second memory;
When the second coordinate, which is the coordinate stored in the second memory in association with the specified pattern, is different from the picking reference coordinate, the second coordinate is converted to the picking reference coordinate, Converting the coordinates other than the second coordinates among the coordinates stored in the second memory based on the coordinate conversion;
Picking the desired chip based on the coordinates stored in the second memory;
A method for manufacturing a semiconductor device.