JP2009130679A - Solid-state image sensor, method of driving solid-state image sensor, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To more surely transfer charge, by a transfer transistor, from a photoelectric conversion element to a gate input part of an amplification transistor. <P>SOLUTION: In a CMOS image sensor, in which unit pixels are disposed in a matrix shape, including a photoelectric conversion element, a transfer transistor, a reset transistor, an amplification transistor and a selection transistor, the timing to bring a select signal SEL into an active state is set to after a reset signal RST is shifted from the active state to an inactive state and before a potential at a gate input part of the amplification transistor is read as a reset level, thereby enlarging a potential difference between under a gate of a transfer transistor 22 and a node FD when the relevant transfer transistor 22 is turned on. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a solid-state imaging device driving method, and an imaging apparatus, and more particularly to a solid-state imaging device having an amplification function for each unit pixel, the solid-state imaging device driving method, and an imaging apparatus using the solid-state imaging device. .

  As a solid-state imaging device having an amplification function for each unit pixel, a CMOS (or MOS-type) solid-state imaging device (hereinafter referred to as “CMOS image sensor”) that can be manufactured by a process similar to a CMOS integrated circuit is known. (For example, refer to Patent Document 1).

  The CMOS image sensor can easily make an active structure having an amplification function for each unit pixel by a miniaturization technique associated with the CMOS process, and can drive a pixel array unit or a pixel array unit. A peripheral circuit unit such as a signal processing circuit that processes a signal output from each pixel can be integrated on the same chip (substrate) as the pixel array unit.

  FIG. 12 shows an example of the configuration of the unit pixel. As shown in FIG. 12, the unit pixel 100 has a configuration including a photoelectric conversion element 101, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105.

  FIG. 13 shows a timing relationship between the selection signal SEL for driving the selection transistor 105, the reset signal RST for driving the reset transistor 103, and the transfer signal TRF for driving the transfer transistor 102.

  As is apparent from FIG. 13, the selection signal SEL is in an active (high level) state during a period from time t11 to time t18. The reset signal RST becomes active during the period from time t12 to time t13 within the active period of the selection signal SEL. The transfer signal TRF becomes active in a period from time t15 to time t16 after time t13 in the active period of the selection signal SEL.

  Next, based on the timing chart of FIG. 13, the operation of the unit pixel 100 will be described using the potential diagrams of FIGS. 14 to 17.

  When the selection transistor 105 is turned on at time t11 and the unit pixel 100 is selected, when the reset transistor 103 is turned on at time t12, the potential of the node (floating diffusion) FD connected to the gate electrode of the amplification transistor 104 is changed. Reset to power supply voltage Vdd. At this time, the potential of the pixel output line 110 is also high (see FIG. 14).

  When the reset transistor 103 is turned off at time t <b> 13, the potential of the node FD and the potential of the pixel output line 110 are lowered by coupling due to the parasitic capacitance of the reset transistor 103. In this state, the potential of the node FD is read to the pixel output line 110 through the amplification transistor 104 and the selection transistor 105 as a reset level at the timing of time t14 (see FIG. 15).

  Next, when the transfer transistor 102 is turned on at time t15, the charge accumulated in the photoelectric conversion element 101 is read to the node FD through the transfer transistor 102. As a result, the potential of the node FD decreases (see FIG. 16). Then, after the transfer transistor 102 is turned off at time t16, the potential of the node FD is read as a signal level to the pixel output line 110 through the amplification transistor 104 and the selection transistor 105 at the timing of time t17 (see FIG. 17).

Japanese Patent Laying-Open No. 2005-311932 (in particular, paragraphs 0024 to 0027 and FIG. 3)

  In the prior art described in Patent Document 1 described above, since the drive timing is such that the selection transistor 105 is turned on before the reset transistor 103 is turned on, the reset transistor 103 is turned off due to the parasitic capacitance of the reset transistor 103. Due to the coupling, the potential of the node FD decreases, and the potential becomes shallower than the level (dashed line) corresponding to the power supply voltage Vdd (see FIG. 15). That the potential of the node FD decreases means that the potential difference between the gate of the transfer transistor 102 and the node FD when the transfer transistor 102 is turned on decreases.

  When the transfer transistor 102 is turned on and the potential difference between the gate of the transfer transistor 102 and the node FD when the transfer transistor 102 is turned on is small, the charge from the photoelectric conversion element 101 to the node FD by the transfer transistor 102 May not be able to be completely transferred, and charge may remain unread (transfer remaining). If there is an unread charge, the information of the current frame image will remain in the next frame.For example, when a moving subject is imaged, the current frame image will remain in the next frame. This is a problem from the viewpoint of image quality.

  Therefore, the present invention provides a solid-state imaging device capable of more reliably transferring charges from the photoelectric conversion element by the transfer transistor to the gate input node of the amplification transistor, a method for driving the solid-state imaging element, and the solid-state imaging element. An object is to provide an imaging apparatus used.

  To achieve the above object, according to the present invention, a plurality of unit pixels including a photoelectric conversion element, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor are arranged, the unit pixel is selected by the selection transistor, and the reset transistor In the solid-state imaging device in which the gate input node of the amplification transistor is reset by the transfer transistor and charges are transferred from the photoelectric conversion element to the gate input node of the amplification transistor by the transfer transistor, a reset signal for driving the reset transistor is activated. After the transition of the reset signal from the active state to the inactive state or within the active period of the reset signal, the selection signal for driving the selection transistor is made active and the selection transistor Adopts a configuration in which the active state of the transfer signal for driving the transfer transistor in the active period of the data.

  In the solid-state imaging device having the above-described configuration and the imaging apparatus using the solid-state imaging device, the timing for setting the selection signal to the active state is after the reset signal transitions from the active state to the inactive state (or during the reset period of the reset signal) ), The potential of the gate input node of the amplification transistor, which is lowered by the coupling due to the parasitic capacitance of the reset transistor when the reset transistor is turned off, is set to the parasitic capacitance of the selection transistor at a timing when the selection transistor is subsequently turned on. The potential at the gate input node of the amplifying transistor can be raised by the coupling due to. This increases the potential difference between the gate of the transfer transistor and the gate input node of the amplification transistor when the transfer transistor is turned on.

  According to the present invention, since the potential difference between the gate of the transfer transistor and the gate input node of the amplification transistor when the transfer transistor is turned on can be increased, the charge from the photoelectric conversion element to the gate input node of the amplification transistor can be increased. Can be transferred more reliably.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a system configuration of a solid-state imaging device to which the present invention is applied. Here, the case of a CMOS image sensor, for example, will be described as an example of the solid-state imaging device.

[System configuration]
In FIG. 1, a pixel array unit 11, a vertical drive circuit 12, a shutter drive circuit 13, a CDS (Correlated Double Sampling) circuit 14, a horizontal drive circuit (column selection circuit) 15, an AGC (Automatic Gain Control) A gain control circuit 16, an A / D (analog / digital) conversion circuit 17, a timing generator 18, and the like are integrated on a substrate (chip) 19.

  Hereinafter, a semiconductor chip in which the pixel array unit 11 and its peripheral circuit units (12 to 18) are mounted on the substrate 19 is referred to as a sensor chip 10.

  In the pixel array unit 11, unit pixels including one or a plurality of photoelectric conversion elements (hereinafter sometimes simply referred to as “pixels”) are arranged in a two-dimensional array. A pixel output line for outputting a pixel signal and various control lines for driving each pixel are wired.

  The unit pixel includes a photoelectric conversion element that photoelectrically converts incident light and stores it, a reading unit that reads signal charges from the photoelectric conversion element to a floating diffusion region (floating diffusion region), a reset unit that resets the floating diffusion region, and A device including at least amplifying means for amplifying the signal charge read to the floating diffusion region as a component is used. A specific circuit example of this type of unit pixel will be described later.

  The vertical drive circuit 12 selects each pixel of the pixel array unit 11 as a read row in units of rows, and supplies a drive signal for performing a signal read operation and a reset operation to the pixel array unit 11. Similarly to the vertical drive circuit 12, the shutter drive circuit 13 selects each pixel of the pixel array unit 11 in units of rows. In the shutter drive circuit 13, the exposure time (accumulation time) of the photoelectric conversion element can be adjusted by adjusting the drive interval with the vertical drive circuit 12.

  The CDS circuit 14 is arranged for each pixel column or a plurality of pixel columns in the pixel array unit 11, and performs CDS processing on signals read from the row selected by the vertical drive circuit 12. Specifically, the fixed level noise for each pixel is removed (cancelled) by receiving the reset level and the signal level from each pixel and taking the difference between the two.

  The horizontal driving circuit 15 sequentially selects the signals stored for each column after the CDS processing in the CDS circuit 14. The AGC circuit 16 amplifies the signal of the column selected by the horizontal drive circuit 15 with an appropriate gain. The A / D conversion circuit 17 converts the analog signal amplified by the AGC circuit 16 into a digital signal and outputs it to the outside of the chip 19.

  The timing generator 18 generates various timing signals and drives each of the vertical drive circuit 12, the shutter drive circuit 13, the CDS circuit 14, the horizontal drive circuit 15, the AGC circuit 16, and the A / D conversion circuit 17.

  The above configuration is an example of a CMOS image sensor and is not limited to this. That is, a configuration without the A / D conversion circuit 17 in the sensor chip 10, a configuration with each pixel column, a configuration with only one CDS circuit 14, a CDS circuit 14, an AGC circuit 16, etc. A configuration having a plurality of output systems including

  FIG. 2 shows an example of a specific configuration of the pixel array unit 11 and its peripheral circuit unit. In FIG. 2, the same parts as those in FIG. Here, for simplification of the drawing, the pixel array of the pixel array unit 11 is shown as a pixel array of 2 rows and 3 columns. In FIG. 2, the arrangement relationship of the CDS circuit 14 and the horizontal drive circuit 15 with respect to the pixel array unit 11 is upside down from the case of FIG.

(Pixel array part)
In the pixel array unit 11, the unit pixels 20 are two-dimensionally arranged in a matrix, and a pixel output line 31 is wired for each column with respect to the matrix-like pixel arrangement, and various control lines, Specifically, three control lines of a transfer signal line 32, a reset signal line 33, and a selection signal line 34 are wired. The pixel array unit 11 is further provided with power supply voltage supply lines 35 that supply the power supply voltage Vdd to each of the unit pixels 20 in a grid pattern, for example.

(Unit pixel)
The unit pixel 20 has a four-transistor configuration including a photoelectric conversion element 21, a transfer transistor 22, an amplification transistor 23, a reset transistor 24, and a selection transistor 25. The transfer transistor 22, the amplification transistor 23, the reset transistor 24, and the selection transistor 25 are, for example, N-type MOS transistors. However, the present invention is not limited to the N-type MOS transistor, and a P-type MOS transistor can also be used.

  The photoelectric conversion element 21 has an anode electrode connected to the ground, photoelectrically converts incident light into charges of electrons (or holes) corresponding to the amount of light, and accumulates the light.

  In the transfer transistor 22, the source electrode is connected to the cathode electrode of the photoelectric conversion element 21, the gate electrode is connected to the transfer signal line 32, and the drain electrode is connected to a node (floating diffusion) FD that is a gate input portion of the amplification transistor 23. . The transfer transistor 22 is turned on when the transfer signal TRF applied to the gate electrode through the transfer signal line 32 becomes active (high level / power supply voltage Vdd), and charges accumulated in the photoelectric conversion element 21 are transferred to the node FD. Forward to.

  The amplification transistor 23 has a gate electrode connected to the node FD, a drain electrode connected to the power supply voltage supply line 35, and a source electrode connected to the drain electrode of the selection transistor 25. The amplification transistor 23 outputs a voltage corresponding to the charge transferred from the photoelectric conversion element 21 to the node FD by the transfer transistor 22 to the source side.

  The reset transistor 24 has a source electrode connected to the node FD, a drain electrode connected to the power supply voltage supply line 35, and a gate electrode connected to the reset signal line 33. The reset transistor 24 is turned on when a reset signal RST applied to the gate electrode through the reset signal line 33 becomes active, and resets the potential of the node FD to the potential of the power supply voltage supply line 35 (power supply voltage Vdd).

  The selection transistor 25 has a drain electrode connected to the source electrode of the amplification transistor 23, a gate electrode connected to the selection signal line 34, and a source electrode connected to the pixel output line 31. The selection transistor 25 is turned on when the selection signal SEL supplied to the gate electrode through the selection signal line 34 is activated, and conducts between the source electrode of the amplification transistor 23 and the pixel output line 31.

  The pixel output lines 31 are connected in parallel with the unit pixels 20 corresponding to the number of rows. One end of the pixel output line 31 is connected to the input end of each column of the CDS circuit 14. The other end of the pixel output line 31 is grounded via a transistor 36.

  In the transistor 36, the gate electrode is biased at a constant voltage by a bias power source 37 so as to operate in a saturation region so as to supply a certain current. That is, the transistor 36 is a constant current transistor that operates as a constant current source.

  The constant current transistor 36 supplies a constant current to the amplification transistor 23 of the unit pixel 20 in the selected row, and operates the amplification transistor 23 as a source follower. As a result, a voltage having a certain potential difference from the gate potential of the amplification transistor 23, that is, the potential of the node FD is read out to the pixel output line 31.

  In this example, the unit pixel 20 has a configuration in which the selection transistor 25 is provided between the source electrode of the amplification transistor 23 and the pixel output line 31. However, the selection transistor 25 is connected to the power supply voltage supply line 36. And the drain electrode of the amplification transistor 23 may be provided.

(Vertical drive circuit)
The vertical drive circuit 12 includes a vertical selection circuit 121 and a logic circuit 122 at the subsequent stage.

  The vertical selection circuit 121 mainly includes, for example, a shift register including unit circuits (shift stages) having the number of stages corresponding to the number of rows of the pixel array unit 11, and sequentially outputs the shift pulse SP from each shift stage of the shift register.

  The logic circuit 122 includes three 2-input AND circuits 1221, 1222, and 1223 for each row of the pixel array unit 11, and includes a shift pulse SP that is sequentially output from the vertical selection circuit 121 and the timing generator 18 (see FIG. 1). The above-mentioned transfer signal TRF, reset signal RST, and selection signal SEL supplied from are input.

  Each of the AND circuits 1221, 1222, and 1223 receives the shift pulse SP supplied from the vertical selection circuit 121 as one input. The AND circuit 1221 receives the transfer signal TRF as the other input, and supplies the transfer signal TRF to each pixel 20 in the selected row when the shift pulse SP is active.

  The AND circuit 1222 receives the reset signal RST as the other input, and supplies the reset signal RST to each pixel 20 in the selected row when the shift pulse SP is active. The AND circuit 1223 receives the selection signal SEL as the other input, and supplies the selection signal SEL to each pixel 20 in the selected row when the shift pulse SP is active.

(Pixel drive signal)
FIG. 3 shows the timing of the drive signal for driving the unit pixel 20, more specifically, the selection signal SEL for driving the selection transistor 25, the reset signal RST for driving the reset transistor 23, and the transfer signal TRF for driving the transfer transistor 22. An example of the relationship is shown.

  As is clear from FIG. 3, the reset signal RST is in an active (high level / power supply voltage Vdd) state during a period from time t1 to time t2. The selection signal SEL becomes active in a period from time t3 to time t8 after time t2. The transfer signal TRF becomes active during the period from time t5 to time t6 within the active period of the selection signal SEL.

  As described above, the timing for setting the selection signal SEL to the active state is set after the reset signal RST transitions from the active state to the inactive state and before the potential of the node FD is read as the reset level. However, this is a feature of this embodiment.

(Circuit operation)
Next, based on the timing chart of FIG. 3, the operation of the unit pixel 20 will be described using the potential diagrams of FIGS. 4 to 7.

  When the reset transistor 23 is turned on at time t1, the gate input portion of the amplification transistor 104, that is, the potential of the node FD is reset to the power supply voltage Vdd (see FIG. 4). Next, after the reset transistor 23 is turned off at time t2, the selection transistor 25 is turned on at time t3.

  At this time, at the timing when the reset transistor 23 is turned off, the potential of the node FD decreases due to coupling due to the parasitic capacitance of the reset transistor 23, and the potential temporarily becomes shallower than the level corresponding to the power supply voltage Vdd. Is turned on, the potential of the node FD rises due to the coupling due to the parasitic capacitance of the selection transistor 25, and the potential becomes deeper than the level (one-dot chain line) that becomes shallower due to the coupling of the reset transistor 23 (see FIG. 5).

  Here, the increase in the potential of the node FD means that the potential difference between the gate of the transfer transistor 22 and the node FD when the transfer transistor 22 is turned on increases and the potential difference increases.

  In a state where the selection transistor 25 is turned on and the unit pixel 20 is selected, the potential of the node FD is read as a reset level to the pixel output line 31 through the amplification transistor 24 and the selection transistor 25 at the timing of time t4. The voltage corresponding to the reset level read out to the pixel output line 31 is read into the subsequent CDS circuit 14 (see FIGS. 1 and 2).

  Next, when the transfer transistor 22 is turned on at time t5, the photoelectric conversion element 21 performs photoelectric conversion, and the charge accumulated in the photoelectric conversion element 21 is read to the node FD through the transfer transistor 22 (see FIG. 6). .

  At this time, the potential difference between the node FD and the gate of the transfer transistor 22 when the transfer transistor 22 is turned on when the potential of the node FD increases due to the coupling due to the parasitic capacitance of the selection transistor 25. Since the potential difference is large and the potential difference is large, it is possible to perform transfer with little unread (transfer residue) when the charge is transferred from the photoelectric conversion element 21 to the node FD by the transfer transistor 22.

  Then, after the transfer transistor 22 is turned off at time t6, the potential of the node FD is read as a signal level to the pixel output line 31 through the amplification transistor 24 and the selection transistor 25 at time t7 (see FIG. 7).

  The voltage corresponding to the signal level read out to the pixel output line 31 is read into the CDS circuit 14 at the subsequent stage. The CDS circuit 14 performs a CDS process that takes the difference between the reset level that has been read in advance and the signal level that has been read this time, so that fixed pattern noise for each unit pixel 20, more specifically, the amplification transistor 24. The fixed pattern noise generated due to variations in the threshold voltage Vth or the like is canceled.

  The pixel signals after CDS processing (original signal levels with fixed pattern noise canceled) held in the CDS circuit 14 for each pixel column are sequentially selected by the horizontal drive circuit 15 in FIG. 141 is output to a subsequent circuit such as the AGC circuit 16 (see FIG. 1).

[Operational effects of this embodiment]
As described above, in the CMOS image sensor in which the unit pixels 20 including the photoelectric conversion element 21, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 are arranged in a matrix, the selection signal SEL is activated. By setting the timing after the reset signal RST transitions from the active state to the inactive state and before reading the potential of the gate input part (node FD) of the amplification transistor 24 as the reset level, An effect can be obtained.

  In the conventional technique of the driving timing when the selection transistor 25 is turned on before the reset transistor 23 is turned on, even if the potential of the node FD is increased by the coupling due to the parasitic capacitance of the selection transistor 25 at the timing when the selection transistor 25 is turned on. The potential of the node FD is reset to the power supply voltage Vdd by the reset operation by the reset transistor 23, and the potential of the node FD is lowered by the coupling due to the parasitic capacitance of the reset transistor 23 at the timing when the reset transistor 23 is subsequently turned off.

  On the other hand, by taking a drive timing to activate the selection signal SEL after the reset signal RST transitions from the active state to the inactive state, the potential of the node FD lowered by the coupling due to the parasitic capacitance of the reset transistor 23 is reduced. Thereafter, at the timing when the selection transistor 25 is turned on, the potential of the node FD can be raised by the coupling due to the parasitic capacitance of the selection transistor 25.

  When the potential of the node FD increases, the potential difference (potential difference) between the gate of the transfer transistor 22 and the node FD when the transfer transistor 22 is turned on is changed before the reset transistor 23 is turned on. Therefore, when the charge transfer from the photoelectric conversion element 21 to the node FD by the transfer transistor 22 is performed, transfer with little unread reading (transfer remaining) becomes possible. That is, it is possible to more reliably transfer charges from the photoelectric conversion element 21 to the node FD by simply changing the drive timing while maintaining the same circuit configuration as the conventional one.

  In this way, when the charge transfer from the photoelectric conversion element 21 to the node FD is realized, it is possible to realize the transfer with little unread of the charge, thereby avoiding that the image information of the current frame remains in the next frame. When capturing a moving subject, the image quality of the captured image can be improved.

[Other embodiment 1]
In the above embodiment, the timing at which the selection signal SEL is activated is set after the reset signal RST transitions from the active state to the inactive state. However, as shown in the timing chart of FIG. 8, the selection signal SEL is activated. The timing for setting the state may be set during the active period of the reset signal RST, that is, during the reset period.

  When such a driving timing is adopted, coupling due to the parasitic capacitance of the selection transistor 25 is performed at a timing when the selection transistor 25 is turned on after the potential of the node FD is reset to the power supply voltage Vdd by the reset operation of the reset transistor 23. Since the potential of the node FD can be raised from the power supply voltage Vdd by the above, even if the potential of the node FD is slightly lowered due to the coupling due to the parasitic capacitance of the reset transistor 23 at the timing when the reset transistor 23 is subsequently turned off, The final potential of FD can be made higher than when the selection transistor 25 is turned on before the reset transistor 23 is turned on.

[Other embodiment 2]
Further, as shown in the timing chart of FIG. 9, the driving timing of the above-described embodiment, that is, the timing of making the selection signal SEL active is after the reset signal RST transitions from the active state to the inactive state, In addition to setting the potential of the node FD before reading as a reset level, the selection signal SEL is made active at time ta before the reset signal RST becomes active, and at time tb before the reset signal RST becomes inactive. It is also possible to take the drive timing to make it inactive.

  When such drive timing is adopted, the influence of coupling due to parasitic capacitance when the reset transistor 23 is turned off can be separated from the pixel output line 31. Then, by making the selection signal SEL active again after the reset transistor 23 is turned off, it is possible to obtain the same operation and effect as in the case of the above-described embodiment. FIG. 10 shows the potential relationship of each part at time tc between time t2 when the reset signal RST becomes inactive and time t3 when the selection signal SEL becomes active again.

[Modification]
Note that the CMOS image sensor according to this embodiment may be formed as a single chip, or a module having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. It may be a form.

  In addition, the present invention is not limited to application to a solid-state image sensor, and can also be applied to an imaging apparatus. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

[Imaging device]
FIG. 11 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 11, the imaging device 50 according to the present invention includes an optical system including a lens group 51, a solid-state imaging device 52, a DSP circuit 53 that is a camera signal processing circuit, a frame memory 54, a display device 55, and a recording device 56. And an operation system 57, a power supply system 58, etc., and a DSP circuit 53, a frame memory 54, a display device 55, a recording device 56, an operation system 57, and a power supply system 58 are connected to each other via a bus line 59. It has become.

  The lens group 51 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 52. The solid-state imaging device 52 converts the amount of incident light imaged on the imaging surface by the lens group 51 into an electrical signal for each pixel and outputs it as a pixel signal. As the solid-state imaging device 52, the CMOS image sensor according to each of the above-described embodiments is used.

  The display device 55 is a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the solid-state image sensor 52. The recording device 56 records a moving image or a still image captured by the solid-state imaging device 52 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 57 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 58 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 53, the frame memory 54, the display device 55, the recording device 56, and the operation system 57 to these supply targets.

  As described above, in an imaging device such as a camera module for a mobile device such as a video camera, a digital still camera, or a mobile phone, by using the CMOS image sensor according to each embodiment described above as the solid-state imaging element 52, In the CMOS image sensor, since charge transfer from the photoelectric conversion element to the gate input node of the amplification transistor can be performed more reliably in the unit pixel, high image quality can be obtained particularly when imaging a moving subject. A captured image can be obtained.

It is a block diagram which shows the outline of the system configuration | structure of the solid-state image sensor to which this invention is applied. It is a circuit diagram which shows an example of a specific structure of a pixel array part and its peripheral circuit part. 6 is a timing chart showing a timing relationship among a selection signal SEL, a reset signal RST, and a transfer signal TRF according to the present embodiment. It is a potential diagram (the 1) with which it uses for operation | movement description of the unit pixel which concerns on this embodiment. It is a potential diagram (the 2) with which it uses for operation | movement description of the unit pixel which concerns on this embodiment. It is a potential diagram (the 3) with which it uses for operation | movement description of the unit pixel which concerns on this embodiment. It is a potential diagram (the 4) with which it uses for operation | movement description of the unit pixel which concerns on this embodiment. 6 is a timing chart showing a timing relationship among a selection signal SEL, a reset signal RST, and a transfer signal TRF according to another embodiment 1; 10 is a timing chart showing a timing relationship among a selection signal SEL, a reset signal RST, and a transfer signal TRF according to another embodiment 2. FIG. 10 is a potential diagram for explaining operations according to another embodiment 2; It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is a circuit diagram which shows an example of a structure of a unit pixel. It is a timing chart which shows the timing relationship of the selection signal SEL of the prior art, the reset signal RST, and the transfer signal TRF. FIG. 6 is a potential diagram (part 1) for explaining an operation of a unit pixel according to the related art. It is a potential diagram (the 2) with which it uses for description of operation | movement of the unit pixel which concerns on a prior art. It is a potential diagram (the 3) with which it uses for operation | movement description of the unit pixel which concerns on a prior art. FIG. 10 is a potential diagram (part 4) for explaining the operation of a unit pixel according to the related art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Sensor chip, 11, 11A, 11B, 11C ... Pixel array part, 12 ... Vertical drive circuit, 13 ... Shutter drive circuit, 14 ... CDS circuit, 15 ... Horizontal drive circuit, 16 ... AGC circuit, 17 ... A / D Conversion circuit, 18 ... timing generator, 20 ... unit pixel, 21 ... photoelectric conversion element, 22 ... transfer transistor, 23 ... amplification transistor, 24 ... reset transistor, 25 ... selection transistor, 31 ... pixel output line

Claims (4)

A plurality of unit pixels including a photoelectric conversion element, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor are arranged, the unit pixel is selected by the selection transistor, a gate input node of the amplification transistor is reset by the reset transistor, A pixel array unit that transfers charges from the photoelectric conversion element to the gate input node of the amplification transistor by the transfer transistor;
A reset signal for driving the reset transistor is set in an active state, and after the transition of the reset signal from an active state to an inactive state or in an active period of the reset signal, a selection signal for driving the selection transistor is set in an active state, A solid-state imaging device comprising: a drive unit that activates a transfer signal that drives the transfer transistor within an active period of the selection transistor. 2. The solid-state imaging device according to claim 1, wherein the driving unit further sets the selection signal to an active state before the reset signal becomes an active state, and sets the selection signal to an inactive state within an active period of the reset signal. . A plurality of unit pixels including a photoelectric conversion element, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor are arranged, the unit pixel is selected by the selection transistor, a gate input node of the amplification transistor is reset by the reset transistor, A method for driving a solid-state imaging device, wherein charge is transferred from the photoelectric conversion element to the gate input node of the amplification transistor by the transfer transistor,
The solid-state imaging device driving method, wherein the selection transistor is turned on after the reset operation by the reset transistor or during the reset operation. A plurality of unit pixels including a photoelectric conversion element, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor are arranged, the unit pixel is selected by the selection transistor, a gate input node of the amplification transistor is reset by the reset transistor, A solid-state imaging device that transfers charges from the photoelectric conversion element to the gate input node of the amplification transistor by the transfer transistor;
A reset signal for driving the reset transistor is set in an active state, and after the transition of the reset signal from an active state to an inactive state or in an active period of the reset signal, a selection signal for driving the selection transistor is set in an active state, A drive unit that activates a transfer signal that drives the transfer transistor within an active period of the selection transistor;
An imaging apparatus comprising: an optical system that forms an image of incident light on an imaging surface of the solid-state imaging device.

Images