JP2009130056A - Mounting structure of semiconductor element - Google Patents

Mounting structure of semiconductor element Download PDF

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JP2009130056A
JP2009130056A JP2007302017A JP2007302017A JP2009130056A JP 2009130056 A JP2009130056 A JP 2009130056A JP 2007302017 A JP2007302017 A JP 2007302017A JP 2007302017 A JP2007302017 A JP 2007302017A JP 2009130056 A JP2009130056 A JP 2009130056A
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semiconductor element
substrate
mounting structure
adhesive
semiconductor
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JP5221940B2 (en
Inventor
Michihiko Ueda
充彦 植田
Yoshiharu Sanagawa
佳治 佐名川
Takamasa Sakai
孝昌 酒井
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Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure of semiconductor elements, reducing a stress generated in a semiconductor element. <P>SOLUTION: In this mounting structure, a semiconductor element 1 is bonded to a substrate in three positions corresponding to three apexes of an imaginary triangle defined based on an outer circumference shape of the semiconductor element 1 through an adhesion part 2 composed of an adhesive (for example, a silicon-based resin such as a silicon resin having an elastic modulus of 1 MPa or less). Here, in the semiconductor element 1, all pads 19 are arranged along one side in the surface side (the above one surface side) opposite a substrate 3 side and the adhesion part 2 is positioned at each apex of an imaginary triangle having three apexes at three positions including two positions of both terminals of the above one side and one position on one side parallel to the above one side, so that a bonding wire is stably bonded to each pad 19. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体素子を基板に実装した半導体素子の実装構造に関するものである。   The present invention relates to a semiconductor element mounting structure in which a semiconductor element is mounted on a substrate.

電子デバイスの小型高機能化のニーズに伴い、層間絶縁膜として低誘電率(low-k)材料を用いたICチップや、MEMS(Micro Electro Mechanical Systems)デバイスなどの半導体素子の開発が各所で行われているが、この種の半導体素子は、脆弱であり、基板(例えば、セラミック基板、プリント配線基板など)に実装する実装工程で発生する応力が問題視されている。   In response to the need for smaller and more functional electronic devices, IC chips using low dielectric constant (low-k) materials as interlayer dielectrics and semiconductor elements such as MEMS (Micro Electro Mechanical Systems) devices are being developed in various places. However, this type of semiconductor element is fragile, and stress generated in a mounting process for mounting on a substrate (for example, a ceramic substrate, a printed wiring substrate, etc.) is regarded as a problem.

これに対して、実装工程で発生する応力を低減した半導体素子の実装構造を採用したものとして、半導体素子である半導体加速度センサチップを基板に実装した加速度センサが提案されている(例えば、特許文献1参照)。   On the other hand, an acceleration sensor in which a semiconductor acceleration sensor chip, which is a semiconductor element, is mounted on a substrate has been proposed as a semiconductor element mounting structure in which stress generated in the mounting process is reduced (for example, patent document). 1).

ここで、上記特許文献1に記載された加速度センサは、例えば、図6に示すように、半導体加速度センサチップからなる半導体素子1’と、一面が開放された箱状であって内底面からなる搭載面3a’に半導体素子1’の裏面側の4箇所が接着剤からなる接着部2’により固着された基板(パッケージ)3’と、半導体素子1’と協働する信号処理回路が形成され半導体素子1’の主表面側の4箇所が接着剤からなる接着部4’により固着されたIC基板5’と、基板3’の上記一面を閉塞する矩形板状のパッケージ蓋6’とを備えている。ここにおいて、上記特許文献1では、上述の接着剤2’,4’として、球状のスペーサが混合されたシリコーン樹脂を用いている。なお、半導体素子1’の主表面側のパッド19’はボンディングワイヤ71’を介してIC基板5’のパッド59’と電気的に接続されている。
特開2006−133123号公報
Here, the acceleration sensor described in Patent Document 1 includes, for example, as shown in FIG. 6, a semiconductor element 1 ′ composed of a semiconductor acceleration sensor chip, and a box shape with one surface open and an inner bottom surface. A substrate (package) 3 ′ in which four positions on the back surface side of the semiconductor element 1 ′ are fixed to the mounting surface 3 a ′ by an adhesive portion 2 ′ made of an adhesive, and a signal processing circuit that cooperates with the semiconductor element 1 ′ are formed. An IC substrate 5 ′ fixed at four locations on the main surface side of the semiconductor element 1 ′ with an adhesive portion 4 ′ made of an adhesive, and a rectangular plate-shaped package lid 6 ′ that closes the one surface of the substrate 3 ′. ing. Here, in the said patent document 1, the silicone resin with which the spherical spacer was mixed is used as above-mentioned adhesive agent 2 ', 4'. The pad 19 ′ on the main surface side of the semiconductor element 1 ′ is electrically connected to the pad 59 ′ of the IC substrate 5 ′ via the bonding wire 71 ′.
JP 2006-133123 A

上述の半導体素子1’の実装構造では、半導体素子1’が4箇所で接着部2’により基板3’に固着されているので、半導体素子1’を基板3’に実装するにあたって、図7(a)に示すように基板3’における半導体素子1’の搭載面3a’上の4箇所に常温下で接着剤2a’を塗布してから半導体素子1’を搭載した後、接着剤2a’が硬化するように所定温度(例えば、150℃)に加熱すると図7(b)に示すように基板3’が熱変形し、その後、常温になると図7(c)に示すように基板3が熱変形のない状態に戻ろうとするが、半導体素子1’は基板3’が熱変形した状態で固定されていたので、半導体素子1’が変形して応力が発生してしまう。   In the mounting structure of the semiconductor element 1 ′ described above, the semiconductor element 1 ′ is fixed to the substrate 3 ′ at the four positions by the bonding portions 2 ′. Therefore, when mounting the semiconductor element 1 ′ on the substrate 3 ′, FIG. As shown in a), after the adhesive 2a ′ is applied to the four places on the mounting surface 3a ′ of the semiconductor element 1 ′ on the substrate 3 ′ at room temperature and then the semiconductor element 1 ′ is mounted, the adhesive 2a ′ is applied. When it is heated to a predetermined temperature (for example, 150 ° C.) so as to be cured, the substrate 3 ′ is thermally deformed as shown in FIG. 7B, and thereafter, when it reaches room temperature, the substrate 3 is heated as shown in FIG. 7C. Although the semiconductor element 1 ′ is fixed in a state where the substrate 3 ′ is thermally deformed, the semiconductor element 1 ′ is deformed and stress is generated, although the semiconductor element 1 ′ is fixed in a state where it is not deformed.

本発明は上記事由に鑑みて為されたものであり、その目的は、半導体素子に生じる応力を低減することが可能な半導体素子の実装構造を提供することにある。   The present invention has been made in view of the above-described reasons, and an object thereof is to provide a semiconductor element mounting structure capable of reducing stress generated in the semiconductor element.

請求項1の発明は、半導体素子を基板に実装した半導体素子の実装構造であって、半導体素子の外周形状が矩形状であり、半導体素子が当該半導体素子の外周形状に基づいて規定した仮想三角形の3つの頂点に対応する3箇所で接着剤からなる接着部により基板に固着されてなることを特徴とする。   The invention of claim 1 is a mounting structure of a semiconductor element in which a semiconductor element is mounted on a substrate, the outer peripheral shape of the semiconductor element is rectangular, and the virtual triangle defined by the semiconductor element based on the outer peripheral shape of the semiconductor element It is characterized in that it is fixed to the substrate at three locations corresponding to the three apexes of the above by adhesive portions made of an adhesive.

この発明によれば、半導体素子が当該半導体素子の外周形状に基づいて規定した仮想三角形の3つの頂点に対応する3箇所で接着剤からなる接着部により基板に固着されているので、基板への実装時などの温度変化に起因して半導体素子が変形するのを抑制することができ、半導体素子に生じる応力を低減することが可能となる。   According to this invention, the semiconductor element is fixed to the substrate by the adhesive portions made of the adhesive at three locations corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element. The semiconductor element can be prevented from being deformed due to a temperature change during mounting or the like, and the stress generated in the semiconductor element can be reduced.

請求項2の発明は、請求項1の発明において、前記接着剤は、シリコーン系樹脂であることを特徴とする。   The invention of claim 2 is characterized in that, in the invention of claim 1, the adhesive is a silicone resin.

この発明によれば、前記接着剤としてエポキシ樹脂に比べて弾性率の低いシリコーン系樹脂を用いることにより、前記基板から前記半導体素子への応力の伝達を抑制することができる。   According to this invention, by using a silicone resin having a lower elastic modulus than the epoxy resin as the adhesive, it is possible to suppress the transmission of stress from the substrate to the semiconductor element.

請求項3の発明は、請求項1または請求項2の発明において、前記接着剤は、球状のスペーサが混合されたものであることを特徴とする。   According to a third aspect of the present invention, in the first or second aspect of the present invention, the adhesive is a mixture of spherical spacers.

この発明によれば、前記半導体素子と前記基板との間のギャップ長をスペーサにより確保することが可能となり、前記半導体素子と前記基板との間の前記接着部の厚み精度の向上が可能となる。また、この発明によれば、前記半導体素子と前記基板との間のギャップ長をスペーサにより大きくすることができ、前記基板から前記半導体素子への応力の伝達抑制効果も大きくなる。   According to this invention, the gap length between the semiconductor element and the substrate can be secured by the spacer, and the thickness accuracy of the adhesive portion between the semiconductor element and the substrate can be improved. . According to the present invention, the gap length between the semiconductor element and the substrate can be increased by the spacer, and the effect of suppressing the transmission of stress from the substrate to the semiconductor element is also increased.

請求項4の発明は、請求項3の発明において、前記スペーサは、シリカもしくはシリコンにより形成されてなることを特徴とする。   According to a fourth aspect of the present invention, in the third aspect of the present invention, the spacer is formed of silica or silicon.

この発明によれば、前記スペーサが金属や合成樹脂により形成されている場合に比べて、前記スペーサの寸法精度を高めることができ、前記半導体素子と前記基板との間の前記接着部の厚み精度をより向上させることが可能となる。   According to this invention, compared with the case where the spacer is formed of metal or synthetic resin, the dimensional accuracy of the spacer can be increased, and the thickness accuracy of the adhesive portion between the semiconductor element and the substrate is increased. Can be further improved.

請求項5の発明は、請求項1ないし請求項4の発明において、前記各接着部は、前記半導体素子の外周部に位置していることを特徴とする。   According to a fifth aspect of the present invention, in the first to fourth aspects of the invention, each of the bonding portions is located on an outer peripheral portion of the semiconductor element.

この発明によれば、前記各接着部が前記半導体素子の外周部よりも内側に位置している場合に比べて、前記半導体素子を安定して固定することができる。   According to this invention, the said semiconductor element can be fixed stably compared with the case where each said adhesion part is located inside the outer peripheral part of the said semiconductor element.

請求項6の発明は、請求項1ないし請求項5の発明において、前記半導体素子は、前記基板側とは反対側の表面側において全てのパッドが1辺に沿って配置されており、当該1辺の両端の2箇所と、当該1辺に平行な辺上の1箇所との3箇所に前記接着部が位置していることを特徴とする。   According to a sixth aspect of the present invention, in the first to fifth aspects of the invention, in the semiconductor element, all the pads are arranged along one side on the surface side opposite to the substrate side. The adhesive portion is characterized by being located at three locations, two locations at both ends of the side and one location on a side parallel to the one side.

この発明によれば、各パッドにボンディングワイヤを安定してボンディングすることができる。   According to this invention, a bonding wire can be stably bonded to each pad.

請求項7の発明は、請求項1ないし請求項5の発明において、前記半導体素子は、前記基板側とは反対側の表面側において全てのパッドが隣り合う2辺に沿って配置されており、当該2辺に共通の一端の1箇所と、当該2辺それぞれの他端の2箇所との3箇所に前記接着部が位置していることを特徴とする。   The invention of claim 7 is the invention of claims 1 to 5, wherein the semiconductor element is arranged along two sides where all pads are adjacent on the surface side opposite to the substrate side, The adhesive portion is located at three locations, one at one end common to the two sides and two at the other end of each of the two sides.

この発明によれば、各パッドにボンディングワイヤを安定してボンディングすることができる。   According to this invention, a bonding wire can be stably bonded to each pad.

請求項1の発明では、半導体素子に生じる応力を低減することが可能となるという効果がある。   According to the first aspect of the invention, there is an effect that the stress generated in the semiconductor element can be reduced.

(実施形態1)
本実施形態では図1に示すように、半導体加速度センサチップからなる半導体素子1を基板(例えば、セラミック基板、ガラスエポキシ樹脂基板を用いたプリント配線基板など)3に実装した実装構造について説明する。
(Embodiment 1)
In the present embodiment, as shown in FIG. 1, a mounting structure in which a semiconductor element 1 composed of a semiconductor acceleration sensor chip is mounted on a substrate 3 (for example, a printed wiring board using a ceramic substrate or a glass epoxy resin substrate) will be described.

半導体素子1は、枠状(本実施形態では、矩形枠状)のフレーム部11を備え、フレーム部11の内側に配置される重り部12が一表面側(図1(b)における上面側)において可撓性を有する4つの短冊状の撓み部13を介してフレーム部11に揺動自在に支持されている。言い換えれば、半導体素子1は、枠状のフレーム部11の内側に配置される重り部12が重り部12から四方へ延長された4つの撓み部13を介してフレーム部11に揺動自在に支持されている。ここにおいて、半導体素子1は、シリコン基板からなる支持基板10a上のシリコン酸化膜からなる絶縁層(埋込酸化膜)10b上にn形のシリコン層(活性層)10cを有するSOIウェハを加工することにより形成してあり、フレーム部11は、SOIウェハの支持基板10a、絶縁層10b、シリコン層10cそれぞれを利用して形成してある。これに対して、撓み部13は、SOIウェハにおけるシリコン層10cを利用して形成してあり、フレーム部11よりも薄肉となっている。   The semiconductor element 1 includes a frame portion 11 having a frame shape (in this embodiment, a rectangular frame shape), and a weight portion 12 arranged inside the frame portion 11 is on one surface side (upper surface side in FIG. 1B). Are supported by the frame portion 11 through four flexible strip portions 13 having flexibility. In other words, the semiconductor element 1 is swingably supported by the frame portion 11 via the four flexure portions 13 extending from the weight portion 12 in the four directions, the weight portion 12 disposed inside the frame-shaped frame portion 11. Has been. Here, the semiconductor element 1 processes an SOI wafer having an n-type silicon layer (active layer) 10c on an insulating layer (buried oxide film) 10b made of a silicon oxide film on a support substrate 10a made of a silicon substrate. The frame portion 11 is formed using the support substrate 10a, the insulating layer 10b, and the silicon layer 10c of the SOI wafer. On the other hand, the bending portion 13 is formed using the silicon layer 10 c in the SOI wafer and is thinner than the frame portion 11.

重り部12は、上述の4つの撓み部13を介してフレーム部11に支持された直方体状のコア部12aと、半導体素子1の上記一表面側から見てコア部12aの四隅それぞれに連続一体に連結された直方体状の4つの付随部12bとを有している。言い換えれば、重り部12は、フレーム部11の内側面に一端部が連結された各撓み部13の他端部が外側面に連結されたコア部12aと、コア部12aと一体に形成されコア部12aとフレーム部11との間の空間に配置される4つの付随部12bとを有している。つまり、各付随部12bは、半導体素子1の上記一表面側から見た平面視において、フレーム部11とコア部12aと互いに直交する方向に延長された2つの撓み部13,13とで囲まれる空間に配置されており、各付随部12bそれぞれとフレーム部11との間にはスリット14が形成され、撓み部13を挟んで隣り合う付随部12b間の間隔が撓み部13の幅寸法よりも長くなっている。ここにおいて、コア部12aは、上述のSOIウェハの支持基板10a、絶縁層10b、シリコン層10cそれぞれを利用して形成し、各付随部12bは、SOIウェハの支持基板10aを利用して形成してある。しかして、半導体素子1の上記一表面側において各付随部12bの表面は、コア部12aの表面を含む平面から半導体素子1の上記他表面側(図1(b)における下面側)へ離間して位置している。なお、半導体素子1の上述のフレーム部11、重り部12、各撓み部13は、マイクロマシニング技術を利用して形成すればよい。   The weight portion 12 is continuously integrated with each of the rectangular parallelepiped core portion 12a supported by the frame portion 11 via the four flexure portions 13 and the four corners of the core portion 12a when viewed from the one surface side of the semiconductor element 1. And four accompanying portions 12b having a rectangular parallelepiped shape connected to each other. In other words, the weight portion 12 is formed integrally with the core portion 12a and the core portion 12a in which the other end portion of each bending portion 13 whose one end portion is connected to the inner side surface of the frame portion 11 is connected to the outer surface. It has four accompanying parts 12b arranged in the space between the part 12a and the frame part 11. In other words, each associated portion 12b is surrounded by the frame portion 11 and the core portion 12a and the two bent portions 13 and 13 extending in a direction orthogonal to each other in a plan view as viewed from the one surface side of the semiconductor element 1. The slits 14 are formed between each of the accompanying portions 12 b and the frame portion 11, and the interval between the adjacent accompanying portions 12 b across the bending portion 13 is larger than the width dimension of the bending portion 13. It is getting longer. Here, the core portion 12a is formed using the above-described SOI wafer support substrate 10a, the insulating layer 10b, and the silicon layer 10c, and each accompanying portion 12b is formed using the SOI wafer support substrate 10a. It is. Thus, on the one surface side of the semiconductor element 1, the surface of each associated portion 12b is separated from the plane including the surface of the core portion 12a to the other surface side of the semiconductor element 1 (the lower surface side in FIG. 1B). Is located. In addition, what is necessary is just to form the above-mentioned flame | frame part 11, the weight part 12, and each bending part 13 of the semiconductor element 1 using micromachining technology.

ところで、図1(a),(b)それぞれの右下に示したように、半導体素子1の上記一表面に平行な面内でフレーム部11の一辺に沿った一方向をx軸の正方向、この一辺に直交する辺に沿った一方向をy軸の正方向、半導体素子1の厚み方向の一方向をz軸の正方向と規定すれば、重り部12は、x軸方向に延長されてコア部12aを挟む2つ1組の撓み部13,13と、y軸方向に延長されてコア部12aを挟む2つ1組の撓み部13,13とを介してフレーム部11に支持されていることになる。なお、上述のx軸、y軸、z軸の3軸により規定した直交座標では、半導体素子1において上述のシリコン層10cにより形成された部分の表面における重り部12の中心位置を原点としている。   By the way, as shown in the lower right of each of FIGS. 1A and 1B, one direction along one side of the frame portion 11 in a plane parallel to the one surface of the semiconductor element 1 is defined as the positive direction of the x axis. If one direction along the side perpendicular to the one side is defined as the positive direction of the y-axis and one direction of the thickness direction of the semiconductor element 1 is defined as the positive direction of the z-axis, the weight portion 12 is extended in the x-axis direction. The pair of flexible portions 13 and 13 sandwiching the core portion 12a and the pair of flexible portions 13 and 13 extending in the y-axis direction and sandwiching the core portion 12a are supported by the frame portion 11. Will be. In the orthogonal coordinates defined by the three axes of the above-described x axis, y axis, and z axis, the center position of the weight portion 12 on the surface of the portion of the semiconductor element 1 formed by the above silicon layer 10c is the origin.

重り部12のコア部12aからx軸の正方向に延長された撓み部13(図1(a)の右側の撓み部13)は、コア部12a近傍に2つ1組のゲージ抵抗Rx2,Rx4が形成されるとともに、フレーム部11近傍に1つのゲージ抵抗Rz2が形成されている。一方、重り部12のコア部12aからx軸の負方向に延長された撓み部13(図1(a)の左側の撓み部13)は、コア部12a近傍に2つ1組のゲージ抵抗Rx1,Rx3が形成されるとともに、フレーム部11近傍に1つのゲージ抵抗Rz3が形成されている。ここに、コア部12a近傍に形成された4つのゲージ抵抗Rx1,Rx2,Rx3,Rx4は、x軸方向の加速度を検出するために形成されたもので、平面形状が細長の長方形状であって、長手方向が撓み部13の長手方向に一致するように形成してあり、図2における左側のブリッジ回路Bxを構成するように図示しない配線(半導体素子1に形成されている拡散層配線、金属配線など)によって接続されている。なお、ゲージ抵抗Rx1〜Rx4は、x軸方向の加速度がかかったときに撓み部13において応力が集中する応力集中領域に形成されている。   A bending portion 13 (the right-side bending portion 13 in FIG. 1A) extending from the core portion 12a of the weight portion 12 in the positive direction of the x-axis is a pair of gauge resistances Rx2 and Rx4 in the vicinity of the core portion 12a. And one gauge resistor Rz2 is formed in the vicinity of the frame portion 11. On the other hand, the bending portion 13 (the bending portion 13 on the left side of FIG. 1A) extending in the negative direction of the x-axis from the core portion 12a of the weight portion 12 has a pair of gauge resistances Rx1 in the vicinity of the core portion 12a. , Rx3, and one gauge resistor Rz3 is formed in the vicinity of the frame portion 11. Here, the four gauge resistors Rx1, Rx2, Rx3, Rx4 formed in the vicinity of the core portion 12a are formed to detect acceleration in the x-axis direction, and the planar shape is an elongated rectangular shape. 2 is formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bending portion 13 and wiring (not shown) (diffuse layer wiring formed on the semiconductor element 1, metal) so as to constitute the left bridge circuit Bx in FIG. Connected by wiring). The gauge resistances Rx1 to Rx4 are formed in a stress concentration region where stress is concentrated in the bending portion 13 when acceleration in the x-axis direction is applied.

また、重り部12のコア部12aからy軸の正方向に延長された撓み部13(図1(a)の上側の撓み部13)はコア部12a近傍に2つ1組のゲージ抵抗Ry1,Ry3が形成されるとともに、フレーム部11近傍に1つのゲージ抵抗Rz1が形成されている。一方、重り部12のコア部12aからy軸の負方向に延長された撓み部13(図1(a)の下側の撓み部13)はコア部12a近傍に2つ1組のゲージ抵抗Ry2,Ry4が形成されるとともに、フレーム部11側の端部に1つのゲージ抵抗Rz4が形成されている。ここに、コア部12a近傍に形成された4つのゲージ抵抗Ry1,Ry2,Ry3,Ry4は、y軸方向の加速度を検出するために形成されたもので、平面形状が細長の長方形状であって、長手方向が撓み部13の長手方向に一致するように形成してあり、図2における中央のブリッジ回路Byを構成するように図示しない配線(半導体素子1に形成されている拡散層配線、金属配線など)によって接続されている。なお、ゲージ抵抗Ry1〜Ry4は、y軸方向の加速度がかかったときに撓み部13において応力が集中する応力集中領域に形成されている。   Further, the bending portion 13 (the upper bending portion 13 in FIG. 1A) extended from the core portion 12a of the weight portion 12 in the positive direction of the y-axis is a pair of gauge resistors Ry1, in the vicinity of the core portion 12a. Ry3 is formed, and one gauge resistor Rz1 is formed in the vicinity of the frame portion 11. On the other hand, the bending portion 13 (the lower bending portion 13 in FIG. 1A) extended from the core portion 12a of the weight portion 12 in the negative direction of the y-axis is a pair of gauge resistances Ry2 in the vicinity of the core portion 12a. , Ry4 are formed, and one gauge resistor Rz4 is formed at the end on the frame part 11 side. Here, the four gauge resistors Ry1, Ry2, Ry3, Ry4 formed in the vicinity of the core portion 12a are formed to detect acceleration in the y-axis direction, and the planar shape is an elongated rectangular shape. 2 is formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bent portion 13 and wiring (not shown) (diffuse layer wiring formed on the semiconductor element 1, metal) so as to constitute the central bridge circuit By in FIG. Connected by wiring). Note that the gauge resistors Ry1 to Ry4 are formed in a stress concentration region where stress is concentrated in the flexure 13 when acceleration in the y-axis direction is applied.

また、フレーム部11近傍に形成された4つのゲージ抵抗Rz1,Rz2,Rz3,Rz4は、z軸方向の加速度を検出するために形成されたものであり、図2における右側のブリッジ回路Bzを構成するように図示しない配線(半導体素子1に形成されている拡散層配線、金属配線など)によって接続されている。ただし、2つ1組となる撓み部13,13のうち一方の組の撓み部13,13に形成したゲージ抵抗Rz1,Rz4は長手方向が撓み部13,13の長手方向と一致するように形成されているのに対して、他方の組の撓み部13,13に形成したゲージ抵抗Rz2,Rz3は長手方向が撓み部13,13の幅方向(短手方向)と一致するように形成されている。   Further, the four gauge resistors Rz1, Rz2, Rz3, and Rz4 formed in the vicinity of the frame portion 11 are formed to detect acceleration in the z-axis direction, and constitute the right bridge circuit Bz in FIG. Thus, they are connected by wiring (not shown) (diffusion layer wiring, metal wiring, etc. formed in the semiconductor element 1). However, the gauge resistances Rz1 and Rz4 formed in one set of the bending portions 13 and 13 of the pair of bending portions 13 and 13 are formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bending portions 13 and 13. On the other hand, the gauge resistances Rz2 and Rz3 formed on the other set of flexures 13 and 13 are formed such that the longitudinal direction coincides with the width direction (short direction) of the flexures 13 and 13. Yes.

ここで、半導体素子1の基本的な動作の一例について説明する。   Here, an example of a basic operation of the semiconductor element 1 will be described.

いま、半導体素子1に加速度がかかっていない状態で、半導体素子1に対してx軸の正方向に加速度がかかったとすると、x軸の負方向に作用する重り部12の慣性力によってフレーム部11に対して重り部12が変位し、結果的にx軸方向を長手方向とする撓み部13,13が撓んで当該撓み部13,13に形成されているゲージ抵抗Rx1〜Rx4の抵抗値が変化することになる。この場合、ゲージ抵抗Rx1,Rx3は引張応力を受け、ゲージ抵抗Rx2,Rx4は圧縮応力を受ける。一般的にゲージ抵抗は引張応力を受けると抵抗値(抵抗率)が増大し、圧縮応力を受けると抵抗値(抵抗率)が減少する特性を有しているので、ゲージ抵抗Rx1,Rx3は抵抗値が増大し、ゲージ抵抗Rx2,Rx4は抵抗値が減少することになる。したがって、図2に示した一対の入力端子VDD,GND間に外部電源から一定の直流電圧を印加しておけば、図2に示した左側のブリッジ回路Bxの出力端子X1,X2間の電位差がx軸方向の加速度の大きさに応じて変化する。同様に、y軸方向の加速度がかかった場合には図2に示した中央のブリッジ回路Byの出力端子Y1,Y2間の電位差がy軸方向の加速度の大きさに応じて変化し、z軸方向の加速度がかかった場合には図2に示した右側のブリッジ回路Bzの出力端子Z1,Z2間の電位差がz軸方向の加速度の大きさに応じて変化する。しかして、上述の半導体素子1は、各ブリッジ回路Bx〜Bzそれぞれの出力電圧の変化を検出することにより、当該半導体素子1に作用したx軸方向、y軸方向、z軸方向それぞれの加速度を検出することができる。   Now, assuming that acceleration is applied to the semiconductor element 1 in the positive x-axis direction while no acceleration is applied to the semiconductor element 1, the frame portion 11 is caused by the inertial force of the weight 12 acting in the negative x-axis direction. Accordingly, the weight 12 is displaced, and as a result, the bending portions 13 and 13 whose longitudinal direction is the x-axis direction are bent, and the resistance values of the gauge resistors Rx1 to Rx4 formed in the bending portions 13 and 13 change. Will do. In this case, the gauge resistances Rx1 and Rx3 are subjected to tensile stress, and the gauge resistances Rx2 and Rx4 are subjected to compressive stress. In general, gauge resistance has a characteristic that resistance value (resistivity) increases when subjected to tensile stress, and resistance value (resistivity) decreases when subjected to compressive stress. As the value increases, the resistance values of the gauge resistors Rx2 and Rx4 decrease. Therefore, if a constant DC voltage is applied from the external power supply between the pair of input terminals VDD and GND shown in FIG. 2, the potential difference between the output terminals X1 and X2 of the left bridge circuit Bx shown in FIG. It changes according to the magnitude of the acceleration in the x-axis direction. Similarly, when acceleration in the y-axis direction is applied, the potential difference between the output terminals Y1 and Y2 of the central bridge circuit By shown in FIG. 2 changes according to the magnitude of the acceleration in the y-axis direction, and the z-axis When acceleration in the direction is applied, the potential difference between the output terminals Z1 and Z2 of the right bridge circuit Bz shown in FIG. 2 changes according to the magnitude of acceleration in the z-axis direction. Therefore, the above-described semiconductor element 1 detects the change in the output voltage of each of the bridge circuits Bx to Bz, thereby accelerating each acceleration acting on the semiconductor element 1 in the x-axis direction, the y-axis direction, and the z-axis direction. Can be detected.

ここにおいて、半導体素子1は、上述の3つのブリッジ回路Bx,By,Bzに共通の2つの入力端子VDD,GNDと、ブリッジ回路Bxの2つの出力端子X1,X2と、ブリッジ回路Byの2つの出力端子Y1,Y2と、ブリッジ回路Bzの2つの出力端子Z1,Z2とを備えており、これらの各入力端子VDD,GNDおよび各出力端子X1,X2,Y1,Y2,Z1,Z2が、上記一表面側にパッド(外部接続用電極)19として設けられている。ここにおいて、8つのパッド19は、半導体素子1の1辺に沿って配置されている。なお、半導体素子1は、上記一表面側において上記シリコン層10c上にシリコン酸化膜とシリコン窒化膜との積層膜からなる絶縁膜16が形成されており、パッド19および上記金属配線は絶縁膜16上に形成されている。   Here, the semiconductor element 1 includes two input terminals VDD and GND common to the above-described three bridge circuits Bx, By, and Bz, two output terminals X1 and X2 of the bridge circuit Bx, and two bridge circuits By. The output terminals Y1 and Y2 and the two output terminals Z1 and Z2 of the bridge circuit Bz are provided. These input terminals VDD and GND and the output terminals X1, X2, Y1, Y2, Z1 and Z2 A pad (external connection electrode) 19 is provided on one surface side. Here, the eight pads 19 are arranged along one side of the semiconductor element 1. In the semiconductor element 1, an insulating film 16 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the silicon layer 10 c on the one surface side, and the pad 19 and the metal wiring are the insulating film 16. Formed on top.

上述の各ゲージ抵抗(ピエゾ抵抗)Rx1〜Rx4,Ry1〜Ry4,Rz1〜Rz4および上記各拡散層配線は、上記シリコン層10cにおけるそれぞれの形成部位に適宜濃度のp形不純物をドーピングすることにより形成され、上記金属配線は、絶縁膜16上にスパッタ法や蒸着法などにより成膜した金属膜(例えば、Al膜、Al合金膜など)をリソグラフィ技術およびエッチング技術を利用してパターニングすることにより形成されている。なお、上記金属配線は絶縁膜16に設けたコンタクトホールを通して拡散層配線と電気的に接続されている。   The gauge resistances (piezoresistors) Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4 and the diffusion layer wirings described above are formed by doping p-type impurities with appropriate concentrations at respective formation sites in the silicon layer 10c. The metal wiring is formed by patterning a metal film (for example, an Al film, an Al alloy film, etc.) formed on the insulating film 16 by sputtering or vapor deposition using a lithography technique and an etching technique. Has been. The metal wiring is electrically connected to the diffusion layer wiring through a contact hole provided in the insulating film 16.

ところで、半導体素子1は、当該半導体素子1の外周形状に基づいて規定した仮想三角形の3つの頂点に対応する3箇所で接着剤(例えば、弾性率が1MPa以下のシリコーン樹脂などのシリコーン系樹脂など)からなる接着部2により基板に固着されている。ここにおいて、半導体素子1は、基板3側とは反対側の表面側(上記一表面側)において全てのパッド19が1辺に沿って配置されており、当該1辺の両端の2箇所と、当該1辺に平行な辺上の1箇所との3箇所とに頂点を有する仮想三角形の各頂点に接着部2が位置しており、各パッド19にボンディングワイヤを安定してボンディングすることができる。   By the way, the semiconductor element 1 has an adhesive (for example, a silicone-based resin such as a silicone resin having an elastic modulus of 1 MPa or less) at three positions corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element 1. Are fixed to the substrate by an adhesive portion 2 made of Here, in the semiconductor element 1, all the pads 19 are arranged along one side on the surface side opposite to the substrate 3 side (the one surface side), and two locations at both ends of the one side, The bonding portion 2 is located at each vertex of a virtual triangle having vertices at three locations, one on a side parallel to the one side, and a bonding wire can be stably bonded to each pad 19. .

以下、半導体素子1を基板3に実装する際の半導体素子1および基板3の状態変化について図3に基づいて説明するが、(a)〜(c)それぞれにおける上段は概略側面図、下段は概略斜視図である。   Hereinafter, the state changes of the semiconductor element 1 and the substrate 3 when the semiconductor element 1 is mounted on the substrate 3 will be described with reference to FIG. 3, wherein the upper stage in each of (a) to (c) is a schematic side view, and the lower stage is a schematic view. It is a perspective view.

半導体素子1を基板3に実装するにあたっては、図3(a)に示すように基板3における半導体素子1の搭載面3a上の3箇所に常温下で接着剤2aをディスペンサなどにより塗布してから半導体素子1を搭載した後、接着剤2aが硬化するように所定温度(例えば、150℃)に加熱すると図3(b)に示すように基板3が熱変形し、その後、常温になると図3(c)に示すように基板3が熱変形のない状態に戻ろうとする。ここで、半導体素子1は基板3が熱変形した状態で固定されていたが、基板3に対して3箇所のみしか接着部2により固着されていないので、常温に戻ったときに温度変化による基板3側の変形が半導体素子1には当該半導体素子1の傾きとして伝わり、半導体素子1の表面を3点で決定でき、半導体素子1が変形して応力が発生するのを防止することができる。基板3が常温に戻ったときに半導体素子1は図1(c)の下段の概略斜視図に示すように若干傾くが、高低差がナノメータレベルの傾きであり、特に問題ない。なお、半導体素子1としてチップサイズが1mm□〜10mm□、厚みが0.1mm〜1mm程度の場合、接着剤2aはφ200μm〜φ1000μm程度の領域に塗布すればよい。   In mounting the semiconductor element 1 on the substrate 3, as shown in FIG. 3A, the adhesive 2a is applied to the three locations on the mounting surface 3a of the semiconductor element 1 on the substrate 3 at room temperature with a dispenser or the like. When the semiconductor element 1 is mounted and then heated to a predetermined temperature (for example, 150 ° C.) so that the adhesive 2a is cured, the substrate 3 is thermally deformed as shown in FIG. As shown in (c), the substrate 3 tries to return to a state without thermal deformation. Here, the semiconductor element 1 is fixed in a state where the substrate 3 is thermally deformed. However, since only the three portions are fixed to the substrate 3 by the bonding portion 2, the substrate due to temperature change when returning to room temperature. The deformation on the three side is transmitted to the semiconductor element 1 as the inclination of the semiconductor element 1, and the surface of the semiconductor element 1 can be determined at three points, and the semiconductor element 1 can be prevented from being deformed and generating stress. When the substrate 3 returns to room temperature, the semiconductor element 1 is slightly inclined as shown in the schematic perspective view in the lower part of FIG. 1C, but the height difference is a nanometer-level inclination, and there is no particular problem. When the chip size of the semiconductor element 1 is 1 mm □ to 10 mm □ and the thickness is about 0.1 mm to 1 mm, the adhesive 2a may be applied to an area of about φ200 μm to φ1000 μm.

以上説明した本実施形態の半導体素子1の実装構造では、基板3への実装時などの温度変化に起因して半導体素子1が変形するのを抑制することができ、半導体素子1に生じる応力を低減することが可能となる。ここで、半導体素子1が上述のような半導体加速度センサチップであれば、フレーム部11の4つの角部を固着した場合(つまり、4箇所で固着した場合)やフレーム部11を全周に亙って固着した場合に比べて、基板3から半導体素子1への応力が撓み部13に作用しにくく安定した精度の高い加速度測定が可能となる。   In the mounting structure of the semiconductor element 1 of the present embodiment described above, it is possible to suppress the deformation of the semiconductor element 1 due to a temperature change during mounting on the substrate 3 and the stress generated in the semiconductor element 1 is suppressed. It becomes possible to reduce. Here, if the semiconductor element 1 is a semiconductor acceleration sensor chip as described above, the four corners of the frame portion 11 are fixed (that is, fixed at four locations) or the frame portion 11 is placed around the entire circumference. Therefore, the stress from the substrate 3 to the semiconductor element 1 is less likely to act on the bent portion 13 than in the case where it is fixed, and stable acceleration measurement with high accuracy is possible.

また、本実施形態では、接着剤2aとしてエポキシ樹脂に比べて弾性率の低いシリコーン系樹脂を用いることにより、基板3から半導体素子1への応力の伝達を抑制する(つまり、応力を緩和する)ことができる。ここにおいて、接着剤2aとして、シリコーン系樹脂に球状のスペーサが混合されたものを用いれば、半導体素子1と基板3との間のギャップ長をスペーサにより確保することが可能となり、半導体素子1と基板3との間の接着部2の厚み精度の向上が可能となり、半導体素子1を構成する半導体加速度センサチップの重り部12の過度な変位による破損を防止することが可能となる。また、半導体素子1と基板3との間のギャップ長をスペーサにより大きくすることができ、基板3から半導体素子1への応力の伝達抑制効果も大きくなる。また、上記スペーサをシリカもしくはシリコンにより形成するようにすれば、金属や合成樹脂により形成する場合に比べて、上記スペーサの寸法精度を高めることができ、半導体素子1と基板3との間の接着部2の厚み精度をより向上させることが可能となる。なお、上記スペーサとしては、例えば、直径が3μm〜30μmのものを用い、シリコーン系樹脂に対して1〜20%程度の割合で混合させればよい。   Further, in the present embodiment, by using a silicone resin having a lower elastic modulus than the epoxy resin as the adhesive 2a, the transmission of stress from the substrate 3 to the semiconductor element 1 is suppressed (that is, the stress is reduced). be able to. Here, if the adhesive 2a is made of a silicone resin mixed with a spherical spacer, the gap length between the semiconductor element 1 and the substrate 3 can be secured by the spacer. It is possible to improve the thickness accuracy of the bonding portion 2 between the substrate 3 and the semiconductor acceleration sensor chip constituting the semiconductor element 1, and to prevent damage due to excessive displacement of the weight portion 12. In addition, the gap length between the semiconductor element 1 and the substrate 3 can be increased by the spacer, and the effect of suppressing the transmission of stress from the substrate 3 to the semiconductor element 1 is also increased. Further, if the spacer is made of silica or silicon, the dimensional accuracy of the spacer can be increased as compared with the case where the spacer is made of metal or synthetic resin, and the adhesion between the semiconductor element 1 and the substrate 3 can be improved. It becomes possible to further improve the thickness accuracy of the portion 2. In addition, as said spacer, what has a diameter of 3 micrometers-30 micrometers is used, for example, what is necessary is just to mix in the ratio of about 1 to 20% with respect to silicone type resin.

また、本実施形態の半導体素子1の実装構造によれば、各接着部2が半導体素子1の外周部に位置しているので、各接着部2が半導体素子1の外周部よりも内側に位置している場合に比べて、半導体素子1を安定して固定することができる。ここで、半導体素子1が上述のような半導体加速度センサチップであれば、各接着部2の一部がフレーム部11と重り部12との間のスリット14や重り部12と基板3との間のギャップまで広がって形成されることによる動作不良をなくすことができる。   Further, according to the mounting structure of the semiconductor element 1 of the present embodiment, each bonding portion 2 is located on the outer peripheral portion of the semiconductor element 1, so that each bonding portion 2 is positioned on the inner side of the outer peripheral portion of the semiconductor element 1. The semiconductor element 1 can be stably fixed as compared with the case where it is used. Here, if the semiconductor element 1 is a semiconductor acceleration sensor chip as described above, a part of each bonding portion 2 is a slit 14 between the frame portion 11 and the weight portion 12 or between the weight portion 12 and the substrate 3. It is possible to eliminate malfunction due to the widening of the gap.

(実施形態2)
本実施形態の半導体素子1の実装構造は実施形態1と略同じであって、図4に示すように、半導体素子1においてパッド19が、一表面側(基板3側とは反対側の表面側)で隣り合う2辺に沿って配置されており(矩形枠状のフレーム部11の4辺のうちの2辺のみに上述のパッド19を設けてあり)、当該2辺に共通の一端の1箇所と、当該2辺それぞれの他端の2箇所との3箇所に前記接着部が位置している点が相違し、他の構成は実施形態1と同様なので説明を省略する。
(Embodiment 2)
The mounting structure of the semiconductor element 1 of the present embodiment is substantially the same as that of the first embodiment. As shown in FIG. 4, the pad 19 in the semiconductor element 1 has one surface side (the surface side opposite to the substrate 3 side). ) Are arranged along two adjacent sides (the above-described pad 19 is provided on only two sides of the four sides of the rectangular frame-shaped frame portion 11), and one end common to the two sides is provided. The difference is that the bonding portion is located at three places, that is, two places at the other end of each of the two sides, and the other configuration is the same as that of the first embodiment, and thus the description thereof is omitted.

しかして、本実施形態の半導体素子1の実装構造では、各パッド19にボンディングワイヤを安定してボンディングすることができ、また、半導体素子1が半導体加速度センサチップのようなMEMSデバイスの場合に配線の設計自由度が高くなり、しかも、パッド19の数を増やすことも可能となる。   Thus, in the mounting structure of the semiconductor element 1 according to the present embodiment, a bonding wire can be stably bonded to each pad 19, and wiring is performed when the semiconductor element 1 is a MEMS device such as a semiconductor acceleration sensor chip. In addition, the degree of design freedom can be increased, and the number of pads 19 can be increased.

ところで、上述の各実施形態では、平面視における外周形状が正方形状の半導体素子1を3箇所で接着部2により基板3に固着しているが、接着部2の位置は各実施形態の位置に限定するものではなく、半導体素子1をバランス良く支持できる位置であればよく、図5の(a)〜(l)の位置でもよい。ここで、図5(a)は実施形態2における各接着部2の配置と同じであり、半導体素子1の3つの端点(角)それぞれに接着部2が位置する例、同図(b)は実施形態1における各接着部2の配置と同じであり、半導体素子1の2つの端点と当該2つの端点を結ぶ辺に平行な辺の中央とに接着部2が位置する例、同図(c),(d)は半導体素子1の2つの端点と当該2つの端点を結ぶ辺に隣り合う1辺の中間とに接着部2が位置する例、同図(e)〜(j)は半導体素子1の1つの端点と4辺のうちの2辺の中間とに接着部2が位置する例、同図(k),(l)は半導体素子1の4辺のうちの3辺の中間に接着部2が位置する例を示している。ここにおいて、3箇所の接着部2は、仮想三角形の頂点に対応するように位置しているが、当該仮想三角形の面積が大きく、且つ、当該仮想三角形内に半導体素子1の中心が内包されることが望ましく、実施形態1のようにパッド19が半導体素子1の1辺に沿って配置されている場合、3箇所の接着部2の配置は、図5(a)〜(j)の中では同図(b)の配置が最良の配置となり、実施形態2のようにパッド19が半導体素子1の隣り合う2辺に沿って配置されている場合、3箇所の接着部2の配置は、同図(a)の配置が最良の配置となる。   By the way, in each of the above-described embodiments, the semiconductor element 1 having a square outer shape in plan view is fixed to the substrate 3 by the bonding portion 2 at three positions. However, the position of the bonding portion 2 is the position of each embodiment. The position is not limited, and any position that can support the semiconductor element 1 in a balanced manner may be used, and the positions shown in FIGS. Here, FIG. 5A is the same as the arrangement of the bonding portions 2 in the second embodiment, and an example in which the bonding portions 2 are positioned at the three end points (corners) of the semiconductor element 1, FIG. An example in which the bonding portion 2 is located at the two end points of the semiconductor element 1 and the center of the side parallel to the side connecting the two end points, which is the same as the arrangement of the bonding portions 2 in the first embodiment, FIG. ), (D) are examples in which the bonding portion 2 is located between two end points of the semiconductor element 1 and one side adjacent to the side connecting the two end points. FIGS. An example in which the bonding portion 2 is located between one end point of 1 and the middle of two of the four sides, FIGS. 5 (k) and (l) are bonded to the middle of three of the four sides of the semiconductor element 1. The example in which the part 2 is located is shown. Here, the three bonding portions 2 are positioned so as to correspond to the vertices of the virtual triangle, but the area of the virtual triangle is large, and the center of the semiconductor element 1 is included in the virtual triangle. Desirably, when the pad 19 is arranged along one side of the semiconductor element 1 as in the first embodiment, the arrangement of the three bonding portions 2 is as shown in FIGS. When the arrangement shown in FIG. 5B is the best arrangement and the pads 19 are arranged along two adjacent sides of the semiconductor element 1 as in the second embodiment, the arrangement of the three bonding portions 2 is the same. The arrangement of FIG. (A) is the best arrangement.

上述の各実施形態では、半導体素子1として、MEMSデバイスの一例としてピエゾ抵抗形の半導体加速度センサチップを例示したが、半導体素子1は、半導体加速度センサチップに限らず、例えば、容量形の加速度センサチップやジャイロセンサ、圧力センサ、マイクロアクチュエータ、マイクロリレー、マイクロバルブ、赤外線センサなどのMEMSデバイスや、ICチップなどにも適用できる。また、半導体素子1の外周形状は正方形状に限らず、矩形状であればよい。   In each of the above-described embodiments, a piezoresistive semiconductor acceleration sensor chip is illustrated as an example of a MEMS device as the semiconductor element 1. However, the semiconductor element 1 is not limited to a semiconductor acceleration sensor chip, and for example, a capacitive acceleration sensor. It can also be applied to MEMS devices such as chips, gyro sensors, pressure sensors, microactuators, microrelays, microvalves, and infrared sensors, and IC chips. Further, the outer peripheral shape of the semiconductor element 1 is not limited to a square shape, but may be a rectangular shape.

実施形態1の半導体素子の実装構造を示し、(a)は要部概略平面図、(b)は要部概略断面図である。1A and 1B show a mounting structure of a semiconductor element according to Embodiment 1, wherein FIG. 3A is a schematic plan view of a main part, and FIG. 同上の半導体素子である半導体加速度センサチップの回路図である。It is a circuit diagram of the semiconductor acceleration sensor chip which is a semiconductor element same as the above. 同上における基板への半導体素子の実装工程の説明図である。It is explanatory drawing of the mounting process of the semiconductor element to the board | substrate in the same as the above. 実施形態2の半導体素子の実装構造を示し、(a)は要部概略平面図、(b)は要部概略断面図である。The mounting structure of the semiconductor element of Embodiment 2 is shown, (a) is a principal part schematic plan view, (b) is a principal part schematic sectional drawing. 同上における各接着部の配置例の説明図である。It is explanatory drawing of the example of arrangement | positioning of each adhesion part in the same as the above. 従来例における加速度センサを示し、(a)は概略分解斜視図、(b)は概略断面図である。The acceleration sensor in a prior art example is shown, (a) is a schematic exploded perspective view, (b) is a schematic sectional drawing. 同上における基板への半導体加速度センサチップからなる半導体素子の実装工程の説明図である。It is explanatory drawing of the mounting process of the semiconductor element which consists of a semiconductor acceleration sensor chip | tip on the board | substrate in the same as the above.

符号の説明Explanation of symbols

1 半導体素子
2 接着部
2a 接着剤
3 基板
19 パッド
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Adhesion part 2a Adhesive 3 Board | substrate 19 Pad

Claims (7)

半導体素子を基板に実装した半導体素子の実装構造であって、半導体素子の外周形状が矩形状であり、半導体素子が当該半導体素子の外周形状に基づいて規定した仮想三角形の3つの頂点に対応する3箇所で接着剤からなる接着部により基板に固着されてなることを特徴とする半導体素子の実装構造。   A semiconductor element mounting structure in which a semiconductor element is mounted on a substrate, the outer peripheral shape of the semiconductor element is rectangular, and the semiconductor element corresponds to three vertices of a virtual triangle defined based on the outer peripheral shape of the semiconductor element. A mounting structure of a semiconductor element, wherein the semiconductor element mounting structure is fixed to a substrate by adhesive portions made of an adhesive at three locations. 前記接着剤は、シリコーン系樹脂であることを特徴とする請求項1記載の半導体素子の実装構造。   The semiconductor element mounting structure according to claim 1, wherein the adhesive is a silicone resin. 前記接着剤は、球状のスペーサが混合されたものであることを特徴とする請求項1または請求項2記載の半導体素子の実装構造。   3. The semiconductor element mounting structure according to claim 1, wherein the adhesive is a mixture of spherical spacers. 前記スペーサは、シリカもしくはシリコンにより形成されてなることを特徴とする請求項3記載の半導体素子の実装構造。   4. The semiconductor element mounting structure according to claim 3, wherein the spacer is made of silica or silicon. 前記各接着部は、前記半導体素子の外周部に位置していることを特徴とする請求項1ないし請求項4のいずれか1項に記載の半導体素子の実装構造。   5. The semiconductor element mounting structure according to claim 1, wherein each of the bonding portions is located on an outer peripheral portion of the semiconductor element. 6. 前記半導体素子は、前記基板側とは反対側の表面側において全てのパッドが1辺に沿って配置されており、当該1辺の両端の2箇所と、当該1辺に平行な辺上の1箇所との3箇所に前記接着部が位置していることを特徴とする請求項1ないし請求項5のいずれか1項に記載の半導体素子の実装構造。   In the semiconductor element, all pads are arranged along one side on the surface side opposite to the substrate side, and two places at both ends of the one side and one on a side parallel to the one side. The semiconductor element mounting structure according to claim 1, wherein the bonding portion is located at three locations. 前記半導体素子は、前記基板側とは反対側の表面側において全てのパッドが隣り合う2辺に沿って配置されており、当該2辺に共通の一端の1箇所と、当該2辺それぞれの他端の2箇所との3箇所に前記接着部が位置していることを特徴とする請求項1ないし請求項5のいずれか1項に記載の半導体素子の実装構造。   In the semiconductor element, all pads are arranged along two adjacent sides on the surface side opposite to the substrate side, and one end common to the two sides and the other of the two sides. The semiconductor element mounting structure according to any one of claims 1 to 5, wherein the bonding portion is located at three locations including two ends.
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US11112424B2 (en) 2017-08-29 2021-09-07 Seiko Epson Corporation Physical quantity sensor, complex sensor, inertial measurement unit, portable electronic device, electronic device, and vehicle

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WO2013145828A1 (en) * 2012-03-30 2013-10-03 日立オートモティブシステムズ株式会社 Inertial sensor module
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