JP2009129922A - Manufacturing method of semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor package, capable of achieving miniaturization and increasing the number of pins. <P>SOLUTION: A wiring pattern 3 is formed on the front surface of a copper plate 1, external terminals 4 are formed on the rear surface and semiconductor chips 5 are flip-chip bonded on the front surface of the copper plate. Subsequently, an underfill material 6 is injected into a gap between the copper plate and the semiconductor chips, the semiconductor chips are sealed with a molding resin and then the copper plate is etched to form a conductive path 8. After that, solder bumps 10 are formed after the conduction, and dicing processing is executed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor package. Specifically, the present invention relates to a method of manufacturing a semiconductor package that can realize a reduction in size of the package.

  In recent years, with the miniaturization of electronic devices, the size and density of semiconductor packages have been required, and semiconductor packages such as QFN (Quad Flat Non-Leaded Package) type have come to be used in large quantities. (For example, refer to Patent Document 1).

6A and 6B are schematic diagrams for explaining a QFN type semiconductor package (FIG. 6A is a schematic cross-sectional view, and FIG. 6B is a schematic bottom view). The semiconductor element 102 is bonded onto the die pad 103 with a conductive adhesive or the like. In addition, an electrode portion (not shown) of the semiconductor element is connected to the lead terminal 105 by a bonding wire 104. Further, in order to protect the semiconductor element from the outside world, a sealing resin (for example, epoxy) as a sealing body Resin) 106 is used to seal the semiconductor element.
As shown in FIG. 6B, the lead terminal is exposed from the lower surface of the semiconductor package to the edge, and the die pad is also exposed at the center of the lower surface.

FIG. 7 is a schematic diagram for explaining the manufacturing process of the above-described QFN type semiconductor package. In the manufacturing method of the QFN type semiconductor package, first, as shown in FIG. The semiconductor element 102 is bonded to the die pad 103 of the copper lead frame 107 formed with a conductive adhesive or the like, and an electrode portion (not shown) on the semiconductor element and the lead terminal 105 are connected by the bonding wire 104. To do.
Subsequently, the lead frame 107 is loaded into the sealing mold 108, and in this state, the sealing resin 106 such as an epoxy resin flows into the sealing mold to perform sealing (see FIG. 7B). Then, in order to separate the lead frame from the single semiconductor package, the cutting blade 109 with diamond particles attached, or a cutting not shown in the figure, bonded to the dicing tape 110 as shown in FIG. 7C. By cutting with a molding die or the like, a QFN type semiconductor package as shown in FIG. 6 can be obtained.

JP 2002-368179 A

  However, the conventional semiconductor package manufacturing method described above uses an etching technique for forming the lead frame pattern, that is, as shown in FIG. 8A, functions as a mask material on the front and back surfaces of the copper plate 120. After the resist 121 to be formed is formed using a general-purpose photolithography technique, a lead frame pattern is formed by etching the copper plate using a general-purpose etching technique as shown in FIG. 8B. When trying to realize a fine pitch of the frame, the thickness of the copper plate is limited. For example, in the case of a copper plate having a thickness of about 125 μm, a pitch of about 150 μm (inner lead width is about 80 μm) Due to the manufacturing limit and the fine pitch of the lead frame is limited, Type conductivity, it is impossible to sufficiently meet the demand of multiple pins.

  As a technology to reduce the size of the semiconductor package, a resin layer for relocation is provided on the active surface of the semiconductor wafer, and the I / O pads of a large number of semiconductor chips built in the semiconductor wafer are rearranged at once. Since then, wafer level chip size packages such as dicing the semiconductor wafer into individual chip size packages have attracted attention (for example, Japanese Patent Laid-Open Nos. 10-178124 and 2000-36518, JP-A-2001-144223, JP-A-2002-76203, JP-A-2002-373968), it is difficult to improve the yield, and there is a concern about an increase in the cost of the semiconductor package.

  The present invention has been devised in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor package that can realize miniaturization and increase in the number of pins.

  In order to achieve the above object, in the method of manufacturing a semiconductor package of the present invention, a step of forming a wiring pattern on the surface of a substrate made of a conductive material and forming an external terminal on the back surface of the substrate, Mounting the semiconductor chip on the surface of the semiconductor chip, electrically connecting the semiconductor chip and the wiring pattern, sealing the semiconductor chip with an insulating material, and etching the substrate. Forming a conductive path connecting the pattern and the external terminal.

  Here, a wiring pattern is formed on the surface of the substrate, the semiconductor chip is mounted on the surface of the substrate, the semiconductor chip and the wiring pattern are electrically connected, and the semiconductor chip is sealed with an insulating material, and then the substrate By etching the wiring pattern, the wiring pattern can remain in the insulating material after the substrate is etched.

  In addition, by etching a substrate made of a conductive material to form a conductive path that connects the wiring pattern and the external terminal, the external terminal formed on the back surface of the substrate is electrically connected to the semiconductor chip. Can do.

  In the method for manufacturing a semiconductor package of the present invention, a through hole is formed in a predetermined region of the substrate, a wiring pattern is formed on the surface of the substrate, an external terminal is formed on the back surface of the substrate, and the through hole is formed. Forming a conductive film electrically connecting the wiring pattern and the external terminal on the inner wall of the hole; mounting a semiconductor chip on the surface of the substrate; and electrically connecting the semiconductor chip and the wiring pattern A step of connecting, a step of sealing the semiconductor chip with an insulating material, and a step of etching the substrate.

  Here, a through hole is formed in a predetermined region of the substrate, a wiring pattern is formed on the surface of the substrate, an external terminal is formed on the back surface of the substrate, and the wiring pattern and the external terminal are electrically connected to the inner wall of the through hole. Forming a conductive film, then mounting the semiconductor chip on the surface of the substrate, sealing the semiconductor chip with an insulating material in a state where the semiconductor chip and the wiring pattern are electrically connected, and then etching the substrate Thus, after the substrate is etched, the wiring pattern can remain in the insulating material, and the external terminal formed on the back surface of the substrate can be electrically connected to the semiconductor chip through the conductive film.

  In the semiconductor package manufacturing method of the present invention, the wiring pattern formed on the surface of the substrate remains in the insulating material even after the substrate is etched, so that the wiring pattern of the semiconductor chip in the semiconductor package can be fine pitched, and the semiconductor package The downsizing and the increase in the number of pins will be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining an example of a method for manufacturing a semiconductor package to which the present invention is applied. In an example of a method for manufacturing a semiconductor package to which the present invention is applied, first, as shown in FIG. Using a general-purpose photolithography technique, a plating resist 2 that functions as a mask material is formed on the front and back surfaces of the copper plate 1.

  Next, a nickel plating layer is formed on the front and back surfaces of the copper plate exposed by nickel plating, and then a gold plating layer is formed on the nickel plating layers on the front and back surfaces of the copper plate exposed by gold plating. (See FIG. 1B.) Subsequently, the plating resist is removed to form the wiring pattern 3 made of the Ni—Au plating layer on the surface of the copper plate, and the Ni—Au plating on the back surface of the copper plate. External terminals 4 made of layers are formed (see FIG. 1C).

  Note that when the nickel plating layer and the gold plating layer are formed, the copper plate is made to function as a seed layer (plating lead) to perform electrolytic plating.

  Next, as shown in FIG. 1 (d), the semiconductor chip 5 is mounted on the wiring pattern 3 formed on the surface of the copper plate by flip chip connection, and then the gap between the copper plate and the semiconductor chip using the dispenser 15. The underfill material 6 is applied to the substrate and the underfill material is cured (see FIG. 1E).

  In this embodiment, the case where the semiconductor chip is mounted on the wiring pattern by flip chip connection is described as an example. However, it is sufficient if the semiconductor chip can be mounted on the wiring pattern. Therefore, it is not always necessary to mount the semiconductor chip by flip-chip connection. The semiconductor chip may be mounted on the wiring pattern by a face-up method, and the semiconductor chip and the wiring pattern may be electrically connected by wire bonding processing. Absent.

  In this embodiment, the case where the underfill material is applied using a dispenser is described as an example. However, it is sufficient if the gap between the copper plate and the semiconductor chip can be filled with an insulating material. However, it is not always necessary to apply the underfill material using a dispenser, and sealing with a sheet resin or transfer molding technology may be used.

  Subsequently, after the protective tape 7 is bonded to the back surface of the semiconductor chip, the semiconductor chip is sealed with a mold resin such as an epoxy resin by using a general-purpose transfer molding technique (see FIG. 2F).

  Here, in this embodiment, the case where the semiconductor chip is sealed using the transfer mold technique is described as an example. However, it is sufficient if the semiconductor chip can be sealed, and the transfer mold is not necessarily required. It is not necessary to seal using a technique, and sealing using a potting technique or sealing using a sheet resin may be used.

  Further, in this embodiment, the case where the semiconductor chip is sealed again after applying the underfill material in the gap between the copper plate and the semiconductor chip is taken as an example. The gap between the copper plate and the semiconductor chip may be filled with an insulating material and the semiconductor chip may be sealed.

  In this embodiment, a case where a protective tape is bonded to protect the back surface of the semiconductor chip is described as an example, but the protective tape is not necessarily required.

Next, the external terminal formed on the back surface of the copper plate is made to function as an etching mask, and copper chloride (CuCl ₂ ), iron chloride (FeCl ₃ ), or alkali etchant (Cu (NH ₃ ) ₄ Cl ₂ ) is used as an etching solution. Then, by selectively etching the copper plate, the wiring pattern formed on the surface of the copper plate is left in the underfill material, and the conductive path 8 that electrically connects the wiring pattern and the external terminal is formed (FIG. 2 (g).)

  Subsequently, by using a general-purpose transfer mold technique, the conductive path is sealed with a mold resin 9 such as an epoxy resin, and the solder bumps 10 are formed on the external terminals, so that the combined body 11 of the semiconductor package can be obtained ( (See FIG. 2 (h)).

  The sealing here is sufficient as long as the conductive path can be sealed, and it is not always necessary to use the transfer mold technique. A solder resist may be applied, or the potting method may be used for sealing. However, in consideration of productivity, it is considered that sealing by a transfer mold technique is preferable.

  Thereafter, the dicing tape 12 is bonded to the combined body of the semiconductor package, and as shown in FIG. 2 (i), the combined body of the semiconductor package is separated into pieces by the dicing blade 13, as shown in FIG. 2 (j). A simple semiconductor package can be obtained. FIG. 2J shows a cross-sectional view and a bottom view of the semiconductor package.

  In an example of a method for manufacturing a semiconductor package to which the present invention is applied, a lead frame is not formed by etching a copper plate, but a wiring pattern formed by plating is used. (For example, a pitch of 150 μm or less) is possible, and the semiconductor package can be downsized and the number of pins can be increased.

  In addition, by forming external terminals on the back surface of the copper plate corresponding to the mounting area of the semiconductor chip, the area under the semiconductor chip that cannot be used in the conventional semiconductor package using the lead frame is also effectively utilized. As a result, the semiconductor package can be reduced in size.

  FIG. 3 is a schematic diagram for explaining another example of a semiconductor package manufacturing method to which the present invention is applied. In another example of a semiconductor package manufacturing method to which the present invention is applied, first, FIG. As shown, the through hole 14 is formed in the copper plate 1 by die processing.

  Moreover, the resist 2 for plating which functions as a mask material is formed in the front and back of the copper plate 1 using a general-purpose photolithography technique (refer FIG.3 (b)).

  Next, a nickel plating layer is formed on the front and back surfaces of the copper plate exposed through nickel plating and the inner walls of the through holes, and then the nickel on the front and back surfaces of the copper plate exposed through gold plating and the inner walls of the through holes. A gold plating layer is formed on the plating layer (see FIG. 3C), and then the plating resist is removed to form a wiring pattern 3 made of a Ni—Au plating layer on the surface of the copper plate. The external terminals 4 made of Ni—Au plating layer are formed on the back surface of the copper plate, and the conductive film 16 made of Ni—Au plating layer is formed on the inner wall of the through hole (see FIG. 3D).

  Note that when the nickel plating layer and the gold plating layer are formed, the copper plate is made to function as a seed layer (plating lead) to perform electrolytic plating.

  Next, as shown in FIG. 3E, the semiconductor chip 5 is mounted on the wiring pattern 3 formed on the surface of the copper plate by a face-up method, and an electrode (not shown) and the wiring pattern of the semiconductor chip are mounted. Wire bonding process for electrical connection is performed.

  In this embodiment, the wiring pattern is formed so that the bonding region (the portion indicated by the symbol A in FIG. 5) in the wiring pattern is electrically connected to the conductive film provided in the semiconductor chip mounting region. The semiconductor chip is formed (see FIG. 5A), and the semiconductor chip mounted on the wiring pattern by the face-up method is subjected to wire bonding processing (see FIG. 5B). External terminals formed in the region can be utilized.

  Here, in this embodiment, the case where the semiconductor chip is mounted on the wiring pattern by the face-up method and the semiconductor chip and the wiring pattern are electrically connected by wire bonding processing is described as an example. It is sufficient if the semiconductor chip can be mounted on the wiring pattern, and it is not always necessary to mount the semiconductor chip on the wiring pattern by the face-up method. The semiconductor chip is mounted on the wiring pattern by flip chip connection. Also good.

  Subsequently, the semiconductor chip is sealed with a mold resin such as an epoxy resin by using a general-purpose transfer mold technique (see FIG. 3F).

  Here, in this embodiment, the case where the semiconductor chip is sealed using the transfer mold technique is described as an example. However, it is sufficient if the semiconductor chip can be sealed, and the transfer mold technique is not necessarily required. There is no need to seal using a potting, and sealing using a potting technique may be used.

Next, the copper plate is completely removed by performing selective etching of the copper plate using copper chloride (CuCl ₂ ), iron chloride (FeCl ₃ ), or alkali etchant (Cu (NH ₃ ) ₄ Cl ₂ ) as an etching solution. As a result, the wiring pattern formed on the surface of the copper plate remains in the mold resin (see FIG. 4G).

  Subsequently, the conductive film is sealed with a mold resin 9 such as an epoxy resin by using a general-purpose transfer mold technique (see FIG. 4H), and solder bumps 10 are formed on the external terminals, so that the semiconductor package is formed. A conjugate 11 can be obtained (see FIG. 4I).

  The sealing here is sufficient as long as the conductive film can be sealed, and it is not always necessary to use the transfer mold technique, and the potting method may be used. In such a case, it is considered that sealing by transfer molding technique is preferable.

  Thereafter, as shown in FIG. 4 (j), a semiconductor package as shown in FIG. 4 (k) can be obtained by separating the combination of the semiconductor packages into pieces by the dicing blade 13. FIG. 4 (k) shows a cross-sectional view and a bottom view of the semiconductor package.

  In another example of the method for manufacturing a semiconductor package to which the present invention is applied, the semiconductor package can be reduced in size and increased in number of pins, as in the example of the semiconductor package to which the present invention is applied.

  In addition, since the through hole is formed in the copper plate and the electrical connection between the wiring pattern and the external terminal is ensured by the conductive film formed on the inner wall of the through hole, the electrical connection between the wiring pattern and the external terminal is ensured. Compared with the case where the conductive path formed by the etching process is used, it is possible to cope with a fine pitch.

It is a schematic diagram (1) for demonstrating an example of the manufacturing method of the semiconductor package to which this invention is applied. It is a schematic diagram (2) for demonstrating an example of the manufacturing method of the semiconductor package to which this invention is applied. It is a schematic diagram (1) for demonstrating another example of the manufacturing method of the semiconductor package to which this invention is applied. It is a schematic diagram (2) for demonstrating another example of the manufacturing method of the semiconductor package to which this invention is applied. It is a schematic diagram for demonstrating a wiring pattern. It is a schematic diagram for demonstrating a QFN type semiconductor package. It is a schematic diagram for demonstrating the manufacturing process of a QFN type semiconductor package. It is a schematic diagram for demonstrating the etching of a lead frame.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Copper plate 2 Resist for plating 3 Wiring pattern 4 External terminal 5 Semiconductor chip 6 Underfill material 7 Protective tape 8 Conductive path 9 Mold resin 10 Solder bump 11 Semiconductor package assembly 12 Dicing tape 13 Dicing blade 14 Through-hole 15 Dispenser 16 Conductivity film

Claims (5)

Forming a wiring pattern on the surface of the substrate made of a conductive material, and forming an external terminal on the back surface of the substrate;
Mounting a semiconductor chip on the surface of the substrate and electrically connecting the semiconductor chip and the wiring pattern;
Sealing the semiconductor chip with an insulating material;
Forming a conductive path connecting the wiring pattern and the external terminal by etching the substrate; and a method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package according to claim 1, wherein the conductive path is formed by etching the substrate with the external terminal functioning as an etching mask. The method of manufacturing a semiconductor package according to claim 1, wherein the external terminal is also formed in a region corresponding to a mounting region of the semiconductor chip. Forming a through hole in a predetermined region of the substrate;
Forming a wiring pattern on the surface of the substrate, forming an external terminal on the back surface of the substrate, and forming a conductive film electrically connecting the wiring pattern and the external terminal on the inner wall of the through hole; ,
Mounting a semiconductor chip on the surface of the substrate and electrically connecting the semiconductor chip and the wiring pattern;
Sealing the semiconductor chip with an insulating material;
And a step of etching the substrate. The method of manufacturing a semiconductor package according to claim 4, wherein the external terminal is also formed in a region corresponding to a mounting region of the semiconductor chip.

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