JP2014138155A - Semiconductor element mounting substrate and semiconductor device - Google Patents
Semiconductor element mounting substrate and semiconductor device Download PDFInfo
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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Abstract
Description
本発明は、金属板の片面側からハーフエッチング加工を行なって柱状形状を形成した半導体素子搭載用基板とその基板を用いた半導体装置に関する。 The present invention relates to a semiconductor element mounting substrate in which a columnar shape is formed by half-etching from one side of a metal plate and a semiconductor device using the substrate.
近年半導体パッケージには携帯機器向けを中心に小型化への要求がさらに強まっており、様々なパッケージ構造および製造方法の提案がなされている。
これらはCSP(Chip Scale Package)と呼ばれ、半導体素子に直接外部接続端子を形成するものや、樹脂基板やリードフレーム等を用いて外部接続端子を形成するものがある。
In recent years, semiconductor packages have been increasingly demanded for downsizing mainly for portable devices, and various package structures and manufacturing methods have been proposed.
These are called CSP (Chip Scale Package), and some of them form an external connection terminal directly on a semiconductor element, and some form an external connection terminal using a resin substrate, a lead frame or the like.
その中でリードフレームを用いるパッケージは多種提案されているが、多ピンに対応できるものとして、例えば特許文献1に開示されるパッケージがある。
特許文献1に記載のパッケージは、銅合金の片面を半導体搭載部や端子部などを残して、それ以外の箇所をハーフエッチングし、半導体搭載部に半導体素子を載せ、外部端子との接続を行って樹脂封止した後、反対側からエッチングを施し、パッケージを完成させるものである。
この方法によれば、端子数が100ピン以上の半導体を小型パッケージに収めることができる。
Among them, a variety of packages using a lead frame have been proposed, but there is a package disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-151620 as one that can handle multiple pins.
In the package described in
According to this method, a semiconductor having 100 pins or more can be accommodated in a small package.
しかし、この半導体パッケージ用基板の製造工程において、特許文献1にあるような端子側面に凹部のあるモールドロック形状を、通常の半導体素子搭載パッド41aで見られる大面積の四辺形で、四隅が円弧で構成されるパターン以外のパターンに付与する事は困難である(図1参照)。
また、一部のパッケージデザインにおいては、図2に示すようなダイパッド41bにモールドロック形状を有さない半導体パッケージ用基板もある。
図1、2において、8は半導体素子、40a、40bは半導体パッケージ、32a、32bは半導体素子搭載用基板、41aは半導体素子搭載パッド、41bはダイパッド、42は接続端子、43はボンディングパッド、44は外部接続端子部、10はボンディングワイヤ、11は封止樹脂である。
However, in the manufacturing process of the semiconductor package substrate, the mold lock shape having a recess on the side of the terminal as in
Further, in some package designs, there is a semiconductor package substrate in which the
1 and 2, 8 is a semiconductor element, 40a and 40b are semiconductor packages, 32a and 32b are semiconductor element mounting substrates, 41a is a semiconductor element mounting pad, 41b is a die pad, 42 is a connection terminal, 43 is a bonding pad, 44 Are external connection terminal portions, 10 is a bonding wire, and 11 is a sealing resin.
このように、図1や図2に示す従来の半導体パッケージ用基板を用いた半導体パッケージでは、ダイパッド41bの樹脂封止後の端子引き抜き強度が不足し、組み立て後の強度確認試験において、半導体素子8が脱落するなどの問題が生じていた。
そこで、本発明は、上記従来の諸問題である、ダイパッドの樹脂封止後の端子引き抜き強度不足を解消した基板を提供するものである。
Thus, in the semiconductor package using the conventional semiconductor package substrate shown in FIG. 1 or FIG. 2, the terminal pull-out strength after resin sealing of the
Accordingly, the present invention provides a substrate that solves the above-described problems of the conventional art and that lacks the terminal pull-out strength after resin sealing of the die pad.
このような状況に鑑み、本発明の第1の発明は、金属板の片面側からハーフエッチング加工を行い、柱状部形状の端子を形成する半導体素子搭載用基板において、半導体素子を搭載するパッド部に、その柱状部形状の端子を有することを特徴とする半導体素子搭載用基板である。 In view of such a situation, the first invention of the present invention is a pad for mounting a semiconductor element in a semiconductor element mounting substrate in which half-etching is performed from one side of a metal plate to form a columnar terminal. In addition, the semiconductor element mounting board includes a terminal having a columnar shape.
本発明の第2の発明は、第1の発明における柱状部形状の端子が、半導体素子を外囲する配置で設けられ、ダイパッドと連結されていることを特徴とする半導体素子搭載用基板である。 According to a second aspect of the present invention, there is provided a substrate for mounting a semiconductor element, wherein the columnar portion-shaped terminals according to the first aspect of the present invention are provided so as to surround the semiconductor element and are connected to a die pad. .
本発明の第3の発明は、第1及び第2の発明における柱状部形状の端子の平面形状が、円形もしくは角部が円弧で形成された矩形であることを特徴とする半導体素子搭載用基板である。 According to a third aspect of the present invention, the planar shape of the columnar terminal in the first and second aspects of the present invention is a semiconductor element mounting substrate characterized in that the planar shape is a circle or a rectangle with corners formed by arcs. It is.
本発明の第4の発明は、半導体素子搭載側から半導体素子用搭載基板のパッド部に、柱状部形状を形成するハーフエッチング加工が施され、そのハーフエッチング加工された凹部位に封止樹脂が充填されていることを特徴とする半導体装置である。 According to a fourth aspect of the present invention, a half etching process for forming a columnar part shape is applied to a pad part of a semiconductor element mounting substrate from the semiconductor element mounting side, and a sealing resin is provided in the recessed part where the half etching process is performed. The semiconductor device is filled.
本発明による基板を用いることによって、半導体素子搭載パッドと封止樹脂との密着力を十分に確保することが可能となり、半導体パッケージ組み立て後の半導体素子脱落不具合を大きく低減する効果を奏する。 By using the substrate according to the present invention, it is possible to sufficiently secure the adhesion between the semiconductor element mounting pad and the sealing resin, and the effect of greatly reducing the problem of dropping off the semiconductor element after assembling the semiconductor package is achieved.
本発明の半導体素子搭載用基板の特徴とするところは、図6の半導体パッケージ用基板の半導体素子周囲のダミーパッド配置と形状を示す平面図に示すような半導体素子8と半導体素子搭載面側のボンディングパッド(図示せず)との間に一定間隔で半導体素子8を外囲するように、例えば図6(a)〜(d)に示すような任意の大きさ、形状のダミー端子21をパターン状に配置し、そのパターン状に配置されたダミー端子21は、外部接続端子面側のダイパッドパターン(図示せず)にてダイパッド(図示せず)と連結されている。
The semiconductor element mounting substrate of the present invention is characterized in that the
図6のような構造を採ることにより、図3に示すように樹脂封止後のダイパッドの封止樹脂に対するモールドロック力は、半導体素子搭載パッド1aのモールドロック形状に加えて、その半導体搭載パッド外周部のダイパッド1bの領域にパターン状に設けたダミー端子21のモールドロック形状も半導体素子8と封止樹脂11との密着性に寄与させることで、封止樹脂からの半導体素子の脱落を防止できる基板構造であり、半導体素子搭載パッド1aとダミー端子21が形成する凹部21aに、封止樹脂11が充填された半導体パッケージ20aとなっている。
By adopting the structure as shown in FIG. 6, as shown in FIG. 3, the mold locking force of the die pad after resin sealing to the sealing resin is in addition to the mold lock shape of the semiconductor
また、図4に見られるようなダイパッド1bにモールドロック形状を持たないパッケージにおいても、その周囲にパターン状に設けたモールドロック形状のダミー端子21及び内部接続端子22を配置する事で、半導体素子8と封止樹脂11との密着強度を改善し、封止樹脂からの半導体素子の脱落を防止できる基板構造となっている。
図3、図4において、8は半導体素子、10はボンディングワイヤ、11は封止樹脂、12a、12bは半導体素子搭載用基板、20a、20bは半導体パッケージ、23はボンディングパッド、24は外部接続端子である。
Further, even in a package that does not have a mold lock shape in the
3 and 4, 8 is a semiconductor element, 10 is a bonding wire, 11 is a sealing resin, 12a and 12b are semiconductor element mounting substrates, 20a and 20b are semiconductor packages, 23 is a bonding pad, and 24 is an external connection terminal. It is.
次に、本発明の実施の形態について説明する。
本発明の半導体素子搭載用基板は、板厚100〜200μmの金属板表裏面に所定形状のめっき層を形成し、その表面側に形成しためっき層を覆うレジストマスクを形成し、裏面側はめっきのない部分、特に最終のエッチング時にエッチング速度の遅くなる部分が開口するようにレジストマスクを形成し、両面からハーフエッチング加工を行い、金属板の深さ方向に板を貫通しないように50〜100μm溶解除去して柱状部を形成するものである。
Next, an embodiment of the present invention will be described.
The substrate for mounting a semiconductor element of the present invention forms a plating layer having a predetermined shape on the front and back surfaces of a metal plate having a thickness of 100 to 200 μm, forms a resist mask covering the plating layer formed on the front surface side, and the back surface side is plated. A resist mask is formed so that there is an opening in a portion having no etching, particularly a portion where the etching rate becomes slow at the time of final etching, and half-etching processing is performed from both sides, and 50 to 100 μm so as not to penetrate the metal plate in the depth direction. The columnar part is formed by dissolution and removal.
金属板としては、一般に銅または銅合金が用いられ、通常のリードフレームで用いられている高強度のものが望ましく、また厚みはハンドリングなどを鑑み、通常100〜200μmの範囲で選択されている。 As the metal plate, copper or a copper alloy is generally used, and a high-strength metal plate used in a normal lead frame is desirable. In view of handling and the like, the thickness is usually selected in the range of 100 to 200 μm.
次に、その製造方法について図5−1、図5−2を参照しながら説明する。
図5−1(1)に示すように、金属板1の両面にドライフィルムレジスト2をラミネートする。
使用するドライフィルムレジスト2の種類、厚みは特に限定されないが、通常感光部が硬化するネガタイプのものを用いる。この他にポジタイプのドライフィルムレジストでも良い。また液状のフォトレジストを塗布することでも良い。
レジストの厚みは、形成するパターンの線幅・線間距離で決定されるが、15〜40μmの範囲を用いることが多い。
Next, the manufacturing method will be described with reference to FIGS.
As shown in FIG. 5A (1), a
The type and thickness of the dry film resist 2 to be used are not particularly limited, but a negative type resist that usually cures the photosensitive portion is used. In addition, a positive type dry film resist may be used. Alternatively, a liquid photoresist may be applied.
The thickness of the resist is determined by the line width and distance between the patterns to be formed, but a range of 15 to 40 μm is often used.
次に、図5−1(2)に示すように、金属板1の両面に所定形状の開口部3が形成されためっき用のレジストマスク2aを形成する。
先ずドライフィルムレジストに、所定位置で所定形状のめっきを形成するためのパターンを露光する。
露光マスクは、ダイパッド部周囲に樹脂封止後の密着向上のためのモールドロック用の任意形状のダミー端子パターンが配された露光マスクを使用する。
モールドロック用の任意形状のダミー端子上面部にめっきが不要な場合は本工程で使用する露光マスクにモールドロック用の任意形状のダミー端子パターンは不要である。
Next, as shown in FIG. 5A (2), a
First, a dry film resist is exposed to a pattern for forming a predetermined shape of plating at a predetermined position.
As the exposure mask, an exposure mask in which a dummy terminal pattern of an arbitrary shape for mold lock for improving adhesion after resin sealing is arranged around the die pad portion is used.
If plating is not required on the upper surface of the dummy terminal having an arbitrary shape for mold lock, an arbitrary shape dummy terminal pattern for mold lock is not required for the exposure mask used in this step.
露光は、一般的な方法で行われる。
先ず、ドライフィルムレジストにパターンを形成したフォトマスクを密着させ、紫外線を照射することでフォトマスクのパターンをドライフィルムレジストに露光する。
照射量は20〜100mJ/cm2程度である。このとき、半導体素子が搭載される面側となる表面側と反対側の外部接続端子となる裏面側が区別される。
The exposure is performed by a general method.
First, a photomask having a pattern formed thereon is brought into close contact with the dry film resist, and the pattern of the photomask is exposed to the dry film resist by irradiating with ultraviolet rays.
The irradiation amount is about 20 to 100 mJ / cm 2 . At this time, the rear surface side which is the external connection terminal on the opposite side to the front surface side which is the surface side on which the semiconductor element is mounted is distinguished.
露光後、現像する。現像には、アルカリ現像型のフォトレジストを用いる場合は通常1%程度の濃度の炭酸ナトリウムを用いる。
このようにして金属板1の両面に所定形状の開口部3が形成されためっき用のレジストマスク2aが形成される。
Develop after exposure. For the development, when an alkali development type photoresist is used, sodium carbonate having a concentration of about 1% is usually used.
In this way, a resist
次に図5−1(3)に示すように、レジストマスク2aの開口部3に、めっきを行なう。
めっきの金属は、耐熱性、半導体素子との接続のためのワイヤボンディング性、およびプリント基板実装時の半田ぬれ性などで適宜選択される。
通常は電気めっきで、Ni、Pd、Au、Agのいずれか、若しくは積層となるようにめっきして、めっき層4を形成する。
Next, as shown in FIG. 5A (3), the
The metal for plating is appropriately selected depending on heat resistance, wire bonding property for connection with a semiconductor element, solder wettability when mounted on a printed circuit board, and the like.
Usually, the
その後、レジストマスクを剥離する。
剥離には、アルカリ現像型のフォトレジストを用いている場合は通常4%程度の濃度の水酸化ナトリウムを用いる。
この工程は予めボンディング性や実装性向上のためにめっきが必要な場合に適用するが、エッチング後にめっきする場合、もしくはめっきが必要ない場合は省略しても良い。
Thereafter, the resist mask is peeled off.
For stripping, when an alkali development type photoresist is used, sodium hydroxide having a concentration of about 4% is usually used.
This step is applied in advance when plating is necessary for improving bonding properties and mountability, but may be omitted when plating is performed after etching or when plating is not necessary.
次に図5−1(4)に示すように、表面側は形成しためっき層4より大きなレジストマスク5を形成し、反対面の裏面側は、全面を覆うようにレジストマスク6を形成する
このレジストマスク形成のための露光マスクは、ダイパッド部周囲に樹脂封止後の密着向上のためのモールドロック用任意形状のダミー端子パターンが配された露光マスクを使用する。この方法は前述のラミネート、露光、現像と同様である。
そして、ハーフエッチング処理の後に端子上端部にめっきのバリが出来ないように、エッチング量や露光の位置ズレを考慮した上でめっきより大きいレジストを形成する。
Next, as shown in FIG. 5A (4), a resist
Then, a resist larger than the plating is formed in consideration of the etching amount and the positional deviation of the exposure so that the burrs of the plating cannot be formed at the upper end portion of the terminal after the half etching process.
次に図5−1(5)に示すように、表面側のレジストマスク開口部5aからハーフエッチングを行ない、モールドロック形状の柱状部7を形成する。
エッチング液は、エッチング抑制剤を含んだエッチング液を用いても良い。このエッチング抑制剤としては、例えばアゾール系化合物が挙げられる。
なお、柱状部7のモールドロック形状とは、図3、4のダミー端子21、内部接続端子22に示されるような漏斗状の上部が末広がりの形状が望ましい。
Next, as shown in FIG. 5A (5), half-etching is performed from the resist
As the etching solution, an etching solution containing an etching inhibitor may be used. Examples of the etching inhibitor include azole compounds.
The mold lock shape of the
次に図5−2(6)に示すように、表裏のレジストマスクを剥離することで半導体素子搭載用基板12が得られる。ここで、7a、7c、9は、半導体素子搭載用基板において、それぞれ内部接続端子、外部接続端子、ダイパッド部に設けられたモールドロック形状のダミー端子である。
この得られた半導体素子搭載用基板12の表面側に半導体素子8を、ダイペースト等を介して搭載し、半導体素子8とモールドロック形状の内部接続端子7aの端子部(ボンディングパッド7b)をボンディングワイヤ10によりワイヤボンディングする。
使用するダイペーストは、銀ペーストが用いられることが多く、ワイヤボンディングは、金ワイヤや銅ワイヤなどの直径20〜40μmの太さのワイヤが用いられる。また半導体素子8と内部接続端子7aとの接続はいわゆるフリップチップでも良い。
そして、次にエポキシ樹脂等の封止樹脂11を用いて金属材の表面側を樹脂封止する(図5−2(7)参照)。
Next, as shown in FIG. 5-2 (6), the semiconductor
The
A silver paste is often used as the die paste to be used, and a wire having a diameter of 20 to 40 μm, such as a gold wire or a copper wire, is used for wire bonding. The connection between the
Then, the surface side of the metal material is resin-sealed using a sealing
樹脂封止後、図5−2(8)に示すように、裏面側に形成しためっきをエッチングマスクとして用い、金属材をエッチング加工して、モールドロック形状の内部接続端子7a、ダミー端子9、外部接続端子7cの端子部を分離独立させる。
そして、ダイシングなどの方法で個々のパッケージサイズに切断する。
このようにして、ダイパッド部と封止樹脂との密着力が強固な半導体パッケージ20を得る。
After resin sealing, as shown in FIG. 5-2 (8), using the plating formed on the back side as an etching mask, the metal material is etched to form mold-locked
Then, it is cut into individual package sizes by a method such as dicing.
In this manner, the
本発明の半導体素子搭載用基板を、図5−1及び図5−2の製造工程フロー図に従って製造した。
先ず、金属板1に、板厚0.125mmの銅系合金材(古河電気工業株式会社製:EFTEC64−T)を用い、その両面にドライフィルムレジスト2(旭化成イーマテリアルズ株式会社製:AQ−2558)をラミネートした(図5−1(1)参照)。
The substrate for mounting a semiconductor element of the present invention was manufactured according to the manufacturing process flow charts of FIGS.
First, a copper-based alloy material (Furukawa Electric Co., Ltd .: EFTEC64-T) having a thickness of 0.125 mm is used for the
ラミネート後、所定パターンで両面に露光、現像を行い、めっきが必要な部分が開口されたレジストマスク2aを形成した(図5−1(2)参照)。
次に、形成したレジストマスク2aの開口部3から露出している金属板1に、Niを厚み1μm、Pdを厚み0.07μm、Auを厚み0.003μmの順でめっきして、めっき層4を形成する(図5−1(3)参照)。
After laminating, exposure and development were performed on both sides with a predetermined pattern to form a resist
Next, the
次に、レジストマスク2aを剥離し、めっき層4が形成された金属板1の両面に、前記と同じドライフィルムレジストをラミネートし、半導体素子8が搭載される表面側は、形成しためっき層4より50μm大きいパターンで露光し現像を行い、めっき層より50μm大きいレジストマスク5を形成した。
そして、反対面の裏面側は、裏面全面を保護するレジストマスク6を形成した(図5−1(4)参照)。
Next, the resist
And the resist
次に、液温40℃のエッチング液を用いて、スプレー圧0.1〜0.2MPaで3分間エッチング加工を行い、表面側から約80μmの深さまでハーフエッチングを行い、柱状部7を形成した(図5−1(5)参照)。
その後、両面のレジストマスク5、6を剥離することで半導体素子搭載用基板12が得られた(図5−2(6)参照)。
Next, using an etching solution with a liquid temperature of 40 ° C., etching was performed for 3 minutes at a spray pressure of 0.1 to 0.2 MPa, and half-etching was performed from the surface side to a depth of about 80 μm to form the
Thereafter, the resist
得られた基板12に、銀ペーストを用いて半導体素子8を搭載し、直径20μmの金のボンディングワイヤ10を用いて、半導体素子8と内部接続端子7aの端子部のボンディングパッド7bを接続し、エポキシ系の封止樹脂を用い樹脂封止11をした(図5−2(7)参照)。
樹脂封止後、アルカリ性の銅エッチング液でエッチングした(図5−2(8)参照)。
その後、ダイシング工程にて個々のパッケージサイズに裁断し、半導体パッケージを得た。
The
After the resin sealing, etching was performed with an alkaline copper etchant (see FIG. 5-2 (8)).
Then, it cut | judged to each package size at the dicing process, and obtained the semiconductor package.
本パッケージの組み立て後の端子密着強度確認試験において、ダイパッドの剥がれ、脱落は発生しなかった。 In the terminal adhesion strength confirmation test after the assembly of this package, the die pad was not peeled off or dropped off.
(比較例1)
一方比較例1として、ダイパッド周辺にモールドロック用のダミー端子を有しない基板を用いて組み立てたパッケージにおける端子密着性強度確認試験において、一部の製品にてダイパッドの封止樹脂からの抜けが確認された。
(Comparative Example 1)
On the other hand, as Comparative Example 1, in a terminal adhesion strength confirmation test in a package assembled using a substrate that does not have a mold lock dummy terminal around the die pad, it was confirmed that the die pad was not detached from the sealing resin in some products. It was done.
1 金属板
1a 半導体素子搭載パッド
1b ダイパッド
2 ドライフィルムレジスト
2a めっき用レジストマスク
3 めっきレジストマスク開口部
4 めっき層
5、6 レジストマスク
5a レジストマスク開口部
7 柱状部
7a 内部接続端子
7b ボンディングパッド
7c 外部接続端子
8 半導体素子
9 ダイパッド部に設けられたモールドロック形状のダミー端子
10 ボンディングワイヤ
11 封止樹脂
12、12a、12b 半導体素子搭載用基板
20、20a、20b、40a、40b 半導体パッケージ
21 ダミー端子
21a 凹部
22 内部接続端子
23 ボンディングパッド
24 外部接続端子
32a、32b 半導体素子搭載用基板
41a 半導体素子搭載パッド
41b ダイパッド
42 接続端子
43 ボンディングパッド
44 外部接続端子部
DESCRIPTION OF
Claims (4)
半導体素子を搭載するパッド部に、前記柱状部形状の端子を有することを特徴とする半導体素子搭載用基板。 In the semiconductor element mounting substrate that performs half-etching from one side of the metal plate and forms the columnar shaped terminal,
A substrate for mounting a semiconductor element, wherein the pad part on which the semiconductor element is mounted has the columnar terminal.
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JP2018098299A (en) * | 2016-12-09 | 2018-06-21 | 大口マテリアル株式会社 | Lead frame |
US11557548B2 (en) | 2017-08-31 | 2023-01-17 | Stmicroelectronics, Inc. | Package with interlocking leads and manufacturing the same |
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JP2008227410A (en) * | 2007-03-15 | 2008-09-25 | Mitsui High Tec Inc | Semiconductor device and manufacturing method of the same |
JP2009302209A (en) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device |
US20100258920A1 (en) * | 2009-04-10 | 2010-10-14 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
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JP2008227410A (en) * | 2007-03-15 | 2008-09-25 | Mitsui High Tec Inc | Semiconductor device and manufacturing method of the same |
JP2009302209A (en) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device |
US20100258920A1 (en) * | 2009-04-10 | 2010-10-14 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
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JP2018098299A (en) * | 2016-12-09 | 2018-06-21 | 大口マテリアル株式会社 | Lead frame |
US11557548B2 (en) | 2017-08-31 | 2023-01-17 | Stmicroelectronics, Inc. | Package with interlocking leads and manufacturing the same |
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