TWI575682B - Chip package structure and stacked chip package structure - Google Patents

Description

Chip package structure and stacked chip package structure

The present invention relates to a package structure, and more particularly to a chip package structure and a stacked chip package structure.

In today's highly developed society, human dependence on electronic products is increasing, and electronic products are demanding high speed, high quality and multi-functional processing. In addition, in order to facilitate the user to carry or save space, electronic products are trending towards light, thin, short and small. Generally, a processing unit or a control unit is generally disposed in the electronic product, wherein the processing unit or the control unit may include a semiconductor wafer and a carrier electrically connected to the semiconductor wafer. Taking the carrier as a lead frame, the semiconductor wafer can be electrically connected to the lead frame through a wire bonding process after being disposed on the lead frame, or electrically connected to the lead frame through a flip chip bonding process.

1 is a schematic cross-sectional view of a conventional wafer package structure. Referring to FIG. 1, a chip package structure 100 includes a wafer 110 and a lead frame 120, wherein the wafer The 110 is electrically connected to the lead frame 120 through a flip chip bonding process, for example. In detail, the wafer 110 is flip-chip bonded to the inner lead 122 of the lead frame 120, wherein the inner lead 122 and the outer lead 121 together define a recess 123, and the recess 123 enables the sealant to be tightly coupled to the lead frame. However, since the wafer 110 and the recess 123 are respectively located on opposite sides of the lead frame 120, such an arrangement may increase the overall thickness of the wafer package structure 100 after packaging, which is disadvantageous for the development of light and thin electronic products.

The present invention provides a wafer package structure and a stacked chip package structure having a thin overall thickness.

The present invention provides a wafer package structure including a wafer and a lead frame. The wafer has an active surface, a side surface that connects the active surface, a plurality of conductive posts on the active surface, and an elastomer on the active surface, wherein the elastomer is closer to the side surface than the conductive pillar. The leadframe has a plurality of outer leads and a plurality of horizontally extending inner pins. The outer and inner pins have inner surfaces, respectively. The inner surface of the outer lead forms a wafer receiving space with the inner surface of the inner lead. The wafer is disposed in the wafer accommodating space, wherein each of the conductive pillars is electrically connected to the corresponding inner lead, and the elastic body abuts on each of the inner leads.

In an embodiment of the invention, the chip package structure further includes an encapsulant. The encapsulant is filled into the wafer housing space and covers the active surface, the side surface, the conductive post and the elastomer of the wafer.

In an embodiment of the invention, the lead frame further has a plurality of patterns The structure is correspondingly disposed on each inner pin and located in the wafer receiving space. Each patterned structure has a positioning trench. Each of the positioning trenches exposes a portion of the corresponding inner pin such that each of the conductive pillars is located in the corresponding positioning trench and is electrically connected to the corresponding inner pin.

The present invention provides a stacked wafer package structure comprising a plurality of the above described wafer package structures. The chip package structures are stacked vertically with each other, and the lead frame of any one of the chip package structures is in contact with and electrically connected to the lead frame of another adjacent chip package structure.

In an embodiment of the invention, the stacked chip package structure further includes an encapsulant. The encapsulant is filled into each of the wafer housing spaces and covers the active surface, the side surface, the conductive posts and the elastomer of each wafer.

Based on the above, the chip package structure of the present invention embeds the wafer in the wafer housing space of the lead frame, wherein the back surface of the wafer embedded in the wafer housing space is, for example, flush with or lower than the outer lead of the lead frame. End face. Therefore, compared with the conventional chip package structure, the chip package structure of the present invention can have a thin overall thickness, which is in line with the trend of lightening and thinning of electronic products today. Similarly, the stacked chip package structure vertically stacked by the wafer package structure of the present invention can also achieve a thin overall thickness. In addition, in the process of disposing the wafer in the wafer accommodating space to electrically connect the conductive post to the inner lead, the elastic body on the active surface of the wafer can abut against the inner lead, thereby exerting a buffering effect.

The above described features and advantages of the invention will be apparent from the following description.

100, 200, 200A, 200B‧‧‧ chip package structure

110, 210‧‧‧ wafer

120, 220‧‧‧ lead frame

121, 221‧‧‧ external pins

122, 222‧‧‧ pin

123‧‧‧ dent

211‧‧‧Active surface

212‧‧‧ side surface

213‧‧‧Backside elastomer

214‧‧‧conductive column

215‧‧‧ Elastomers

221a, 222a‧‧‧ inner surface

221b, 222b‧‧‧ end face

223‧‧‧Wafer accommodating space

224‧‧‧ openings

225‧‧‧patterned structure

226‧‧‧ Positioning Ditch

230, 310‧‧‧Package colloid

300, 300A, 300B‧‧‧ stacked chip package structure

G‧‧‧ spacing

1 is a schematic cross-sectional view of a conventional wafer package structure.

2 is a cross-sectional view showing a wafer package structure in accordance with an embodiment of the present invention.

3 is a cross-sectional view showing a wafer package structure according to another embodiment of the present invention.

4 is a cross-sectional view showing a wafer package structure according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a stacked wafer package structure according to an embodiment of the present invention.

6 is a cross-sectional view showing a stacked wafer package structure according to another embodiment of the present invention.

7 is a cross-sectional view showing a stacked wafer package structure according to still another embodiment of the present invention.

2 is a cross-sectional view showing a wafer package structure in accordance with an embodiment of the present invention. Referring to FIG. 2, in the embodiment, the chip package structure 200 includes a wafer 210 and a lead frame 220, wherein the wafer 210 has an active surface 211, a side surface 212 connecting the active surface 211, and a back surface 213 opposite to the active surface 211. The elastic body 215 on the active surface 211 and the plurality of conductive pillars 214, the side surface 212 surrounds the active surface 211, and the elastic body 215 is, for example, closer to the side surface 212 than the conductive pillar 214, wherein one side edge of the elastic body 215 is substantially opposite to the side surface 212 is flush, but the invention is not limited thereto.

The elastic body 215 may include a plurality of elastic blocks, a plurality of elastic strips or at least one bullet The ring is, for example, circumferentially disposed around the conductive post 214. In this embodiment, the elastic body 215 may be pre-disposed on the active surface 211 of the wafer 210 before the wafer 210 is disposed on the lead frame 220. The material of the elastic body 215 may be resin, rubber, adhesive (DAF) or Foam, or other insulating material with the same elasticity. On the other hand, the material of the conductive pillar 214 may be selected from a material consisting of copper, gold, silver or an alloy of the above metals. Preferably, the conductive pillar 214 may be a copper or copper alloy pillar, but The invention is not limited thereto.

The lead frame 220 has a plurality of outer leads 221 and a plurality of horizontally extending inner leads 222, and the outer leads 221 are connected to the corresponding inner leads 222 and are perpendicular to each other. In detail, the outer lead 221 has an inner surface 221a, and the inner lead 222 has an inner surface 222a connected to the inner surface 221a, wherein the inner surface 221a and the inner surface 222a are substantially perpendicular to each other and collectively form a wafer receiving space 223. As shown in FIG. 2, the depth of the wafer housing space 223 is, for example, equal to the total height of the wafer 210 and the conductive pillars 214, and thus the wafer 210 is disposed on the wafer surface with its active surface 211 facing the inner surface 222a of the inner lead 222. After the space 223 is disposed, and each of the conductive pillars 214 abuts against the inner surface 222a of the corresponding inner lead 222, the back surface 213 of the wafer 210 with respect to the active surface 211 will not exceed the end surface 221b of the outer lead 221, and the wafer 210 The back surface 213 is substantially flush with the end surface 221b of the outer lead 221 . In addition, the side surface 212 of the wafer 210 disposed in the wafer housing space 223 is maintained at an appropriate spacing G from the inner surface 221a of the outer lead 221 .

Since the elastic body 215 is made of an elastic insulating material, the wafer 210 is flipped in the wafer receiving space 223 to make the respective conductive pillars 214 and the pair When the inner leads 222 are electrically connected, the elastic body 215 disposed on the active surface 211 of the wafer 210 can directly abut on the inner leads 222, thereby slowing the direct impact of the flip-chip bonding on the conductive pillars 214, thereby further Play the role of buffering. For example, the ends of the respective conductive pillars 214 for abutting the corresponding inner leads 222 may be provided with tin or solder paste (not shown), and the conductive pillars 214 may be tinned on the ends thereof or After the solder paste (not shown) abuts the corresponding inner lead 222, the solder or solder paste (not shown) on the end of each of the conductive pillars 214 is reflowed, so that the conductive pillars 214 can be electrically connected. Connected to the corresponding inner pin 222. In another embodiment, the inner surface 222a may also be provided with a thin layer of tin corresponding to the position of the conductive pillars 214 for use in flip chip bonding.

In this embodiment, the chip package structure 200 further includes an encapsulant 230, which may be made of epoxy resin (Epoxy Resin). The encapsulant 230 is filled into the wafer receiving space 223 and covers the active surface 211 of the wafer 210, the side surface 212, the conductive post 214 and the elastic body 214. As shown in FIG. 2, the encapsulant 230 filled in the wafer housing space 223 covers the inner surface 221a of the outer lead 221, the inner surface 222a of the inner lead 222, and further fills the opening 224 of the lead frame 220. The back surface 213 of the wafer 210 and a portion of the lead frame 220 (ie, the end surface 221b of the outer lead 221 and the end surface 222b of the inner lead 222) are exposed to the outside of the encapsulant 230, for example. In addition, one end surface of the encapsulant 230 is, for example, flush with the end surface 221b of the outer lead 221, and the other end surface of the encapsulant 230 with respect to the end surface is, for example, flush with the end surface 222b of the inner lead 222, so that The end faces 221b, 222b of the leads 221 and the inner leads 222 are exposed to the encapsulant 230 for subsequent electrical connection or vertical stacking.

In the case where the back surface 213 of the wafer 210 is exposed outside the encapsulant 230, It will help to quickly dissipate the heat generated by the operation of the wafer 210 to the outside world. On the other hand, since the wafer package structure 200 of the present embodiment embeds the wafer 210 in the wafer housing space 223, the overall thickness of the wafer package structure 200 can be effectively reduced.

Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

3 is a cross-sectional view showing a wafer package structure according to another embodiment of the present invention. Referring to FIG. 3, the chip package structure 200A of FIG. 3 is substantially similar to the chip package structure 200 of FIG. 2, except that the main difference between the two is that the lead frame 220 of the chip package structure 200A further has a plurality of patterned structures 225. The patterned structures 225 are disposed on the inner surface 222a of each of the inner leads 222 and are located in the wafer receiving space 223. Each patterned structure 225 has a positioning trench 226 thereon to expose a portion of the inner surface 222a of the corresponding inner lead 222. In general, the patterned structure 225 is composed of, for example, a solder mask, a photoresist material, a dielectric material, or other suitable insulating material, and is subjected to a printing process, an etching process, or a laser. The hole process defines a positioning trench 226 for limiting the conductive pillars 214 for assisting positioning through the positioning trenches 226 when the wafer 210 is flip-chip bonded.

In this embodiment, the conductive pillars on the wafer 210 can be made in the process of embedding the wafer 210 to the wafer housing space 223 by the positioning trench 226. The 214 is guided by the corresponding positioning trench 226 to accurately abut the corresponding inner lead 222. At the same time, the elastomer 215 can abut against the patterned structure 225 of each of the inner leads 222. In another embodiment, the elastomer 215 can be bonded with a die bond (DAF), so that the wafer 210 can be bonded and fixed during the flip chip process. In addition, after each of the conductive pillars 214 is located in the corresponding positioning trench 226, the wafer 210 can be initially fixed in the wafer receiving space 223, and is, for example, through a flip chip bonding process to electrically connect the wafer 210 to the lead frame. 220.

For example, the ends of the respective conductive pillars 214 for abutting the corresponding inner leads 222 may be provided with tin or solder paste (not shown), and the conductive pillars 214 may be tinned on the ends thereof or After the solder paste (not shown) abuts the corresponding inner lead 222, the solder or solder paste (not shown) on the end of each of the conductive pillars 214 is reflowed, so that the conductive pillars 214 can be electrically connected. Connected to the corresponding inner pin 222. In addition, the solder or solder paste (not shown) that is reflowed is also limited by the positioning trench 226, and does not overflow at the time of melting. As shown in FIG. 3, since the encapsulant 230 is filled into the positioning trench 226, the bonding strength between the encapsulant 230 and the lead frame 220 can be made higher, thereby preventing the encapsulation colloid 230 from being delaminated or peeled off.

4 is a cross-sectional view showing a wafer package structure according to another embodiment of the present invention. Referring to FIG. 4, the chip package structure 200B of FIG. 4 is substantially similar to the chip package structure 200A of FIG. 3, but the main difference between the two is that the depth of the wafer housing space 223 of the lead frame 220 of the chip package structure 200B is, for example, greater than The total height of the wafer 210 and the conductive pillars 214, and thus the back surface 213 of the wafer 210 disposed in the wafer housing space 223 is slightly lower than the end surface 221b of the outer lead 221 . At this time, the back of the wafer 210 Face 213 is covered, for example, by encapsulant 230.

FIG. 5 is a cross-sectional view showing a stacked wafer package structure according to an embodiment of the present invention. Referring to FIG. 5 , in the embodiment, the stacked chip package structure 300 is formed by stacking a plurality of chip package structures 200 (two schematically shown in FIG. 5 ) vertically, one of the chip package structures 200 . (the lower layer in FIG. 5) will be in contact with and electrically connected by the lead frame 220 to the inner lead 222 of the lead frame 220 of another adjacent chip package structure 200 (the upper layer in FIG. 5).

In detail, the lead frame 220 in the lower layer in FIG. 5 is offset by its respective outer lead 221 and the corresponding inner lead 222 of the lead frame 220 in the upper layer in FIG. For example, a solder or solder paste (not shown) may be disposed on the end surface 221b of each of the outer leads 221 of the lead frame 220 of the lower layer in FIG. 5, and the outer lead of the lower lead frame 220 is shown in FIG. The leg 221 is abutted against the corresponding inner lead 222 of the lead frame 220 of the upper layer in FIG. 5 by solder or solder paste (not shown) on the end surface 221b, and the end surface 221b of each outer lead 221 is reflowed. The tin material or solder paste (not shown) can electrically connect the lead frame 220 in the lower layer in FIG. 5 to the lead frame 220 in the upper layer in FIG.

It is worth mentioning that the encapsulant 310 is filled in the respective wafer accommodating spaces 223, for example, after the plurality of chip package structures 200 are vertically stacked on each other and electrically connected through the two-contact lead frames 220. The active surface 211, the side surface 212, the conductive pillars 214 and the elastic body 214 of the respective wafers 210 are coated, and the back surface 213 of the wafer 210 in the lower layer in FIG. 5 is also covered by the encapsulant 230a.

6 is a cross section of a stacked wafer package structure according to another embodiment of the present invention; schematic diagram. Referring to FIG. 6, the stacked chip package structure 300A of FIG. 6 is substantially similar to the stacked chip package structure 300 of FIG. 5, but the main difference between the two is that the chip package structure 300A is, for example, a plurality of chip package structures 200A ( Figure 6 shows schematically two) stacked vertically one above the other.

7 is a cross-sectional view showing a stacked wafer package structure according to still another embodiment of the present invention. Referring to FIG. 7, the stacked chip package structure 300B of FIG. 7 is substantially similar to the stacked chip package structure 300A of FIG. 6, but the main difference between the two is that the chip package structure 300B is, for example, a plurality of chip package structures 200B ( Figure 7 shows schematically two) stacked vertically one above the other.

In summary, the chip package structure of the present invention embeds the wafer in the wafer housing space of the lead frame, wherein the back surface of the wafer embedded in the wafer housing space is, for example, flush or lower than the lead frame. The end face of the foot. Therefore, compared with the conventional chip package structure, the chip package structure of the present invention can have a thin overall thickness, which is in line with the trend of lightening and thinning of electronic products today. Similarly, the stacked chip package structure vertically stacked by the wafer package structure of the present invention can also achieve a thin overall thickness. In addition, in the process of disposing the wafer in the wafer accommodating space to electrically connect the conductive post to the inner lead, the elastic body on the active surface of the wafer can abut against the inner lead, thereby exerting a buffering effect.

On the other hand, the lead frame of the chip package structure may have a patterned structure in which the patterned structure is disposed on the inner lead and located in the wafer receiving space. The patterned structure can have a positioning trench to expose portions of the inner leads. By locating the trenches, each of the wafers can be made in the process of embedding the wafers into the wafer housing space. The conductive post is guided by the corresponding positioning trench to accurately abut the inner lead.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

200‧‧‧ Chip package structure

210‧‧‧ wafer

211‧‧‧Active surface

212‧‧‧ side surface

213‧‧‧ back

214‧‧‧conductive column

215‧‧‧ Elastomers

220‧‧‧ lead frame

221‧‧‧External pin

222‧‧‧ inner pin

221a, 222a‧‧‧ inner surface

221b, 222b‧‧‧ end face

223‧‧‧Wafer accommodating space

224‧‧‧ openings

230‧‧‧Package colloid

G‧‧‧ spacing

Claims (11)

A chip package structure comprising: a wafer having an active surface, a side surface connecting the active surface, a plurality of conductive pillars connecting the active surface, and an elastic body connecting the active surface, wherein the elastic body is electrically conductive a lead frame is adjacent to the side surface; and a lead frame having a plurality of outer pins and a plurality of horizontally extending inner pins, the outer pins and the inner pins respectively having an inner surface, the outer leads The inner surface and the inner surface of the inner leads form a wafer accommodating space, and the wafer is disposed in the wafer accommodating space, wherein each of the conductive pillars is electrically connected to the corresponding one through a flip chip bonding process. An inner pin, and the elastic body abuts on each of the inner pins. The chip package structure of claim 1, further comprising: an encapsulant filled in the wafer accommodating space, and covering the active surface of the wafer, the side surface, the conductive pillars and the Elastomer. The wafer package structure of claim 2, wherein the wafer further has a back surface opposite to the active surface, the encapsulant coating the back surface and exposing a portion of the lead frame. The wafer package structure of claim 2, wherein the wafer further has a back surface opposite to the active surface, the encapsulant exposing the back surface and exposing a portion of the lead frame. The chip package structure of claim 2, wherein the side surface of the wafer is spaced apart from the inner surface of the outer leads of the lead frame. The chip package structure of claim 1, wherein the wire The frame further has a plurality of patterned structures correspondingly disposed on the inner leads and located in the wafer receiving space, each of the patterned structures having a positioning trench, and each of the positioning trenches exposes a corresponding portion of the inner lead a foot such that each of the conductive posts is limited to the corresponding positioning trench and electrically connected to the corresponding inner lead. The chip package structure of claim 6, wherein each of the patterned structures is a dielectric material. The chip package structure of claim 6, wherein the elastomer abuts the patterned structure on each of the inner leads. The wafer package structure of claim 1, wherein the elastomer comprises a plurality of elastic blocks, a plurality of elastic strips or at least one elastic ring. A stacked chip package structure comprising: a plurality of chip package structures according to claim 1, wherein the chip package structures are vertically stacked with each other, and the lead frame of any of the chip package structures and adjacent ones The lead frame of the chip package structure is in contact with and electrically connected. The stacked chip package structure of claim 10, further comprising: an encapsulant filled in each of the wafer accommodating spaces, and covering the active surface, the side surface, and the Conductive column and the elastomer.