JP2009123852A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a semiconductor device including a thin film transistor capable of being manufactured with high yield and high precision; and a manufacturing method thereof, by forming an alignment mark for producing the semiconductor device with high yield, without increasing the number of processes for producing the semiconductor device. <P>SOLUTION: This semiconductor device is a semiconductor device 1 in which a polycrystalline silicon semiconductor film 13 and an alignment mark 4 made of a silicon film 5 defined as a graphic at least by silicon phases 6a, 6p having surfaces different from each other are formed on a substrate 10. These different silicon phases 6a, 6p are a polycrystalline silicon phase 6p and an amorphous silicon phase 6a. Such different silicon phases 6a, 6p can be formed by a method including: forming a mask pattern A for forming a polycrystalline silicon semiconductor film 13 in a semiconductor element part 2; forming a mask pattern B for forming an alignment mark 4 in an alignment mark part 3; and implanting ions from above the mask patterns A, B to convert at least the surface of an exposed part of the polycrystalline silicon film which is not covered by the mask patterns A, B to an amorphous silicon phase. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a high yield and accuracy without increasing the number of steps for an alignment mark for manufacturing the semiconductor device with a high yield, and a method for manufacturing the same.

  In an active matrix driving type display device, a semiconductor device including a polycrystalline silicon thin film transistor (hereinafter referred to as “polycrystalline silicon TFT”) includes a switching element provided in each pixel and a peripheral circuit on a display substrate of the display device. Is used as a circuit element constituting the. Liquid crystal display panels, one of active matrix drive type display devices, are often used for mobile display applications such as mobile phones and PDAs. In recent years, the use of plastic substrates instead of glass substrates has further reduced weight. In addition, a low-cost semiconductor device having shock resistance is desired.

In such a semiconductor device, the alignment for accurately forming (or patterning) each layer in a predetermined position by accurately aligning the substrate and the photomask at the periphery of the semiconductor element portion where the semiconductor element is formed. A mark is formed. For example, in Patent Document 1, when a TFT of a flat display device is manufactured, a conductive film formed on a glass substrate is subjected to pattern etching to form a scanning signal line and a gate electrode, and at the same time, the conductive film is subjected to pattern etching. It has been proposed to form alignment marks. Further, in Patent Document 2, a step portion formed at the boundary between a silicon portion and a silicon oxide film portion is used as an alignment mark at the time of manufacturing a semiconductor device (paragraph 0004 of the same document), or an antioxidant film. It has been proposed to use an edge step between the LOCOS oxide film and the LOCOS oxide film as an alignment mark (paragraph 0012 of the same document).
JP-A-2-234116 (FIG. 1) JP-A-2004-319637 (paragraphs 0004 and 0012)

  The alignment mark proposed in Patent Document 1 can be formed at the same time when a conductive film is first formed on a glass substrate and the conductive film is etched to form a scanning signal line and a gate electrode. When a silicon film is first formed on a substrate and a channel region is formed by performing ion implantation and activation treatment on the silicon film, the silicon film is dry-etched to form an alignment mark, and the alignment is performed. In general, a film to be provided thereafter is accurately patterned by aligning a mark and a photomask. In such a case, dry etching only for forming the alignment mark is performed as an additional process, and the presence of the dry etching process contributes to the deterioration of the yield.

  Also in Patent Document 2, since the formation of the alignment mark composed of the stepped portion is an additional process, the presence of the alignment mark forming process contributes to the deterioration of the yield.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an alignment mark for manufacturing a semiconductor device including a thin film transistor with a high yield without increasing the number of processes and with a high yield and accuracy. A semiconductor device and a manufacturing method thereof are provided.

  In order to solve the above problems, a semiconductor device according to the present invention includes a polycrystalline silicon semiconductor film and an alignment mark formed of a silicon film patterned with a silicon phase having at least a different surface formed on a substrate. Features.

  According to the present invention, the alignment mark formed on the substrate is composed of a silicon film that is patterned with a silicon phase having at least a different surface. Such a structure is formed of polycrystalline silicon at a position where the alignment mark is formed. Since it can be obtained by ion implantation after providing a mask pattern on the film, it does not require the conventional additional process of forming an alignment mark by dry etching the silicon film formed on the substrate Presents. As a result, since the semiconductor device of the present invention can be obtained by omitting the dry etching process that contributes to the deterioration of the yield, the yield and accuracy can be improved.

  As a preferred aspect of the semiconductor device of the present invention, the different silicon phases are configured to be a polycrystalline silicon phase and an amorphous silicon phase.

  According to the present invention, different silicon phases are composed of a polycrystalline silicon phase and an amorphous silicon phase, and such a structure is similar to the above in that a mask pattern is formed on a polycrystalline silicon film at a site where an alignment mark is to be formed. The silicon film which is obtained by ion implantation after the formation of the film and is patterned in both phases has a sufficient contrast difference to be recognized as an alignment mark.

  As a preferred aspect of the semiconductor device of the present invention, the different silicon phases are configured to be 30% or more and 60% or less in a difference in reflection spectrum.

  According to the present invention, a figure having a reflection spectrum difference of 30% or more and 60% or less made of different silicon phases has a contrast difference sufficient to be recognized as an alignment mark.

  As a preferred aspect of the semiconductor device of the present invention, the polycrystalline silicon semiconductor film and the alignment mark are configured to be provided on the substrate via a buffer film.

A method of manufacturing a semiconductor device according to the present invention for solving the above-described problem is a method of manufacturing a semiconductor device in which a semiconductor element portion having a polycrystalline silicon semiconductor film and an alignment mark portion having an alignment mark are formed on a substrate. Because
A step of forming an amorphous silicon film on the substrate; a step of polycrystallizing the amorphous silicon film to form a polycrystalline silicon film; and the polycrystalline silicon film in a semiconductor element portion of the polycrystalline silicon film. Forming a mask pattern A for forming a semiconductor film and forming a mask pattern B for forming the alignment mark on the alignment mark portion of the polycrystalline silicon film; and from above the mask patterns A and B A step of implanting ions to change at least the surface of the exposed portion of the polycrystalline silicon film not covered with the mask patterns A and B into an amorphous silicon phase, and activating only the semiconductor element portion A step of forming a polycrystalline silicon semiconductor film on the portion, and a step of removing the mask patterns A and B,
Alignment marks formed with different silicon phases comprising a polycrystalline silicon phase and an amorphous silicon phase on at least the surface of the silicon film formed in the alignment mark portion by the step of changing to the amorphous silicon phase It is characterized by forming.

  In the present invention, alignment is performed by ion implantation from above the mask patterns A and B to change at least the surface of the exposed portion of the polycrystalline silicon film not covered with the mask patterns A and B into an amorphous silicon phase. Alignment marks (marks formed with different silicon phases composed of a polycrystalline silicon phase and an amorphous silicon phase) are formed on at least the surface of the silicon film formed in the mark portion. According to the present invention, since there is no need for an additional step of forming an alignment mark by dry etching a silicon film formed on a substrate as in the prior art, there is a dry etching step that contributes to a decrease in yield. Therefore, the manufacturing method can improve yield and accuracy.

  As a preferred aspect of the method for manufacturing a semiconductor device according to the present invention, only the semiconductor element portion is activated by laser annealing after shielding the alignment mark portion.

  According to the present invention, since the semiconductor element portion is activated after the alignment mark portion is shielded, the silicon film formed in a different silicon phase remains as it is. As described above, in the activation process, the alignment mark is formed by a simple method of arranging a shielding plate for shielding the laser, an absorption plate for absorbing the laser, or the like between the alignment mark portion and the laser. be able to.

  As a preferred aspect of the method for manufacturing a semiconductor device according to the present invention, the alignment mark is configured to be used in a process after the process of forming a gate insulating film on the polycrystalline silicon semiconductor film.

  According to the present invention, it is possible to accurately position the gate insulating film forming mask to be formed next to the polycrystalline silicon semiconductor film, and it is also possible to accurately form various films to be formed thereafter. .

  As a preferred aspect of the method for manufacturing a semiconductor device of the present invention, the polycrystalline silicon semiconductor film and the alignment mark are formed on the substrate via a buffer film.

  According to the semiconductor device of the present invention, an alignment mark (at least a mark made of a silicon film formed with a different silicon phase on the surface) is ion-implanted after a mask pattern is provided on the polycrystalline silicon film at the formation site. This is a structural form that does not require a conventional additional process of forming an alignment mark by dry-etching the silicon film. It is obtained by omitting. As a result, this semiconductor device has high yield and accuracy.

  Note that by combining the semiconductor device of the present invention with, for example, an organic EL element, a liquid crystal display element, or the like, a display with high yield and accuracy can be designed.

  According to the semiconductor device manufacturing method of the present invention, ions are implanted from above the mask patterns A and B, and at least the surface of the exposed portion of the polycrystalline silicon film not covered with the mask patterns A and B is amorphous silicon. Because the process of changing to a phase forms an alignment mark (marked with a different silicon phase comprising a polycrystalline silicon phase and an amorphous silicon phase) on at least the surface of the silicon film formed in the alignment mark portion. The conventional additional process of forming the alignment mark by dry etching the silicon film formed on the substrate is not required. As a result, this manufacturing method does not have a dry etching process that contributes to the deterioration of yield, and thus becomes a manufacturing method that improves yield and accuracy.

  Hereinafter, the semiconductor device and the manufacturing method thereof according to the present invention will be described in detail. However, the present invention is not limited to the form of the drawings and the following embodiments.

(Semiconductor device)
FIG. 1 is a cross-sectional view showing an example of a semiconductor device 1 of the present invention. FIG. 2 is a plan view showing an example of the alignment mark 4 formed in the alignment mark portion 3 of the semiconductor device of the present invention. As shown in FIG. 1, the semiconductor device 1 of the present invention includes a polycrystalline silicon semiconductor film 13 and an alignment mark 4 made of a silicon film 5 that is formed into a figure with at least silicon phases (6a, 6p) having different surfaces. It is formed on the substrate 10. Such a semiconductor device 1 has a semiconductor element portion 2 in which a thin film transistor (TFT) is formed, and an alignment mark portion 3 in which an alignment mark 4 is formed. For example, as a display panel constituting an active matrix drive type display device Is available.

  More specifically, the semiconductor element portion 2 of the semiconductor device 1 illustrated in FIG. 1 includes a substrate 10, an inorganic adhesion film 11 formed on the substrate 10, a buffer film 12 formed on the inorganic adhesion film 11, A polycrystalline silicon semiconductor film 13 (source side diffusion film 13s, channel film 13c and drain side diffusion film 13d) formed on the buffer film 12, and a gate insulating film 14 formed on the polycrystalline silicon semiconductor film 13; A metal electrode 15 (source electrode 15s, gate electrode 15g and drain electrode 15d) formed on the gate insulating film 14 or through a contact hole of the gate insulating film 14, and a protective film 18 covering the metal electrode 15 and the like ,have.

  On the other hand, in the alignment mark portion 3 of the semiconductor device 1 illustrated in FIG. 1, at least the surface of the silicon film 5 formed by the polycrystalline silicon phase 6 p and the amorphous silicon phase 6 a acts as the alignment mark 4. . FIG. 2A shown as an example of the alignment mark 4 is a figure formed by a polycrystalline silicon phase 6p formed in a cross shape and an amorphous silicon phase 6a formed in other portions. FIG. 2B is a diagram of a triangular polycrystalline silicon phase 6p and an amorphous silicon phase 6a.

(Manufacturing process)
In the method for manufacturing a semiconductor device 1 according to the present invention, at least a semiconductor element portion 2 having a polycrystalline silicon semiconductor film 13 (13s, 13c, 13d) and an alignment mark portion 3 having an alignment mark 4 are formed on a substrate 10. A method for manufacturing a semiconductor device. The manufacturing process includes, in order, a process of forming an amorphous silicon film 21a on the substrate 10, a process of polycrystallizing the amorphous silicon film 21a to form a polycrystalline silicon film 21p, and a polycrystalline silicon film. A mask pattern A for forming the polycrystalline silicon semiconductor film 13 is formed in the semiconductor element portion 2 of the film 21p, and a mask for forming the alignment mark 4 in the alignment mark portion 3 of the polycrystalline silicon film 21p. A step of forming pattern B and ion implantation from above mask patterns A and B change at least the surface of the exposed portion of polycrystalline silicon film 21a not covered with mask patterns A and B into an amorphous silicon phase. A step of activating only the semiconductor element portion 2 to form a polycrystalline silicon semiconductor film 13 on the semiconductor element portion 2; And a step of removing the pattern A, B. The present invention includes the polycrystalline silicon phase 6p and the amorphous silicon phase 6a on at least the surface of the silicon film formed on the alignment mark portion 3 by the process of changing to the amorphous silicon phase in such a manufacturing process. The alignment marks 4 are formed in different silicon phases.

  Hereinafter, the structure of the semiconductor element portion 2 in which the TFT having the top gate / top contact structure shown in FIG. 1 is formed will be described as an example in the order of the manufacturing steps shown in FIGS.

  First, the substrate 10 is prepared. The substrate 10 forms a support substrate for the semiconductor device 1 and may be an organic substrate or an inorganic substrate. Examples of organic substrates include polyethersulfone (PES), polyethylene naphthalate (PEN), polyamide, polybutylene terephthalate, polyethylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, polycarbonate, and polynorbornene. An organic substrate made of resin, polysulfone, polyarylate, polyamideimide, polyetherimide, thermoplastic polyimide, or the like, or a composite substrate thereof can be given. Such an organic substrate may have rigidity, or may be a thin flexible film having a thickness of about 5 μm to 300 μm. The use of a flexible plastic substrate can be applied to a film display or the like because the semiconductor device 1 having TFTs can be a flexible substrate.

  Moreover, as an inorganic substrate, a glass substrate, a silicon substrate, a ceramic substrate etc. can be mentioned, for example. The glass substrate may be a glass substrate for liquid crystal displays having a thickness of about 0.05 mm to 3.0 mm.

  Next, as shown in FIG. 3A, an inorganic adhesion film 11 is formed on the prepared substrate 10 as necessary. The inorganic adhesion film 11 is not an essential film, and may not be provided when the adhesion between a buffer film 12 and a substrate 10 described later is good. When the inorganic adhesion film 11 is provided, it is necessary to form at least the semiconductor element portion 2 where the TFT is formed and the alignment mark portion 3 where the alignment mark 4 is formed, but it is not formed in other regions. It may or may not be formed, and may be formed on the entire surface of the substrate 10. In the example shown in FIG. 3A, the inorganic adhesion film 11 is formed on the entire surface. The inorganic adhesion film 11 is formed of any material selected from the group consisting of chromium, titanium, aluminum, silicon, chromium oxide, titanium oxide, aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. Among these, a metal-based inorganic adhesion film made of chromium, titanium, aluminum, silicon, or the like is preferably used.

  Although the range of the thickness of the inorganic adhesion film 11 varies slightly depending on the material constituting the film, it is usually preferably in the range of 1 to 200 nm, and more preferably in the range of 3 to 50 nm. In the case of a metal-based inorganic adhesion film made of chromium, titanium, aluminum, or silicon, it is more preferably within a range of 3 to 10 nm, and chromium oxide, titanium oxide, aluminum oxide, silicon oxide, silicon nitride. In the case of a compound-based inorganic adhesion film made of silicon oxynitride, it is more preferably in the range of 5 to 50 nm.

  The inorganic adhesion film 11 can be formed by various methods such as a DC sputtering method, an RF magnetron sputtering method, and a plasma CVD method, but in practice, a preferable method according to the material constituting the film is adopted. Is done. Usually, a DC sputtering method, an RF magnetron sputtering method, or the like is preferably used.

  Next, as shown in FIG. 3B, the buffer film 12 is formed on the substrate 10 (on the inorganic adhesion film 11 when the inorganic adhesion film 11 is formed on the substrate 10). For example, when a substrate such as a plastic substrate having slightly inferior heat resistance is used as the substrate 10, the buffer film 12 acts as a thermal buffer film against heat applied in a later process, or for example, a stress of a film formed in a later process For example, it is a film that acts as a stress buffer film that relaxes the above, or acts as a barrier film that prevents impurities in the substrate 10 from entering the TFT. The buffer film 12 is a film that is preferably formed in the semiconductor element portion 2 where the TFT is formed and the alignment mark portion 3 where the alignment mark 4 is formed, but may be formed in other regions. Alternatively, it may be formed on the entire surface of the substrate 10. In the example shown in FIG. 3B, the buffer film 12 is formed on the entire surface. The buffer film 12 is directly provided on the substrate 10 without the inorganic adhesion film 11 as described above when the adhesion between the buffer film 12 and the substrate 10 is good.

  The buffer film 12 is preferably formed of any material selected from the group of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, silicon oxynitride, etc. From this point of view, silicon oxide is preferable.

  The thickness of the buffer film 12 is not particularly limited, and the range is slightly different depending on the material of the actually formed film. However, the thickness is usually preferably in the range of 100 nm to 1000 nm. From the point of time, it is more preferable to be within the range of 100 nm to 500 nm.

  The buffer film 12 can be formed by various methods such as an RF magnetron sputtering method and a plasma CVD method. In practice, a preferable method according to the material constituting the film is employed. Usually, the RF magnetron sputtering method is preferably used.

Next, as shown in FIG. 3C, a non-doped amorphous silicon film 21 a is formed on the buffer film 12. The amorphous silicon film 21a can be formed by various methods such as an RF magnetron sputtering method and a CVD method. For example, in the case of forming an amorphous silicon film by RF magnetron sputtering, for example, a film thickness of room temperature, a film formation pressure: 0.2 Pa, and a thickness of, for example, 50 nm under a film formation condition of gas: argon. Can be formed. In addition, even when an amorphous silicon film is formed by the CVD method, the film can be formed at a film formation temperature of about 25 ° C. However, since SiH ₄ is used as a source gas, dehydration at about 400 ° C. is performed after the film formation. Elementary treatment (about 1 hour in vacuum) is required. The buffer film 12 preferably acts as a buffer film against heat applied during the dehydrogenation process.

  A silicon oxide film (not shown) is preferably formed on the amorphous silicon film 21a. This silicon oxide film is formed to have a thickness of about 50 to 150 nm by, for example, RF magnetron sputtering, and the amorphous silicon film 21a or the multi-layer is formed in steps such as laser irradiation, mask pattern formation, ion implantation, and laser activation described later. It acts to protect the crystalline silicon film 21p. This silicon film (not shown) is removed by wet etching using, for example, a 2% HF solution at least before the defect processing step of the polycrystalline silicon film 13 described later.

Next, as shown in FIG. 3D, laser irradiation 22 is performed to polycrystallize the amorphous silicon film 21a into a low resistance polycrystalline silicon film 21p. The laser irradiation 22 is a crystallization means for polycrystallizing the amorphous silicon film 21a into the polycrystalline silicon film 21p, and is performed using various lasers such as a XeCl excimer laser and a CW (Continuous Wave) laser. Can do. For example, when crystallization is performed using a XeCl excimer laser with a wavelength of 308 nm, as an example, pulse width: 30 nsec (FWHM (full width at half maximum)), energy density: 200 to 300 mJ / cm ² Can be carried out at room temperature. The buffer film 12 preferably acts as a buffer film for buffering the heat applied during laser irradiation in this step.

  Next, as shown in FIG. 3E, a mask pattern is formed on the polycrystalline silicon film 21p. This mask pattern includes a mask pattern A for forming a polycrystalline silicon semiconductor film (source-side diffusion film 13s and drain-side diffusion film 13d) in the semiconductor element portion 2 of the polycrystalline silicon film 21p, and the polycrystalline silicon film 21p. The mask pattern B for forming the alignment mark 4 in the alignment mark part 3 can be mentioned. Such mask patterns A and B are formed by a mask layer 23. Such a mask layer 23 may be formed by patterning an inorganic film such as a silicon oxide film or by patterning a resist film. And acts to shield ion implantation described later. The mask pattern B for forming the alignment mark 4 is a mask pattern for forming a pattern as shown in FIG. 2, for example, and the mask layer 23 is formed in the shape of reference numeral 6p in FIG. This is a pattern in which the mask layer 23 is not formed in the shape of 6a.

  The mask layer 23 can be formed of an inorganic film such as a silicon oxide film having a thickness of about 100 nm to 300 nm or a resist film having a thickness of about 700 nm. The inorganic film is formed by a film forming means such as a sputtering method, and then patterned by photolithography. On the other hand, the resist film can be formed of various positive photoresists, for example. A similar resist film is also used when patterning the inorganic film by photolithography, and such a resist film is formed on the entire surface by means of a spinner or the like and dried and cured. The formed resist film is exposed through a photomask, developed with a predetermined resist remover, and patterned. The photomask at this time is a photomask that can form the above-described mask patterns A and B. For example, a photomask in which a chromium pattern is formed on a glass substrate can be used.

Next, as shown in FIG. 3E, ion implantation 24 is performed from above the mask patterns A and B. In the ion implantation 24, for example, phosphorus (P) is implanted at an implantation voltage of 10 keV and a room temperature at a dose of 5 × 10 ¹⁴ ions / cm ² to 2 × 10 ¹⁵ ions / cm ² . When the ion implantation amount (dose amount) is less than 5 × 10 ¹⁴ ions / cm ² , the crystal phase polycrystalline silicon film 21p does not change to the amorphous phase amorphous silicon film 21a, which is sufficient as described later. Contrast cannot be obtained. On the other hand, 2 × 10 ¹⁵ ions / cm ² is the upper limit because the crystal phase is sufficiently changed to the amorphous phase by the ion implantation amount (dose amount) within the above range. This is because there is no significant difference in contrast. As the implantation element, in addition to phosphorus, a known element that can be ion-implanted into the polycrystalline silicon film, such as boron, antimony, and arsenic, may be arbitrarily selected and implanted.

  When ions are implanted into a portion (exposed portion) where the mask patterns A and B are not formed by such ion implantation, the polycrystalline silicon film 21p changes from a crystalline phase to an amorphous phase and the amorphous silicon film 21a. become. On the other hand, in the portion where the mask patterns A and B are formed, even if ion implantation is performed from above the mask patterns A and B, the ions do not reach the polycrystalline silicon film 21p. Does not change to amorphous. It should be noted that the thickness of the mask patterns A and B (mask layer 23) for preventing the polycrystalline silicon film 21p from changing to amorphous may be 100 nm or more under the above ion implantation conditions.

  In the alignment mark part 3, a figure is formed in a different silicon phase composed of a polycrystalline silicon phase (polycrystalline silicon film 21p) and an amorphous silicon phase (amorphous silicon film 21a) on at least the surface of the silicon film by ion implantation. The aligned alignment mark 4 is formed (see FIGS. 1 and 2). Here, “at least the surface” is because the surface of the alignment mark 4 may be a silicon phase having a different level so that the difference in contrast can be recognized in order to recognize the contrast. It is preferable that all of the thickness directions are different silicon phases.

  Next, as shown in FIG. 3F, the polycrystalline silicon film 21p and the amorphous silicon film 21a formed according to the mask patterns A and B are activated by laser annealing, and amorphous by ion implantation. The amorphous silicon film 21a that has changed into a phase is recrystallized to change into a polycrystalline silicon film 21p. At this time, only the semiconductor element portion 2 is activated, and the amorphous silicon film 21a is recrystallized to form the source side diffusion film 13s and the drain side diffusion film 13d. As a result, the polycrystalline silicon film 21p between the source side diffusion film 13s and the drain side diffusion film 13d becomes the channel film 13c. Here, the laser annealing is a process of recrystallization by irradiating an energy beam 25 such as a laser, and it is not always necessary to use a laser.

  On the other hand, the alignment mark part 3 is not activated. In order to activate only the semiconductor element part 2 without activating the alignment mark part 3, the semiconductor element part 2 is activated after shielding the alignment mark part 3 as shown in FIG. . As a result, in the alignment mark portion 3, the silicon film formed in a different silicon phase remains as it is. In this way, the mask member 7 such as a shielding plate that shields the energy beam 25 or an absorbing plate that absorbs the energy beam 25 is disposed between the alignment mark portion 3 and the energy beam 25 during the activation process. An alignment mark can be formed by a simple method.

As the energy beam 25 for the activation treatment, for example, a XeCl excimer laser with a wavelength of 308 nm can be used. As an example, pulse width: 30 nsec (FWHM), energy density: 150 to 250 mJ / cm ² , room temperature conditions Can be done.

  Next, as shown in FIG. 3G, the mask layer 23 is removed. When the mask layer 23 is formed of silicon oxide, it can be removed by wet etching using, for example, a hydrogen fluoride solution. Further, when the mask layer 23 is formed of a resist, it can be removed by a plasma ashing method. In the step shown in FIG. 3C, when a silicon oxide film (not shown) is formed on the amorphous silicon film 21a, it is removed by wet etching using a hydrogen fluoride solution or the like as described above. can do.

  The plasma ashing method is a method in which a plasma oxygen gas reacts with a resist, and the organic resist is decomposed (incinerated) into carbon dioxide gas or water to be removed. This plasma ashing method uses a commercially available apparatus called plasma asher (not shown), for example, gas: oxygen gas, gas flow rate: 60 sccm, applied power: 500 W, pressure: 6.6 Pa, treatment time: 10 minutes. Can be done under conditions. Specifically, after the inside of the chamber is set to a predetermined oxygen gas atmosphere, a substrate in the process of manufacturing the TFT is placed on the cathode electrode plate, and a high frequency signal is generated between the cathode electrode plate and the opposing anode electrode by an RF transmitter. A device that generates oxygen plasma by applying a voltage is used.

Next, as shown in FIG. 4H, the silicon film of the semiconductor element portion 2 and the silicon film of the alignment mark portion 3 are formed into islands. The island formation is performed by photolithography of the silicon film, but is usually performed by dry etching after forming a mask. As the etching gas at this time, SF ₆ or the like can be used. In addition, by forming the silicon film 5 of the alignment mark portion 3 into an island, the alignment mark 4 made of a silicon film formed with different silicon phases (polycrystalline silicon phase 6p and amorphous silicon phase 6a) appears.

  After the above island formation, defect processing by oxygen plasma is usually performed to reduce defects in the polycrystalline silicon semiconductor films (13s, 13c, 13d). For example, the oxygen plasma treatment is performed under conditions of RF 100 W, 1 Torr (133 Pa), and 150 ° C., and thereafter, a drying treatment is performed under the condition of 120 ° C. The following steps are exclusively steps for forming the semiconductor element portion 2 and are not involved in the alignment mark portion 3. Therefore, the description of the alignment mark portion 3 is omitted and the description thereof is omitted in FIG.

Next, as shown in FIG. 4I, a gate insulating film 14 is formed on the entire surface including the source side diffusion film 13s, the channel film 13c, and the drain side diffusion film 13d. The gate insulating film 14 is formed by using, for example, an RF magnetron sputtering apparatus and applying power to an 8-inch SiO ₂ target: 1.0 kW (= 3 W / cm ² ), pressure: 1.0 Pa, gas: argon + O ₂ ( A silicon oxide film having a thickness of about 100 nm is formed under the deposition conditions of 50%.

  Next, as shown in FIG. 4J, the contact hole 26 is formed by selectively etching the gate insulating film 14 on the source side diffusion film 13s and the drain side diffusion film 13d using a resist process. . For example, after a mask layer such as a resist is formed on the gate insulating film 14, the mask layer is patterned by exposure and development by a resist process using a photomask. The gate insulating film 14 in the contact hole forming portion exposed by the patterning is wet-etched using, for example, a 2% HF solution to form a contact hole 26, and then the mask layer is formed by resist stripping and plasma ashing similar to the above. Remove.

  Next, as shown in FIG. 4 (K), treatment with high-pressure steam 28 is performed to terminate defects and interface defects in the silicon film of the polycrystalline silicon semiconductor film 13 (13s, 13c, 13d). For example, a method of terminating dangling bonds on the silicon surface and eliminating a leak path at the interface between the polycrystalline silicon semiconductor film 13 and the gate insulating film 14 by high-pressure steam treatment at about 0.5 MPa · 150 ° C. is used.

  Next, as shown in FIG. 4L, an aluminum (Al) film having a thickness of, for example, 50 nm or more is deposited on the entire surface, and then patterned by wet etching to form a source electrode 15s, a drain electrode 15d, and a gate electrode 15g. Form. Note that the electrode material may be copper (Cu), other conductive materials in addition to aluminum, or may be formed by other film forming processes such as sputtering.

  Next, as shown in FIG. 4K, a protective film 18 is formed so as to cover the entire element including the semiconductor element portion 2 and the alignment mark portion 3. A preferable example of the protective film 18 is a silicon oxide film. The protective film 18 is preferably formed with a thickness of about 20 nm by, for example, RF magnetron sputtering. Thus, the semiconductor device 1 of one embodiment shown in FIG. 4M is manufactured.

  3 and 4 are manufacturing examples of the semiconductor device 1 shown in FIG. 1 in a 150 ° C. process, the semiconductor device 1 of the present invention is not limited to the illustrated process examples, and various modifications are possible. It can be formed in a manner.

  As described above, according to the semiconductor device 1 of the present invention illustrated in FIGS. 1 and 2, the alignment mark 4 formed on the substrate 10 has at least a silicon phase (non-polycrystalline silicon phase 6p and non-crystalline silicon phase) different in surface. The silicon film is made of a crystalline silicon phase 6a), and such a different phase structure is formed by ion implantation after the mask pattern B is provided on the polycrystalline silicon film 21p where the alignment mark 4 is to be formed. As a result, the silicon film formed on the substrate 10 is dry etched to form an alignment mark, which does not require a conventional additional process. As a result, since the semiconductor device 1 of the present invention can be obtained by omitting the dry etching process that causes the deterioration of the yield, the yield and accuracy can be improved.

  A silicon film formed in different phases (6a, 6p) formed on the alignment mark portion 3 has a sufficient contrast difference and can be preferably used as the alignment mark 4. The contrast difference at this time can be sufficiently discriminated from the difference between the two phases (6a, 6p) by visual observation, but the difference is remarkable even when measured by the reflection spectrum, and it is sufficient even by instrument measurement. Can be identified.

  The reflection spectrum can be evaluated with a spectrophotometer (manufactured by Shimadzu Corporation, model number: UV-3100PC), and the difference in reflection spectrum between the polycrystalline silicon phase 6p and the amorphous silicon phase 6a is shown in FIG. 5 and the following table. Based on the experimental results shown in FIG. 1, the range is preferably 30% or more and 60% or less, and more preferably 39% or more and 55% or less. If the reflection spectrum difference is less than 30%, it is difficult to obtain a contrast that can be used as an alignment mark. The upper limit of the difference in the reflection spectrum is not particularly limited, and a larger value is desirable because the contrast is increased. However, most of the cases where the polycrystalline silicon phase 6p and the amorphous silicon phase 6a are actually formed are visible. Since the maximum value of the difference in reflection spectrum measured in the light region is about 60%, the upper limit is set to 60%. The reason why the range of the reflection spectrum difference is more preferably 39% or more and 55% or less is that, in the present invention, the polycrystalline silicon phase 6p and the amorphous silicon phase 6a within such a range can be easily obtained. In the experimental results, the contrast was sufficient in that range. As a result, the alignment mark portion 3 having the reflection spectrum difference in this range has a sufficient contrast between the crystalline silicon phase 6p and the amorphous silicon phase 6a. The mask can be accurately positioned.

  The range of the reflection spectrum difference was specified from the following results. FIG. 5 is a graph showing the reflection spectrum of the polycrystalline silicon phase and the reflection spectrum of the amorphous silicon phase obtained in Example 1 described later. In the alignment mark part 3 obtained in Example 1 described later, the reflection spectrum of the polycrystalline silicon phase 6p and the reflection spectrum of the amorphous silicon phase 6a are measured with a spectrophotometer (manufactured by Shimadzu Corporation, model number: UV-3100PC). did. As a result, as shown in FIG. 5 and Table 1 below, the absolute value (%) of the reflection spectrum difference was different at each wavelength in the visible region. Based on this result, using the optical filter, the range of 400 nm to 800 nm shown in Table 1 is used as the wavelength light for each 25 nm, and the alignment mark portion 3 when each wavelength light is irradiated is photographed with a camera and used as a monitor. displayed. When the contrast of the displayed alignment mark portion 3 was visually observed, it was found that the range was preferably 30% or more and 60% or less, and more preferably 39% or more and 55% or less. Even if it is between 10% and 30%, if image processing is performed to emphasize the boundary between the polycrystalline silicon phase 6p and the amorphous silicon phase 6a, the above preferable range (39% to 55%) It was also possible to have the same level of discrimination as below.

  Specifically, as shown in Table 1, the alignment mark portion 3 when irradiated with light of 400 nm to 440 nm where the absolute value (%) of the reflection spectrum difference is 30% or more was displayed on the monitor with good contrast. However, the alignment mark portion 3 when irradiated with light of 450 nm to 500 nm where the absolute value (%) of the reflection spectrum difference is less than 30% was displayed with an insufficient contrast on the monitor. Similarly, the alignment mark portion 3 when irradiated with light of 510 nm to 610 nm where the absolute value (%) of the reflection spectrum difference is 30% or more was displayed with good contrast on the monitor, but the absolute value ( %) Was less than 30%, and the alignment mark portion 3 when irradiated with light of 620 nm to 800 nm was displayed with a contrast that was not sufficient for the monitor. A range with particularly good contrast is a range in which the absolute value (%) of the difference in reflection spectrum is 39% or more and 55% or less. In this experiment, the range was obtained when light of 520 nm to 600 nm was irradiated.

  The reflection spectrum difference may be an absolute value, and the reflectivity of the polycrystalline silicon phase 6p and the amorphous silicon phase 6a may be high or low. Further, since this result is a result of the alignment mark portion 3 obtained in Example 1, the wavelength is not particularly limited as long as the reflection spectrum difference is within the above range, and within the above range (30 % To 60% is preferable, and a range of 39% to 55% is more preferable).

  Further, in the method for manufacturing the semiconductor device 1 of the present invention illustrated in FIGS. 3 and 4, ions are implanted from above the mask patterns A and B, and the polycrystalline silicon film not covered with the mask patterns A and B is exposed. At least the surface of the part is changed to an amorphous silicon phase, and an alignment mark (a figure with a different silicon phase comprising a polycrystalline silicon phase and an amorphous silicon phase is formed on at least the surface of the silicon film formed in the alignment mark part. Formed mark). Therefore, according to the manufacturing method of the present invention, there is no need for an additional step of forming an alignment mark by dry etching the silicon film formed on the substrate as in the prior art. Since there is no etching step, the manufacturing method can improve yield and accuracy.

  Further, in the manufacturing method of the present invention, after the alignment mark portion 3 is shielded by the mask member 7, the semiconductor element portion 2 is activated by laser annealing (energy beam 25), so that different silicon phases (6a, 6p) are used. The figured silicon film remains as it is. As a result, the alignment mark 4 can be formed by a simple method in which the mask member 7 that shields or absorbs the laser is disposed between the alignment mark portion 3 and the energy beam 25 during the activation process. it can. Such alignment marks 4 can accurately position the gate insulating film forming mask formed next to the polycrystalline silicon semiconductor film 13, and can also accurately form various films formed thereafter. it can.

  Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples. In addition, this invention is not limited to a following example.

Example 1
A polyether sulfone (PES) substrate having a thickness of 0.2 mm and a thickness of 50 mm × 50 mm is used as the sample substrate 10, and an aluminum film as the inorganic adhesion film 11 is formed on the substrate by a DC sputtering method (deposition pressure 0.2 Pa, After forming a thickness of 5 nm in an argon atmosphere, input power of 1 kW, and deposition time of 10 seconds, a silicon oxide film as the buffer film 12 is further formed by RF magnetron sputtering (deposition pressure of 0.3 Pa (argon gas: oxygen gas = 3: 1), input power 2 kW, and film formation time 2 hours) to form a thickness of 500 nm. Next, an amorphous silicon film 21a was formed on the buffer film 12 so as to have a thickness of 50 nm by RF magnetron sputtering (deposition temperature: room temperature, deposition pressure: 1.0 Pa, argon atmosphere).

Thereafter, laser irradiation 22 was performed to polycrystallize the amorphous silicon film 21a into a low resistance polycrystalline silicon film 21p. The laser irradiation 22 was performed using a XeCl excimer laser (pulse width: 30 nsec (FWHM), energy density: 325 mJ / cm ² ) having a wavelength of 308 nm under room temperature conditions. Next, after forming a 100 nm-thick silicon oxide film as a mask layer 23 on the polycrystalline silicon film 21p, the mask layer 23 is patterned into a predetermined pattern by photolithography, and FIGS. Mask patterns A and B having the form shown in E) were formed. Next, phosphorus (P) was ion-implanted from above the mask patterns A and B at an implantation voltage of 10 keV and a room temperature at a dose of 5 × 10 ¹⁴ ions / cm ² .

Next, only the semiconductor element portion 2 was laser-annealed to recrystallize the amorphous silicon film 21a changed to an amorphous phase by ion implantation into a polycrystalline silicon film 21p. With respect to the alignment mark portion 3, a mask member 7 that shields the energy beam 25 is disposed on the alignment mark portion 3 so that recrystallization does not occur. As the energy beam 25 at this time, a XeCl excimer laser (pulse width: 30 nsec (FWHM), energy density: 225 mJ / cm ² , room temperature) having a wavelength of 308 nm was used. Next, after removing the mask layer 23 with 2% hydrogen fluoride solution, photolithography is performed in which the silicon film of the semiconductor element portion 2 and the silicon film of the alignment mark portion 3 are dry-etched with SF ₆ after forming a mask. Made an island. Next, defect processing by oxygen plasma for reducing defects of the polycrystalline silicon semiconductor films (13s, 13c, 13d) was performed under conditions of RF 100 W, 1 Torr (133 Pa), and 150 ° C.

Next, a gate insulating film 14 having a thickness of 100 nm was formed on the entire surface including the source side diffusion film 13s, the channel film 13c, and the drain side diffusion film 13d. This gate insulating film 14 is applied to an 8-inch SiO ₂ target using an RF magnetron sputtering apparatus. Electric power: 1.0 kW (= 3 W / cm ² ), pressure: 1.0 Pa, gas: argon + O ₂ (50%) The film was formed under the following film forming conditions. Next, the gate insulating film 14 was selectively etched using a resist process to form a contact hole 26, and thereafter, high-pressure steam treatment at 0.5 MPa · 150 ° C. was performed. Next, after depositing an aluminum (Al) film having a thickness of 50 nm or more on the entire surface, patterning is performed by wet etching to form a source electrode 15s, a drain electrode 15d, and a gate electrode 15g, and then alignment with the semiconductor element portion 2 A silicon oxide film having a thickness of 20 nm was formed as a protective film 18 so as to cover the entire element including the mark portion 3.

  Thus, the semiconductor device 1 of Example 1 was manufactured. In the alignment mark portion 3 of the obtained semiconductor device 1, different silicons comprising a polycrystalline silicon phase (polycrystalline silicon film 21p) and an amorphous silicon phase (amorphous silicon film 21a) are formed on the silicon film by ion implantation. An alignment mark 4 having a shape as shown in FIG. When the alignment mark 4 was observed with the naked eye, the alignment mark 4 was formed with a contrast sufficient to clearly show the boundary between the polycrystalline silicon phase 6p and the amorphous silicon phase 6a. Further, when the reflection spectrum of the alignment mark 4 was measured with a spectrophotometer (manufactured by Shimadzu Corporation, model number: UV-3100PC), the reflection spectrum of the polycrystalline silicon phase at a wavelength of 550 nm was 64. As shown in FIG. The reflection spectrum of the amorphous silicon phase was 13.4%, and the difference in reflection spectrum was 51.3%.

It is sectional drawing which shows an example of the semiconductor device of this invention. It is a top view which shows the example of the alignment mark formed in the alignment mark part of the semiconductor device of this invention. It is explanatory drawing which shows the manufacturing process of the semiconductor device of this invention. It is explanatory drawing which shows the manufacturing process of the semiconductor device of this invention. 2 is a graph showing a reflection spectrum of a polycrystalline silicon phase and an amorphous silicon phase obtained in Example 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element part 3 Alignment mark part 4 Alignment mark 5 Silicon film 6a Amorphous silicon phase 6p Polycrystalline silicon phase 7 Mask member 10 Substrate 11 Inorganic adhesion film 12 Buffer film 13 Polycrystalline silicon semiconductor film 13s Source side diffusion Film 13c Channel film 13d Drain side diffusion film 14 Gate insulating film 15s Source electrode 15g Gate electrode 15d Drain electrode 18 Protective film 21a Amorphous silicon film 21p Polycrystalline silicon film 22 Laser irradiation 23 Mask layer 24 Ion implantation 25 Energy beam 26 Contact Hall 28 High-pressure steam A, B Mask pattern

Claims (8)

  A semiconductor device comprising: a polycrystalline silicon semiconductor film; and an alignment mark made of a silicon film patterned with a silicon phase having at least a different surface.   The semiconductor device according to claim 1, wherein the different silicon phases are a polycrystalline silicon phase and an amorphous silicon phase.   The semiconductor device according to claim 1, wherein the different silicon phases are 30% or more and 60% or less in a difference in reflection spectrum.   The semiconductor device according to claim 1, wherein the polycrystalline silicon semiconductor film and the alignment mark are provided on the substrate via a buffer film. A method of manufacturing a semiconductor device, wherein at least a semiconductor element portion having a polycrystalline silicon semiconductor film and an alignment mark portion having an alignment mark are formed on a substrate,
Forming an amorphous silicon film on the substrate;
Polycrystallizing the amorphous silicon film to form a polycrystalline silicon film;
A mask pattern A for forming the polycrystalline silicon semiconductor film is formed in the semiconductor element portion of the polycrystalline silicon film, and a mask pattern B for forming the alignment mark in the alignment mark portion of the polycrystalline silicon film. Forming a step;
Ion implantation from above the mask patterns A and B to change at least the surface of the exposed portion of the polycrystalline silicon film not covered with the mask patterns A and B into an amorphous silicon phase;
Activating only the semiconductor element portion to form a polycrystalline silicon semiconductor film on the semiconductor element portion;
Removing the mask patterns A and B,
Alignment marks formed with different silicon phases comprising a polycrystalline silicon phase and an amorphous silicon phase on at least the surface of the silicon film formed in the alignment mark portion by the step of changing to the amorphous silicon phase Forming a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein only the semiconductor element portion is activated by laser annealing after shielding the alignment mark portion.   The method of manufacturing a semiconductor device according to claim 5, wherein the alignment mark is used in a process subsequent to a process of forming a gate insulating film on the polycrystalline silicon semiconductor film.   The method for manufacturing a semiconductor device according to claim 5, wherein the polycrystalline silicon semiconductor film and the alignment mark are formed on the substrate via a buffer film.

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