JP2009110150A - Semiconductor device and method for operating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent performance of a system accessing a memory part from being deteriorated by preventing delay of a delete operation. <P>SOLUTION: A second control part issues a write command to a corresponding memory part on the basis of a write request issued from a first control part. When any of a plurality of memory parts can be deleted, the second control part issues a delete command after the write operation of any of memory parts which respond to the write command. Furthermore, the second control part issues write completion notification based on the write command to the first control part a first period after issuing the delete command. Thus, it is possible to surely advance the delete operation even when a write request frequently occurs. As a result, it is possible to prevent delay of the delete operation, and to prevent the performance of the system accessing the memory part from being deteriorated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of writing and erasing data.

  In a nonvolatile semiconductor memory such as a flash memory, a value held in a memory cell becomes a logic 1 by an erase operation, and becomes a logic 0 by a write operation, for example. In general, the erasing operation is performed in units of blocks such as sectors and takes time. A block that is executing an erase operation cannot execute a write operation and a read operation.

Recently, a flash memory having a function of interrupting and resuming an erase operation and executing a write operation or a read operation while the erase operation is interrupted, and a control method for interrupting and resuming the erase operation of the flash memory Has been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, there has been proposed a flash memory in which the memory cell array is divided into a plurality of banks and the read operation of the other bank can be executed during the erase operation of one bank (see, for example, Patent Document 3).
JP-A-11-250674 JP 2004-30438 A JP 2000-322894 A

  In a flash memory having a function of interrupting and resuming an erase operation, the frequency of a write request or a read request increases, and if the erase operation is frequently interrupted, the time until the erase operation is completed becomes long. If a write request for the area occurs before the erase operation is completed, the write operation cannot be performed until the erase operation is completed. As a result, there is a problem in that the system performance deteriorates when the operation of the system accessing the flash memory is stopped for a long period of time.

  An object of the present invention is to prevent the progress of the erasing operation from being delayed and to prevent the performance of the system accessing the memory unit from being deteriorated.

  The second control unit issues a write command to the corresponding memory unit based on the write request issued from the first control unit. The second control unit issues an erase command after any write operation of the memory unit responding to the write command when any of the plurality of memory units includes an erasable memory unit. Further, the second control unit issues a write completion notification based on the write command to the first control unit after a first period from the issue of the erase command.

  Since a part of the erasing operation can be executed from the completion of the writing operation until the writing completion notification is issued, the erasing operation can surely proceed even when a write request frequently occurs. Since it is possible to prevent the progress of the erase operation from being delayed, it is possible to prevent a write request from being generated for the memory unit during the erase operation. As a result, it is possible to prevent waiting for completion of the erase operation from occurring for a long time, and it is possible to prevent the performance of the system accessing the memory unit from being deteriorated.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. A part of the block to which the thick line is connected is composed of a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted.

  FIG. 1 illustrates one embodiment. The semiconductor device SEM is, for example, a single chip microcomputer incorporating a CPU, a flash memory FLASH (hereinafter also referred to as FLASH), and a RAM. The CPU, FLASH, and RAM are connected to each other via a bus BUS. The address space of FLASH and RAM is assigned to an address space accessible by the CPU. Note that the semiconductor device SEM may include peripheral circuits such as a timer, a DMAC, and a serial interface circuit. Although not particularly illustrated, the semiconductor device SEM is mounted together with other semiconductor devices on a substrate connected to an input device, a display device, and the like to constitute a system device.

  The FLASH includes a command control circuit CCNT, a voltage generation circuit VGEN, an address control circuit ACNT, a data control circuit DCNT, and a memory cell array ARY. The command control circuit CCNT receives a command signal CMD, an address signal AD, and a data signal DQ from the CPU as commands, decodes the received command, and controls the access to the memory cell array ARY, a voltage generation circuit VGEN, Control signals for controlling operations of the address control circuit ACNT and the data control circuit DCNT are generated. Examples of command signals (operation commands) received by the command control circuit CCNT include an erase command, a write command (program command), a read command, a suspend command, and a resume command. The suspend command is a command that temporarily stops the erase operation. The resume command is a command for resuming the erase operation that has been stopped. Details of the operation command will be described with reference to FIG.

  The voltage generation circuit VGEN generates the high voltage V1 used in the erase operation and the write operation using the power supply voltage. The power supply voltage is supplied from the outside of the semiconductor device SEM. The address control circuit ACNT receives the address signal AD supplied from the CPU together with the command signal CMD, and outputs the received signal to the memory cell array ARY as the address signal AD1. The data control circuit DCNT receives the data signal DQ supplied from the CPU together with the command signal CMD (write command), and outputs the received signal to the memory cell array ARY as the data signal DT. The data control circuit DCNT receives the data signal DT output from the memory cell array ARY in response to the command signal CMD (read command) and outputs the received signal to the bus BUS.

  The memory cell array ARY has, for example, a plurality of sectors SEC (SEC0-5; memory unit). Each sector SEC0-5 has nonvolatile memory cells arranged in a so-called NOR structure. The nonvolatile memory cell is a floating gate type or a trap gate type (mirror bit type) for trapping charges. For example, sectors SEC0-1 are used for storing data. The sector SEC2-5 is used for storing a program executed by the CPU. In this embodiment, the sectors SEC0-5 are accessed by one control signal group CNT generated by the command control circuit CCNT. For this reason, when any of the sectors SEC is performing an access operation (erase operation, write operation, or read operation), the remaining sectors SEC cannot perform the access operation. Here, for simplicity of explanation, an example in which the memory cell array ARY has six sectors SEC is shown, but the number of sectors SEC is not limited to this.

  The CPU has a first control unit CNT1 and a second control unit CNT2. The first and second control units CNT1-2 may be realized by a logic circuit (hardware) or may be realized by a program (software) executed by the CPU. Alternatively, the first and second control units CNT1-2 may be realized by a control circuit and a program that controls the logic circuit.

  The first control unit CNT1 issues an access request for the sector SEC0-1 to the second control unit CNT2. For example, the access requests are the write request WREQ, the read request RREQ, and the power-off request POFF shown in FIGS. When the first control unit CNT1 is realized by software, the first control unit CNT1 receives the second request according to an access request (such as a load instruction or a store instruction) included in a program (such as an application program) executed by the CPU. An access request (such as an access request packet) is issued to the control unit CNT2. When the first control unit CNT1 is realized by hardware, the first control unit CNT1 issues an access request to the second control unit CNT2 in response to a FLASH access request (such as an interrupt) supplied from the outside of the CPU. To do.

  The second control unit CNT2 issues an access command to FLASH based on the access request from the first control unit CNT1. The access commands are the write command WC and the read command RC shown in FIGS. Further, the second control unit CNT2 issues a polling command PL, an erase command EC, a suspend command SU, and a resume command RE shown in FIGS. 3 to 5 to the FLASH according to the operation state of the FLASH. The polling command PL is a kind of read command, and is a command for monitoring the operating state of FLASH. The suspend command SU is a command for temporarily interrupting the erase operation. The resume command RE is a command for restarting the interrupted erase operation.

  When the second control unit CNT2 is realized by software, the second control unit CNT2 functions as driver software (FLASH access management program) that controls access to FLASH. The second control unit CNT2 issues an access command to FLASH in response to an access request (such as an access request packet) from the first control unit CNT1. When the second control unit CNT2 is realized by hardware, the second control unit CNT2 functions as a memory controller that controls access to FLASH. The second control unit CNT2 issues an access command to FLASH in response to an access request (such as a trigger signal) from the first control unit CNT1.

  The RAM is used for storing data or a program executed by the CPU. In particular, when at least a part of the first and second control units CNT1-2 is realized by software, the CPU cannot fetch the program stored in the sector SEC2-5 during the FLASH erase operation. At this time, the CPU fetches the program stored in the RAM and confirms the operation state of FLASH.

  FIG. 2 shows an example of access to the memory cell array ARY shown in FIG. Here, in order to simplify the explanation, the sector SEC0 (first area) is composed of four storage areas MR (MR01-04), and the sector SEC1 (second area) is composed of four storage areas MR (MR11-14). However, the number of storage areas is not limited to this. Each storage area MR is a minimum unit for writing or reading, and is composed of, for example, 16 bits. A shaded storage area MR indicates a state in which data is written, a white storage area MR indicates that data is erased, and a hatched storage area MR indicates that data is being erased.

  In a nonvolatile semiconductor memory such as a flash memory, by programming a memory cell in an erased state (for example, logic 1), the memory cell is changed to a written state (for example, logic 0). The erase operation for changing from the write state to the erase state is executed in units of sectors SEC. For this reason, in each sector SEC0-1, when writing new data to the storage area MR in the written state, it is necessary to erase the data in that sector SEC.

  In the example shown in the figure, data is sequentially held in the sectors SEC0-1. Each time the second control unit CNT2 receives a write request WREQ together with a write address, write data, and the like, the second control unit CNT2 outputs the write command WC, the write address, and the write data to FLASH, and writes the write data in the storage area MR indicated by the write address. Further, after writing data in the first storage area MR (MR01 or MR11) in one sector SEC, the second control unit CNT2 determines that the data in the other sector SEC is no longer needed, and the other sector SEC. An erase command EC is output to FLASH in order to erase the data (for example, FIGS. 2A and 2B). That is, when any of the sectors SEC becomes erasable, the second control unit CNT2 issues an erase command EC to the sector.

  For example, the access shown in the figure shows a part of the operation of the system device for controlling the engine of the automobile. Specifically, the first control unit CNT1 (for example, an application program) designed to control the engine periodically monitors information such as the engine speed, the speed of the automobile, and the fuel consumption. In order to sequentially write the data obtained by the monitor to FLASH, a write request WREQ is issued. For example, the monitoring is performed every 5 ms, and the write request WREQ is issued every 10-50 ms depending on the write state of FLASH. In addition, the first control unit CNT1 reads the data written in the FLASH, and feeds back the read data to the ignition system so that an optimum engine output can be obtained.

  The second control unit CNT2 (for example, the access management program) that actually accesses FLASH in response to a request from the first control unit CNT1 writes the data in the sectors SEC0-1 in order to cyclically write the data to the sectors SEC0-1. Manage writing and erasing. Then, when data is written in all the storage areas MR in one sector SEC and data is written in one of the storage areas in the other sector SEC, an erase command EC is issued to erase the data in one sector SEC. Issue. Generally, the erase time of a sector of flash memory is several hundred ms. This erase time is longer than the maximum interval (50 ms) of the write request WREQ. For this reason, the second control unit CNT2 issues a write command WC while the erase operation is temporarily stopped using a suspend command and a resume command (not shown). When the frequency of the write request WREQ is high, data is written to all the storage areas MR of the other sector SEC before the erase operation of the one sector SEC is completed. On the other hand, new data cannot be written in the sector SEC before the erase operation is completed. Therefore, the second control unit CNT2 needs to complete the erase operation of the sector SEC before receiving the write request WREQ corresponding to the sector SEC of interest.

  Note that the issuing timing of the erase command EC for one sector SEC may be when data is written a plurality of times in the other sector SEC. Alternatively, an erase command may be issued to one sector SEC before the first data is written to the other sector SEC. Further, some of the data written in one sector SEC may be preliminarily written in the other sector SEC.

  3 and 4 show an example of the operation of the semiconductor device SEM shown in FIG. In the figure, the address signal and the data signal are not shown. The shading of the storage area MR has the same meaning as in FIG. A thick solid line indicates an operation period of the first control unit CNT1, the second control unit CNT2, and the FLASH. For example, the operation of the first control unit CNT1 is a period during which the CPU executes an application program. The operation of the second control unit CNT2 is a period during which the CPU executes the access management program stored in the sector SEC2-5 of FLASH. A thick broken line in the second control unit CNT2 is a period during which the CPU executes the access management program stored in the RAM. While the FLASH is executing the write operation WR or the erase operation ER, the CPU cannot read the program stored in the sectors SEC2-5 of the FLASH. Therefore, the CPU fetches a program stored in the RAM, a polling process (polling command PL) for monitoring the completion of the write operation WR and a suspend process (suspend command SU) for interrupting the erase operation ER. It will be implemented.

  At the beginning of the figure, data is written in the storage area MR01-03 of the sector SEC0. Sector SEC1 (MR11-14) has been erased. The first control unit CNT1 issues a write request WREQ to write newly obtained data into the FLASH storage area MR04 (FIG. 3A). For example, when the function of the first control unit CNT1 is realized by an application program, the program sets parameters such as a write request WREQ, a write address, and write data in a register or work area, and then writes a write function in the access management program Make a subroutine call to the program. The same applies to processing of a read request RREQ, which will be described later.

  The second control unit CNT2 (access management program) issues a write command WC (program command) to FLASH based on the write request WREQ from the first control unit CNT1 (FIG. 3B). The four arrows in the figure indicate that four bus cycles are required to start the write operation. The write command WC includes a write address and write data. Since the command sequence of the NOR flash memory such as the write command WC and the erase command EC is publicly known, detailed description thereof is omitted. FLASH starts the write operation WR in response to the write command WC (FIG. 3C).

  The second controller CNT2 periodically issues a polling command PL (a kind of read command) to FLASH in order to detect the completion of the write operation WR (FIG. 3 (d)). Since there is no interrupted erase operation and no sector SEC requiring the erase operation at this time, the second control unit CNT2 sends a completion notification WEND of the write operation WR in response to the completion of the write operation WR. Issued to CNT1 (FIG. 3E). Specifically, the process returns to the original application program. Thereby, the control is transferred to the first control unit CNT1.

  Next, the first control unit CNT1 issues a write request WREQ to write newly obtained data into the FLASH storage area MR11 (FIG. 3 (f)). Thereafter, the processing up to the completion of the write operation WR is the same as described above. Since data is written in all the storage areas MR01-03 of the sector SEC0 and data is written in the first storage area MR11 of the sector SEC1, the second control unit CNT2 first issues an erase command EC to the sector SEC1. Issue (Fig. 3 (g)). Thereafter, the second control unit CNT2 waits for the first period P1 without immediately issuing the completion notification WEND (FIG. 3 (h)). The first period P1 is generated, for example, when the second control unit CNT2 repeats the NOP instruction a predetermined number of times.

  After the period P1, the second control unit CNT2 issues a suspend command SU to FLASH and interrupts the erase operation ER (FIG. 3 (i)). The erase operation ER is executed only for the period P1. Furthermore, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 (FIG. 3 (j)).

  Next, the first control unit CNT1 issues a write request WREQ to write newly obtained data into the FLASH storage area MR12 (FIG. 3 (k)). Thereafter, the process until the completion of the write operation WR is the same as described above. After the completion of the write operation WR, the second control unit CNT2 issues a resume command RE to FLASH in order to resume the erase operation ER (FIG. 3 (l)). Thereafter, as described above, the second control unit CNT2 waits for the period P1 and issues a suspend command SU to FLASH (FIG. 3 (m, n)). Then, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 (FIG. 3 (o)). As a result, the erase operation ER is executed only for the period P1.

  Next, in FIG. 4, the first control unit CNT1 issues a read request RREQ in order to read data held in the storage area MR02, for example (FIG. 4A). The second control unit CNT2 issues a read command RC to FLASH based on the read request RREQ (FIG. 4B). The read command RC includes a read address. FLASH executes the read operation RD in response to the read command RC (FIG. 4C).

  After the completion of the read operation RD, the second control unit CNT2 issues a resume command RE to FLASH in order to resume the erase operation ER (FIG. 4 (d)). Thereafter, as described above, the second control unit CNT2 waits for the period P1, issues a suspend command SU to FLASH, and issues a read operation RD completion notification REND to the first control unit CNT1 (FIG. 4 ( e, f, g)). As a result, the erase operation ER is executed only for the period P1.

  Next, the first control unit CNT1 issues a write request WREQ in order to write the newly obtained data to the FLASH storage area MR13 (FIG. 4 (h)). Thereafter, the operation is the same as described above except that the erase operation ER of the sector SEC0 is completed until the completion notification WEND is issued. Note that the second control unit CNT2 may issue a polling command PL to the FLASH during the period P1 in order to detect the completion timing of the erase operation ER. In this case, the completion notification WEND can be issued immediately after the erase operation ER is completed.

  Next, the first control unit CNT1 issues a write request WREQ to write newly obtained data into the FLASH storage area MR14 (FIG. 4 (i)). The second control unit CNT2 issues a write command WC and a polling command PL to FLASH in the same manner as described above (FIG. 4 (j, k)). At this time, there is no erase operation that is suspended and no sector SEC that needs to be erased. Therefore, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 without issuing the resume command RE and the erase command EC and without waiting for the period P1 (FIG. 4 (l)). .

  FIG. 5 shows an example of the operation when the semiconductor device SEM shown in FIG. 1 is powered off. The first control unit CNT1 issues a power-off request POFF to the second control unit CNT2 when the power supply of the system device on which the semiconductor device SEM is mounted is shut off (FIG. 5A). The operation until the power-off request POFF is issued is the same as that shown in FIGS.

  Based on the power-off request POFF, the first control unit CNT1 issues a resume command RE to FLASH in order to resume the erase operation ER (FIG. 5B). The first control unit CNT1 periodically issues a polling command PL to FLASH until the completion of the erase operation ER is detected (FIG. 5C). The second control unit CNT2 issues a completion notification EEND of the erase operation ER to the first control unit CNT1 in synchronization with the detection of the completion of the erase operation ER (FIG. 5 (d)). Thereby, it is possible to prevent the supply of power from being stopped during the erasing operation ER, and to prevent the FLASH from malfunctioning.

  FIG. 6 shows the operation of the second control unit CNT2 shown in FIG. When the second control unit CNT2 is realized by software, a program is designed according to the flow of FIG. When the second control unit CNT2 is realized by hardware, the flow of FIG. 6 is replaced with a circuit description, and a logic circuit is designed. The flow in FIG. 6 summarizes the operations in FIGS. 4 to 6.

  Based on the write request WREQ, the second control unit CNT2 writes data to the FLASH storage area in operation 10. In operation 12, the second control unit CNT2 determines whether or not it is necessary to start the erase operation ER. When it is necessary to start the erase operation ER, the second control unit CNT2 issues an erase command EC to FLASH in operation 14 and starts the erase operation ER. When the erasing operation ER is unnecessary, the second control unit CNT2 determines in operation 16 whether or not FLASH is being suspended. When the operation is suspended, in operation 18, the second control unit CNT2 issues a resume command RE to FLASH and restarts the erase operation ER. When not being suspended, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1 (RETURN). “RETURN” in the figure indicates one of the completion notifications WEND, REND, and EEND shown in FIGS.

  When the erase operation ER is started or restarted, the second control unit CNT2 waits for the period P1 in the operation 20. Next, in operation 22, the second controller CNT2 issues a suspend command SU to FLASH in order to interrupt the erase operation ER.

  On the other hand, based on the read request RREQ, the second control unit CNT2 issues a read command RC to FLASH in operation 24, and reads data from any of the storage areas MR. Thereafter, in the operation 26 to the operation 32, as in the operation 16 to the operation 22 described above, the second control unit CNT2 issues the resume command RE when the FALSE is suspended, and resumes the erase operation ER. After waiting for P1, a suspend command SU is issued. When not being suspended, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1. The control from the operation 26 to the operation 32 may not be performed. That is, the period P1 may be secured only in response to the write request WREQ.

  Further, based on the power-off request POFF, the second control unit CNT2 determines whether FLASH is being suspended in the operation 34. When the operation is suspended, in operation 36, the second control unit CNT2 issues a resume command RE to FLASH and restarts the erase operation ER. When not being suspended, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1. In operation 38, the second control unit CNT2 repeatedly issues the polling command PL to FLASH until the completion of the erase operation ER is detected. Then, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1.

  FIG. 7 shows an example of the operation of the semiconductor device SEM before the second control unit CNT2 shown in FIG. 1 is proposed. Detailed descriptions of the same operations as those in FIGS. 3 and 4 are omitted. Also in this example, the first control unit CNT1 issues a write request WREQ sequentially in order to write data in the storage area MR11-14, as in FIGS. The second controller CNT2 issues an erase command EC or a resume command RE to FLASH after the write operation WR (FIG. 7 (a, b, c, d)). Thereafter, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 (FIG. 7 (e, f, g, h)). However, the second control unit CNT2 issues a completion notification WEND without waiting for the period P1.

  Similar to FIGS. 3 and 4, the first control unit CNT1 issues a write request WREQ after receiving the completion notification WEND (FIG. 7 (i, j, k, l)). Based on the new write request WREQ, the second control unit CNT2 issues a suspend command SU to FLASH to interrupt the erase operation ER of FLASH, and issues a write command WC to FLASH to execute the write operation WR. Issue (FIG. 7 (m, n, o)).

  However, in this example, since there is no period P1, the period from the start or restart of the erase operation ER to the interruption is short. For this reason, before the erase operation ER of one sector SEC (SEC0 in this example) is completed, data is written in all the storage areas MR11-14 of the other sector SEC (SEC1 in this example). (FIG. 7 (p)). Even if the second control unit CNT2 receives a write request WREQ for writing data to the storage area MR01 of the sector SEC0, it cannot issue the write command WC until the erase operation ER of the sector SEC0 is completed (FIG. 7 (q) ). As a result, a period during which data cannot be written to FLASH occurs. In other words, a long period for waiting for the completion of erasure occurs, and the apparent erasure period becomes long. In the worst case, the operation of the system device on which the semiconductor device SEM is mounted stops for a long time.

  As described above, in this embodiment, by setting the time lag P1 between the issuance of the erase command WC or the resume command RE and the issuance of the completion notification WEND or REND, the erase operation is performed after the write operation WR or the read operation RD is completed. The operation ER can be executed for a relatively long period. Therefore, the erase operation ER can be reliably advanced even when the write request WREQ is frequently generated. Since the progress of the erase operation ER can be prevented from being delayed, it is possible to prevent the write request WREQ from occurring for the sector SEC during the erase operation ER. As a result, it is possible to prevent the performance of the system device that accesses FLASH from being deteriorated.

  FIG. 8 shows another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the CPU has a register P1REG that holds a value for setting the length of the period P1. The value of the register P1REG is rewritten when the first control unit CNT1 issues a register setting command REGS. The second control unit CNT2 sets the period P1 based on the value held in the register P1REG. Other configurations are the same as those in FIG. When the register P1REG is set only once when the semiconductor device SEM is powered on, the period P1 has a fixed length, and the operation of the semiconductor device SEM is the same as that shown in FIGS.

  FIG. 9 shows an example of the operation of the semiconductor device SEM shown in FIG. The difference from FIG. 3 is that the period P1 is changed by issuing a register setting command REGS from the first controller CNT1 and rewriting the value of the register P1REG. Other operations are the same as those in FIG. 3 except that the length of the period P1 is different.

As described above, also in this embodiment, the same effects as those of the embodiment shown in FIGS. 1 to 6 can be obtained. Furthermore, in this embodiment, the balance between the frequency of occurrence of the write request WREQ and the duration of the erase operation ER can always be set optimally by changing the period P1, which is the duration of the erase operation ER. As a result, it is possible to prevent the erasing operation ER from continuing for a long period of time as shown in FIG. 7 and to prevent the operation of the system device on which the semiconductor device SEM is mounted from being stopped. Further, it is possible to prevent the data written in the sectors SEC0-1 from overflowing. In particular, when the frequency of the write request WREQ is expected to increase, the period P1 is lengthened before the frequency increases, so that the apparent erase period becomes longer when the frequency of the write request WREQ increases. Can be prevented.

FIG. 10 shows another embodiment. Detailed description of the same elements as those described in the above embodiment will be omitted. In the semiconductor device SEM of this embodiment, the second control unit CNT2 and the flash memory FLASH are different from those in FIG. Other configurations are the same as those in FIG. That is, the semiconductor device SEM is mounted on a substrate connected to an input device, a display device, and the like together with other semiconductor devices to constitute a system device. The operation of the second control unit CNT2 is shown in FIGS.

  The FLASH memory cell array ARY includes a bank BKA (first memory block) and a bank BKB (second memory block). The bank BKA has two sectors SECA (SECA0-1). The configuration of the sector SECA0-1 is the same as that of the sector SEC0-1 shown in FIGS. The bank BKB has four sectors SECB (SECB0-3). Each sector SECA0-1 and SECB0-3 has nonvolatile memory cells arranged in a so-called NOR structure. The nonvolatile memory cell is a floating gate type or a trap gate type (mirror bit type) for trapping charges. For example, the bank BKA is used for storing data. The bank BKB is used for storing a program executed by the CPU. The number of sectors SECA and SECB is not limited to this.

  The command control circuit CCNT receives a command signal CMD, an address signal AD and a data signal DQ from the CPU as commands, decodes the received commands, and independently receives control signals CNTA and CNTB for controlling access to the banks BKA and BKB, respectively. Generate control signals for controlling operations of the voltage generation circuit VGEN, the address control circuit ACNT, and the data control circuit DCNT. The banks BKA and BKB are identified by an address signal AD (bank address).

  The voltage generation circuit VGEN generates the high voltages V1A and V1B used in the erase operation and the write operation using the power supply voltage and supplies them to the banks BKA and BKB, respectively. The power supply voltage is supplied from the outside of the semiconductor device SEM. The address control circuit ACNT receives the address signal AD (excluding the bank address) supplied from the CPU together with the command signal CMD, and outputs the received signals to the banks BKA and BKB as address signals AD1A and AD1B, respectively. The data control circuit DCNT receives the data signal DQ supplied from the CPU together with the command signal CMD (write command), and outputs the received signals to the banks BKA and BKB as data signals DTA and DTB, respectively. The data control circuit DCNT receives data signals DTA and DTB output from the banks BKA and BKB, respectively, in response to the command signal CMD (read command), and outputs the received signals to the bus BUS.

  The second control unit CNT2 issues an access command to FLASH based on the access request from the first control unit CNT1. The access commands are the write command WC and the read command RC shown in FIGS. Further, the second control unit CNT2 issues a polling command PL, an erase command EC, a suspend command SU, and a resume command RE shown in FIGS. 11 to 13 to the FLASH according to the operation state of the FLASH.

  For example, the second control unit CNT2 is configured as software (access management program) or hardware (memory controller), or is configured by combining software and hardware. The RAM is used for storing data or a program executed by the CPU. However, since the FLASH of this embodiment is a so-called dual bank type, the CPU can fetch the program of the bank BKB while erasing each sector SECA0-1 of the bank BKA. For this reason, the semiconductor device SEM can operate without having the RAM.

  11 and 12 show an example of the operation of the semiconductor device SEM shown in FIG. The shading of the storage area MR has the same meaning as in FIG. That is, the data write sequence to the sectors SECA0-1 is the same as in FIG. Thick lines and arrows in the figure have the same meaning as in FIG. Here, for the sake of simplicity, an example is shown in which each sector SECA0-1 is composed of four storage areas MR (MR01-04, MR11-14), but the number of storage areas is limited to this. Not. Each storage area MR is a minimum unit for writing or reading, and is composed of, for example, 16 bits.

  In this embodiment, for example, the second control unit CNT2 operates based on an access management program stored in the bank BKB without accessing the RAM. The operation until the second control unit CNT2 issues the erase command EC to FLASH is the same as that in FIG. 3 except that the RAM is not accessed. The second controller CNT2 issues a completion notification WEND to the first controller CNT1 without issuing the suspend command SU after the erasing operation ER is started and the period P1 has elapsed (FIG. 11A). The suspend command SU is issued after the first control unit CNT1 issues a write request WREQ for the storage area MR12 (FIG. 11B). Accordingly, when the dual bank type FLASH is used, the duration of the erase operation ER can be made longer than that in FIG.

  The second controller CNT2 periodically issues a polling command PL to FLASH in order to detect completion of the write operation WR for the storage area MR12 (FIG. 11 (c)). In response to the completion of the write operation WR, the second control unit CNT2 issues a resume command RE to FLASH and restarts the erase operation ER. Then, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 without issuing a suspend command SU (FIG. 11 (d)).

  Next, in FIG. 12, the first control unit CNT1 issues a read request RREQ in order to read data held in the storage area MR02, for example (FIG. 12A). Even after completion of the read operation RD, the second control unit CNT2 issues a completion notification REND to the first control unit CNT1 without issuing a suspend command SU after the period P1 has elapsed (FIG. 12B). ). Thereafter, similarly to FIG. 11, the write operation WR and the erase operation ER are executed based on the write request WREQ.

  FIG. 13 shows an example of the operation when the semiconductor device SEM shown in FIG. 10 is powered off. The difference from FIG. 5 is that the suspend command SU is issued immediately after the write request WREQ, not immediately before the completion notification WEND (FIG. 13A). As a result, the erase operation ER can be continued during the period from the last completion notification WEND to the power-off request POFF (FIG. 13B). As a result, the time from the start of the erase operation ER to the completion thereof can be shortened. Note that the operation in FIG. 13 can prevent the supply of power from being stopped during the erase operation ER, and can prevent the FLASH from malfunctioning, as in FIG.

  FIG. 14 shows the operation of the second control unit CNT2 shown in FIG. When the second control unit CNT2 is realized by software, a program is designed according to the flow of FIG. When the second control unit CNT2 is realized by hardware, the flow in FIG. 14 is replaced with a circuit description, and a logic circuit is designed. The flow in FIG. 14 summarizes the operations in FIGS. 11 to 13.

  When receiving the write request WREQ, the second control unit CNT2 determines whether or not the FLASH erase operation ER is executed in the operation 40. When the erase operation ER is not executed, the second controller CNT2 performs the operation 44. When the erase operation ER is being executed, the second controller CNT2 issues a suspend command SU to FLASH in operation 42 in order to temporarily interrupt the erase operation ER.

  In operation 44, the second control unit CNT2 issues a write command WC to FLASH in order to execute the write operation WR based on the write request WREQ. Next, the second control unit CNT2 determines whether or not the erase operation ER needs to be started in the operation 46. When it is necessary to start the erase operation ER, the second control unit CNT2 issues an erase command EC to FLASH in operation 48, and starts the erase operation ER. When it is not necessary to start the erase operation ER, the second control unit CNT2 determines whether or not the FLASH erase operation ER needs to be restarted in operation 50. When the erasing operation ER needs to be resumed, the second control unit CNT2 issues a resume command RE to FLASH and performs an operation 54 in order to resume the erasing operation ER in the operation 52. When it is not necessary to restart the erase operation ER, that is, when FLASH is not suspended, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1 (RETURN). In the operation 54, the second control unit CNT2 waits for the period P1, ends the operation, and returns to the operation of the first control unit CNT1. “RETURN” in the drawing indicates one of the completion notifications WEND, REND, and EEND shown in FIGS.

  On the other hand, when receiving the read request RREQ, the second control unit CNT2 determines whether or not the FLASH erase operation ER is being performed in the operation 56. When the erasing operation ER is not executed, the second control unit CNT2 performs the operation 60. When the erase operation ER is being executed, the second controller CNT2 issues a suspend command SU to FLASH in operation 58 in order to temporarily interrupt the erase operation ER.

Next, in operation 60, the second control unit CNT2 issues a read command RC to FLASH based on the read request RREQ, and reads data from one of the storage areas MR. Thereafter, in operation 62, the second control unit CNT2 determines whether or not the FLASH erase operation ER needs to be restarted. When it is necessary to restart the erase operation ER, the second control unit CNT2 issues a resume command RE to FLASH in operation 64 in order to restart the erase operation ER. In operation 66, the second control unit CNT2 ends the operation after waiting for the first period P1, and returns to the operation of the first control unit CNT1. When it is unnecessary to restart the erase operation ER in the operation 62, that is, when the FLASH is not suspended, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1. Note that the control of the operation 66 may not be performed. That is, the period P1 may be secured only in response to the write request WREQ.

  Furthermore, when receiving the power-off request POFF, the second control unit CNT2 determines in operation 68 whether or not the FLASH erase operation ER is being performed. When the erasing operation ER is not executed, the second control unit CNT2 ends the operation and returns to the operation of the first control unit CNT1. When the erase operation ER is being executed, the second controller CNT2 repeatedly issues a polling command PL to FLASH until the completion of the erase operation ER is detected in operation 70. Then, the operation of the second control unit CNT2 is terminated and the operation returns to the operation of the first control unit CNT1.

  FIG. 15 shows an example of the operation of the semiconductor device SEM before the second control unit CNT2 shown in FIG. 10 is proposed. Detailed descriptions of the same operations as those in FIGS. 11 and 12 are omitted. Also in this example, the first control unit CNT1 issues a write request WREQ sequentially in order to write data to the storage area MR11-14, as in FIGS. The second control unit CNT2 issues an erase command EC or a resume command RE to FLASH after the write operation WR (FIG. 15 (a, b, c, d)). Thereafter, the second control unit CNT2 issues a completion notification WEND to the first control unit CNT1 (FIG. 15 (e, f, g, h)). However, the second control unit CNT2 issues a completion notification WEND without waiting for the period P1.

  Similar to FIGS. 11 and 12, the first control unit CNT1 issues a write request WREQ after receiving the completion notification WEND (FIG. 15 (i, j, k, l)). Based on the new write request WREQ, the second control unit CNT2 issues a suspend command SU to FLASH to interrupt the erase operation ER of FLASH, and issues a write command WC to FLASH to execute the write operation WR. Issue (FIG. 15 (m, n, o)).

  However, in this example, since there is no period P1, the period from the start or restart of the erase operation ER to the interruption is short. For this reason, before the erase operation ER of one sector SEC (SEC0 in this example) is completed, data is written in all the storage areas MR11-14 of the other sector SEC (SEC1 in this example). (FIG. 15 (p)). Even if the second control unit CNT2 receives a write request WREQ for writing data to the storage area MR01 of the sector SEC0, it cannot issue the write command WC until the erase operation ER of the sector SEC0 is completed (FIG. 15 (q) ). As a result, as in FIG. 7, a period during which data cannot be written to FLASH occurs. In other words, a long period for waiting for the completion of erasure occurs, and the apparent erasure period becomes long. In the worst case, the operation of the system device on which the semiconductor device SEM is mounted stops for a long time.

  As described above, also in this embodiment, the same effects as those of the embodiment shown in FIGS. 1 to 6 can be obtained. Furthermore, this embodiment can be applied to a flash memory FLASH having a plurality of banks BKA and BKB that operate independently. In particular, in the flash memory FLASH having a plurality of banks BKA and BKB, the first controller CNT1 can access the bank BKB and issue a write request WREQ and the like even while the bank BKA is executing the erase operation ER. Therefore, the execution efficiency of the erase operation ER can be improved and the progress of the erase operation ER can be prevented from being delayed.

  FIG. 16 shows another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the CPU has a register P1REG for setting the length of the period P1, as in FIG. Other configurations are the same as those in FIG.

  In this embodiment, as described in FIG. 9, the second control unit CNT2 rewrites the register P1REG based on the register setting command REGS from the first control unit CNT1. Then, the second control unit CNT2 sets the period P1 based on the value held in the register P1REG. As described above, also in this embodiment, the same effects as those of the embodiments shown in FIGS. 1 to 6, 8, and 9 can be obtained.

  In the above-described embodiment, the example applied to the NOR type flash memory has been described. However, the above-described embodiments may be applied to a NAND flash memory. Or you may apply to EEPROM.

  In the above-described embodiment, the example in which data is cyclically written in the two sectors SEC0-1 has been described. However, data may be cyclically written in three or more sectors SEC.

The following additional notes are disclosed with respect to the embodiment shown in FIGS.
(Appendix 1)
A plurality of memory units;
A first control unit that issues a data write request to each of the plurality of memory units;
Any of the memory units responding to the write command when a write command is issued to the corresponding memory unit based on the write request and there is an erasable memory unit in any of the plurality of memory units A second control unit that issues an erase command to execute an erase operation after the write operation;
The second control unit issues a write completion notification based on the write command to the first control unit after a first period from the issue of the erase command.
(Appendix 2)
In the semiconductor device according to attachment 1,
Two of the plurality of memory units are a first area and a second area,
The second control unit sequentially issues the write command to the first area and the second area based on the write request,
Issuing the erase command to the first area based on a predetermined write command among the write commands to the second area,
A semiconductor device, wherein a write completion notification based on the predetermined write command is issued to the first control unit after the first period from the issue of the erase command to the first region.
(Appendix 3)
In the semiconductor device according to attachment 1,
Each of the memory units includes a plurality of storage areas,
The second controller is
Issuing a plurality of the write commands to sequentially write data to the storage area based on the sequentially issued write requests;
When data written to the storage area is no longer needed in any of the memory units, the memory unit that no longer needs data is erased after issuing the write command to any of the other memory units. Issue the erase command to execute,
A semiconductor device, wherein after the first period from the issuance of the erase command to the storage area, a write completion notification based on a write command to any of the other memory units is issued to the first control unit.
(Appendix 4)
In the semiconductor device according to any one of supplementary notes 1 to 3,
The second control unit issues a suspend command for interrupting the erase operation to the memory unit that has started the erase operation in response to the erase command during the first period.
(Appendix 5)
In the semiconductor device according to attachment 4,
The second control unit issues a write command to the corresponding memory unit based on a data write request to any of the plurality of memory units, and interrupts the erase operation to any of the plurality of memory units. When there is a memory unit that is present, issue a resume command to resume the erase operation after any write operation of the memory unit in response to the write command,
A semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the resume command.
(Appendix 6)
In the semiconductor device according to attachment 4,
The second control unit issues a read command to a corresponding memory unit based on a data read request to any of the plurality of memory units, and interrupts an erasing operation to any of the plurality of memory units. Issuing a resume command to resume the erase operation after any read operation of the memory unit in response to the read command,
A semiconductor device, wherein a read completion notification based on the read command is issued to the first control unit after a first period from the issue of the resume command.
(Appendix 7)
In the semiconductor device according to appendix 5 or appendix 6,
The second control unit issues a suspend command to interrupt the erase operation to the memory unit that has resumed the erase operation in response to the resume command during the first period after the resume command is issued. A featured semiconductor device.
(Appendix 8)
The semiconductor device according to any one of appendices 1 to 7,
The second control unit issues the resume command to restart the erase operation when there is a memory unit that interrupts the erase operation when receiving a power-off request from the first control unit, A semiconductor device that issues an erasure completion notice to the first controller based on completion of an erasure operation.
(Appendix 9)
In the semiconductor device according to any one of appendices 1 to 8,
A first semiconductor memory having the memory unit and a memory unit in which a program for realizing the operation of the second control unit is stored;
And a second semiconductor memory in which a program for monitoring completion of the write operation is stored during the write operation.
(Appendix 10)
In the semiconductor device according to any one of appendices 1 to 3,
A first memory block including the memory unit;
A program for realizing the operation of the second control unit is stored, and the second memory block operates independently of the first memory block, and
The second control unit writes the data into a memory unit that is not performing an erase operation based on a new write request when any of the memory units is performing an erase operation in response to the erase command. A semiconductor device characterized by issuing a suspend command for interrupting an erase operation before issuing a command.
(Appendix 11)
In the semiconductor device according to attachment 10,
The second controller is
When any of the memory units is performing an erase operation in response to the erase command, before issuing the write command to a memory unit that is not performing an erase operation based on a new write request, Issue a suspend command to interrupt the erase operation,
Issuing a resume command to resume the erase operation after any write operation of the memory unit in response to the write command,
A semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the resume command.
(Appendix 12)
In the semiconductor device according to attachment 10,
The second controller is
When any of the memory units is performing an erase operation in response to the erase command, before issuing the read command to a memory unit that is not performing an erase operation based on a new read request, Issue a suspend command to interrupt the erase operation,
Issuing a resume command to resume the erase operation after any read operation of the memory unit in response to the read command,
A semiconductor device, wherein a read completion notification based on the read command is issued to the first control unit after a first period from the issue of the resume command.
(Appendix 13)
The semiconductor device according to any one of appendices 10 to 12,
The second control unit erases the first control unit based on the completion of the erase operation when there is a memory unit performing the erase operation when receiving a power-off request from the first control unit. A semiconductor device characterized by issuing a completion notice.
(Appendix 14)
The semiconductor device according to any one of appendices 1 to 13,
A register in which a value indicating the first period is set;
The semiconductor device according to claim 2, wherein the second control unit sets the first period based on a value set in the register.
(Appendix 15)
Issuing a data write request to each of the plurality of memory areas;
Based on the write request, issue a write command to the corresponding memory unit,
When there is an erasable memory area in any of the plurality of memory areas, issue an erase command to execute an erase operation after any write operation of the memory unit in response to the write command;
A method of operating a semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the erase command.
(Appendix 16)
In the operation method of the semiconductor device according to attachment 15,
Two of the plurality of memory units are a first area and a second area,
Sequentially issue the write command to the first area and the second area based on the write request;
Issuing the erase command to the first area based on a predetermined write command among the write commands to the second area,
A method of operating a semiconductor device, wherein a write completion notification based on the predetermined write command is issued to the first controller after the first period from the issue of the erase command to the first region.
(Appendix 17)
In the operation method of the semiconductor device according to attachment 15,
Each of the memory units includes a plurality of storage areas,
Issuing a plurality of the write commands to sequentially write data to the storage area based on the sequentially issued write requests;
When data written to the storage area is no longer needed in any of the memory units, the memory unit that no longer needs data is erased after issuing the write command to any of the other memory units. Issue the erase command to execute,
A write completion notification based on a write command to one of other memory units is issued to the first control unit after the first period from the issuance of the erase command to the storage area. How it works.
(Appendix 18)
In the operation method of the semiconductor device according to any one of appendix 15 to appendix 17,
A method of operating a semiconductor device, wherein a suspend command for interrupting an erasing operation is issued to a memory portion that has started an erasing operation in response to the erasing command during the first period.
(Appendix 19)
In the operation method of the semiconductor device according to attachment 18,
When a write command is issued to the corresponding memory unit based on a data write request to one of the plurality of memory units, and there is a memory unit that interrupts the erasing operation in any of the plurality of memory units , After any write operation of the memory unit responding to the write command, issue a resume command to resume the erase operation,
A method of operating a semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the resume command.
(Appendix 20)
In the operation method of the semiconductor device according to any one of appendix 15 to appendix 17,
A first memory block including the memory unit;
A program for realizing the operation of the second control unit is stored, and the second memory block operates independently of the first memory block, and
When any of the memory units is performing an erase operation in response to the erase command, before issuing the write command to a memory unit that is not performing an erase operation based on a new write request, A method of operating a semiconductor device, wherein a suspend command for interrupting an erase operation is issued.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

1 illustrates one embodiment. An example of access to the memory cell array shown in FIG. 1 is shown. 2 illustrates an example of the operation of the semiconductor device illustrated in FIG. 1. The continuation of the example of operation | movement of the semiconductor device shown in FIG. 1 is shown. 2 illustrates an example of an operation when the semiconductor device illustrated in FIG. 1 is powered off. The operation | movement of the 2nd control part shown in FIG. 1 is shown. The example of operation | movement of the semiconductor device before the 2nd control part shown in FIG. 1 is proposed is shown. Figure 3 shows another embodiment. 9 shows an example of the operation of the semiconductor device shown in FIG. Figure 3 shows another embodiment. 11 shows an example of the operation of the semiconductor device shown in FIG. 11 shows a continuation of an example of the operation of the semiconductor device shown in FIG. 11 illustrates an example of an operation when the semiconductor device illustrated in FIG. 10 is powered off. The operation | movement of the 2nd control part shown in FIG. 10 is shown. 11 shows an example of the operation of the semiconductor device before the second control unit shown in FIG. 10 is proposed. Figure 3 shows another embodiment.

Explanation of symbols

  ACNT: Address control circuit; ARY: Memory cell array; CCNT: Command control circuit; CNT1: First control unit; CNT2: Second control unit: DCNT: Data control circuit; Operation: MR01-04, MR11-14 Storage area: PL Polling command; POFF Power-off request; RC Read command; RD Read operation; RE Resume command; REND Completion notification; -5, SECA0-1, SECB0-3, sector; SU, suspend command; VGEN, voltage generation circuit; WC, write command; WEND, completion notification; WR, write operation;

Claims (7)

A plurality of memory units;
A first control unit that issues a data write request to each of the plurality of memory units;
Any of the memory units responding to the write command when a write command is issued to the corresponding memory unit based on the write request and there is an erasable memory unit in any of the plurality of memory units A second control unit that issues an erase command to execute an erase operation after the write operation;
The second control unit issues a write completion notification based on the write command to the first control unit after a first period from the issue of the erase command. The semiconductor device according to claim 1,
Each of the memory units includes a plurality of storage areas,
The second controller is
Issuing a plurality of the write commands to sequentially write data to the storage area based on the sequentially issued write requests;
When data written to the storage area is no longer needed in any of the memory units, the memory unit that no longer needs data is erased after issuing the write command to any of the other memory units. Issue the erase command to execute,
A semiconductor device, wherein after the first period from the issuance of the erase command to the storage area, a write completion notification based on a write command to any of the other memory units is issued to the first control unit. The semiconductor device according to claim 1 or 2,
The second control unit issues a suspend command for interrupting the erase operation to the memory unit that has started the erase operation in response to the erase command during the first period. The semiconductor device according to claim 1 or 2,
A first memory block including the memory unit;
A program for realizing the operation of the second control unit is stored, and the second memory block operates independently of the first memory block, and
The second control unit writes the data into a memory unit that is not performing an erase operation based on a new write request when any of the memory units is performing an erase operation in response to the erase command. A semiconductor device characterized by issuing a suspend command for interrupting an erase operation before issuing a command. The semiconductor device according to claim 4.
The second controller is
When any of the memory units is performing an erase operation in response to the erase command, before issuing the write command to a memory unit that is not performing an erase operation based on a new write request, Issue a suspend command to interrupt the erase operation,
Issuing a resume command to resume the erase operation after any write operation of the memory unit in response to the write command,
A semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the resume command. The semiconductor device according to claim 4.
The second controller is
When any of the memory units is performing an erase operation in response to the erase command, before issuing the read command to a memory unit that is not performing an erase operation based on a new read request, Issue a suspend command to interrupt the erase operation,
Issuing a resume command to resume the erase operation after any read operation of the memory unit in response to the read command,
A semiconductor device, wherein a read completion notification based on the read command is issued to the first control unit after a first period from the issue of the resume command. Issuing a data write request to each of the plurality of memory areas;
Based on the write request, issue a write command to the corresponding memory unit,
When there is an erasable memory area in any of the plurality of memory areas, issue an erase command to execute an erase operation after any write operation of the memory unit in response to the write command;
A method of operating a semiconductor device, wherein a write completion notification based on the write command is issued to the first control unit after a first period from the issue of the erase command.

Images