JP2009100281A - Differential amplification apparatus and overcurrent protection apparatus - Google Patents

Differential amplification apparatus and overcurrent protection apparatus Download PDF

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JP2009100281A
JP2009100281A JP2007270179A JP2007270179A JP2009100281A JP 2009100281 A JP2009100281 A JP 2009100281A JP 2007270179 A JP2007270179 A JP 2007270179A JP 2007270179 A JP2007270179 A JP 2007270179A JP 2009100281 A JP2009100281 A JP 2009100281A
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resistor
semiconductor element
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Shunzo Oshima
俊藏 大島
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Yazaki Corp
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Yazaki Corp
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<P>PROBLEM TO BE SOLVED: To provide a differential amplification apparatus and an overcurrent protection apparatus can detecting occurrence of overcurrent with high precision by avoiding the effect caused by an offset voltage that an operational amplifier has. <P>SOLUTION: There are provided a series connection circuit of resistors R3, R4, R5 provided between a drain of a switching MOSFET (T1) and a ground and a series connection circuit of a resistor R1, resistor R2 and transistor (T2) provided between a source of the MOSFET (T1) and the ground. Furthermore, a current Ix is extracted from a resistor R7 provided between a forward input terminal a1 of an amplifier (AMP1) and a point (a) and a current Iy is extracted from a resistor R8 provided between a backward input terminal b1 of the amplifier (AMP1) and a point (b), thereby reducing a voltage Vab that occurs between the point (a) and the point (b). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電源と負荷との間にスイッチング用の半導体素子を設けて負荷を駆動する回路の、過電流を検出して回路を保護する過電流保護装置、及び該過電流保護装置等に適用可能な差動増幅装置に関する。   INDUSTRIAL APPLICABILITY The present invention is applied to an overcurrent protection device that protects a circuit by detecting an overcurrent of a circuit that drives a load by providing a semiconductor element for switching between a power source and a load, and the overcurrent protection device. It relates to a possible differential amplifier.

例えば、車両に搭載されるランプ、モータ等の負荷を駆動する負荷回路では、電源（バッテリ）と負荷との間にスイッチング用の半導体素子を設け、該半導体素子をオン、オフ操作することにより、負荷の駆動、停止を制御する。また、負荷回路にデッドショート、或いはレアショート等による過電流が流れた場合には、これを検出して即時に負荷回路を遮断するために、過電流保護装置が設けられている。   For example, in a load circuit that drives a load such as a lamp or a motor mounted on a vehicle, a semiconductor element for switching is provided between a power source (battery) and the load, and the semiconductor element is turned on and off, Controls driving and stopping of the load. Further, an overcurrent protection device is provided in order to detect and immediately shut off the load circuit when an overcurrent due to a dead short circuit or a rare short circuit flows in the load circuit.

このような過電流保護装置の従来例として、例えば、特開２００２−３５３７９４号公報（特許文献１）に記載されたものが知られている。   As a conventional example of such an overcurrent protection device, for example, one described in Japanese Patent Application Laid-Open No. 2002-353794 (Patent Document 1) is known.

上記特許文献１に記載された技術では、半導体素子として用いるＭＯＳＦＥＴのドレイン・ソース間電圧（Ｖds）をオペアンプで増幅し、増幅した電圧を予め設定した判定電圧と比較して、過電流が発生しているか否かを判定する。   In the technique described in Patent Document 1 above, the drain-source voltage (Vds) of a MOSFET used as a semiconductor element is amplified by an operational amplifier, and the amplified voltage is compared with a preset determination voltage to generate an overcurrent. It is determined whether or not.

図６は、従来における過電流保護装置の回路図であり、同図を参照して従来例について説明する。同図に示すように、ランプ或いはモータ等の負荷ＲＬと電源ＶＢとの間には、スイッチング用のＭＯＳＦＥＴ（Ｔ１０１）が設けられており、該ＭＯＳＦＥＴ（Ｔ１０１）のゲートは、抵抗Ｒ１１０を介してドライバ１０１に接続されている。従って、ドライバ１０１より出力される制御信号により、ＭＯＳＦＥＴ（Ｔ１０１）がオン、オフ操作され、負荷ＲＬの駆動、停止が制御される。   FIG. 6 is a circuit diagram of a conventional overcurrent protection device, and a conventional example will be described with reference to FIG. As shown in the figure, a switching MOSFET (T101) is provided between a load RL such as a lamp or a motor and a power supply VB, and the gate of the MOSFET (T101) is connected via a resistor R110. It is connected to the driver 101. Therefore, the MOSFET (T101) is turned on and off by the control signal output from the driver 101, and the driving and stopping of the load RL are controlled.

ＭＯＳＦＥＴ（Ｔ１０１）のドレイン・ソース間電圧Ｖdsは、ＭＯＳＦＥＴ（Ｔ１０１）のドレイン電圧（点Ｐ１の電圧）をＶ１、ソース電圧（点Ｐ２の電圧）をＶ２、ＭＯＳＦＥＴ（Ｔ１０１）のオン抵抗をＲon、ドレイン電流をＩＤとすると、以下の（１）式で示される。   The drain-source voltage Vds of the MOSFET (T101) is the drain voltage (voltage at the point P1) of the MOSFET (T101) is V1, the source voltage (voltage at the point P2) is V2, the on-resistance of the MOSFET (T101) is Ron, When the drain current is ID, it is expressed by the following equation (1).

Ｖds＝Ｖ１−Ｖ２＝Ｒon＊ＩＤ …（１）
また、ドレイン・ソース間電圧Ｖdsは、抵抗Ｒ１０３、Ｒ１０５、トランジスタ（Ｔ１０２）、オペアンプＡＭＰ１０１からなる増幅回路で増幅される。なお、図６の各抵抗の符号の下に記載している数字は、抵抗値の例を示している。例えば、抵抗Ｒ１０３は、抵抗値が１００［Ω］である。 Vds = V1-V2 = Ron * ID (1)
Further, the drain-source voltage Vds is amplified by an amplifier circuit including resistors R103 and R105, a transistor (T102), and an operational amplifier AMP101. In addition, the number described under the code | symbol of each resistance of FIG. 6 has shown the example of resistance value. For example, the resistance value of the resistor R103 is 100 [Ω].

抵抗Ｒ１０３とトランジスタ（Ｔ１０２）の接続点Ｐ３の電圧Ｖａが、オペアンプＡＭＰ１０１の正転入力端子に入力され、ＭＯＳＦＥＴ（Ｔ１０１）のソース電圧（点Ｐ２の電圧）Ｖ２が、オペアンプＡＭＰ１０１の反転入力端子に入力され、オペアンプＡＭＰ１０１出力は、トランジスタ（Ｔ１０２）の制御端子に入力される。   The voltage Va at the connection point P3 between the resistor R103 and the transistor (T102) is input to the normal input terminal of the operational amplifier AMP101, and the source voltage (voltage at the point P2) V2 of the MOSFET (T101) is input to the inverting input terminal of the operational amplifier AMP101. The operational amplifier AMP101 output is input to the control terminal of the transistor (T102).

そして、点Ｐ１→抵抗Ｒ１０３→トランジスタ（Ｔ１０２）→抵抗Ｒ１０５→グランドの経路を流れる電流Ｉ１の大きさは、アンプＡＭＰ１０１とトランジスタ（Ｔ１０２）が常にＶａ＝Ｖ２となるように制御する結果として定まる電流値になる。ここで、アンプＡＭＰ１０１のオフセット電圧を±Ｖoffとすると、次の（２）式が得られる。   The magnitude of the current I1 flowing through the path of the point P1, the resistor R103, the transistor (T102), the resistor R105, and the ground is determined as a result of controlling the amplifier AMP101 and the transistor (T102) to always have Va = V2. Value. Here, when the offset voltage of the amplifier AMP101 is ± Voff, the following equation (2) is obtained.

Ｖds±Ｖoff＝Ｒ１０３＊Ｉ１ …（２）
また、抵抗Ｒ１０５に生じる電圧Ｖ５が、電圧Ｖdsを増幅した電圧となり、Ｒ１０５／Ｒ１０３＝ｍとすると、電圧Ｖ５は、次の（３）式で示される。 Vds ± Voff = R103 * I1 (2)
Further, when the voltage V5 generated in the resistor R105 is a voltage obtained by amplifying the voltage Vds, and R105 / R103 = m, the voltage V5 is expressed by the following equation (3).

Ｖ５＝Ｒ１０５＊Ｉ１＝（Ｒ１０５／Ｒ１０３）＊Ｒ１０３＊Ｉ１
＝Ｒ１０５／Ｒ１０３＊（Ｖds±Ｖoff）
＝ｍ＊（Ｒon＊ＩＤ±Ｖoff） …（３）
（３）式から理解されるように、アンプＡＭＰ１０１のオフセット電圧（±Ｖoff）をｍ倍した電圧が、電圧Ｖ５のばらつきとして発生する。 V5 = R105 * I1 = (R105 / R103) * R103 * I1
= R105 / R103 * (Vds ± Voff)
= M * (Ron * ID ± Voff) (3)
As understood from the equation (3), a voltage obtained by multiplying the offset voltage (± Voff) of the amplifier AMP101 by m is generated as a variation in the voltage V5.

増幅された電圧Ｖ５がコンパレータＣＭＰ１０１の反転入力端子に入力され、コンパレータＣＭＰ１０１の正転入力端子には、点Ｐ４に生じる判定電圧Ｖ４が入力される。判定電圧Ｖ４は、電源ＶＢの出力電圧、即ち点Ｐ１の電圧Ｖ１を、抵抗Ｒ１０１と抵抗Ｒ１０２で分圧して生成される。   The amplified voltage V5 is input to the inverting input terminal of the comparator CMP101, and the determination voltage V4 generated at the point P4 is input to the normal input terminal of the comparator CMP101. The determination voltage V4 is generated by dividing the output voltage of the power supply VB, that is, the voltage V1 at the point P1 by the resistors R101 and R102.

ここで、ドレイン電流ＩＤが過電流状態になると、ＭＯＳＦＥＴ（Ｔ１０１）のドレイン・ソース間電圧Ｖdsが大きくなり、Ｖ５＞Ｖ４となって、コンパレータＣＭＰ１０１の出力が反転することにより、過電流状態が検出される。過電流として検知されるドレイン電流ＩＤの値を、Ｉovcとすると、次の（４）式が得られる。   Here, when the drain current ID becomes an overcurrent state, the drain-source voltage Vds of the MOSFET (T101) increases, and V5> V4, and the output of the comparator CMP101 is inverted, thereby detecting the overcurrent state. Is done. If the value of the drain current ID detected as an overcurrent is Iovc, the following equation (4) is obtained.

Ｖ５＝ｍ＊（Ｒon＊Ｉovc±Ｖoff）＝Ｖ４
∴Ｉovc＝（Ｖ４／ｍ／Ｒon）±（Ｖoff／Ｒon） …（４）
ここで、アンプＡＭＰ１０１にオフセット電圧が存在しなければ、即ち、Ｖoff＝０であれば、過電流検出値ＩovcはＶ４，Ｒ１０３，Ｒ１０５，Ｒonで決まる一定値となる。しかし、アンプＡＭＰ１０１のオフセット電圧（±Ｖoff）が存在する場合には、過電流検出値Ｉovcがばらつき、そのばらつき量は（±Ｖoff／Ｒon）となり、同一オフセット電圧に対しては、オン抵抗Ｒonが小さくなるに連れてＩovcのばらつき幅が大きくなる。 V5 = m * (Ron * Iovc ± Voff) = V4
∴Iovc = (V4 / m / Ron) ± (Voff / Ron) (4)
Here, if there is no offset voltage in the amplifier AMP101, that is, if Voff = 0, the overcurrent detection value Iovc is a constant value determined by V4, R103, R105, and Ron. However, when the offset voltage (± Voff) of the amplifier AMP101 exists, the overcurrent detection value Iovc varies, and the variation amount becomes (± Voff / Ron). For the same offset voltage, the on-resistance Ron is As it decreases, the variation width of Iovc increases.

また、アンプＡＭＰ１０１を含めて増幅回路がＩＣ化された場合、オフセット電圧（±Ｖoff）のばらつき幅はＩＣ化プロセスに依存し、通常のＩＣでは±１０［ｍＶ］程度のばらつき幅となるので、Ｒon＝３［ｍΩ］とすれば、遮断電流値は±３．３［Ａ］ばらつくことになる。
特開２００２−３５３７９４号公報 In addition, when the amplifier circuit including the amplifier AMP101 is integrated, the variation width of the offset voltage (± Voff) depends on the IC integration process, and in a normal IC, the variation width is about ± 10 [mV]. If Ron = 3 [mΩ], the cutoff current value varies by ± 3.3 [A].
JP 2002-353794 A

上述したように、スイッチング素子として用いる半導体素子（ＭＯＳＦＥＴ）のドレイン・ソース間電圧Ｖdsを増幅し、この増幅出力を用いて過電流判定を行う過電流保護装置では、アンプＡＭＰ１０１のオフセット電圧Ｖoffは過電流検出値のばらつき要因となり、過電流検出値の精度を低下させる。更に、今後ＭＯＳＦＥＴ（Ｔ１）のオン抵抗Ｒonが小さくなる傾向が進むと、相対的にばらつき幅が増大し、精度低下はますます大きくなるので、増幅回路におけるアンプＡＭＰ１０１のオフセット電圧の影響を回避することが重要な問題となる。   As described above, in the overcurrent protection device that amplifies the drain-source voltage Vds of the semiconductor element (MOSFET) used as the switching element and performs the overcurrent determination using the amplified output, the offset voltage Voff of the amplifier AMP101 is excessive. This causes variation in the current detection value and reduces the accuracy of the overcurrent detection value. Furthermore, if the on-resistance Ron of the MOSFET (T1) tends to decrease in the future, the variation width will increase relatively and the accuracy will decrease further, so the influence of the offset voltage of the amplifier AMP101 in the amplifier circuit is avoided. Is an important issue.

本発明は、このような従来の課題を解決するためになされたものであり、その目的とするところは、オペアンプが有するオフセット電圧による影響を回避し、高精度に過電流の発生を検出することが可能な過電流保護装置、及び該過電流検出装置等に適用可能な差動増幅装置を提供することにある。   The present invention has been made to solve such a conventional problem, and an object of the present invention is to avoid the influence of the offset voltage of the operational amplifier and to detect the occurrence of overcurrent with high accuracy. It is an object of the present invention to provide an overcurrent protection device capable of performing the above and a differential amplification device applicable to the overcurrent detection device and the like.

上記目的を達成するため、本願請求項１に記載の差動増幅装置は、増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）と第２の抵抗（Ｒ２）の接続点ｂを接続し、正転入力端子ａ１に第３の抵抗（Ｒ３）と第４の抵抗（Ｒ４）の接続点ａを接続し、前記第２の抵抗の他端に第２の半導体素子（Ｔ２）の第１の主電極（ソース）を接続し、前記第２の半導体素子の第１の主電極（ドレイン）を接地し、制御電極（ゲート）を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、前記第４の抵抗の他端を第５の抵抗（Ｒ５）を経由して接地し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力し、前記第２の抵抗と前記第２の半導体素子との接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１，Ｒ３，Ｒ７，Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、「Ｉｙ−Ｉｘ」が前記Ｖabに比例し、且つ、（Ｒ１＋Ｒ７）＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するようにＩｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする。   In order to achieve the above object, in the differential amplifying device according to claim 1 of the present application, the connection point b between the first resistor (R1) and the second resistor (R2) is connected to the inverting input terminal b1 of the amplifying means (AMP1). Is connected to the forward rotation input terminal a1, and the connection point a of the third resistor (R3) and the fourth resistor (R4) is connected to the second semiconductor element (T2) at the other end of the second resistor. A first main electrode (source) of the second semiconductor element, a first main electrode (drain) of the second semiconductor element is grounded, a control electrode (gate) is connected to an output terminal of the amplification means, and the first The other end of the third resistor is connected to the power supply terminal d, the other end of the fourth resistor is grounded via a fifth resistor (R5), and the other end of the power supply terminal d and the first resistor An input voltage (Vds) is input between the second resistor and the second semiconductor element, a connection point y between the second resistor and the second resistor, and the fourth resistor and the second resistor. In the differential amplifying apparatus using the potential difference between the resistor x and the connection point x as the output voltage, a seventh resistor (R7) is inserted between the normal rotation input terminal a1 and the connection point a, and the inversion is performed. An eighth resistor (R8) is inserted between the input terminal b1 and the connection point b, the offset voltage of the amplification means is “Voff”, and the potential difference between the connection point a and the connection point b is “Vab”. The resistance values of the first, third, seventh, and eighth resistors are “R1, R3, R7, R8” (where R1 = R3, R7 = R8), power source → R3 → R7 → ground, respectively. Where “Ix” is the current flowing through the path of “1”, and “Iy” is the current flowing through the path of power supply → input voltage (Vds) → R1 → R8 → ground, and “Iy−Ix” is proportional to Vab, and To control Ix and Iy so that (R1 + R7) * (Ix−Iy) + Voff = 0 is satisfied. Thus, it is possible to reduce an error caused by an offset voltage (Voff) of the amplifying means, which is generated when the input voltage (Vds) is amplified to generate an output voltage.

請求項２に記載の差動増幅装置は、増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）を接続し、接続点をｂとし、正転入力端子ａ１に第３の抵抗（Ｒ３）を接続し、接続点をａとし、第２の抵抗（Ｒ２）の一端を接地し、他端を第２の半導体素子（Ｔ２）の第２の主電極（ソース）に接続し、前記第２の半導体素子の第１の主電極（ドレイン）を前記接続点ｂに接続し、制御電極（ゲート）を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、第４の抵抗の一端を接地し、他端を第５の抵抗（Ｒ５）を経由して前記接続点ａに接続し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力し、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１，Ｒ３，Ｒ７，Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、「Ｉｙ−Ｉｘ」が前記Ｖabに比例し、且つ、（Ｒ１＋Ｒ７）＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するようにＩｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする。   In the differential amplifying device according to claim 2, the first resistor (R1) is connected to the inverting input terminal b1 of the amplifying means (AMP1), the connection point is b, and the third resistance is connected to the normal rotation input terminal a1. (R3) is connected, the connection point is a, one end of the second resistor (R2) is grounded, the other end is connected to the second main electrode (source) of the second semiconductor element (T2), The first main electrode (drain) of the second semiconductor element is connected to the connection point b, the control electrode (gate) is connected to the output terminal of the amplification means, and the other end of the third resistor is connected to the power source. Connected to the terminal d, one end of the fourth resistor is grounded, the other end is connected to the connection point a via the fifth resistor (R5), and the other of the power supply terminal d and the first resistor An input voltage (Vds) is input between the terminal, the connection point y between the second resistor and the second semiconductor element, the fourth resistor, and the fifth resistor. In a differential amplifying apparatus that uses a potential difference between a resistor connection point x and an output voltage as an output voltage, a seventh resistor (R7) is inserted between the normal rotation input terminal a1 and the connection point a, and the inverting input An eighth resistor (R8) is inserted between the terminal b1 and the connection point b, the offset voltage of the amplification means is “Voff”, and the potential difference between the connection point a and the connection point b is “Vab”. The resistance values of the first, third, seventh, and eighth resistors are “R1, R3, R7, R8” (where R1 = R3, R7 = R8), power supply → R3 → R7 → ground. When the current flowing through the path is “Ix” and the current flowing through the path of power source → input voltage (Vds) → R1 → R8 → ground is “Iy”, “Iy−Ix” is proportional to Vab, and ( R1 + R7) * (Ix−Iy) + Voff = 0 by controlling Ix and Iy. Thus, an error due to the offset voltage (Voff) of the amplifying means, which occurs when the input voltage (Vds) is amplified to generate an output voltage, is reduced.

請求項３、請求項４に記載の差動増幅装置は、請求項１または２において、前記Ｉｘ、Ｉｙを生成する方法は、前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３および第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極（ソース）に接続し、前記第３の半導体素子（Ｔ３）の制御電極（ゲート）を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極（ゲート）を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、および第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）の各半導体素子の第２の主電極（ソース）を接地し、前記第５の半導体素子の第１の主電極（ドレイン）と制御電極（ゲート）を接続し、更にこの接続点に前記第６、第７の半導体素子の制御電極（ゲート）を接続し、前記第５の半導体素子の第１の主電極（ドレイン）を、前記第３及び第８の半導体素子の第１の主電極（ドレイン）に接続し、前記第６の半導体素子の第１の主電極（ドレイン）を前記増幅手段（ＡＭＰ１）の正転入力端子ａ１に接続し、一方、前記第１０の半導体素子の第１の主電極（ドレイン）と制御電極（ゲート）を接続し、更にこの接続点に前記第８、第９の半導体素子の制御電極（ゲート）を接続し、前記第１０の半導体素子の第１の主電極（ドレイン）を、前記第４及び第７の半導体素子の第１の主電極（ドレイン）に接続し、前記第９の半導体素子の第１の主電極（ドレイン）を前記増幅手段の正転入力端子ｂ１に接続し、前記第６の半導体素子のドレイン電流を前記Ｉｘ、前記第９の半導体素子のドレイン電流を前記Ｉｙとすることを特徴とする。   The differential amplifying device according to claim 3 or claim 4 is the method of generating the Ix and Iy according to claim 1 or 2, wherein one end of a constant current source (Ia) is connected to the power supply terminal d. The other end is connected to the second main electrode (source) of the third and fourth semiconductor elements (T3, T4), and the control electrode (gate) of the third semiconductor element (T3) is connected to the connection point a. And the control electrode (gate) of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), seventh (T7), and tenth The second main electrode (source) of each of the (T10), eighth (T8), and ninth (T9) semiconductor elements is grounded, and the first main electrode (drain) and control electrode of the fifth semiconductor element (Gate) is connected, and furthermore, the control electrodes (gates) of the sixth and seventh semiconductor elements are connected to this connection point, The first main electrode (drain) of the fifth semiconductor element is connected to the first main electrode (drain) of the third and eighth semiconductor elements, and the first main electrode (drain) of the sixth semiconductor element is connected. The electrode (drain) is connected to the normal input terminal a1 of the amplification means (AMP1), while the first main electrode (drain) and the control electrode (gate) of the tenth semiconductor element are connected, and this The control electrodes (gates) of the eighth and ninth semiconductor elements are connected to a connection point, and the first main electrode (drain) of the tenth semiconductor element is connected to the fourth and seventh semiconductor elements. The first main electrode (drain) of the ninth semiconductor element is connected to the normal input terminal b1 of the amplifying means, and the drain current of the sixth semiconductor element is connected to the main electrode (drain) of the ninth semiconductor element. Ix and the drain current of the ninth semiconductor element are Iy and And wherein the Rukoto.

請求項５に記載の過電流保護装置は、電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、前記負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項１または３に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項１または３に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、前記電源端子ｄと前記接続点ｙとの間の電圧が、前記電源端子ｄと前記接続点ｘ間の電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする。   In the overcurrent protection device according to claim 5, the first semiconductor element (T1) is disposed between the power source (VB) and the load (RL), and the first main electrode of the first semiconductor is used as the power source. The second main electrode is connected to the load side, the other end of the load is connected to a ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element, An overcurrent protection device that is provided in a load circuit that controls driving and stopping of a load, and that protects the load circuit when an overcurrent occurs by using the differential amplifying device according to claim 1 or 3, The first main electrode of one semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. Alternatively, as the input voltage (Vds) of the differential amplifying device according to 3, the first main electrode of the first semiconductor element and the second voltage A voltage between the electrodes is input, the resistance value of the second resistor is set to be larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set to be equal, When the voltage between the power supply terminal d and the connection point y becomes smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage between the power supply terminal d and the connection point x, the current flows to the load. It is determined that the current is an overcurrent, and the first semiconductor element is cut off.

請求項６に記載の過電流保護装置は、電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項２または４に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項２または４に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、前記接続点ｙの電圧が、前記接続点ｘの電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする。   In the overcurrent protection device according to claim 6, the first semiconductor element (T1) is disposed between the power source (VB) and the load (RL), and the first main electrode of the first semiconductor is used as the power source. And the second main electrode is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element, An overcurrent protection device that is provided in a load circuit that controls driving and stopping of a load, and that protects the load circuit when an overcurrent occurs by using the differential amplifier according to claim 2, The first main electrode of one semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. Alternatively, as the input voltage (Vds) of the differential amplifying device described in 4, the first main electrode and the second main electrode of the first semiconductor element A voltage between the electrodes is input, the resistance value of the second resistor is set to be larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set to be equal, When the voltage at the connection point y is smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage at the connection point x, it is determined that the current flowing through the load is an overcurrent, and the first The semiconductor element is cut off.

請求項７に記載の差動増幅装置は、増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）と第２の抵抗（Ｒ２）の接続点ｂを接続し、正転入力端子ａ１に第３の抵抗（Ｒ３）と第４の抵抗（Ｒ４）の接続点ａを接続し、前記第２の抵抗の他端に第２の半導体素子（Ｔ２）の第２の主電極（ソース）を接続し、前記第２の半導体素子の第１の主電極（ドレイン）を接地し、且つ、制御電極（ゲート）を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、前記第４の抵抗の他端を第５の抵抗（Ｒ５）を経由して接地し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力して、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１、Ｒ３、Ｒ７、Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）とし、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」とし、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流「Ｉｙ」とするとき、前記Ｉｘが前記第１の抵抗を流れ、前記Ｉｙが前記第３の抵抗を流れるように構成し、且つ、Ｒ７＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するように、前記Ｉｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする。   The differential amplifying device according to claim 7 connects the connection point b of the first resistor (R1) and the second resistor (R2) to the inverting input terminal b1 of the amplifying means (AMP1), and the normal input terminal The connection point a of the third resistor (R3) and the fourth resistor (R4) is connected to a1, and the second main electrode (source) of the second semiconductor element (T2) is connected to the other end of the second resistor. ), The first main electrode (drain) of the second semiconductor element is grounded, the control electrode (gate) is connected to the output terminal of the amplification means, and the other end of the third resistor Is connected to the power supply terminal d, the other end of the fourth resistor is grounded via a fifth resistor (R5), and an input voltage is connected between the power supply terminal d and the other end of the first resistor. (Vds) is input, a connection point y between the second resistor and the second semiconductor element, a connection point x between the fourth resistor and the fifth resistor, In the differential amplifying apparatus using the potential difference therebetween as an output voltage, a seventh resistor (R7) is inserted between the normal rotation input terminal a1 and the connection point a, and the inverting input terminal b1 and the connection point b are connected. An eighth resistor (R8) is inserted between them, the offset voltage of the amplification means is “Voff”, the potential difference between the connection point a and the connection point b is “Vab”, the first, third, and second 7 and 8 are set to “R1, R3, R7, R8” (where R1 = R3, R7 = R8), and the current flowing through the path of power source → R3 → R7 → ground is “Ix” , And the current “Iy” flowing through the path of power source → input voltage (Vds) → R1 → R8 → ground so that the Ix flows through the first resistor and the Iy flows through the third resistor. And satisfying R7 * (Ix−Iy) + Voff = 0. x, by controlling the Iy, resulting in generating an output voltage by amplifying the input voltage (Vds), characterized in that to reduce the error due to the offset voltage (Voff) of said amplifying means.

請求項８に記載の差動増幅装置は、増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）を接続し、この接続点をｂとし、正転入力端子ａ１に第３の抵抗（Ｒ３）を接続し、この接続点をａとし、第２の抵抗の一端を接地し、他端を第２の半導体素子（Ｔ２）の第２の主電極（ソース）に接続し、前記第２の半導体素子の第１の主電極（ドレイン）を前記接続点ｂに接続し、制御電極（ゲート）を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、第４の抵抗の一端を接地し、他端を第５の抵抗（Ｒ５）を経由して前記接続点ａに接続し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力して、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１、Ｒ３、Ｒ７、Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）とし、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」とし、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、前記Ｉｘが前記第１の抵抗を流れ、前記Ｉｙが前記第３の抵抗を流れるように構成し、且つ、Ｒ７＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するように、前記Ｉｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする。   In the differential amplifying device according to claim 8, the first resistor (R1) is connected to the inverting input terminal b1 of the amplifying means (AMP1), this connection point is b, and the third rotation input terminal a1 is connected to the third input terminal a1. A resistor (R3) is connected, the connection point is a, one end of the second resistor is grounded, and the other end is connected to the second main electrode (source) of the second semiconductor element (T2), The first main electrode (drain) of the second semiconductor element is connected to the connection point b, the control electrode (gate) is connected to the output terminal of the amplification means, and the other end of the third resistor is the power supply terminal. d, one end of the fourth resistor is grounded, the other end is connected to the connection point a via a fifth resistor (R5), and the other end of the power supply terminal d and the first resistor An input voltage (Vds) is input between the second resistor and the second semiconductor element, a connection point y between the second resistor and the second resistor, and the fourth resistor and the second resistor. In the differential amplifying apparatus using the potential difference between the resistor x and the connection point x as the output voltage, a seventh resistor (R7) is inserted between the normal rotation input terminal a1 and the connection point a, and the inversion is performed. An eighth resistor (R8) is inserted between the input terminal b1 and the connection point b, the offset voltage of the amplification means is “Voff”, and the potential difference between the connection point a and the connection point b is “Vab”. The resistance values of the first, third, seventh, and eighth resistors are “R1, R3, R7, R8” (where R1 = R3, R7 = R8), and the power source → R3 → R7 → When the current flowing through the ground path is “Ix” and the current flowing through the power supply → input voltage (Vds) → R1 → R8 → ground path is “Iy”, the Ix flows through the first resistor, Iy is configured to flow through the third resistor, and R7 * (Ix−Iy) + Voff = By controlling the Ix and Iy so as to satisfy the above, an error due to the offset voltage (Voff) of the amplifying means generated when the input voltage (Vds) is amplified to generate an output voltage is reduced. It is characterized by.

請求項９、請求項１０に記載の差動増幅装置は、請求項７または８において、前記Ｉｘ、Ｉｙを生成する方法は、前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３及び第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極（ソース）に接続し、前記第３の半導体素子（Ｔ３）の制御電極（ゲート）を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極（ゲート）を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、第２０（Ｔ２０）、及び第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）、第２１（Ｔ２１）の各半導体素子の第２の主電極（ソース）を接地し、前記第５の半導体素子の第１の主電極（ドレイン）と制御電極（ゲート）を接続し、且つ、この接続点に前記第６、第７、第２０の半導体素子の制御電極（ゲート）を接続し、前記第５の半導体素子の第１の主電極（ドレイン）を前記第３及び第８の半導体素子の第１の主電極（ドレイン）に接続し、前記第６の半導体素子の第１の主電極（ドレイン）を前記増幅手段の正転入力端子ａ１に接続し、前記第２０の半導体素子のチャンネル幅、及びチャンネル長を前記第６の半導体素子と同一に設定し、且つ第２０の半導体素子の第１の主電極（ドレイン）を前記接続点ｂに接続し、一方、前記第１０の半導体素子の第１の主電極（ドレイン）と制御電極（ゲート）を接続し、且つ、この接続点に前記第８、第９、第２１の半導体素子の制御電極（ゲート）を接続し、前記第１０の半導体素子の第１の主電極（ドレイン）を前記第４及び第７の半導体素子の第１の主電極（ドレイン）に接続し、前記第９の半導体素子の第１の主電極（ドレイン）を前記増幅手段の反転入力端子ｂ１に接続し、前記第２１の半導体素子のチャンネル幅、及びチャンネル長を前記第９の半導体素子と同一に設定し、且つ第２１の半導体素子の第１の主電極（ドレイン）を前記接続点ａに接続し、前記第６の半導体素子のドレイン電流をＩｘ、前記第９の半導体素子のドレイン電流をＩｙとすることを特徴とする。   The differential amplifying device according to any one of claims 9 and 10 is the method of generating the Ix and Iy according to the seventh or eighth aspect, wherein one end of a constant current source (Ia) is connected to the power supply terminal d. The other end is connected to the second main electrode (source) of the third and fourth semiconductor elements (T3, T4), and the control electrode (gate) of the third semiconductor element (T3) is connected to the connection point a. And the control electrode (gate) of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), seventh (T7), and twentyth ( T20), and the tenth (T10), eighth (T8), ninth (T9), and twenty-first (T21) semiconductor element second main electrodes (sources) are grounded, and the fifth semiconductor element The first main electrode (drain) and the control electrode (gate) are connected, and the sixth, seventh, second are connected to this connection point. The control electrode (gate) of the semiconductor element is connected, and the first main electrode (drain) of the fifth semiconductor element is connected to the first main electrode (drain) of the third and eighth semiconductor elements. The first main electrode (drain) of the sixth semiconductor element is connected to the normal input terminal a1 of the amplifying means, and the channel width and channel length of the twentieth semiconductor element are set to the sixth semiconductor element. And the first main electrode (drain) of the twentieth semiconductor element is connected to the connection point b, while the first main electrode (drain) of the tenth semiconductor element and the control electrode (Gate) is connected, and the control electrode (gate) of the eighth, ninth, and twenty-first semiconductor elements is connected to the connection point, and the first main electrode (drain) of the tenth semiconductor element is connected. The first main electrode of the fourth and seventh semiconductor elements The first main electrode (drain) of the ninth semiconductor element is connected to the inverting input terminal b1 of the amplifying means, and the channel width and channel length of the twenty-first semiconductor element are set to the first And the first main electrode (drain) of the twenty-first semiconductor element is connected to the connection point a, the drain current of the sixth semiconductor element is set to Ix, The drain current of the semiconductor element is Iy.

請求項１１に記載の過電流保護装置は、電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項７または９に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の一端に接続して前記請求項７または９に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、前記電源端子ｄと前記接続点ｙとの間の電圧が、前記電源端子ｄと前記接続点ｘとの間の電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする。   In the overcurrent protection device according to claim 11, the first semiconductor element (T1) is disposed between the power source (VB) and the load (RL), and the first main electrode of the first semiconductor is used as the power source. And the second main electrode is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element, An overcurrent protection device that is provided in a load circuit that controls driving and stopping of a load, and that protects the load circuit when an overcurrent occurs, using the differential amplifier according to claim 7 or 9, wherein The first main electrode of one semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to one end of the first resistor. As an input voltage (Vds) of the differential amplifying device according to claim 9, the first main electrode of the first semiconductor element and the second voltage A voltage between the electrodes is input, the resistance value of the second resistor is set to be larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set to be equal, When the voltage between the power supply terminal d and the connection point y becomes smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage between the power supply terminal d and the connection point x, the load It is determined that the current flowing through the capacitor is an overcurrent, and the first semiconductor element is shut off.

請求項１２に記載の過電流保護装置は、電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項８または１０に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項８または１０に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、前記接続点ｙの電圧が、前記接続点ｘの電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする。   The overcurrent protection device according to claim 12, wherein a first semiconductor element (T1) is disposed between a power source (VB) and a load (RL), and the first main electrode of the first semiconductor is used as a power source. And the second main electrode is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element, An overcurrent protection device that is provided in a load circuit that controls driving and stopping of a load, and that protects the load circuit when an overcurrent occurs, using the differential amplifier according to claim 8 or 10, wherein The first main electrode of one semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. Alternatively, as the input voltage (Vds) of the differential amplifying device according to 10, the first main electrode of the first semiconductor element and the first voltage The voltage between the main electrodes is input, the resistance value of the second resistor is set larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set equal to each other. When the voltage at the connection point y becomes smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage at the connection point x, it is determined that the current flowing through the load is an overcurrent, One semiconductor element is cut off.

本発明に係る差動増幅装置、及び過電流保護装置では、増幅手段（ＡＭＰ１）の正転入力端子ａ１と接続点ａとの間に第７の抵抗（Ｒ７）を設け、且つ、増幅手段（ＡＭＰ１）の反転入力端子ｂ１と接続点ｂとの間に第８の抵抗（Ｒ８）を設ける。そして、第７の抵抗を介して電流Ｉｘをグランドに流し、且つ第８の抵抗を介して電流Ｉｙをグランドに流すことにより、増幅手段（ＡＭＰ１）が有するのオフセット電圧Ｖoffにより発生する電位差を低減させる。これにより、増幅手段が有するオフセット電圧の影響を除去することができ、ひいては過電流検出値のばらつきを抑制することができ、高精度な過電流検出が可能となる。更に、過電流判定値のばらつきが抑制されることにより、負荷回路を構成する電線サイズを低減することができる。   In the differential amplifying device and the overcurrent protection device according to the present invention, the seventh resistor (R7) is provided between the normal input terminal a1 and the connection point a of the amplifying means (AMP1), and the amplifying means ( An eighth resistor (R8) is provided between the inverting input terminal b1 and the connection point b of AMP1). The potential difference generated by the offset voltage Voff of the amplifying means (AMP1) is reduced by flowing the current Ix to the ground via the seventh resistor and the current Iy to the ground via the eighth resistor. Let As a result, the influence of the offset voltage of the amplifying means can be removed, and the variation of the overcurrent detection value can be suppressed, and high-precision overcurrent detection can be performed. Furthermore, the size of the electric wire which comprises a load circuit can be reduced by suppressing the dispersion | variation in an overcurrent determination value.

以下、本発明の実施形態を図面に基づいて説明する。なお、以下に示すＭＯＳＦＥＴ（電界効果トランジスタ）は、半導体素子の一例であり、ドレインを第１の主電極とし、ソースを第２の主電極とし、ゲートを制御電極とした場合を例に挙げている。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that a MOSFET (field effect transistor) shown below is an example of a semiconductor element, and an example is given in which a drain is a first main electrode, a source is a second main electrode, and a gate is a control electrode. Yes.

［第１実施形態］
図１は、本発明の第１実施形態に係る差動増幅装置を含む過電流保護装置が搭載された負荷回路の構成を示す回路図である。図２は、理解を促進する際の煩雑さを避けるため、図１からアンプ（ＡＭＰ１）のオフセット電圧Ｖoffを補正する回路を取り去った回路を示している。まず、図２を参照して、全体構成の概略について説明する。 [First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a load circuit equipped with an overcurrent protection device including a differential amplifier according to the first embodiment of the present invention. FIG. 2 shows a circuit in which the circuit for correcting the offset voltage Voff of the amplifier (AMP1) is removed from FIG. 1 in order to avoid complexity when promoting understanding. First, an outline of the overall configuration will be described with reference to FIG.

図２に示すように、電源ＶＢ（例えば１２Ｖ直流電源）と、ランプ或いはモータ等の負荷ＲＬとの間には、ＭＯＳＦＥＴ（Ｔ１；第１の半導体素子）が設けられており、ドライバ１１より出力される駆動信号により、ＭＯＳＦＥＴ（Ｔ１）のオン、オフが切り換えられ、負荷ＲＬの駆動、停止が制御される。即ち、ドライバ１１の出力信号がＨレベル（電源ＶＢの電圧より約１０Ｖ高い電圧）となり、このＨレベルの出力信号がＭＯＳＦＥＴ（Ｔ１）のゲートに供給されると、該ＭＯＳＦＥＴ（Ｔ１）がオンとなり、電源ＶＢより出力される電力が負荷ＲＬに供給される。これにより、負荷ＲＬが駆動する。   As shown in FIG. 2, a MOSFET (T1; first semiconductor element) is provided between a power supply VB (for example, 12V DC power supply) and a load RL such as a lamp or a motor, and an output from the driver 11 is provided. In response to the drive signal, the MOSFET (T1) is turned on and off, and the drive and stop of the load RL are controlled. That is, when the output signal of the driver 11 becomes H level (voltage approximately 10V higher than the voltage of the power supply VB) and this H level output signal is supplied to the gate of the MOSFET (T1), the MOSFET (T1) is turned on. The power output from the power supply VB is supplied to the load RL. As a result, the load RL is driven.

また、ＭＯＳＦＥＴ（Ｔ１）のドレイン、即ち、点ｄ（電圧Ｖ１）は３系統に分岐しており、このうち、１つ目の分岐線は、抵抗Ｒ３（第３の抵抗；例えば５［ＫΩ］）と、抵抗Ｒ４（第４の抵抗；例えば２５［ＫΩ］）と、抵抗Ｒ５（第５の抵抗；例えば３０［ＫΩ］）の直列接続回路を介して、グランドに接続されている。抵抗Ｒ３とＲ４の接続点をａとする。   Further, the drain of the MOSFET (T1), that is, the point d (voltage V1) is branched into three systems, among which the first branch line is a resistor R3 (third resistor; for example, 5 [KΩ] ), A resistor R4 (fourth resistor; for example, 25 [KΩ]) and a resistor R5 (fifth resistor; for example, 30 [KΩ]) are connected to the ground. A connection point between the resistors R3 and R4 is a.

２つ目の分岐線は、トランジスタ（Ｔ１１；例えばＭＯＳＦＥＴ）と、抵抗Ｒ１１（例えば２．２７［ＫΩ］）と、抵抗Ｒ１２（例えば８０［ＫΩ］）の直列接続回路を介して、グランドに接続されている。抵抗Ｒ１１とＲ１２との接続点をｅとする。また、３つ目の分岐線は、図２では省略されており、図１を参照して後述する。   The second branch line is connected to the ground via a series connection circuit of a transistor (T11; for example, MOSFET), a resistor R11 (for example, 2.27 [KΩ]), and a resistor R12 (for example, 80 [KΩ]). Has been. A connection point between the resistors R11 and R12 is represented by e. The third branch line is omitted in FIG. 2, and will be described later with reference to FIG.

図２において、ＭＯＳＦＥＴ（Ｔ１）のソース（電圧Ｖ２）は、抵抗Ｒ１（第１の抵抗；例えば５［ＫΩ］）と、抵抗Ｒ２（第２の抵抗；例えば２５［ＫΩ］）と、トランジスタ（Ｔ２；第２の半導体素子、例えばＭＯＳＦＥＴ）の直列接続回路を介して、グランドに接続されている（接地されている）。   In FIG. 2, the source (voltage V2) of the MOSFET (T1) includes a resistor R1 (first resistor; eg, 5 [KΩ]), a resistor R2 (second resistor; eg, 25 [KΩ]), and a transistor ( T2: connected to the ground (grounded) through a series connection circuit of second semiconductor elements (for example, MOSFET).

抵抗Ｒ３と抵抗Ｒ４の接続点（点ａ）は、アンプ（ＡＭＰ１；増幅手段）の正転入力端子に接続され、抵抗Ｒ１と抵抗Ｒ２の接続点（点ｂ）は、アンプ（ＡＭＰ１）の反転入力端子に接続されている。アンプ（ＡＭＰ１）の出力端子は、トランジスタ（Ｔ２）の制御端子に接続されている。また、アンプ（ＡＭＰ１）が有するオフセット電圧Ｖoffを、反転入力端子に接続された電圧Ｖoffとして記載している。   The connection point (point a) between the resistors R3 and R4 is connected to the normal input terminal of the amplifier (AMP1; amplification means), and the connection point (point b) between the resistors R1 and R2 is the inversion of the amplifier (AMP1). Connected to the input terminal. The output terminal of the amplifier (AMP1) is connected to the control terminal of the transistor (T2). Further, the offset voltage Voff included in the amplifier (AMP1) is described as the voltage Voff connected to the inverting input terminal.

また、抵抗Ｒ４と抵抗Ｒ５の接続点（点ｘ）は、アンプ（ＡＭＰ２）の正転入力端子に接続され、抵抗Ｒ１１と抵抗Ｒ１２の接続点（点ｅ）は、アンプ（ＡＭＰ２）の反転入力端子に接続されている。また、該アンプ（ＡＭＰ２）の出力端子は、トランジスタ（Ｔ１１）の制御端子に接続されている。   A connection point (point x) between the resistors R4 and R5 is connected to a normal rotation input terminal of the amplifier (AMP2), and a connection point (point e) between the resistors R11 and R12 is an inverting input of the amplifier (AMP2). Connected to the terminal. The output terminal of the amplifier (AMP2) is connected to the control terminal of the transistor (T11).

トランジスタ（Ｔ１１）のソースは、抵抗Ｒ９（例えば１０［ＫΩ］）を介してコンパレータＣＭＰ１の正転入力端子に接続され、抵抗Ｒ２とトランジスタ（Ｔ２）のソースとの接続点（点ｙ）は、抵抗Ｒ１０（例えば１０［ＫΩ］）を介して、コンパレータＣＭＰ１の反転入力端子に接続されている。また、コンパレータＣＭＰ１の出力端子は、ドライバ１１に接続されている。   The source of the transistor (T11) is connected to the normal input terminal of the comparator CMP1 via the resistor R9 (for example, 10 [KΩ]), and the connection point (point y) between the resistor R2 and the source of the transistor (T2) is The resistor R10 (eg, 10 [KΩ]) is connected to the inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the driver 11.

次に、図１に示す回路図を参照して、アンプ（ＡＭＰ１）のオフセット電圧Ｖoffを補正する回路について説明する。図１に示すように、アンプ（ＡＭＰ１）の正転入力端子と点ａとの間には、抵抗Ｒ７（第７の抵抗；例えば５［ＫΩ］）が設けられ、アンプ（ＡＭＰ１）の反転入力端子に設けられるオフセット電圧Ｖoffと点ｂとの間には、抵抗Ｒ８（第８の抵抗；例えば５［ＫΩ］）が設けられている。そして、アンプ（ＡＭＰ１）の正転入力端子と抵抗Ｒ７との接続点を点ａ１とし、オフセット電圧Ｖoffと抵抗Ｒ８との接続点を点ｂ１とする。   Next, a circuit for correcting the offset voltage Voff of the amplifier (AMP1) will be described with reference to the circuit diagram shown in FIG. As shown in FIG. 1, a resistor R7 (seventh resistor; for example, 5 [KΩ]) is provided between the normal rotation input terminal of the amplifier (AMP1) and the point a, and the inverting input of the amplifier (AMP1) is provided. A resistor R8 (eighth resistor; for example, 5 [KΩ]) is provided between the offset voltage Voff provided at the terminal and the point b. A connection point between the normal input terminal of the amplifier (AMP1) and the resistor R7 is a point a1, and a connection point between the offset voltage Voff and the resistor R8 is a point b1.

ＭＯＳＦＥＴ（Ｔ１）のドレイン（点ｄ）には、定電流源Ｉａが接続されており、この定電流源Ｉａの出力端子は、２系統に分岐されている。   A constant current source Ia is connected to the drain (point d) of the MOSFET (T1), and the output terminal of the constant current source Ia is branched into two systems.

１つ目の分岐線は、トランジスタ（Ｔ３；第３の半導体素子、例えばＰ型のＭＯＳＦＥＴ）のソースに接続され、該トランジスタ（Ｔ３）のドレインは、トランジスタ（Ｔ５；例えばＭＯＳＦＥＴ）のドレイン及びゲート、及びトランジスタ（Ｔ８；例えばＭＯＳＦＥＴ）のドレインに接続されている。また、トランジスタ（Ｔ３）のゲートは、点ａに接続されている。更に、トランジスタ（Ｔ５）のゲートは、トランジスタ（Ｔ６；例えばＭＯＳＦＥＴ）のゲートに接続され、該トランジスタ（Ｔ６）のドレインは、点ａ１に接続されている。   The first branch line is connected to the source of the transistor (T3; third semiconductor element, eg, P-type MOSFET), and the drain of the transistor (T3) is the drain and gate of the transistor (T5; eg, MOSFET) , And the drain of a transistor (T8; for example, MOSFET). The gate of the transistor (T3) is connected to the point a. Further, the gate of the transistor (T5) is connected to the gate of the transistor (T6; for example, MOSFET), and the drain of the transistor (T6) is connected to the point a1.

２つ目の分岐線は、トランジスタ（Ｔ４；第４の半導体素子、例えばＰ型のＭＯＳＦＥＴ）のソースに接続され、該トランジスタ（Ｔ４）のドレインは、トランジスタ（Ｔ１０；例えばＭＯＳＦＥＴ）のドレイン及びゲート、及びトランジスタ（Ｔ７；例えばＭＯＳＦＥＴ）のドレインに接続されている。また、トランジスタ（Ｔ４）のゲートは、点ｂに接続されている。更に、トランジスタ（Ｔ１０）のゲートは、トランジスタ（Ｔ９；例えばＭＯＳＦＥＴ）のゲートに接続され、該トランジスタ（Ｔ９）のドレインは、点ｂ１に接続されている。   The second branch line is connected to the source of the transistor (T4; fourth semiconductor element, eg, P-type MOSFET), and the drain of the transistor (T4) is the drain and gate of the transistor (T10; eg, MOSFET). , And the drain of a transistor (T7; for example, MOSFET). The gate of the transistor (T4) is connected to the point b. Further, the gate of the transistor (T10) is connected to the gate of the transistor (T9; for example, MOSFET), and the drain of the transistor (T9) is connected to the point b1.

更に、トランジスタ（Ｔ６）のゲートとトランジスタ（Ｔ７）のゲートが接続され、トランジスタ（Ｔ９）のゲートとトランジスタ（Ｔ８）のゲートが接続されている。   Further, the gate of the transistor (T6) and the gate of the transistor (T7) are connected, and the gate of the transistor (T9) and the gate of the transistor (T8) are connected.

トランジスタ（Ｔ５〜Ｔ７）、及びトランジスタ（Ｔ８〜Ｔ１０）は、それぞれトランジスタ（Ｔ５）、トランジスタ（Ｔ１０）をレファレンストランジスタとするカレントミラー回路を形成する。   The transistors (T5 to T7) and the transistors (T8 to T10) form a current mirror circuit using the transistors (T5) and (T10) as reference transistors, respectively.

また、各電圧、電流の符号を図１に示すように設定する。即ち、ＭＯＳＦＥＴ（Ｔ１）のドレイン・ソース間電圧を「Ｖds」、ドレイン電流を「ＩＤ」、抵抗Ｒ１に生じる電圧を「Ｖds-C」、ＭＯＳＦＥＴ（Ｔ１）のドレイン（点ｄ）と点ｙとの間の電圧を「Ｖｙ」とする。更に、抵抗Ｒ２に流れる電流をＩ23、トランジスタ（Ｔ９）に流れる電流をＩｙ、抵抗Ｒ１に流れる電流をＩ23＋Ｉｙ、トランジスタ（Ｔ１０）に流れる電流をＩ21、トランジスタ（Ｔ７）に流れる電流をＩ22、トランジスタ（Ｔ４）に流れる電流をＩ２とする。   Further, the sign of each voltage and current is set as shown in FIG. That is, the drain-source voltage of the MOSFET (T1) is “Vds”, the drain current is “ID”, the voltage generated in the resistor R1 is “Vds-C”, the drain (point d) and the point y of the MOSFET (T1) The voltage between is assumed to be “Vy”. Further, the current flowing through the resistor R2 is I23, the current flowing through the transistor (T9) is Iy, the current flowing through the resistor R1 is I23 + Iy, the current flowing through the transistor (T10) is I21, the current flowing through the transistor (T7) is I22, and the transistor ( The current flowing through T4) is I2.

また、抵抗Ｒ３に生じる電圧をＶａ、抵抗Ｒ３とＲ４に生じる電圧をＶｘ、抵抗Ｒ１１に生じる電圧をＶｓ、抵抗Ｒ４，Ｒ５に流れる電流をＩ13、トランジスタ（Ｔ６）に流れる電流をＩｘ、抵抗Ｒ３に流れる電流をＩ13＋Ｉｘ、トランジスタ（Ｔ５）に流れる電流をＩ11、トランジスタ（Ｔ８）に流れる電流をＩ12、トランジスタ（Ｔ３）に流れる電流をＩ１とする。なお、図１に示す一点鎖線で囲まれる部分は、通常１個のＩＣで構成されることとなる。   The voltage generated in the resistor R3 is Va, the voltage generated in the resistors R3 and R4 is Vx, the voltage generated in the resistor R11 is Vs, the current flowing in the resistors R4 and R5 is I13, the current flowing in the transistor (T6) is Ix, and the resistor R3 Is I13 + Ix, the current flowing through the transistor (T5) is I11, the current flowing through the transistor (T8) is I12, and the current flowing through the transistor (T3) is I1. In addition, the part enclosed with the dashed-dotted line shown in FIG. 1 will be normally comprised by one IC.

次に、図１に示す過電流保護装置の動作について説明する。   Next, the operation of the overcurrent protection device shown in FIG. 1 will be described.

ＭＯＳＦＥＴ（Ｔ１）のオン抵抗をＲonとすると、該ＭＯＳＦＥＴ（Ｔ１）のドレイン・ソース間には、電圧降下Ｖds＝Ｒon＊ＩＤが発生する。そして、電圧Ｖdsの大きさが予め設定された判定値を上回ると過電流と判定され、負荷回路を保護するために、ＭＯＳＦＥＴ（Ｔ１）が遮断される。   When the on-resistance of the MOSFET (T1) is Ron, a voltage drop Vds = Ron * ID is generated between the drain and source of the MOSFET (T1). And when the magnitude | size of the voltage Vds exceeds the preset judgment value, it will determine with an overcurrent and MOSFET (T1) will be interrupted | blocked in order to protect a load circuit.

上記の電圧Ｖdsの大きさを検出し、予め設定した判定値と比較するため、アンプ（ＡＭＰ１）、アンプ（ＡＭＰ２）、コンパレータ（ＣＭＰ１）、トランジスタ（Ｔ２，Ｔ１１）、及び抵抗Ｒ１〜Ｒ５、Ｒ９〜Ｒ１２からなる回路が組み込まれている。   In order to detect the magnitude of the voltage Vds and compare it with a predetermined determination value, an amplifier (AMP1), an amplifier (AMP2), a comparator (CMP1), a transistor (T2, T11), and resistors R1 to R5, R9 A circuit consisting of ~ R12 is incorporated.

ここで、Ｒ１＝Ｒ３、Ｒ２＝Ｒ４とし、Ｒ２／Ｒ１＝Ｒ４／Ｒ３＝ｐとする。そして、オフセット電圧Ｖoffがゼロであれば（Ｖoff＝０）、点ａ〜点ｂ間の電位差Ｖab＝０［Ｖ］となり、Ｖａ＝Ｖds＋Ｖds-Cとなるので、次の（５）式が得られる。   Here, R1 = R3, R2 = R4, and R2 / R1 = R4 / R3 = p. If the offset voltage Voff is zero (Voff = 0), the potential difference Vab = 0 [V] between the points a and b and Va = Vds + Vds−C, so that the following equation (5) is obtained. .

Ｖｘ＝Ｖａ＊（Ｒ４＋Ｒ３）／Ｒ３＝Ｖａ＊（ｐ＋１）
Ｖｙ＝Ｖds＋Ｖds-C＊（Ｒ２＋Ｒ１）／Ｒ１＝Ｖds＋Ｖds-C＊（ｐ＋１）
∴Ｖｘ−Ｖｙ＝（ｐ＋１）（Ｖａ−Ｖds-C）−Ｖds＝ｐ＊Ｖds …（５）
他方、オフセット電圧Ｖoffがゼロでない場合（Ｖoff≠０）には、次の（６）式が得られる。 Vx = Va * (R4 + R3) / R3 = Va * (p + 1)
Vy = Vds + Vds-C * (R2 + R1) / R1 = Vds + Vds-C * (p + 1)
∴Vx−Vy = (p + 1) (Va−Vds−C) −Vds = p * Vds (5)
On the other hand, when the offset voltage Voff is not zero (Voff ≠ 0), the following equation (6) is obtained.

Ｖａ＝Ｖds＋Ｖds-C−Ｖoff
Ｖｘ−Ｖｙ＝（ｐ＋１）＊Ｖａ−（Ｖds＋Ｖds-C＊（ｐ＋１））
＝（ｐ＋１）＊（Ｖds＋Ｖds-C−Ｖoff）−（Ｖds＋Ｖds-C＊（ｐ＋１））
＝ｐ＊（Ｖds−Ｖoff）−Ｖoff …（６）
ここで、アンプ（ＡＭＰ１）、及び抵抗Ｒ１〜Ｒ４を含む回路は、電圧Ｖds-Cと電圧Ｖａを同一の抵抗比（ｐ）で増幅することになるので、電圧Ｖdsを入力とし、電圧（Ｖｘ−Ｖｙ）を出力とする差動増幅回路（差動増幅装置）となる。 Va = Vds + Vds-C-Voff
Vx−Vy = (p + 1) * Va− (Vds + Vds−C * (p + 1))
= (P + 1) * (Vds + Vds-C-Voff)-(Vds + Vds-C * (p + 1))
= P * (Vds-Voff) -Voff (6)
Here, since the circuit including the amplifier (AMP1) and the resistors R1 to R4 amplifies the voltage Vds-C and the voltage Va with the same resistance ratio (p), the voltage Vds is input and the voltage (Vx A differential amplifier circuit (differential amplifier) that outputs −Vy) is obtained.

上記の（５）式より、Ｖoff＝０であれば、「Ｖｘ−Ｖｙ」は、ＭＯＳＦＥＴ（Ｔ１）のドレイン・ソース間電圧Ｖdsをｐ倍した電圧となっているので、この大きさを求めることにより、ドレイン電流ＩＤが過電流となっているか否かを判定することができる。   From the above equation (5), if Voff = 0, “Vx−Vy” is a voltage obtained by multiplying the drain-source voltage Vds of the MOSFET (T1) by p. Thus, it can be determined whether or not the drain current ID is an overcurrent.

しかし、一般的にはＶoff≠０であるから、（６）式に示すように「Ｖｘ−Ｖｙ」には、Ｖoffがｐ倍に増幅されて含まれることになり、これが誤差となる。本発明は、この誤差を補正するために、図１に示す定電流源Ｉａからグランドに繋がる回路を設けている。詳細については、後述する。   However, since generally Voff ≠ 0, as shown in equation (6), “Vx−Vy” includes Voff amplified by p times, which is an error. In the present invention, in order to correct this error, a circuit connected from the constant current source Ia shown in FIG. 1 to the ground is provided. Details will be described later.

次に、点ｘの電圧Ｖｘと点ｙの電圧Ｖｙの差分電圧（Ｖｘ−Ｖｙ）に基づいて、過電流が発生しているか否かを判定する動作について説明する。   Next, an operation for determining whether or not an overcurrent has occurred based on the differential voltage (Vx−Vy) between the voltage Vx at the point x and the voltage Vy at the point y will be described.

この判定処理は、電圧Ｖｘから所定電圧Ｖｓを差し引いた電圧（Ｖｘ−Ｖｓ）を生成し、この電圧（Ｖｘ−Ｖｓ）と電圧Ｖｙとを、コンパレータ（ＣＭＰ１）で比較することにより行う。電圧（Ｖｘ−Ｖｓ）を生成するために、アンプ（ＡＭＰ２）、トランジスタ（Ｔ１１）、抵抗Ｒ１１，Ｒ１２が用いられる。   This determination process is performed by generating a voltage (Vx−Vs) obtained by subtracting the predetermined voltage Vs from the voltage Vx, and comparing the voltage (Vx−Vs) and the voltage Vy by a comparator (CMP1). In order to generate the voltage (Vx−Vs), an amplifier (AMP2), a transistor (T11), and resistors R11 and R12 are used.

アンプ（ＡＭＰ２）とトランジスタ（Ｔ１１）でボルテージレギュレータが形成され、点ｘの電圧と、点ｅの電圧が等しくなるように制御され、抵抗Ｒ１１に生じる電圧降下が上記の所定電圧Ｖｓとなる。点ｅとグランドとの間に生じる電圧、即ち、点ｘとグランドとの間に生じる電圧は、電源電圧Ｖ１に比例するので、所定電圧Ｖｓは、電源電圧Ｖ１に比例する。その大きさは、抵抗Ｒ１１と抵抗Ｒ１２の抵抗比で任意に設定することができる。   A voltage regulator is formed by the amplifier (AMP2) and the transistor (T11), the voltage at the point x and the voltage at the point e are controlled to be equal, and the voltage drop generated in the resistor R11 becomes the predetermined voltage Vs. Since the voltage generated between the point e and the ground, that is, the voltage generated between the point x and the ground is proportional to the power supply voltage V1, the predetermined voltage Vs is proportional to the power supply voltage V1. The magnitude can be arbitrarily set by the resistance ratio of the resistors R11 and R12.

抵抗Ｒ１１とトランジスタ（Ｔ１１）の接続点がコンパレータ（ＣＭＰ１）の正転入力端子に入力され、点ｙがコンパレータ（ＣＭＰ１）反転入力端子に接続されるので、コンパレータ（ＣＭＰ１）は、電圧（Ｖｘ−Ｖｓ）と電圧Ｖｙを比較することになる。ＭＯＳＦＥＴ（Ｔ１）のドレイン・ソース間電圧Ｖdsが大きくなると、電圧Ｖｙが減少し、電圧（Ｖｘ−Ｖｓ）を下回るとコンパレータ（ＣＭＰ１）の出力信号が反転し、過電流と判定される。この出力信号は、ドライバ１１に出力され、該ドライバ１１の制御により、ＭＯＳＦＥＴ（Ｔ１）を遮断する。即ち、過電流保護が行われる。   Since the connection point between the resistor R11 and the transistor (T11) is input to the normal input terminal of the comparator (CMP1) and the point y is connected to the reverse input terminal of the comparator (CMP1), the comparator (CMP1) has the voltage (Vx− Vs) is compared with the voltage Vy. When the drain-source voltage Vds of the MOSFET (T1) increases, the voltage Vy decreases, and when it falls below the voltage (Vx−Vs), the output signal of the comparator (CMP1) is inverted, and it is determined as an overcurrent. This output signal is output to the driver 11, and the MOSFET (T1) is cut off under the control of the driver 11. That is, overcurrent protection is performed.

次に、図１に示したアンプ（ＡＭＰ１）のオフセット電圧Ｖoffを補正する動作について説明する。   Next, an operation for correcting the offset voltage Voff of the amplifier (AMP1) shown in FIG. 1 will be described.

［記号の説明及び前提条件］
電圧Ｖoffは、アンプ（ＡＭＰ１）が有するオフセット電圧である。電圧Ｖabは、点ａ〜点ｂ間の電位差であり、点ａの電位が点ｂの電位より高いときプラスとする。 [Explanation of symbols and assumptions]
The voltage Voff is an offset voltage that the amplifier (AMP1) has. The voltage Vab is a potential difference between the points a and b, and is positive when the potential at the point a is higher than the potential at the point b.

係数「ｍ」は、ｍ＝（Ｔ７のＷ）／（Ｔ５のＷ）＝（Ｔ８のＷ）／（Ｔ１０のＷ）であり、カレントミラー比を示す。但し、「Ｗ」は各トランジスタ（ＭＯＳＦＥＴ）のチャンネル幅を示す。トランジスタＴ５〜トランジスタＴ１０のチャンネル長さは同一であるとする。   The coefficient “m” is m = (W of T7) / (W of T5) = (W of T8) / (W of T10) and represents the current mirror ratio. However, “W” indicates the channel width of each transistor (MOSFET). The channel lengths of the transistors T5 to T10 are the same.

係数「ｎ」は、ｎ＝（Ｔ６のＷ）／（Ｔ５のＷ）＝（Ｔ９のＷ）／（Ｔ１０のＷ）であり、カレントミラー比を示す。ｐは抵抗増幅率であり、ｐ＝Ｒ２／Ｒ１＝Ｒ４／Ｒ３である。   The coefficient “n” is n = (W of T6) / (W of T5) = (W of T9) / (W of T10) and represents the current mirror ratio. p is a resistance amplification factor, and p = R2 / R1 = R4 / R3.

また、前提条件として、Ｒ１＝Ｒ３、Ｒ２＝Ｒ４、Ｒ７＝Ｒ８とする。また、トランジスタ（Ｔ３）、（Ｔ４）のスレッショルド電圧Ｖthが等しいとする。   As preconditions, R1 = R3, R2 = R4, and R7 = R8. Further, it is assumed that the threshold voltages Vth of the transistors (T3) and (T4) are equal.

最初に、電圧Ｖabと、トランジスタ（Ｔ６）に流れる電流Ｉｘとトランジスタ（Ｔ１０）に流れる電流Ｉｙとの電流差（Ｉｘ−Ｉｙ）の関係を求める。   First, the relationship between the voltage Vab and the current difference (Ix−Iy) between the current Ix flowing through the transistor (T6) and the current Iy flowing through the transistor (T10) is obtained.

Ｉ11＝Ｉ１−Ｉ12＝Ｉ１−ｍ＊Ｉ21 …（７）
Ｉ21＝Ｉ２−Ｉ22＝Ｉ２−ｍ＊Ｉ11 …（８）
（７）式右辺の「Ｉ21」に（８）式を代入すると、次のようになる。 I11 = I1-I12 = I1-m * I21 (7)
I21 = I2-I22 = I2-m * I11 (8)
Substituting equation (8) into “I21” on the right side of equation (7) yields the following.

Ｉ11＝Ｉ１−ｍ＊Ｉ２＋ｍ２＊Ｉ11
∴Ｉ11＝（Ｉ１−ｍ＊Ｉ２）／（１−ｍ２）
また、（８）式の右辺の「Ｉ11」に（７）式を代入すると、次のようになる。 I11 = I1-m * I2 + m 2 * I11
∴I11 = (I1-m * I2 ) / (1-m 2)
Further, when the equation (7) is substituted into “I11” on the right side of the equation (8), the following is obtained.

Ｉ21＝Ｉ２−ｍ＊Ｉ１＋ｍ２＊Ｉ21
∴Ｉ21＝（Ｉ２−ｍ＊Ｉ１）／（１−ｍ２）
従って、「Ｉ11−Ｉ21」は、次のようになる。 I21 = I2-m * I1 + m 2 * I21
∴I21 = (I2-m * I1 ) / (1-m 2)
Therefore, “I11-I21” is as follows.

Ｉ11−Ｉ21＝（１＋ｍ）＊（Ｉ１−Ｉ２）／（１−ｍ２）
＝（Ｉ１−Ｉ２）／（１−ｍ）
Ｉｘ−Ｉｙ＝ｎ＊Ｉ11−ｎ＊Ｉ21＝ｎ＊（Ｉ11−Ｉ21）
＝ｎ／（１−ｍ）＊（Ｉ１−Ｉ２）
一方、（Ｉ１−Ｉ２）は、−Ｖabに比例するので、比例定数をｋとすると、次の（９）式が得られる。 I11-I21 = (1 + m ) * (I1-I2) / (1-m 2)
= (I1-I2) / (1-m)
Ix-Iy = n * I11-n * I21 = n * (I11-I21)
= N / (1-m) * (I1-I2)
On the other hand, since (I1-I2) is proportional to -Vab, if the proportionality constant is k, the following equation (9) is obtained.

Ｖab＝−ｋ（Ｉ１−Ｉ２）
＝−ｋ＊（１−ｍ）／ｎ＊（Ｉｘ−Ｉｙ） …（９）
ここで、オフセット電圧Ｖoff＝０［Ｖ］のとき、Ｖab＝０［Ｖ］になるから、Ｉ１＝Ｉ２となり、Ｉｘ−Ｉｙ＝０となる。従って、電流（Ｉｘ−Ｉｙ）、及びカレントミラー比ｎ、ｍは、回路動作に影響しなくなる。 Vab = -k (I1-I2)
= -K * (1-m) / n * (Ix-Iy) (9)
Here, when the offset voltage Voff = 0 [V], Vab = 0 [V], so that I1 = I2 and Ix−Iy = 0. Therefore, the current (Ix−Iy) and the current mirror ratios n and m do not affect the circuit operation.

他方、Ｖoff≠０［Ｖ］の場合には、Ｒ７＝Ｒ８＝Ｒｂとおくと、電圧Ｖabは、次式で示される。   On the other hand, when Voff ≠ 0 [V], when R7 = R8 = Rb, the voltage Vab is expressed by the following equation.

Ｖab＝Ｖoff＋Ｒ７＊Ｉｘ−Ｒ８＊Ｉｙ
＝Ｖoff＋Ｒｂ（Ｉｘ−Ｉｙ）
ここで、上述した（９）式を用いて、電圧Ｖabを消去すると、オフセット電圧Ｖoffは、次の（１０）式で示される。 Vab = Voff + R7 * Ix-R8 * Iy
= Voff + Rb (Ix-Iy)
Here, when the voltage Vab is deleted using the above-described equation (9), the offset voltage Voff is expressed by the following equation (10).

Ｖoff＝Ｖab−Ｒｂ（Ｉｘ−Ｉｙ）
＝−ｋ＊（１−ｍ）／ｎ＊（Ｉｘ−Ｉｙ）−Ｒｂ（Ｉｘ−Ｉｙ）
＝−｛ｋ＊（１−ｍ）／ｎ＋Ｒｂ ｝（Ｉｘ−Ｉｙ） …（１０）
（１０）式より、差電流（Ｉｘ−Ｉｙ）は、オフセット電圧Ｖoffに比例することが分かる。 Voff = Vab−Rb (Ix−Iy)
= -K * (1-m) / n * (Ix-Iy) -Rb (Ix-Iy)
=-{K * (1-m) / n + Rb} (Ix-Iy) (10)
From the equation (10), it can be seen that the difference current (Ix−Iy) is proportional to the offset voltage Voff.

以上をまとめると、オフセット電圧Ｖoff≠０［Ｖ］であれば、電圧Ｖabが発生する。差電流（Ｉｘ−Ｉｙ）は、この電圧Ｖabを打ち消す電圧降下を抵抗Ｒ７、及び抵抗Ｒ８に発生させる。この電圧Ｖabの打ち消し効果は、ｎ／（１−ｍ）で決まり、調整することができる。打ち消し効果ゼロのとき、Ｖab＝Ｖoffである。   In summary, the voltage Vab is generated when the offset voltage Voff ≠ 0 [V]. The difference current (Ix−Iy) generates a voltage drop in the resistor R7 and the resistor R8 that cancels the voltage Vab. The canceling effect of the voltage Vab is determined by n / (1-m) and can be adjusted. When the cancellation effect is zero, Vab = Voff.

打ち消し効果を大きくすると、同一のオフセット電圧Ｖoffに対して、電圧Ｖabは小さくなる。しかし、電圧Ｖabが小さくなると、差電流（Ｉ１−Ｉ２）が小さくなり、これに伴って差電流（Ｉｘ−Ｉｙ）が小さくなり、従って、Ｖabの打ち消し効果も小さくなるので、Ｖabはゼロにすることはできない。   When the cancellation effect is increased, the voltage Vab decreases with respect to the same offset voltage Voff. However, when the voltage Vab is reduced, the difference current (I1-I2) is reduced, and accordingly, the difference current (Ix-Iy) is reduced. Therefore, the effect of canceling Vab is also reduced, so that Vab is zero. It is not possible.

以下、電圧Ｖoffの補正処理をより具体的に説明する。最初に、Ｖｘ−Ｖｙを求めると、次の（１１）式となる。   Hereinafter, the correction process of the voltage Voff will be described more specifically. First, when Vx−Vy is obtained, the following equation (11) is obtained.

Ｖｘ−Ｖｙ＝Ｒ３（Ｉ13＋Ｉｘ）＋Ｒ４＊Ｉ13
−｛Ｖds＋Ｒ１（Ｉ23＋Ｉｙ）＋Ｒ２＊Ｉ23｝ …（１１）
ここで、点ｄ→点ａ→点ａ１→点ｂ１→点ｂ→Ｔ１→点ｄのループからなる配線経路の電圧降下を足し合わせるとゼロになるから、次の（１２）式が得られる。 Vx-Vy = R3 (I13 + Ix) + R4 * I13
-{Vds + R1 (I23 + Iy) + R2 * I23} (11)
Here, when the voltage drop of the wiring path consisting of the loop of the point d → the point a → the point a1 → the point b1 → the point b → T1 → the point d is added to zero, the following equation (12) is obtained.

Ｒ３（Ｉ13＋Ｉｘ）＋Ｒ７＊Ｉｘ＋Ｖoff
−Ｒ８＊Ｉｙ−Ｒ１（Ｉ23＋Ｉｙ）−Ｖds＝０ …（１２）
ここで、Ｒ１＝Ｒ３＝Ｒａ、Ｒ７＝Ｒ８＝Ｒｂ、Ｒ２／ｐ＝Ｒ４／ｐ＝Ｒａとして、上記（１１）式、（１２）式を書き直すと、次の（１３）式、（１４）式が得られる。 R3 (I13 + Ix) + R7 * Ix + Voff
-R8 * Iy-R1 (I23 + Iy) -Vds = 0 (12)
Here, when R1 = R3 = Ra, R7 = R8 = Rb, R2 / p = R4 / p = Ra, and rewriting the above equations (11) and (12), the following equations (13) and (14) The formula is obtained.

Ｖｘ−Ｖｙ＝Ｒａ（Ｉ13＋Ｉｘ）＋ｐ＊Ｒａ＊Ｉ13
−｛Ｖds＋Ｒａ（Ｉ23＋Ｉｙ）＋ｐ＊Ｒａ＊Ｉ23｝
＝ｐ＊Ｒａ（Ｉ13−Ｉ23）＋Ｒａ（Ｉ13−Ｉ23）
＋Ｒａ（Ｉｘ−Ｉｙ）−Ｖds …（１３）
Ｒａ（Ｉ13＋Ｉｘ）＋Ｒｂ＊Ｉｘ＋Ｖoff
−Ｒｂ＊Ｉｙ−Ｒａ（Ｉ23＋Ｉｙ）−Ｖds＝０
Ｖds＝Ｒａ（Ｉ13−Ｉ23）＋（Ｒａ＋Ｒｂ）（Ｉｘ−Ｉｙ）＋Ｖoff …（１４）
上記の（１４）式において、次の（１５）式が成立すれば、下記（１６）式が得られる。 Vx-Vy = Ra (I13 + Ix) + p * Ra * I13
− {Vds + Ra (I23 + Iy) + p * Ra * I23}
= P * Ra (I13-I23) + Ra (I13-I23)
+ Ra (Ix-Iy) -Vds (13)
Ra (I13 + Ix) + Rb * Ix + Voff
-Rb * Iy-Ra (I23 + Iy) -Vds = 0
Vds = Ra (I13-I23) + (Ra + Rb) (Ix-Iy) + Voff (14)
In the above equation (14), if the following equation (15) is established, the following equation (16) is obtained.

（Ｒａ＋Ｒｂ）（Ｉｘ−Ｉｙ）＋Ｖoff＝０ …（１５）
Ｖds＝Ｒａ（Ｉ13−Ｉ23） …（１６）
（１５）式の左辺を、上述した（１０）式を用いて変形すると、次式が得られる。 (Ra + Rb) (Ix−Iy) + Voff = 0 (15)
Vds = Ra (I13-I23) (16)
When the left side of equation (15) is transformed using equation (10) described above, the following equation is obtained.

（Ｒａ＋Ｒｂ）（Ｉｘ−Ｉｙ）＋Ｖoff
＝（Ｒａ＋Ｒｂ）（Ｉｘ−Ｉｙ）−｛ｋ＊（１−ｍ）／ｎ＋Ｒｂ｝（Ｉｘ−Ｉｙ）
＝（Ｒａ−ｋ＊（１−ｍ）／ｎ）（Ｉｘ−Ｉｙ）
＝Ｒａ＊（Ｉｘ−Ｉｙ）＋Ｖab
従って、次の（１７）式を成立させれば、差電流（Ｉｘ−Ｉｙ）に関わらず、上述の（１５）式が成立することとなる。 (Ra + Rb) (Ix-Iy) + Voff
= (Ra + Rb) (Ix-Iy)-{k * (1-m) / n + Rb} (Ix-Iy)
= (Ra-k * (1-m) / n) (Ix-Iy)
= Ra * (Ix-Iy) + Vab
Therefore, if the following equation (17) is established, the above equation (15) is established regardless of the difference current (Ix−Iy).

Ｒａ−ｋ＊（１−ｍ）／ｎ＝０ …（１７）
上記の（１７）式は、ｍ、ｎの値を調整することにより実現することができる。このとき、Ｒａ＊（Ｉｘ−Ｉｙ）＋Ｖab＝０となる。 Ra-k * (1-m) / n = 0 (17)
The above equation (17) can be realized by adjusting the values of m and n. At this time, Ra * (Ix−Iy) + Vab = 0.

ここで、（１５）式、（１６）式を上述した（１３）式に代入すると、次の（１８）式が得られる。   Here, when the expressions (15) and (16) are substituted into the above-described expression (13), the following expression (18) is obtained.

Ｖｘ−Ｖｙ＝ｐ＊Ｖds−Ｒａ／（Ｒａ＋Ｒｂ）＊Ｖoff …（１８）
以上より、上述した前提条件に加えて、（１５）式、または（１７）式が成立するようにｍ、ｎの値を調整すると、（Ｖｘ−Ｖｙ）は電圧Ｖdsをｐ倍に増幅した電圧と、Ｒａ／（Ｒａ＋Ｒｂ）＊Ｖoffとの差分として示されることになる。 Vx−Vy = p * Vds−Ra / (Ra + Rb) * Voff (18)
As described above, in addition to the preconditions described above, when the values of m and n are adjusted so that the formula (15) or the formula (17) is satisfied, (Vx−Vy) is a voltage obtained by amplifying the voltage Vds by p times. And Ra / (Ra + Rb) * Voff.

この場合、（１８）式の右辺第２項の「Ｒａ／（Ｒａ＋Ｒｂ）＊Ｖoff」はｐ倍に増幅されないので、増幅後の電圧Ｖdsに対するオフセット電圧Ｖoffの比は、Ｒａ／（Ｒａ＋Ｒｂ）／ｐに低減されることとなる。   In this case, since “Ra / (Ra + Rb) * Voff” in the second term on the right side of the equation (18) is not amplified p times, the ratio of the offset voltage Voff to the amplified voltage Vds is Ra / (Ra + Rb) / p. Will be reduced.

一例として、ｐ＝１０とし、Ｒａ＝Ｒｂとすれば、増幅後のＶdsに対して、Ｖoffは１／２０になり、実質的にはＶds検出におけるばらつき要因ではなくなる。即ち、アンプ（ＡＭＰ１）のオフセット電圧Ｖoffが補正されることを示す。   As an example, if p = 10 and Ra = Rb, Voff becomes 1/20 with respect to the amplified Vds, which is substantially not a variation factor in Vds detection. That is, the offset voltage Voff of the amplifier (AMP1) is corrected.

ここで、上述したように、Ｒａ＝Ｒ１＝Ｒ３であるから、Ｒａ＊（Ｉｘ−Ｉｙ）＋Ｖab＝（Ｒ３＊Ｉｘ−Ｒ１＊Ｉｙ）＋Ｖab＝０と表現することができる。   Here, as described above, since Ra = R1 = R3, it can be expressed as Ra * (Ix−Iy) + Vab = (R3 * Ix−R1 * Iy) + Vab = 0.

これは電流Ｉｘと電流Ｉｙがそれぞれ抵抗Ｒ３、及び抵抗Ｒ１に流れて発生させる電圧降下の差が、点ａ〜点ｂ間に生じる電位差Ｖabに等しくなる条件であると解釈できる。即ち、第１実施形態では、Ｖab≠０での状態で、オフセット電圧Ｖoffの補正を行っていることを示す。   This can be interpreted as a condition in which the difference in voltage drop generated by the currents Ix and Iy flowing through the resistors R3 and R1 is equal to the potential difference Vab generated between the points a and b. That is, the first embodiment indicates that the offset voltage Voff is corrected in a state where Vab ≠ 0.

このようにして、第１実施形態に係る過電流保護装置では、カレントミラー比ｍ、ｎの値を適宜調整することにより、オフセット電圧の影響を補正することができる。従って、アンプ（ＡＭＰ１）に存在するオフセット電圧Ｖoffの影響を回避し、負荷ＲＬに流れる過電流判定を高精度に行うことができる。その結果、過電流が発生した際には、迅速且つ確実にＭＯＳＦＥＴ（Ｔ１）を遮断して、負荷回路を保護することができる。   Thus, in the overcurrent protection device according to the first embodiment, the influence of the offset voltage can be corrected by appropriately adjusting the values of the current mirror ratios m and n. Therefore, it is possible to avoid the influence of the offset voltage Voff existing in the amplifier (AMP1), and to perform overcurrent determination flowing through the load RL with high accuracy. As a result, when an overcurrent occurs, the MOSFET (T1) can be shut off quickly and reliably to protect the load circuit.

なお、上記の説明では、ＰＭＯＳである各トランジスタ（Ｔ３），（Ｔ４）のスレッショルド電圧Ｖthが等しいことを前提としたが、この前提条件が成立しなくても、本発明の効果は発揮される。即ち、各トランジスタ（Ｔ３），（Ｔ４）のスレッショルド電圧Ｖthが相違すると、電圧Ｖabが異なることになるが、電圧Ｖabに対して補正が働くので、スレッショルド電圧Ｖthが等しくないときでも、電圧Ｖabに対しても補正が働く。但し、（Ｒ３＊Ｉｘ−Ｒ１＊Ｉｙ）＋Ｖab＝０が成立しなくなるので、Ｖthが等しくないときは補正効果が低下する。   In the above description, it is assumed that the threshold voltages Vth of the transistors (T3) and (T4) that are PMOS are equal. However, even if this precondition is not satisfied, the effect of the present invention is exhibited. . That is, when the threshold voltage Vth of the transistors (T3) and (T4) is different, the voltage Vab is different. However, since the correction is applied to the voltage Vab, even when the threshold voltage Vth is not equal, the voltage Vab is changed. The correction also works. However, since (R3 * Ix−R1 * Iy) + Vab = 0 is not established, the correction effect is reduced when Vth is not equal.

次に、上述した第１実施形態の、変形例について説明する。図３は、第１実施形態の変形例に係る差動増幅装置を含む過電流保護装置の構成を示す回路図である。   Next, a modification of the above-described first embodiment will be described. FIG. 3 is a circuit diagram illustrating a configuration of an overcurrent protection device including a differential amplifier according to a modification of the first embodiment.

図３に示す変形例では、図１に示した回路に対して、抵抗Ｒ２の取り付け位置、及び抵抗Ｒ４の取り付け位置を変更している。即ち、図１に示した回路では、抵抗Ｒ２を点ｂに接続したが、図３に示す変形例では、グランドに接続している。これに伴い、トランジスタ（Ｔ２）をＰ型ＭＯＳＦＥＴからＮ型ＭＯＳＦＥＴに変更し、トランジスタ（Ｔ２）のソースを抵抗Ｒ２に接続し、この接続点を点ｙとし、トランジスタ（Ｔ２）のドレインを点ｂに接続している。また、点ｙの電圧をＶｙとする。   In the modification shown in FIG. 3, the attachment position of the resistor R2 and the attachment position of the resistor R4 are changed with respect to the circuit shown in FIG. That is, in the circuit shown in FIG. 1, the resistor R2 is connected to the point b, but in the modification shown in FIG. 3, it is connected to the ground. Accordingly, the transistor (T2) is changed from the P-type MOSFET to the N-type MOSFET, the source of the transistor (T2) is connected to the resistor R2, this connection point is set to the point y, and the drain of the transistor (T2) is set to the point b. Connected to. The voltage at the point y is Vy.

また、図３に示す変形例では、図１に示した第１実施形態に対して、抵抗Ｒ４と抵抗Ｒ５の取り付け位置を入れ替えている。よって、抵抗Ｒ４と抵抗Ｒ５の接続点である点ｘの電圧をＶｘとすると（Ｖｘ−Ｖｙ）＝ｍ＊Ｖdsとなる。従って、電圧Ｖｙが電圧Ｖｘよりも所定電圧Ｖｓを超えて低下したとき、過電流と判定する。判定電圧は電圧Ｖｘを基準として生成し、電圧Ｖｘを抵抗Ｒ１１と抵抗Ｒ１２で分圧した電圧、即ち、抵抗Ｒ１１と抵抗Ｒ１２の接続点である点ｅと点ｘとの間の電位差が、所定電圧Ｖｓとなる。そして、点ｅを、コンパレータ（ＣＭＰ１）の正転入力端子に入力し、電圧Ｖｙを反転入力端子に入力することにより過電流を判定することができる。   Moreover, in the modification shown in FIG. 3, the attachment positions of the resistor R4 and the resistor R5 are exchanged with respect to the first embodiment shown in FIG. Therefore, if the voltage at the point x, which is the connection point between the resistors R4 and R5, is Vx, (Vx−Vy) = m * Vds. Therefore, when the voltage Vy falls below the voltage Vx by exceeding the predetermined voltage Vs, it is determined as an overcurrent. The determination voltage is generated based on the voltage Vx, and a voltage obtained by dividing the voltage Vx by the resistor R11 and the resistor R12, that is, a potential difference between the point e and the point x that is a connection point of the resistor R11 and the resistor R12 is predetermined. The voltage is Vs. The overcurrent can be determined by inputting the point e to the normal input terminal of the comparator (CMP1) and inputting the voltage Vy to the inverted input terminal.

それ以外の動作については、上述した第１実施形態と同様であるので、詳しい説明を省略する。   Since other operations are the same as those in the first embodiment described above, detailed description thereof will be omitted.

［第２実施形態］
次に、本発明の第２実施形態について説明する。上述した第１実施形態では、Ｉｘ≠Ｉｙとなる電流Ｉｘ、電流Ｉｙがそれぞれ抵抗Ｒ３、抵抗Ｒ１に流れ、オフセット電圧Ｖoffの補正の一端を担っている。また、そのためにＶab≠０となっている。これに対して、第２実施形態では、Ｖab≒０として、オフセット電圧Ｖoffを補正する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described. In the first embodiment described above, the current Ix and the current Iy satisfying Ix ≠ Iy flow in the resistor R3 and the resistor R1, respectively, and play a part in correcting the offset voltage Voff. For this reason, Vab ≠ 0. On the other hand, in the second embodiment, the offset voltage Voff is corrected by setting Vab≈0.

図４は、第２の実施形態に係る差動増幅器を含む過電流保護装置の構成を示す回路図でる。図４に示す回路は、前述したは図１に示した回路に対し、トランジスタ（Ｔ２０；例えばＮ型ＭＯＳＦＥＴ）、及び、トランジスタ（Ｔ２１；例えばＮ型ＭＯＳＦＥＴ）を追加し、更に、上述したカレントミラー比ｍ、ｎの値を変更したものである。それ以外の構成については、図１に示した回路と同様である。   FIG. 4 is a circuit diagram showing a configuration of an overcurrent protection device including a differential amplifier according to the second embodiment. The circuit shown in FIG. 4 has a transistor (T20; for example, N-type MOSFET) and a transistor (T21; for example, N-type MOSFET) added to the circuit shown in FIG. The values of the ratios m and n are changed. Other configurations are the same as those of the circuit shown in FIG.

図４において、トランジスタ（Ｔ２０）のドレインは点ｂに接続され、トランジスタ（Ｔ２１）のドレインは点ａに接続される。また、トランジスタ（Ｔ２０）のゲートはトランジスタ（Ｔ５）のゲートに接続され、ソースはグランドに接続されている。トランジスタ（Ｔ２１）のゲートはトランジスタ（Ｔ１０）のゲートに接続され、ソースはグランドに接続されている。また、各トランジスタ（Ｔ２０），（Ｔ２１）のチャンネル幅はそれぞれ、トランジスタ（Ｔ６），（Ｔ９）と同様である。従って、トランジスタ（Ｔ２０）のドレイン電流をＩｘｘとし、トランジスタ（Ｔ２１）のドレイン電流をＩｙｙとすると、Ｉｘｘ＝Ｉｘ、Ｉｙｙ＝Ｉｙとなる。その結果、補正回路が抵抗Ｒ３、及び抵抗Ｒ１に流す電流は（Ｉｘ＋Ｉｙ）となり、両者は等しくなる。更にカレントミラー比ｍ、ｎを十分に大きくして、（Ｉ１−Ｉ２）に対する（Ｉｘ−Ｉｙ）の増幅比を大きく設定して、Ｖab≒０にする。   In FIG. 4, the drain of the transistor (T20) is connected to the point b, and the drain of the transistor (T21) is connected to the point a. The gate of the transistor (T20) is connected to the gate of the transistor (T5), and the source is connected to the ground. The gate of the transistor (T21) is connected to the gate of the transistor (T10), and the source is connected to the ground. The channel widths of the transistors (T20) and (T21) are the same as those of the transistors (T6) and (T9), respectively. Therefore, when the drain current of the transistor (T20) is Ixx and the drain current of the transistor (T21) is Iyy, Ixx = Ix and Iyy = Iy. As a result, the current that the correction circuit passes through the resistor R3 and the resistor R1 is (Ix + Iy), and both are equal. Further, the current mirror ratios m and n are sufficiently increased, and the amplification ratio of (Ix−Iy) with respect to (I1−I2) is set to be Vab≈0.

ここで、第１実施形態では（Ｉｘ−Ｉｙ）を大きくしてＶab≒０とすると、（Ｉｘ−Ｉｙ）がゼロにならないため、抵抗Ｒ３、抵抗Ｒ１にそれぞれ電流Ｉｘ，Ｉｙが流れて、電圧降下差（Ｒ３＊Ｉｘ−Ｒ１＊Ｉｙ）を発生させ、オフセット電圧Ｖoffに対して過補正となる場合がある。これに対して、第２実施形態は、この過補正を除去する方式と解釈することができる。   Here, in the first embodiment, if (Ix−Iy) is increased and Vab≈0, (Ix−Iy) does not become zero, so that the currents Ix and Iy flow through the resistors R3 and R1, respectively. A drop difference (R3 * Ix−R1 * Iy) is generated, and the offset voltage Voff may be overcorrected. In contrast, the second embodiment can be interpreted as a method of removing this overcorrection.

このようにして、第２実施形態に係る差動増幅装置及び過電流保護装置では、上述した第１実施形態と同様に、カレントミラー比ｍ、ｎの値を適宜調整することにより、オフセット電圧の影響を補正することができる。この際、オフセット電圧Ｖoffに対して過補正となることを防止して、アンプ（ＡＭＰ１）に存在するオフセット電圧Ｖoffの影響を回避することができる。その結果、負荷ＲＬに流れる過電流判定を高精度に行うことができ、過電流が発生した際には、迅速且つ確実にＭＯＳＦＥＴ（Ｔ１）を遮断して、負荷回路を保護することができる。   As described above, in the differential amplifying device and the overcurrent protection device according to the second embodiment, as in the first embodiment described above, the values of the current mirror ratios m and n are adjusted as appropriate, thereby reducing the offset voltage. The influence can be corrected. At this time, it is possible to prevent the offset voltage Voff from being overcorrected and to avoid the influence of the offset voltage Voff existing in the amplifier (AMP1). As a result, the overcurrent flowing through the load RL can be determined with high accuracy, and when an overcurrent occurs, the MOSFET (T1) can be quickly and reliably cut off to protect the load circuit.

次に、上述した第２実施形態の、変形例について説明する。図５は、第２実施形態の変形例に係る差動増幅装置を含む過電流保護装置の構成を示す回路図である。   Next, a modification of the above-described second embodiment will be described. FIG. 5 is a circuit diagram showing a configuration of an overcurrent protection device including a differential amplifier according to a modification of the second embodiment.

図５に示す変形例では、図４に示した回路に対して、抵抗Ｒ２の取り付け位置、及び抵抗Ｒ４の取り付け位置を変更している。即ち、図４に示した回路では、抵抗Ｒ２を点ｂに接続したが、図５に示す変形例では、グランドに接続している。これに伴い、トランジスタ（Ｔ２）をＰ型ＭＯＳＦＥＴからＮ型ＭＯＳＦＥＴに変更し、トランジスタ（Ｔ２）のソースを抵抗Ｒ２に接続し、この接続点を点ｙとし、トランジスタ（Ｔ２）のドレインを点ｂに接続している。また、点ｙの電圧をＶｙとする。   In the modification shown in FIG. 5, the attachment position of the resistor R2 and the attachment position of the resistor R4 are changed with respect to the circuit shown in FIG. That is, in the circuit shown in FIG. 4, the resistor R2 is connected to the point b, but in the modification shown in FIG. 5, it is connected to the ground. Accordingly, the transistor (T2) is changed from the P-type MOSFET to the N-type MOSFET, the source of the transistor (T2) is connected to the resistor R2, this connection point is set to the point y, and the drain of the transistor (T2) is set to the point b. Connected to. The voltage at the point y is Vy.

また、図５に示す変形例では、図４に示した第２実施形態に対して、抵抗Ｒ４と抵抗Ｒ５の取り付け位置を入れ替えている。よって、抵抗Ｒ４と抵抗Ｒ５の接続点である点ｘの電圧をＶｘとすると（Ｖｘ−Ｖｙ）＝ｍ＊Ｖdsとなる。従って、電圧Ｖｙが電圧Ｖｘよりも所定電圧Ｖｓを超えて低下したとき、過電流と判定する。判定電圧は電圧Ｖｘを基準として生成し、電圧Ｖｘを抵抗Ｒ１１と抵抗Ｒ１２で分圧した電圧、即ち、抵抗Ｒ１１と抵抗Ｒ１２の接続点である点ｅと点ｘとの間の電位差が、所定電圧Ｖｓとなる。そして、点ｅを、コンパレータ（ＣＭＰ１）の正転入力端子に入力し、電圧Ｖｙを反転入力端子に入力することにより過電流を判定することができる。   Moreover, in the modification shown in FIG. 5, the attachment position of resistance R4 and resistance R5 is replaced with respect to 2nd Embodiment shown in FIG. Therefore, if the voltage at the point x, which is the connection point between the resistors R4 and R5, is Vx, (Vx−Vy) = m * Vds. Therefore, when the voltage Vy falls below the voltage Vx by exceeding the predetermined voltage Vs, it is determined as an overcurrent. The determination voltage is generated based on the voltage Vx, and a voltage obtained by dividing the voltage Vx by the resistor R11 and the resistor R12, that is, a potential difference between the point e and the point x that is a connection point of the resistor R11 and the resistor R12 is predetermined. The voltage is Vs. The overcurrent can be determined by inputting the point e to the normal input terminal of the comparator (CMP1) and inputting the voltage Vy to the inverted input terminal.

それ以外の動作については、上述した第２実施形態と同様であるので、詳しい説明を省略する。   Since other operations are the same as those of the second embodiment described above, detailed description thereof is omitted.

以上、本発明の差動増幅装置及び過電流保護装置を図示の実施形態に基づいて説明したが、本発明はこれに限定されるものではなく、各部の構成は、同様の機能を有する任意の構成のものに置き換えることができる。   As described above, the differential amplifying device and the overcurrent protection device according to the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit may be any arbitrary function having the same function. It can be replaced with a configuration one.

負荷回路に過電流が発生した際に、迅速且つ高精度に回路を遮断して回路を保護する上で極めて有用である。   When an overcurrent occurs in the load circuit, it is extremely useful for protecting the circuit by breaking the circuit quickly and with high accuracy.

本発明の第１実施形態に係る差動増幅装置を含む過電流保護装置の構成を示す回路図である。1 is a circuit diagram showing a configuration of an overcurrent protection device including a differential amplifier device according to a first embodiment of the present invention. 図１に示した過電流保護装置から、オフセット電圧を補正する回路を取り除いた回路図である。FIG. 2 is a circuit diagram in which a circuit for correcting an offset voltage is removed from the overcurrent protection device shown in FIG. 1. 本発明の第１実施形態に係る差動増幅装置を含む過電流保護装置の変形例の構成を示す回路図である。It is a circuit diagram which shows the structure of the modification of the overcurrent protection apparatus containing the differential amplifier which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る差動増幅装置を含む過電流保護装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the overcurrent protection apparatus containing the differential amplifier which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る差動増幅装置を含む過電流保護装置の変形例の構成を示す回路図である。It is a circuit diagram which shows the structure of the modification of the overcurrent protection apparatus containing the differential amplifier which concerns on 2nd Embodiment of this invention. 従来における過電流保護装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the conventional overcurrent protection apparatus.

符号の説明Explanation of symbols

１１ ドライバ
ＶＢ 電源
ＲＬ 負荷
Ｔ１ ＭＯＳＦＥＴ（第１の半導体素子）
Ｔ２ トランジスタ（第２の半導体素子）
Ｔ３ トランジスタ（第３の半導体素子）
Ｔ４ トランジスタ（第４の半導体素子）
Ｔ５〜Ｔ１１，Ｔ２０，Ｔ２１ トランジスタ
ＡＭＰ１ アンプ（増幅手段）
ＡＭＰ２ アンプ
ＣＭＰ１ コンパレータ
Ｉａ 定電流源 11 Driver VB Power supply RL Load T1 MOSFET (first semiconductor element)
T2 transistor (second semiconductor element)
T3 transistor (third semiconductor element)
T4 transistor (fourth semiconductor element)
T5 to T11, T20, T21 Transistor AMP1 Amplifier (amplifying means)
AMP2 amplifier CMP1 comparator Ia constant current source

Claims (12)

増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）と第２の抵抗（Ｒ２）の接続点ｂを接続し、正転入力端子ａ１に第３の抵抗（Ｒ３）と第４の抵抗（Ｒ４）の接続点ａを接続し、前記第２の抵抗の他端に第２の半導体素子（Ｔ２）の第１の主電極を接続し、前記第２の半導体素子の第１の主電極を接地し、制御電極を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、前記第４の抵抗の他端を第５の抵抗（Ｒ５）を経由して接地し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力し、前記第２の抵抗と前記第２の半導体素子との接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、
前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、
前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１，Ｒ３，Ｒ７，Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、「Ｉｙ−Ｉｘ」が前記Ｖabに比例し、且つ、（Ｒ１＋Ｒ７）＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するようにＩｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする差動増幅装置。 A connection point b between the first resistor (R1) and the second resistor (R2) is connected to the inverting input terminal b1 of the amplifying means (AMP1), and a third resistor (R3) and a fourth resistor are connected to the normal input terminal a1. A connection point a of the second resistor (R4), a first main electrode of the second semiconductor element (T2) is connected to the other end of the second resistor, and a first point of the second semiconductor element is connected. The main electrode is grounded, the control electrode is connected to the output terminal of the amplification means, the other end of the third resistor is connected to the power supply terminal d, and the other end of the fourth resistor is connected to the fifth resistor (R5). ), An input voltage (Vds) is input between the power supply terminal d and the other end of the first resistor, and a connection point between the second resistor and the second semiconductor element. In the differential amplifying apparatus in which the potential difference between y and the connection point x of the fourth resistor and the fifth resistor is an output voltage,
A seventh resistor (R7) is inserted between the normal input terminal a1 and the connection point a, and an eighth resistor (R8) is inserted between the inverted input terminal b1 and the connection point b;
The offset voltage of the amplifying means is “Voff”, the potential difference between the connection point a and the connection point b is “Vab”, and the resistance values of the first, third, seventh, and eighth resistors are respectively set. “R1, R3, R7, R8” (where R1 = R3, R7 = R8), power supply → R3 → R7 → current flowing through the path “Ix”, power supply → input voltage (Vds) → R1 → R8 → When the current flowing through the ground path is “Iy”, “Iy−Ix” is proportional to the above Vab, and Ix and Iy are controlled to satisfy (R1 + R7) * (Ix−Iy) + Voff = 0. By doing so, the error due to the offset voltage (Voff) of the amplifying means, which occurs when the input voltage (Vds) is amplified to generate the output voltage, is reduced. 増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）を接続し、接続点をｂとし、正転入力端子ａ１に第３の抵抗（Ｒ３）を接続し、接続点をａとし、第２の抵抗（Ｒ２）の一端を接地し、他端を第２の半導体素子（Ｔ２）の第２の主電極に接続し、前記第２の半導体素子の第１の主電極を前記接続点ｂに接続し、制御電極を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、第４の抵抗の一端を接地し、他端を第５の抵抗（Ｒ５）を経由して前記接続点ａに接続し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力し、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、
前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、
前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１，Ｒ３，Ｒ７，Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、「Ｉｙ−Ｉｘ」が前記Ｖabに比例し、且つ、（Ｒ１＋Ｒ７）＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するようにＩｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする差動増幅装置。 The first resistor (R1) is connected to the inverting input terminal b1 of the amplifying means (AMP1), the connection point is b, the third resistance (R3) is connected to the normal rotation input terminal a1, and the connection point is a. One end of the second resistor (R2) is grounded, the other end is connected to the second main electrode of the second semiconductor element (T2), and the first main electrode of the second semiconductor element is connected to the second resistor (R2). Connected to point b, the control electrode is connected to the output terminal of the amplifying means, the other end of the third resistor is connected to the power supply terminal d, one end of the fourth resistor is grounded, and the other end is connected to the fifth terminal. Connected to the connection point a via the resistor (R5), an input voltage (Vds) is input between the power supply terminal d and the other end of the first resistor, and the second resistor and the In a differential amplifying apparatus using a potential difference between a connection point y of the second semiconductor element and a connection point x of the fourth resistor and the fifth resistor as an output voltage. Te,
A seventh resistor (R7) is inserted between the normal input terminal a1 and the connection point a, and an eighth resistor (R8) is inserted between the inverted input terminal b1 and the connection point b;
The offset voltage of the amplifying means is “Voff”, the potential difference between the connection point a and the connection point b is “Vab”, and the resistance values of the first, third, seventh, and eighth resistors are respectively set. “R1, R3, R7, R8” (where R1 = R3, R7 = R8), power supply → R3 → R7 → current flowing through the path “Ix”, power supply → input voltage (Vds) → R1 → R8 → When the current flowing through the ground path is “Iy”, “Iy−Ix” is proportional to the above Vab, and Ix and Iy are controlled to satisfy (R1 + R7) * (Ix−Iy) + Voff = 0. By doing so, the error due to the offset voltage (Voff) of the amplifying means, which occurs when the input voltage (Vds) is amplified to generate the output voltage, is reduced. 前記Ｉｘ、Ｉｙを生成する方法は、
前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３および第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極に接続し、前記第３の半導体素子（Ｔ３）の制御電極を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、および第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）の各半導体素子の第２の主電極を接地し、
前記第５の半導体素子の第１の主電極と制御電極を接続し、更にこの接続点に前記第６、第７の半導体素子の制御電極を接続し、
前記第５の半導体素子の第１の主電極を、前記第３及び第８の半導体素子の第１の主電極に接続し、前記第６の半導体素子の第１の主電極を前記増幅手段（ＡＭＰ１）の正転入力端子ａ１に接続し、
一方、前記第１０の半導体素子の第１の主電極と制御電極を接続し、更にこの接続点に前記第８、第９の半導体素子の制御電極を接続し、
前記第１０の半導体素子の第１の主電極を、前記第４及び第７の半導体素子の第１の主電極に接続し、前記第９の半導体素子の第１の主電極を前記増幅手段の正転入力端子ｂ１に接続し、
前記第６の半導体素子のドレイン電流を前記Ｉｘ、前記第９の半導体素子のドレイン電流を前記Ｉｙとすることを特徴とする請求項１に記載の差動増幅装置。 The method of generating Ix and Iy is as follows:
One end of a constant current source (Ia) is connected to the power supply terminal d, the other end is connected to second main electrodes of third and fourth semiconductor elements (T3, T4), and the third semiconductor element ( The control electrode of T3) is connected to the connection point a, and the control electrode of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), 7 (T7), and 10th (T10), 8th (T8), and 9th (T9) semiconductor element 2nd main electrode are grounded,
Connecting the first main electrode and the control electrode of the fifth semiconductor element, and further connecting the control electrodes of the sixth and seventh semiconductor elements to this connection point;
The first main electrode of the fifth semiconductor element is connected to the first main electrode of the third and eighth semiconductor elements, and the first main electrode of the sixth semiconductor element is connected to the amplification means ( AMP1) is connected to the normal rotation input terminal a1,
On the other hand, connecting the first main electrode and the control electrode of the tenth semiconductor element, and further connecting the control electrodes of the eighth and ninth semiconductor elements to this connection point,
The first main electrode of the tenth semiconductor element is connected to the first main electrode of the fourth and seventh semiconductor elements, and the first main electrode of the ninth semiconductor element is connected to the amplifying means. Connect to forward input terminal b1,
The differential amplifier according to claim 1, wherein the drain current of the sixth semiconductor element is Ix, and the drain current of the ninth semiconductor element is Iy. 前記Ｉｘ、Ｉｙを生成する方法は、
前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３および第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極に接続し、前記第３の半導体素子（Ｔ３）の制御電極を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、および第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）の各半導体素子の第２の主電極を接地し、
前記第５の半導体素子の第１の主電極と制御電極を接続し、更にこの接続点に前記第６、第７の半導体素子の制御電極を接続し、
前記第５の半導体素子の第１の主電極を、前記第３及び第８の半導体素子の第１の主電極に接続し、前記第６の半導体素子の第１の主電極を前記増幅手段（ＡＭＰ１）の正転入力端子ａ１に接続し、
一方、前記第１０の半導体素子の第１の主電極と制御電極を接続し、更にこの接続点に前記第８、第９の半導体素子の制御電極を接続し、
前記第１０の半導体素子の第１の主電極を、前記第４及び第７の半導体素子の第１の主電極に接続し、前記第９の半導体素子の第１の主電極を前記増幅手段の正転入力端子ｂ１に接続し、
前記第６の半導体素子のドレイン電流を前記Ｉｘ、前記第９の半導体素子のドレイン電流を前記Ｉｙとすることを特徴とする請求項２に記載の差動増幅装置。 The method of generating Ix and Iy is as follows:
One end of a constant current source (Ia) is connected to the power supply terminal d, the other end is connected to second main electrodes of third and fourth semiconductor elements (T3, T4), and the third semiconductor element ( The control electrode of T3) is connected to the connection point a, and the control electrode of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), 7 (T7), and 10th (T10), 8th (T8), and 9th (T9) semiconductor element 2nd main electrode are grounded,
Connecting the first main electrode and the control electrode of the fifth semiconductor element, and further connecting the control electrodes of the sixth and seventh semiconductor elements to this connection point;
The first main electrode of the fifth semiconductor element is connected to the first main electrode of the third and eighth semiconductor elements, and the first main electrode of the sixth semiconductor element is connected to the amplification means ( AMP1) is connected to the normal rotation input terminal a1,
On the other hand, connecting the first main electrode and the control electrode of the tenth semiconductor element, and further connecting the control electrodes of the eighth and ninth semiconductor elements to this connection point,
The first main electrode of the tenth semiconductor element is connected to the first main electrode of the fourth and seventh semiconductor elements, and the first main electrode of the ninth semiconductor element is connected to the amplifying means. Connect to forward input terminal b1,
The differential amplifier according to claim 2, wherein the drain current of the sixth semiconductor element is Ix, and the drain current of the ninth semiconductor element is Iy. 電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、前記負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項１または３に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、
前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項１または３に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、
前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、
前記電源端子ｄと前記接続点ｙとの間の電圧が、前記電源端子ｄと前記接続点ｘ間の電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする過電流保護装置。 A first semiconductor element (T1) is disposed between a power supply (VB) and a load (RL), the first main electrode of the first semiconductor is connected to the power supply side, and the second main electrode Is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element to provide a load circuit for controlling the driving and stopping of the load. And an overcurrent protection device that protects the load circuit when an overcurrent occurs, using the differential amplifying device according to claim 1 or 3,
The first main electrode of the first semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. The voltage between the first main electrode and the second main electrode of the first semiconductor element is input as the input voltage (Vds) of the differential amplifying device according to Item 1 or 3,
The resistance value of the second resistor is set to be larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set to be equal,
When the voltage between the power supply terminal d and the connection point y becomes smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage between the power supply terminal d and the connection point x, the current flows to the load. An overcurrent protection device that determines that the current is an overcurrent and shuts off the first semiconductor element. 電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項２または４に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、
前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項２または４に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、
前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、
前記接続点ｙの電圧が、前記接続点ｘの電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする過電流保護装置。 A first semiconductor element (T1) is disposed between a power supply (VB) and a load (RL), the first main electrode of the first semiconductor is connected to the power supply side, and the second main electrode Is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element to provide a load circuit for controlling the driving and stopping of the load. And an overcurrent protection device that protects the load circuit when an overcurrent occurs, using the differential amplifying device according to claim 2 or 4,
The first main electrode of the first semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. The voltage between the first main electrode and the second main electrode of the first semiconductor element is input as the input voltage (Vds) of the differential amplifier according to Item 2 or 4,
The resistance value of the second resistor is set to be larger than the first resistance, and the resistance values of the second resistor and the fourth resistor are set to be equal,
When the voltage at the connection point y is smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage at the connection point x, it is determined that the current flowing through the load is an overcurrent, and the first An overcurrent protection device that cuts off a semiconductor element. 増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）と第２の抵抗（Ｒ２）の接続点ｂを接続し、正転入力端子ａ１に第３の抵抗（Ｒ３）と第４の抵抗（Ｒ４）の接続点ａを接続し、前記第２の抵抗の他端に第２の半導体素子（Ｔ２）の第２の主電極を接続し、前記第２の半導体素子の第１の主電極を接地し、且つ、制御電極を前記増幅手段の出力端子に接続し、
前記第３の抵抗の他端を電源端子ｄに接続し、前記第４の抵抗の他端を第５の抵抗（Ｒ５）を経由して接地し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力して、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、
前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、
前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１、Ｒ３、Ｒ７、Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）とし、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」とし、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流「Ｉｙ」とするとき、前記Ｉｘが前記第１の抵抗を流れ、前記Ｉｙが前記第３の抵抗を流れるように構成し、且つ、Ｒ７＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するように、前記Ｉｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする差動増幅装置。 A connection point b between the first resistor (R1) and the second resistor (R2) is connected to the inverting input terminal b1 of the amplifying means (AMP1), and a third resistor (R3) and a fourth resistor are connected to the normal input terminal a1. A connection point a of the resistor (R4), a second main electrode of the second semiconductor element (T2) is connected to the other end of the second resistor, and a first point of the second semiconductor element is connected. The main electrode is grounded, and the control electrode is connected to the output terminal of the amplification means,
The other end of the third resistor is connected to a power supply terminal d, the other end of the fourth resistor is grounded via a fifth resistor (R5), and the power supply terminal d and the first resistor are connected to each other. An input voltage (Vds) is inputted between the other end, a connection point y between the second resistor and the second semiconductor element, and a connection point x between the fourth resistor and the fifth resistor. In the differential amplifying apparatus in which the potential difference between and
A seventh resistor (R7) is inserted between the normal input terminal a1 and the connection point a, and an eighth resistor (R8) is inserted between the inverted input terminal b1 and the connection point b;
The offset voltage of the amplifying means is “Voff”, the potential difference between the connection point a and the connection point b is “Vab”, and the resistance values of the first, third, seventh, and eighth resistors are respectively set. “R1, R3, R7, R8” (where R1 = R3, R7 = R8), the current flowing through the power source → R3 → R7 → ground path is “Ix”, and the power source → the input voltage (Vds) → R1 → When the current “Iy” flowing through the path of R8 → ground is assumed, the Ix flows through the first resistor, the Iy flows through the third resistor, and R7 * (Ix−Iy) By controlling the Ix and Iy so as to satisfy + Voff = 0, an error caused by the offset voltage (Voff) of the amplifying means that occurs when the input voltage (Vds) is amplified to generate an output voltage is eliminated. A differential amplifying device characterized by being reduced. 増幅手段（ＡＭＰ１）の反転入力端子ｂ１に第１の抵抗（Ｒ１）を接続し、この接続点をｂとし、正転入力端子ａ１に第３の抵抗（Ｒ３）を接続し、この接続点をａとし、第２の抵抗の一端を接地し、他端を第２の半導体素子（Ｔ２）の第２の主電極に接続し、前記第２の半導体素子の第１の主電極を前記接続点ｂに接続し、制御電極を前記増幅手段の出力端子に接続し、前記第３の抵抗の他端を電源端子ｄに接続し、第４の抵抗の一端を接地し、他端を第５の抵抗（Ｒ５）を経由して前記接続点ａに接続し、前記電源端子ｄと前記第１の抵抗の他端との間に入力電圧（Ｖds）を入力して、前記第２の抵抗と前記第２の半導体素子の接続点ｙと、前記第４の抵抗と前記第５の抵抗の接続点ｘと、の間の電位差を出力電圧とする差動増幅装置において、
前記正転入力端子ａ１と前記接続点ａの間に第７の抵抗（Ｒ７）を挿入し、前記反転入力端子ｂ１と前記接続点ｂの間に第８の抵抗（Ｒ８）を挿入し、
前記増幅手段のオフセット電圧を「Ｖoff」、前記接続点ａと前記接続点ｂの間の電位差を「Ｖab」、前記第１、第３、第７、および第８の各抵抗の抵抗値をそれぞれ「Ｒ１、Ｒ３、Ｒ７、Ｒ８」（但し、Ｒ１＝Ｒ３，Ｒ７＝Ｒ８）とし、電源→Ｒ３→Ｒ７→接地の経路で流れる電流を「Ｉｘ」とし、電源→入力電圧（Ｖds）→Ｒ１→Ｒ８→接地の経路で流れる電流を「Ｉｙ」とするとき、前記Ｉｘが前記第１の抵抗を流れ、前記Ｉｙが前記第３の抵抗を流れるように構成し、且つ、Ｒ７＊（Ｉｘ−Ｉｙ）＋Ｖoff＝０を満足するように、前記Ｉｘ、Ｉｙを制御することにより、前記入力電圧（Ｖds）を増幅して出力電圧を生成する際に生じる、前記増幅手段のオフセット電圧（Ｖoff）による誤差を低減することを特徴とする差動増幅装置。 The first resistor (R1) is connected to the inverting input terminal b1 of the amplifying means (AMP1), this connection point is set to b, the third resistance (R3) is connected to the normal rotation input terminal a1, and this connection point is a, one end of the second resistor is grounded, the other end is connected to the second main electrode of the second semiconductor element (T2), and the first main electrode of the second semiconductor element is connected to the connection point. b, the control electrode is connected to the output terminal of the amplification means, the other end of the third resistor is connected to the power supply terminal d, one end of the fourth resistor is grounded, and the other end is connected to the fifth terminal. Connected to the connection point a via a resistor (R5), an input voltage (Vds) is input between the power supply terminal d and the other end of the first resistor, and the second resistor and the A differential amplifying apparatus using a potential difference between a connection point y of the second semiconductor element and a connection point x of the fourth resistor and the fifth resistor as an output voltage. Stomach,
A seventh resistor (R7) is inserted between the normal input terminal a1 and the connection point a, and an eighth resistor (R8) is inserted between the inverted input terminal b1 and the connection point b;
The offset voltage of the amplifying means is “Voff”, the potential difference between the connection point a and the connection point b is “Vab”, and the resistance values of the first, third, seventh, and eighth resistors are respectively set. “R1, R3, R7, R8” (where R1 = R3, R7 = R8), the current flowing through the power source → R3 → R7 → ground path is “Ix”, and the power source → the input voltage (Vds) → R1 → When the current flowing through the path R8 → ground is “Iy”, the Ix flows through the first resistor, the Iy flows through the third resistor, and R7 * (Ix−Iy ) An error due to the offset voltage (Voff) of the amplifying means that occurs when the input voltage (Vds) is amplified to generate an output voltage by controlling the Ix and Iy so that + Voff = 0 is satisfied. A differential amplifying device characterized in that 前記Ｉｘ、Ｉｙを生成する方法は、
前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３及び第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極に接続し、前記第３の半導体素子（Ｔ３）の制御電極を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、第２０（Ｔ２０）、及び第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）、第２１（Ｔ２１）の各半導体素子の第２の主電極を接地し、
前記第５の半導体素子の第１の主電極と制御電極を接続し、且つ、この接続点に前記第６、第７、第２０の半導体素子の制御電極を接続し、前記第５の半導体素子の第１の主電極を前記第３及び第８の半導体素子の第１の主電極に接続し、前記第６の半導体素子の第１の主電極を前記増幅手段の正転入力端子ａ１に接続し、前記第２０の半導体素子のチャンネル幅、及びチャンネル長を前記第６の半導体素子と同一に設定し、且つ第２０の半導体素子の第１の主電極を前記接続点ｂに接続し、
一方、前記第１０の半導体素子の第１の主電極と制御電極を接続し、且つ、この接続点に前記第８、第９、第２１の半導体素子の制御電極を接続し、前記第１０の半導体素子の第１の主電極を前記第４及び第７の半導体素子の第１の主電極に接続し、前記第９の半導体素子の第１の主電極を前記増幅手段の反転入力端子ｂ１に接続し、前記第２１の半導体素子のチャンネル幅、及びチャンネル長を前記第９の半導体素子と同一に設定し、且つ第２１の半導体素子の第１の主電極を前記接続点ａに接続し、
前記第６の半導体素子のドレイン電流をＩｘ、前記第９の半導体素子のドレイン電流をＩｙとすることを特徴とする請求項７に記載の差動増幅装置。 The method of generating Ix and Iy is as follows:
One end of a constant current source (Ia) is connected to the power supply terminal d, the other end is connected to second main electrodes of third and fourth semiconductor elements (T3, T4), and the third semiconductor element ( The control electrode of T3) is connected to the connection point a, and the control electrode of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), 7 (T7), 20th (T20), 10th (T10), 8th (T8), 9th (T9), and 21st (T21) of the second main electrode of each semiconductor element is grounded,
Connecting the first main electrode and the control electrode of the fifth semiconductor element, and connecting the control electrodes of the sixth, seventh and twentieth semiconductor elements to the connection point; and the fifth semiconductor element. The first main electrode is connected to the first main electrode of the third and eighth semiconductor elements, and the first main electrode of the sixth semiconductor element is connected to the normal input terminal a1 of the amplifying means. The channel width and the channel length of the twentieth semiconductor element are set to be the same as those of the sixth semiconductor element, and the first main electrode of the twentieth semiconductor element is connected to the connection point b,
On the other hand, the first main electrode and the control electrode of the tenth semiconductor element are connected, and the control electrodes of the eighth, ninth, and twenty-first semiconductor elements are connected to the connection point, and the tenth The first main electrode of the semiconductor element is connected to the first main electrode of the fourth and seventh semiconductor elements, and the first main electrode of the ninth semiconductor element is connected to the inverting input terminal b1 of the amplification means. Connecting, setting the channel width and channel length of the twenty-first semiconductor element to be the same as those of the ninth semiconductor element, and connecting the first main electrode of the twenty-first semiconductor element to the connection point a,
8. The differential amplifier according to claim 7, wherein the drain current of the sixth semiconductor element is Ix, and the drain current of the ninth semiconductor element is Iy. 前記Ｉｘ、Ｉｙを生成する方法は、
前記電源端子ｄに定電流源（Ｉａ）の一端を接続し、他端を第３及び第４の半導体素子（Ｔ３、Ｔ４）の第２の主電極に接続し、前記第３の半導体素子（Ｔ３）の制御電極を前記接続点ａに接続し、且つ、前記第４の半導体素子（Ｔ４）の制御電極を前記接続点ｂに接続し、第５（Ｔ５）、第６（Ｔ６）、第７（Ｔ７）、第２０（Ｔ２０）、及び第１０（Ｔ１０）、第８（Ｔ８）、第９（Ｔ９）、第２１（Ｔ２１）の各半導体素子の第２の主電極を接地し、
前記第５の半導体素子の第１の主電極と制御電極を接続し、且つ、この接続点に前記第６、第７、第２０の半導体素子の制御電極を接続し、前記第５の半導体素子の第１の主電極を前記第３及び第８の半導体素子の第１の主電極に接続し、前記第６の半導体素子の第１の主電極を前記増幅手段の正転入力端子ａ１に接続し、前記第２０の半導体素子のチャンネル幅、及びチャンネル長を前記第６の半導体素子と同一に設定し、且つ第２０の半導体素子の第１の主電極を前記接続点ｂに接続し、
一方、前記第１０の半導体素子の第１の主電極と制御電極を接続し、且つ、この接続点に前記第８、第９、第２１の半導体素子の制御電極を接続し、前記第１０の半導体素子の第１の主電極を前記第４及び第７の半導体素子の第１の主電極に接続し、前記第９の半導体素子の第１の主電極を前記増幅手段の反転入力端子ｂ１に接続し、前記第２１の半導体素子のチャンネル幅、及びチャンネル長を前記第９の半導体素子と同一に設定し、且つ第２１の半導体素子の第１の主電極を前記接続点ａに接続し、
前記第６の半導体素子のドレイン電流をＩｘ、前記第９の半導体素子のドレイン電流をＩｙとすることを特徴とする請求項８に記載の差動増幅装置。 The method of generating Ix and Iy is as follows:
One end of a constant current source (Ia) is connected to the power supply terminal d, the other end is connected to second main electrodes of third and fourth semiconductor elements (T3, T4), and the third semiconductor element ( The control electrode of T3) is connected to the connection point a, and the control electrode of the fourth semiconductor element (T4) is connected to the connection point b, and the fifth (T5), sixth (T6), 7 (T7), 20th (T20), 10th (T10), 8th (T8), 9th (T9), and 21st (T21) of the second main electrode of each semiconductor element is grounded,
Connecting the first main electrode and the control electrode of the fifth semiconductor element, and connecting the control electrodes of the sixth, seventh and twentieth semiconductor elements to the connection point; and the fifth semiconductor element. The first main electrode is connected to the first main electrode of the third and eighth semiconductor elements, and the first main electrode of the sixth semiconductor element is connected to the normal input terminal a1 of the amplifying means. The channel width and the channel length of the twentieth semiconductor element are set to be the same as those of the sixth semiconductor element, and the first main electrode of the twentieth semiconductor element is connected to the connection point b,
On the other hand, the first main electrode and the control electrode of the tenth semiconductor element are connected, and the control electrodes of the eighth, ninth, and twenty-first semiconductor elements are connected to the connection point, and the tenth The first main electrode of the semiconductor element is connected to the first main electrode of the fourth and seventh semiconductor elements, and the first main electrode of the ninth semiconductor element is connected to the inverting input terminal b1 of the amplification means. Connecting, setting the channel width and channel length of the twenty-first semiconductor element to be the same as those of the ninth semiconductor element, and connecting the first main electrode of the twenty-first semiconductor element to the connection point a,
9. The differential amplifier according to claim 8, wherein the drain current of the sixth semiconductor element is Ix, and the drain current of the ninth semiconductor element is Iy. 電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項７または９に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、
前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の一端に接続して前記請求項７または９に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、
前記電源端子ｄと前記接続点ｙとの間の電圧が、前記電源端子ｄと前記接続点ｘとの間の電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする過電流保護装置。 A first semiconductor element (T1) is disposed between a power supply (VB) and a load (RL), the first main electrode of the first semiconductor is connected to the power supply side, and the second main electrode Is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element to provide a load circuit for controlling the driving and stopping of the load. An overcurrent protection device that protects the load circuit when an overcurrent occurs, using the differential amplifying device according to claim 7 or 9,
The first main electrode of the first semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to one end of the first resistor. The voltage between the first main electrode and the second main electrode of the first semiconductor element is input as the input voltage (Vds) of the differential amplifier according to 7 or 9, and the second resistor A resistance value is set larger than the first resistance, and the resistance values of the second resistance and the fourth resistance are set equal to each other;
When the voltage between the power supply terminal d and the connection point y becomes smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage between the power supply terminal d and the connection point x, the load The overcurrent protection device is characterized in that it determines that the current flowing through is an overcurrent and shuts off the first semiconductor element. 電源（ＶＢ）と負荷（ＲＬ）との間に第１の半導体素子（Ｔ１）を配置し、該第１の半導体の第１の主電極を電源側に接続し、且つ、第２の主電極を負荷側に接続し、該負荷の他端は接地電位レベルに接続し、前記第１の半導体素子の制御電極に制御信号を供給して、前記負荷の駆動、停止を制御する負荷回路に設けられ、前記請求項８または１０に記載の差動増幅装置を用いて、過電流発生時に該負荷回路を保護する過電流保護装置であり、
前記第１の半導体素子（Ｔ１）の第１の主電極を前記第３の抵抗（Ｒ３）の一端に接続し、第２の主電極を前記第１の抵抗の他端に接続して前記請求項８または１０に記載の差動増幅装置の入力電圧（Ｖds）として、前記第１の半導体素子の第１の主電極と第２の主電極の間の電圧を入力し、前記第２の抵抗の抵抗値を前記第１の抵抗より大きく設定し、且つ、前記第２の抵抗と第４の抵抗の抵抗値を等しい値に設定し、
前記接続点ｙの電圧が、前記接続点ｘの電圧から所定の電圧（Ｖｓ）を差し引いた電圧より小さくなったときに、前記負荷に流れる電流が過電流であると判定し、前記第１の半導体素子を遮断することを特徴とする過電流保護装置。 A first semiconductor element (T1) is disposed between a power supply (VB) and a load (RL), the first main electrode of the first semiconductor is connected to the power supply side, and the second main electrode Is connected to the load side, the other end of the load is connected to the ground potential level, and a control signal is supplied to the control electrode of the first semiconductor element to provide a load circuit for controlling the driving and stopping of the load. An overcurrent protection device that protects the load circuit when an overcurrent occurs, using the differential amplifying device according to claim 8 or 10;
The first main electrode of the first semiconductor element (T1) is connected to one end of the third resistor (R3), and the second main electrode is connected to the other end of the first resistor. The voltage between the first main electrode and the second main electrode of the first semiconductor element is input as the input voltage (Vds) of the differential amplifier of Item 8 or 10, and the second resistor And a resistance value of the second resistor and the fourth resistor are set equal to each other.
When the voltage at the connection point y is smaller than the voltage obtained by subtracting a predetermined voltage (Vs) from the voltage at the connection point x, it is determined that the current flowing through the load is an overcurrent, and the first An overcurrent protection device that cuts off a semiconductor element.
JP2007270179A 2007-10-17 2007-10-17 Differential amplification apparatus and overcurrent protection apparatus Pending JP2009100281A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009148063A1 (en) * 2008-06-04 2009-12-10 矢崎総業株式会社 Overcurrent protective device for load circuit
KR20230014487A (en) * 2021-07-21 2023-01-30 비테스코 테크놀로지스 게엠베하 Apparatus for protecting motor from over current

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009148063A1 (en) * 2008-06-04 2009-12-10 矢崎総業株式会社 Overcurrent protective device for load circuit
JP2009296263A (en) * 2008-06-04 2009-12-17 Yazaki Corp Overcurrent protective device for load circuit
US8295021B2 (en) 2008-06-04 2012-10-23 Yazaki Corporation Overcurrent protection apparatus for load circuit
KR20230014487A (en) * 2021-07-21 2023-01-30 비테스코 테크놀로지스 게엠베하 Apparatus for protecting motor from over current
KR102602800B1 (en) 2021-07-21 2023-11-15 비테스코 테크놀로지스 게엠베하 Apparatus for protecting motor from over current

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