JP2006060971A - Controller of semiconductor switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller of semiconductor switch for protecting a circuit, while preventing wrong interruptions due to inrush current during transient period, and that is capable of interrupting a semiconductor switch surely on the occurrence of short circuit or grounding. <P>SOLUTION: An MOSFET(T1) is interrupted, when an overcurrent flows due to a fault occurring in a second wiring 22 and the voltage between terminals (VDS) of the MOSFET(T1) exceeds a judgment voltage level V4, wherein the transition period, when the MOSFET(T1) is turned on is set, such that the voltage between terminals (VDS) does not exceed the deciding voltage level V4, by operating an attenuator to attenuate the voltage between terminals (VDS). When the second wiring 22 is short-circuited or grounded during the operation of the attenuator, the magnitude of a back-emf E1 induced in a first wiring 21 by a short circuit current is detected; and if it exceeds a predetermined decision value, the MOSFET(T1) is interrupted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor switch control device for controlling on / off of a semiconductor switch interposed between a power source and a load.

  For example, loads such as motors and lamps mounted on a vehicle are switched between driving and stopping by operating on and off of a semiconductor switch provided between the load and a battery (power source). .

  In such a circuit, when an overcurrent flows in the wiring connecting the semiconductor switch and the load due to short-circuit grounding or the like, the power supply side terminal and the load side of the semiconductor switch are protected in order to protect the semiconductor switch. Utilizing the fact that the potential difference between the terminals is proportional to the current flowing through the semiconductor switch, it is determined that an overcurrent has flowed when the potential difference exceeds a predetermined value, and the wiring and the semiconductor element itself are protected. An overcurrent protection method is known (see, for example, JP 2000-253560 A).

  However, in this method, during the transition period in which the semiconductor element transitions from the off state to the on state, the potential difference between both ends of the semiconductor switch is a predetermined value even if there is no abnormality in the wiring due to the essential characteristics of the semiconductor switch. There is a problem of exceeding.

  Therefore, conventionally, the following methods (A1) and (A2) have been used as overcurrent protection methods in which the overcurrent protection function operates even during a transition period and does not make a misjudgment. .

  (A1) The overcurrent detection function is stopped for a certain period immediately after the start. That is, a certain mask period is provided. However, this method can prevent the semiconductor switch from being erroneously cut off, but cannot detect when an overcurrent occurs during the mask period and cannot protect the semiconductor switch. Even when the mask period is set to the minimum, if the short-circuit grounding occurs before the start, the protection function is inevitably lowered.

  (A2) The sensitivity of the overcurrent detection function is lowered for a certain period immediately after the start so that the overcurrent determination is not performed even when the voltage between the terminals of the semiconductor switch increases. Specifically, after amplifying the voltage between the terminals of the semiconductor switch, this amplified voltage is compared with a predetermined value (determination voltage), the amplification factor is set to a small value immediately after the start, and time passes. Then gradually restore the standard gain.

  The method (A2) will be described below with reference to the circuit diagram shown in FIG. In the figure, an N-type MOSFET (T101) as a semiconductor switch is provided between a load 121 and a power supply VB.

  The drain-source voltage VDS of the MOSFET (T101) is amplified by a circuit including the resistor R103, the N-type MOSFET (T102), the resistor R105, and the amplifier AMP101, and appears as a voltage V5 (= R5 voltage drop). . That is, the current I1 is adjusted by the operation of the amplifier AMP101 so that the voltage generated at both ends of the resistor R103 is equal to the drain-source voltage VDS. Therefore, the voltage V5 generated at the resistor R105 is the voltage VDS (R105). / R103) times the amplified voltage.

  Then, the determination voltage V4 generated by dividing the power supply voltage V1 by the resistors R101 and R102 and the above voltage V5 are compared by the comparator CMP101, and when V5> V4, it is determined that the current is overcurrent. ing.

  More specifically, in the amplifier circuit, the voltage V3 at the coupling point between the resistor R103 and the drain of the MOSFET (T102) is always equal to the source voltage V2 of the MOSFET (T101) by the feedback operation by the amplifier AMP101 and the MOSFET (T102). It is controlled to become.

  As a result, the voltage drop of the resistor R103 is equal to the drain-source voltage VDS (= V1-V2) of the MOSFET (T1). Assuming that the on-resistance of the MOSFET (T101) is Ron, the current flowing through the MOSFET (T101) is ID, and the current flowing through the point P1 (voltage V1) → R103 → T102 → R105 → ground is I1, the voltage V5 is as follows ( 1) It can be shown by the formula.

V5 = R105 * I1 = R105 * VDS / R103
= R105 * Ron * ID / R103
= R105 * Ron / R103 * ID (1)
When the load current ID is in a normal state with respect to the determination voltage V4, the resistance values of the resistors R103 and R105 are selected so that V5≈ (1/2) * V4. When the load current ID increases to more than twice the normal state, V5> V4 and it is determined that an overcurrent has flowed.

  Here, the problem with the above method is that there is a period in which the on-resistance Ron is high immediately after the start.

  The on-resistance Ron depends on the gate-source voltage VGS of the MOSFET (T101). When the MOSFET (T101) is in a stable state, that is, after 1 [ms] or more has elapsed from the start, the voltage VGS is saturated and reaches nearly 10 V, and the on-resistance Ron is a constant resistance value determined by the characteristics of the FET, For example, a low resistance value of about 10 mΩ is obtained.

  In this state, the voltage V5 is proportional to the load current ID. When the load current ID is normal, V5 <V4. When the load current ID is doubled, the voltage V5 is also doubled and V5> V4. Judgment is made. However, since the voltage VGS starts increasing from zero immediately after the start, the on-resistance Ron starts from a high resistance, and gradually decreases as the voltage VGS increases. Follow the process of convergence.

  That is, during the period from the start until the voltage VGS is saturated, the on-resistance Ron shows a high resistance value, and even if the load current ID is normal, the voltage V5 increases according to the above equation (1). The voltage V4 will be exceeded.

  As a countermeasure, in the circuit shown in FIG. 8, when the MOSFET (T101) is turned off and the source voltage V2 becomes zero, the positive input terminal voltage of the amplifier AMP101 is forcibly lowered by the diode D103, and the amplifier AMP101 is used. The negative input terminal is pulled up by the voltage V4 and the diode D102 so that the output of the amplifier AMP101 becomes L level. Further, a circuit of a diode D101 and a resistor R104 is added so that the determination value voltage V4 increases as the voltage V2 increases.

  In such a circuit configuration, when the MOSFET (T101) is turned on, the voltage V2 starts to increase. However, when V2 <V4-0.6V, the output of the amplifier AMP101 decreases and the voltage V5 is held at 0V. The When the voltage V2 increases and exceeds V4-0.6V, the output of the amplifier AMP101 starts to increase and the voltage V5 increases.

  The maximum value of the rising speed of the voltage V5 is determined by the slew rate (response characteristic) of the amplifier AMP101. On the other hand, the voltage V4 also rises and rises along the path V2-> R104-> D101-> V4 due to the increase in the voltage V2.

  If the rising speed of the voltage V4 is larger than the maximum rising speed of the voltage V5 determined by the slew rate of the amplifier AMP101, V4> V5 is maintained. This equivalently reduces the gain of the amplifier AMP101. When the voltage VGS is saturated during that time, the on-resistance Ron converges to a low resistance value, and if the load current ID is in the normal range, V5 <V4 is maintained, and the MOSFET (T101) continues to be turned on without being cut off.

If short-circuit grounding occurs during this time, the voltage V2 rises slowly, while the voltage V5 rises at a speed determined by the slew rate regardless of the presence or absence of short-circuit grounding, so that V5> V4 and the comparator CMP101 is inverted and the MOSFET is inverted. (T101) is blocked. That is, even during the period immediately after the start, the overcurrent can be detected and the MOSFET (T101) can be shut off.
JP 2000-253560 A

  However, the conventional semiconductor switch control method described above has the following problems.

  (B1) The rising speed of the voltage V4, that is, the voltage V2, must be made faster than the maximum rising speed of the voltage V5 determined by the slew rate of the amplifier AMP101. That is, the control depends on the slew rate of the amplifier AMP101 and depends on it.

  (B2) The rate of increase of the voltage V2 is determined by the rate of increase of the voltage VGS, and thus is determined by the time constant formed by the product of the gate capacitance of the MOSFET (T101) and the series resistance R110 between the driver and the gate. Here, when it is necessary to smooth the switching waveform of the load current ID as a countermeasure for radio noise, there is a desire to increase this time constant. However, the time constant is set only within the range of the slew rate of the amplifier AMP101. I can't make it bigger. Therefore, in order to realize a desired time constant, it is necessary to change the slew rate of the amplifier AMP101 to a small value.

  (B3) On the other hand, when the start period is over and the MOSFET (T101) is in a stable ON state, the slew rate of the amplifier AMP101 is larger in order to detect a sudden increase in current due to short-circuit grounding (dead short) or the like. desirable. This is in conflict with the needs of (B2) above.

  The present invention has been made to solve such a conventional problem. The object of the present invention is to make a circuit malfunction even immediately after the semiconductor switch is turned on regardless of the slew rate of the amplifier. (If it is normal, it is not erroneously detected as abnormal), and if an overcurrent condition occurs, this will be detected reliably and the protection function will be activated, adversely affecting the operation after the transient period has passed. It is an object of the present invention to provide a control device for a semiconductor switch that can be controlled without affecting the above.

  In order to achieve the above object, according to the first aspect of the present invention, one end of the semiconductor switch is connected to the positive terminal of the power supply by the first wiring, and the other end is connected to the load by the second wiring. In the semiconductor switch control device for controlling the semiconductor switch of the power supply circuit, the other end of which is connected to the negative terminal of the power source, when an overcurrent flows due to a wiring abnormality occurring in the second wiring, the semiconductor switch By detecting whether or not the magnitude of the voltage (VDS) between terminals exceeds a first determination value, and when the semiconductor switch shifts from OFF to ON, The terminal voltage (VDS) is attenuated by operating an attenuator during a transient period in which the terminal voltage (VDS) exceeds the first determination value (V4) even though the wiring of 2 is normal. When the voltage between the terminals (VDS) is less than or equal to the first determination value and the second wiring is short-circuited or grounded during the period when the attenuator is operating, The magnitude of the counter electromotive force (E1) generated in the first wiring due to the short-circuit current is detected, and the detected counter electromotive force (E1) is generated by the transient current when the wiring is normal. The semiconductor switch is shut off when a second determination value set to a larger value is exceeded.

  According to a second aspect of the present invention, the voltage between the terminals (VDS) of the semiconductor switch is amplified during a period of operating the attenuator, and the amplified voltage is saturated due to the restriction of the power supply voltage. The voltage (V5) obtained by the amplification is a period exceeding the first determination value (V4).

  According to a third aspect of the present invention, there is provided a comparator (CMP1) for comparing the voltage (V5) obtained by amplifying the voltage between the terminals and the first determination value (V4) via the attenuator. ) And the first determination value is input to the first input terminal of the comparator, and the second input terminal of the comparator is connected to the terminal via the first resistor (R15). A voltage amplification result (V5) is input, an attenuator capacitor (C1) is disposed between the second input terminal of the comparator and the ground level, and the second input terminal of the comparator (CMP1) is a diode ( D3) and a second resistor (R16) to be connected to the load side terminal of the semiconductor switch, and the attenuator includes the first resistor (R15), the attenuator capacitor (C1), It consists of a diode (D3) and a second resistor (R16). And butterflies.

  According to a fourth aspect of the present invention, when the voltage (V5) obtained by amplifying the voltage between the terminals becomes smaller than the first determination value (V4) after a transient period when the semiconductor switch is turned on, It is characterized in that the function of the attenuator is removed.

  According to the fifth aspect of the present invention, the magnitude of the counter electromotive force generated in the first wiring in spite of the fact that the second wiring is short-circuited to ground while the attenuator is operating. Is lower than the second determination value, it detects that the increasing slope of the load-side terminal voltage (V2) of the semiconductor switch is more gradual than when the wiring is normal, and shuts off the semiconductor switch. It is characterized by that.

  According to a sixth aspect of the present invention, there is provided a method for detecting that the increasing slope of the load-side terminal voltage (V2) of the semiconductor switch is more gradual than when the wiring is normal, the load-side terminal voltage (V2) of the semiconductor switch. ) Is lower than the second input terminal voltage (V6) of the comparator, which is the output of the attenuator, and is longer than when the wiring is normal, when the short-circuit grounding occurs in the second wiring. It is characterized by.

  According to a seventh aspect of the present invention, there is provided a plurality of circuits in which the semiconductor switch and the load are connected in series via the second wiring in the semiconductor switch control device according to the first to sixth aspects. A circuit configuration in which the semiconductor switch side of the parallel circuit is connected to the positive terminal of the power source via the only first wiring, and the load side of the parallel circuit is connected to the power source negative terminal. When the back electromotive force generated in the first wiring exceeds the second determination value, all of the plurality of semiconductor switches are temporarily turned off to interrupt the current flowing through the loads, and then By individually turning on each of the semiconductor switches again, only the semiconductor switch connected to the second short-circuited wiring is cut off, and the semiconductor element connected to the normal second wiring is operated normally. Characterized in that the.

  According to an eighth aspect of the present invention, the semiconductor switch control device according to any one of the first to sixth aspects includes a plurality of circuits in which the semiconductor switch and the load are connected in series via the second wiring. A circuit configuration in which the semiconductor switch side of the parallel circuit is connected to the positive terminal of the power source via the only first wiring, and the load side of the parallel circuit is connected to the power source negative terminal. When a plurality of signals for turning on each of the semiconductor switches are input at the same time, they are individually turned on with a certain time interval.

  A power supply circuit in which one end of the semiconductor switch is connected to the power supply plus terminal, the other end is connected to the load, the other end of the load is connected to the minus terminal of the power supply, and the power supplied to the load by the semiconductor switch is controlled In this method, a method of using the magnitude of the voltage between the terminals of the semiconductor switch to detect an abnormal state in which the wiring (second wiring) between the semiconductor switch and the load is short-circuited to ground and an overcurrent is generated. Are known.

  This method has an excellent feature that the detection circuit is simple, but in the transition period from when the semiconductor switch is turned on until the on-resistance becomes stable, the on-resistance becomes higher than when it is stable, and the wiring is Even if it is normal, the voltage between terminals exceeds the judgment value. In other words, it does not hold in principle during the transition period.

  In order to solve this problem, the present invention specifies a period in which the voltage between the terminals of the semiconductor switch exceeds the judgment value even if the wiring is normal, and the signal generated from the voltage between the terminals has a time constant within that period. By adding an attenuator (capacitor charging circuit) and comparing with the determination value, the semiconductor element is shifted to the on state in the normal state without being cut off.

  On the other hand, when a wiring abnormality occurs during the transition period, a short-circuit current flowing through the power supply side wiring (first wiring) with respect to a short-circuit ground (dead short) that requires an emergency measure is generated. Detecting a sudden drop in the power supply side terminal voltage or detecting a decrease in the increase slope of the load side terminal voltage by comparison with the time constant circuit to cut off the short circuit current, The element and wiring were protected. As a result, the problem of the conventional method of detecting overcurrent using the voltage between terminals can be solved, and an overcurrent protection method having a simple configuration can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a control device for a semiconductor switch according to an embodiment of the present invention. As shown in the figure, this semiconductor switch control device includes a load 11 (for example, a lamp and a motor mounted on a vehicle) that is driven by applying a DC voltage, and a power source VB (for example, mounted on a vehicle). And a MOSFET (T1; semiconductor switch) that switches between driving and stopping of the load 11, and controls the amplifier circuit 12, the counter electromotive force detection circuit 13, and the capacitor charging circuit (attenuation). Unit 14, a determination voltage generation circuit 15, a comparison circuit 16, and a drive circuit 17.

  The drain of the MOSFET (T1) is connected to the point P1, and the point P1 is further connected to the positive side terminal of the power supply VB via the first wiring 21 having the inductance L1 and the resistance Rw1. The source of the MOSFET (T1) is a point P2, and the point P2 is connected to one end of the load 11 via a second wiring 22 having an inductance L2 and a resistance Rw2. The other end of the load 11 is connected to the ground (the negative terminal of the power supply VB).

  The amplifier circuit 12 generates a voltage having a magnitude obtained by amplifying a differential voltage V1-V2 (= VDS) between the voltage generated at the point P1 and the voltage V2 generated at the point P2 to a desired magnification, and the resistor R3. (Resistance value 80 [Ω]), MOSFET (T2) and resistor R5 (resistance value 1 to 8 [KΩ]) in series connection circuit, one end of resistor R3 is connected to point P1, and one end of resistor R5 is grounded Connected to. The amplifier AMP1, the diode D5, and the resistors R7 (resistance value 10 [KΩ]) and R8 (resistance value 10 [KΩ]) are provided, and the plus-side input terminal of the amplifier AMP1 is connected to the resistor R3 via the resistor R7. And a connection point (P3) between the drain of the MOSFET (T2). The voltage at this connection point is V3.

  Further, the negative input terminal of the amplifier AMP1 is connected to the point P2 through the resistor R8, and the negative input terminal is connected to a connection point (P4) of resistors R1 and R2, which will be described later, through the diode D5. Has been.

  Further, the resistor R5 includes four resistors having resistance values of 8 [KΩ], 8 [KΩ], 4 [KΩ], and 2 [KΩ], respectively, as shown in the figure, and when the switch group 31 is OFF. When the resistance value of the resistor R5 is 8 KΩ and the switch group 31 is ON, the resistance value of the resistor R5 is 1 [KΩ] as a parallel combined resistance of four resistors.

  The amplifier circuit 12 passes the current I1 through the series connection circuit of the resistor R3, the MOSFET (T2), and the resistor R5 so that the voltage V2 at the point P2 is equal to the voltage V3 of the drain of the MOSFET (T2). . That is, an output signal corresponding to the difference between the voltages V2 and V3 is output from the amplifier AMP1, and thereby the gate voltage of the MOSFET (T2) is controlled, so that the voltages V2 and V3 are controlled to be equal. As a result, the voltage V5 generated in the resistor R5 has a magnitude obtained by multiplying the differential voltage VDS between the points P1 and P2 by (R5 / R3).

  The operation of the amplifier circuit 12 is as follows. The voltage V3 at the point P3 is input to the plus side input terminal of the amplifier AMP1 via the resistor R7, while the source voltage V2 of the MOSFET (T1) is input to the minus side input terminal via the resistor R8. The

  A diode D5 is placed between the point P4 and the negative input terminal of the amplifier AMP1 so that the input terminal of the amplifier AMP1 does not fall below the ground level when the source voltage V2 of the MOSFET (T1) drops below the ground level. ing. Since the output terminal of the amplifier AMP1 is coupled to the gate of the MOSFET (T2), the output of the amplifier AMP1 rises when V3> V2, and the current I1 flowing through the path of point P1, R3, T2, R5, and ground increases. Then, the voltage drop of the resistor R3 increases and the voltage V3 decreases, and V3 = V2.

  Further, when V3 <V2, the output of the amplifier AMP1 decreases, the current I1 decreases, and the voltage drop across the resistor R3 decreases, so that V3 = V2. That is, the amplifier AMP1 controls the current I1 through the MOSFET (T2) so that V3 = V2. The amplification result is a voltage V5. When the on-resistance of the MOSFET (T1) is Ron and the current flowing through the MOSFET (T1) is ID, VDS = Ron * ID = R3 * I1. 1) It can be shown by the formula.

V5 = R5 * I1
= R5 * VDS / R3
= R5 * Ron / R3 * ID (1)
The voltage V5 at the point P5 is input to the positive input terminal of the comparator CMP1 via the resistor R15. A capacitor charging circuit 14 is added between the input terminal and the ground, and the capacitor Since the capacitor C1 included in the charging circuit 14 is provided between the point P6 and the ground, the voltage V6 is attenuated with respect to the rise of the voltage V5 and is supplied to the plus side input terminal of the comparator CMP1.

  The determination voltage generation circuit 15 includes a resistor R1 (resistance value 10 [KΩ]), a resistor R2 (resistance value 10 [KΩ]), a resistor R4 (resistance value 2 [KΩ]), and a diode D1. The resistors R1 and R2 are connected in series, one end of the resistor R1 is connected to the point P1, and one end of the resistor R2 is connected to the ground. Further, a point P4 which is a connection point of the resistors R1 and R2 is connected to the point P2 via the diode D1 and the resistor R4, and the point P4 is connected to a minus side input terminal of the comparator CMP1 described later. Here, the voltage at the point P4 is defined as a determination voltage V4 (first determination value).

  Accordingly, the voltage V4 is a voltage obtained by dividing the voltage V1 at the point P1 by the resistors R1 and R2, and thus becomes (1/2) V1. Further, since the point P4 is connected to the point P2 via the diode D1, the resistor R4, and is connected to the point P2 via the diode D5, the resistor R8, the voltage V4 is V4-V2> 0.6. In the case of [V], a current flows through the path of D5 and R8 and is pulled down from (1/2) V1, and when V4-V2 <0.6 [V] and V2-V4 <0.6 [V], V4 = (1/2) V1, and when V2-V4> 0.6 [V], current flows through the path of R4 and D1, and the voltage V4 is raised. Here, 0.6 [V] is the voltage drop of the diode.

  Note that the point P4 is also connected to a series circuit composed of a diode D4 and a resistor R17 of the capacitor charging circuit 14 to be described later, but the resistance value of the resistor R17 is extremely larger than the resistance value of the resistor R4, and should be ignored. Can do.

  The capacitor charging circuit 14 has a resistor R15 (resistance value 10 [KΩ]) connected to a point P5 which is one end of the resistor R5. The point P6 which is the other end of the resistor R15 is connected to the point of the comparator CMP1. Connected to the positive input terminal. A MOSFET (T3) is provided in parallel with the resistor R15.

  Further, a capacitor C1 is provided between the point P6 and the ground. The point P6 is connected to the point P2 through the diode D3 and the resistor R16. Furthermore, a diode D2 is provided between the cathode of the diode D3 and the ground. The diode D2 is for clamping so that the voltage (V6) at the positive side input terminal of the comparator CMP1 does not drop below the ground level.

  The point P5 is connected to the emitter of the transistor T4, and the collector of the transistor T4 is connected to the ground via the resistor R18 and is connected to the gate of a MOSFET (T7) described later. Further, the base of the transistor T4 is connected to the point P4 via the resistor R17 and the diode D4. The transistor (T4) is turned on when V5−V4> 1.2 [V].

  Then, when the MOSFET (T3) is off, the capacitor charging circuit 14 causes the voltage V6 at the point P6 to gradually increase with respect to the increase in the voltage V5 by the time constant set by the resistor R15 and the capacitor C1. When the MOSFET (T3) is on, the voltages V5 and V6 are substantially matched.

  The comparison circuit 16 includes a comparator CMP1 and a resistor R14 for pulling up the output terminal of the comparator CMP1 to a voltage of 5V. The voltage V6 is input to the plus side input terminal of the comparator CMP1, and the voltage V4 is input to the minus side input terminal. Therefore, the output signal of the comparator CMP1 is at the H level when V6> V4, and is at the L level when V6 <V4.

  The counter electromotive force detection circuit 13 includes resistors R9 and R10, a MOSFET (T5), resistors R11 and R12, a capacitor C2, a Zener diode ZD1, and a timer 18.

  The resistors R9 and R10 are connected in series, one end of the resistor R10 is connected to the point P1, the point P7 that is one end of the resistor R9 is connected to the capacitor C2, and the other end is connected to the ground. The source of the MOSFET (T5) is connected to the point P7, the gate is connected to the connection point of the resistors R9 and R10, and the drain is connected to the ground via a series circuit of the resistors R11 and R12. A point P8, which is a connection point between the resistors R11 and R12, is connected to the timer 18, and an output terminal of the timer 18 is connected to one input terminal of an AND circuit AND2 described later. The point P8 is connected to the ground via a Zener diode ZD1 for voltage stabilization.

  In the back electromotive force detection circuit 13, when the second wiring 22 is short-circuit grounded (dead short) and the back electromotive force E1 is generated in the first wiring, the voltage V7 at the point P7 is slower than the voltage V1. The occurrence of short-circuit grounding is detected by utilizing the fact that it fluctuates.

  When the back electromotive force E1 is zero, that is, when the current flowing through the first wiring 21 does not change, the capacitor C2 is charged to the power supply voltage VB by the resistors R10 and R9. As a result, the voltage V7 on the non-grounded side (point P7) of the capacitor C2 becomes equal to the voltage VB. Further, when a short circuit current flows through the first wiring 21, a back electromotive force E1 is generated by the inductance L1, and the drain voltage V1 of the MOSFET (T1) decreases.

  At this time, since the non-ground side voltage V7 of the capacitor C2 cannot be decreased immediately, if the voltage of E1 * R9 / (R9 + R10) exceeds the threshold voltage of the MOSFET (T5), the MOSFET (T5) The switch is turned on, and a voltage is generated in the series circuit of the resistors R11 and R12.

  The Zener diode ZD1 limits the voltage V8 at the connection point P8 of the resistors R11 and R12 so as not to exceed the operating voltage 5 [V] of the logic circuit. When the voltage V8 rises, the timer 18 operates and outputs a signal at H level for a certain time to the AND circuit AND2. That is, when the back electromotive force E1 exceeds a predetermined determination value (second determination value) while the transistor (T4) is on, the output of the AND circuit AND2 becomes H level, and this H level signal is ORed. The signal is input to the latch DF1 via the circuit OR1.

  The drive circuit 17 includes AND circuits AND1, AND2, MOSFET (T7), OR circuit OR1, latch DF1, driver 19, charge pump 20, resistors R6 and R13, MOSFET (T6), and switch SW1. It has. The switch SW1A will be described later.

  One input terminal of the AND circuit AND2 is connected to the output terminal of the timer 18, the other input terminal is connected to the source of the MOSFET (T7), and its gate is connected to the collector of the transistor (T4). . The drain of the MOSFET (T7) is connected to the power supply 5V.

  The output terminal of the AND circuit AND2 is connected to one input terminal of the OR circuit OR1, and the other input terminal is connected to the output terminal of the comparator CMP1. The output terminal of the OR circuit OR1 is connected to the latch DF1, and the + Q output of the latch DF1 is connected to the gate of the MOSFET (T6). The -Q output of the latch DF1 is connected to one input terminal of the AND circuit AND1, the other input terminal is connected to the power supply VB via the switch SW1, and is connected to the ground via the resistor R6. .

  The latch DF1 is reset when the input signal switch SW1 is off, and outputs two types of outputs + Q and -Q. The + Q output becomes L level when reset, and the -Q output becomes H level when reset. When the + Q output becomes H level, the MOSFET (T6) is turned on, and the MOSFET (T1) is turned off by connecting the gate of the MOSFET (T1) to the ground.

  The output terminal of the AND circuit AND1 is connected to a driver 19 for controlling the driving of the MOSFET (T1), and the output terminal of the driver 19 is connected to the gate of the MOSFET (T1) via a resistor R13. Therefore, when the output signal of the AND circuit AND1 becomes H level, the driver 19 supplies the voltage output from the charge pump 10 to the gate of the MOSFET (T1) and performs control to turn on the MOSFET (T1). .

  Next, the operation of the semiconductor switch control device according to the present embodiment configured as described above will be described. In the semiconductor switch control device according to the present embodiment, the MOSFET (T1) is controlled in the transient state and the normal state based on the contents shown in the following (A) to (C).

  (B) After the MOSFET (T1) is turned on, until the transient state ends, the voltage V5 at the point P5 obtained by amplifying the voltage between the terminals (drain-source voltage; VDS) of the MOSFET (T1) Instead of comparing the determination value voltage V4, the capacitor C1 is charged using the amplified voltage V5, and the charging voltage V6 of the capacitor C1 is compared with the determination value voltage V4.

  When the second wiring 22 is not short-circuited and is normal, the charging time constant of the capacitor C1 is set so that the charging voltage of the capacitor C1 does not exceed the determination value V4. As a result, no erroneous interruption occurs when the second wiring 22 is normal. The capacitor charging circuit 14 serves as an attenuator when the voltage V5 is input to the comparator CMP1.

  (B) The transition period of the MOSFET (T1) varies depending on the gate capacitance of the MOSFET (T1) and the gate series resistance interposed between the gate and the driver output, that is, the size of the resistor R13, but usually 10 [μs] to 200 [Μs]. What cannot be left unattended due to the wiring abnormality occurring in this short period is short-circuit grounding accompanied by generation of a large overcurrent.

  A wiring abnormality (for example, an overcurrent value of 60 A or less) in which the overcurrent does not increase so much is detected after the transient period ends and reaches a stable state, and even if it is cut off, it is still in time. Therefore, the protection to be performed during the transition period may be limited to a short circuit ground fault. When the MOSFET (T1) is turned on in a state where the second wiring 22 between the MOSFET (T1) and the load 11 is short-circuited, the increasing gradient of the load side terminal voltage V2 of the MOSFET (T1) is gentler than that in the normal wiring. become. A short-circuit grounding of the second wiring 22 is detected using the change (relaxation) of the wiring gradient. The charging voltage gradient of the capacitor C1 described above is used as a determination criterion at that time.

  (C) Furthermore, if the transient period at the start of the MOSFET (T1) is shortened, in other words, if the switching speed is increased, the overcurrent increase rate (gradient) due to short-circuit grounding is increased and is generated in the first wiring 21. The back electromotive force E1 to be increased. If the magnitude of the back electromotive force E1 exceeds the upper limit of the back electromotive force generated by an inrush current or the like in the normal state of the wiring, it is determined that the short circuit is grounded.

  Based on the contents of (A) to (C) above, specific operations will be described below. When the switch SW1 is off, the latch DF1 is reset, and the + Q output is outputted at L level, so the MOSFET (T6) is turned off, and the -Q output is outputted at H level, so one input of the AND circuit AND1. Is held at the H level.

  Further, since the switch SW1 is off, the other input terminal of the AND circuit AND1 becomes L level, and the output signal of the AND circuit AND1 becomes L level. Accordingly, the MOSFET (T1) is turned off, and the source voltage V2 of the MOSFET (T1) is zero. Note that the switch SW1A is used in the following description, and is assumed to be connected in this case.

  When the switch SW1 is turned on, one input signal of the AND circuit AND1 becomes H level, and on the other hand, since the -Q output of the latch DF1 is H level, the output signal of the AND circuit AND1 becomes H level. A drive signal is supplied to the gate of the MOSFET (T1).

  As a result, the MOSFET (T1) is turned on, the voltage output from the power supply VB is applied to the load 11, and the load 11 starts driving.

  Since the drain voltage of the MOSFET (T1) is V1 and the source voltage is V2, the drain-source voltage VDS of the MOSFET (T1) is VDS = V1-V2. The voltage VDS is amplified by an amplifier circuit 12 including resistors R3, R5, R7, R8, a diode D5, a MOSFET (T2), and an amplifier AMP1, and the amplified voltage is a source voltage (point P5) of the MOSFET (T2). Voltage) V5.

  Hereinafter, an operation when the wiring is normal, an operation when a short-circuit ground is generated, an operation when a plurality of FET channels are provided, and an operation when the switching time is long will be described.

<Operation when wiring is normal>
When the wiring is normal at first, that is, when a short circuit does not occur, the amplification factor when the voltage VDS is generated by amplifying the voltage VDS as shown in the above equation (1) is R5 / R3. expressed. Since R3 = 80 [Ω] and R5 corresponds to the inrush current of the load 11 as described above, the resistance value is changed in the period during which the inrush current flows and the stable state thereafter. R5 = 1 [KΩ] in the transition period immediately after the start, and R5 = 8 [KΩ] in the stable state.

  Therefore, in the stable state, R5 / R3 = 8 [KΩ] / 80 [Ω] = 100, and therefore the amplification factor is 100 times. Considering the case where the load 11 is a single headlamp, the load current ID in the stable state is about 5A. As the MOSFET (T1) for driving the load 11, one having an on-resistance of about Ron = 10 [mΩ] is usually used.

  Accordingly, VDS = 50 mV and V5 = 5 [V] after normal state and after the transition period of the MOSFET (T1) ends.

  In the transient period, since R5 = 1 [KΩ], the amplification factor is 12.5 times. Since the upper limit of the voltage V5 cannot exceed the power supply voltage VB, if VB = 12.5 [V], the output signal of the amplifier AMP1 sticks to the upper limit while the voltage VDS exceeds 1 [V]. V5 rises from the power supply voltage VB, which is the upper limit of the output voltage of the amplifier AMP1, to a voltage lower by the threshold voltage Vth2 of the MOSFET (T2), and is held at that voltage. That is, V5 = VB−Vth2. At this time, the determination voltage V4 is set so that V5> V4. The waveform at this time is shown in FIG.

  FIG. 3 shows waveforms of V1, V2, V4, V5, V6, and ID. The numerical value in parentheses of V1 (2 [V / div], 6V) represents the vertical axis scale, the voltage of the vertical scale 1 scale is 2V, and the scale of the center scale (horizontal line) is 6V, the waveform of V1 is represented. Indicates that The display for other waveforms is the same. The horizontal axis is [20 μs / div].

  As understood from the figure, when the MOSFET (T1) is off (before it is turned on at time t1), V2 = 0 [V], so that the plus side input terminal (point P6) of the comparator CMP1. The voltage V6 is pulled down by the diode D3 and the resistor R16 and approaches the ground level.

  Here, when R15 = 10 [KΩ], R16 = [3 KΩ], VB = 12.5 [V], and Vth2 = 1 [V], the plus side input terminal voltage V6 of the comparator CMP1 is 3.25 [3] V]. At this time, the voltage V4 is about 4.8 V because it is pulled down from VB / 2 = 6.25 [V] by the voltage V2 via the diode D5 and the resistor R8.

  Therefore, V6 <V4, and the output signal of the comparator CMP1 becomes L level. When the input switch SW1 is turned on at time t1, the output signal of the AND circuit AND1 becomes H level, the MOSFET (T1) is turned on, and the source voltage V2 of the MOSFET (T1) starts to rise. At this time, the transistor (T4) illustrated in FIG. 1 is in an on state since V5−V4> 1.2.

  Then, since the cathode side voltage of the diode D3 rises, the anode side voltage, that is, the plus side input terminal voltage V6 of the comparator CMP1 also starts to rise. The voltage V4 also starts to rise from the initial value of 4.8V, and when the voltage V2 exceeds V4 + 0.6 [V], the voltage V4 is raised by the voltage V2. At this time, the rising speed of the voltage V6 is set so that V4> V6 is always satisfied until the end of the transition period. Thus, when the MOSFET (T1) is in the transition period, the voltage V6 does not exceed the determination value voltage V4, and the occurrence of trouble that the MOSFET (T1) is erroneously cut off due to the inrush current in the transition period is avoided. be able to.

  The rising speed of V6 can be determined by the voltage V5, the resistance value of the resistor R15, and the capacitance of the capacitor C1. In the range of VDS> 1 [V], the source voltage V5 of the MOSFET (T2) is V1-1 [V], so that the capacitor C1 is charged through the resistor R15 by this voltage V5, and a waveform close to an exponential curve. Thus, the voltage V6 increases with the voltage V5 as a target value.

  In the meantime, when the voltage V2 rises to V1−V2 <1 [V], the amplifier AMP1 starts a feedback operation, and V3 = V2. When the wiring is normal, V5 <V4, so that the transistor (T4) is turned off, and the collector of the transistor (T4) is grounded by the resistor R18.

  As a result, the MOSFET (T3) is turned on and V5 = V6. Since the voltage V5 is lowered, the voltage V6 that was in the middle of the rise is also lowered, and is stabilized at V4> V6 = V5. If there is no abnormality in the wiring, by appropriately setting the values of the resistor R15 and the capacitor C1, the MOSFET (T1) shifts to a stable state through a transient period at the start without being cut off.

  That is, a circuit composed of a resistor R15, a capacitor C1, a diode D3, a resistor R16, and a source voltage V2 of the MOSFET (T1) interposed between the point P5 (voltage V5) and the positive side input terminal of the comparator CMP1 generates the voltage V5. It can be regarded as an attenuator that is attenuated and input to the positive side input terminal of the comparator CMP1. It can be interpreted that the decay rate is greatest immediately after turning on, then decreases with time, and becomes zero when the transient period ends. The capacitance of the capacitor C1 is in the range of 1000 to 13000 [pf] when R15 = 10 [KΩ].

  Thus, when no wiring abnormality has occurred, the MOSFET (T1) can be reliably operated during the transient period of the MOSFET (T1) without being erroneously interrupted by an inrush current.

<Operation when short-circuit grounding occurs>
Next, the operation when short-circuit grounding occurs in the second wiring 22 connecting the MOSFET (T1) and the load 11 will be described. In FIG. 1, it is assumed that a short-circuit grounding occurs at some point in the wiring (second wiring) connecting the source (point P2) of the MOSFET (T1) and the load 11, and the path from the point P2 to the grounding point, that is, the first The resistance of the wiring 3 is Rw3, and the inductance is L3.

  First, a case where the switching time (transient period) of the MOSFET (T1) is normal, that is, a case where the switching time is about 60 [μs] as shown in FIG. 3 will be described. In this case, the value of the capacitor C1 is set small. In FIG. 3, 2200 pf is an appropriate value when R15 = 10 KΩ.

  Before the MOSFET (T1) is turned on, V2 = 0 and the transistor (T4) is turned on. Even after the MOSFET (T1) is turned on, the transistor (T4) remains on for a while. When the transistor (T4) is turned on, the MOSFET (T7) is turned on, and one input of the AND circuit AND2 becomes H level.

  When the switching time of the MOSFET (T1) is normal, the increasing gradient of the short-circuit current is increased, and the back electromotive force E1 generated in the first wiring 21 is increased. The counter electromotive force E1 appears as a difference between the non-ground side voltage V7 of the capacitor C2 and the voltage V1 at the point P1. That is, V7−V1 = E1.

  When the voltage E1 exceeds a predetermined value, that is, a value that does not occur in the inrush voltage, the MOSFET (T5) is turned on, the voltage V8 rises, the output signal of the timer 18 becomes H level, and the other of the AND circuit AND2 Input signal becomes H level. As a result, the output signal of the AND circuit AND2, that is, the output of the OR circuit OR1, changes to H level, and the latch DF1 is set.

  As a result, since the + Q output of the latch DF1 becomes H level, the MOSFET (T6) is turned on, the gate of the MOSFET (T1) is grounded, the MOSFET (T1) is turned off, and the short-circuit current is cut off. That is, if the back electromotive force E1 exceeds a predetermined value while the transistor (T4) is on, it is determined that a short-circuit ground has occurred and the MOSFET (T1) is cut off. The waveform at this time is shown in FIG.

  In the characteristic diagram shown in FIG. 4, the scale on the horizontal axis is enlarged 10 times as large as 2 [μs / div] compared to FIG. 3, and the current ID is (5 A / div, 15 A). Since the second wiring 22 is short-circuited to ground, the current ID rapidly rises simultaneously with the turning on of the MOSFET (T1) (time t1), so that the back electromotive force E1 is generated in the first wiring 21 and the voltage V1 is Declines rapidly.

  Thereby, since the counter electromotive force E1 exceeds a predetermined determination value, the output of the timer 18 rises and the MOSFET (T1) is cut off. When a short circuit occurs, the MOSFET (T1) is turned off after about 4 [μs] after the MOSFET (T1) is turned on, and the peak of the current ID during this period is 15 [A]. It can be seen that the overcurrent is suppressed by the high-speed judgment / cutoff, and the power loss generated in the MOSFET (T1) is clearly smaller than that at the normal start shown in FIG.

  That is, when a short circuit ground occurs in the second wiring 22, the MOSFET (T1) can be cut off in a very short time by detecting the occurrence of the back electromotive force E1, and the circuit and the MOSFET (T1). It can reliably protect itself.

<Operation when a plurality of FET channels are provided>
Here, in the circuit shown in FIG. 1, a case where one MOSFET (one channel) and one load are connected to the first wiring 21 is shown, but actually, a plurality of points are connected between the point P1 and the ground. A series circuit of a MOSFET and a load (hereinafter referred to as “FET channel”) may be connected in parallel. In such a case, when a plurality of FET channels are turned on simultaneously, all the FET channels can be turned off by the above procedure to protect the circuit. It is impossible to specify whether E1 exceeding the value is generated.

  In such a case, all the FET channels started at the same time are once turned off, and then turned on again in order at regular intervals, whereby the FET channel where the short-circuit ground is generated can be specified.

  This operation is performed by a logic circuit. FIG. 2 is a circuit diagram showing a 5-channel sequential start circuit as an example of a logic circuit. As shown in the figure, this sequential start circuit includes switches SW11 to SW15 for turning on and off MOSFETs included in the load circuits of five channels, AND circuits AND11 to AND19, D flip-flops DF11 to DF15, and an exclusive NOR circuit. Circuits XNOR1 to XNOR5 and a clock circuit CL are provided. The output signals (SW1A to SW5A) of the AND circuits AND11 to AND15 correspond to the switch SW1A shown in FIG.

  In this order start circuit, for example, if the switching time (transient period) is 60 [μs], the channels are sequentially turned on channel by channel at intervals of 60 [μs].

  In the normal channel, the back electromotive force E1 exceeding a predetermined value is not generated during the transition period, so that the normal channel continues to be turned on, and the abnormal channel in which the short circuit ground is generated is cut off again. When the back electromotive force E1 is generated by turning on an abnormal channel, a channel that has already been turned on among other normal channels is not blocked.

  In addition, a normal channel that has not yet been started has a cut-off signal due to the generation of the back electromotive force E1, but is not affected because it is turned off at this point. That is, when the back electromotive force E1 due to short-circuit grounding is detected, the normal channel and the abnormal channel can be identified by turning off all the channels once and then starting them one by one in order.

  Even if there are 10 channels, the time required to start sequentially at intervals of 60 [μs] is 600 [μs], and this delay time is not a practical problem in most cases.

  Next, the operation of the circuit shown in FIG. 2 will be described. When the input switches SW11 to SW15 of channels 1 to 5 are input at the same time, the signals of SW1A to SW5A are sequentially output from the start circuit in synchronization with the clock signal.

  The period of the clock signal output from the clock circuit CL is 60 [μs]. The input switches SW11 to SW15 are assumed to be at L level (= 0) when turned off and at H level (= 1) when turned on. When the switches SW11 to SW15 are off, the Q outputs of the D flip-flops DF11 to DF15 are 0 and the Q bar output is 1.

  The AND circuits AND11 to 15 output 0 because the two inputs are both 0, and the switches SW1A to SW5A are turned off. When the switches SW11 to 15 are input simultaneously, the outputs of the exclusive NOR circuits (XNOR1 to 4) become zero.

  When the clock rises, the Q output of the D flip-flop DF11 whose D terminal signal is 1 becomes 1, the SW1A which is the output of the AND circuit AND11 becomes 1, and the first channel is turned on.

  However, in the D flip-flops DF12 to DF15 to 15 in which the D terminal signal is input via the AND circuits AND16 to 19, these AND circuits are closed by the 0 output of the exclusive NOR circuit (XNOR1 to 4). When the clock is input, the Q outputs of the DFs 12 to 15 become 0, the outputs SW2A to SW5A of the AND circuits AND12 to 15 remain 0, and the second to fifth channels cannot be turned on.

  When the output of the D flip-flop DF11 becomes 1, the output of XNOR1 changes from 0 to 1, and the output of the AND circuit AND16, that is, the D terminal signal of DF12 is changed to 1. At the second rise of the clock, the Q output of the D flip-flop DF12 changes to 1, and the output SW2A of the AND circuit AND12 becomes 1.

  As a result, the second channel is turned on at the second clock rise. The third to fifth channels cannot be turned on by the zero outputs of the exclusive NOR circuits XNOR2 to XNO4. When the second channel is turned on, the output of the exclusive NOR circuit XNOR2 changes from 0 to 1.

  When the above operations are arranged, priorities are set in the order of the switches SW11 to SW15 by the exclusive NOR circuits XNOR1 to XNOR4 and the AND circuits AND16 to AND19, and each time the clock rises, the channels are turned on in order from the channel with the highest priority.

  The switch SW1A (first channel) is turned on unconditionally in synchronization with the rising edge of the clock, but the switch SW5A (fifth channel) is synchronized with the clock only when the outputs of the exclusive NOR circuits XNOR1 to XNOR4 are all 1. Can be turned on. The output of the exclusive NOR circuits XNOR1 to XNOR4 being 1 indicates that the channel is not in the transition period from off to on or from on to off, in other words, it is in a stable on or off state. If this logic circuit is used, even if an ON signal is simultaneously input to two or more channels, it is possible to start up one channel at a time.

  By adopting such a configuration, when a back electromotive force E1 at the time of short-circuit grounding is generated in the first wiring 21 when a load circuit of a plurality of channels exists, all the channels are shut off, and then Then, the switches SW11 to SW15 shown in FIG. As a result, a channel in which short-circuit grounding has occurred cannot be activated, and a normal channel in which short-circuit ground has not occurred can be activated.

  Therefore, even in the case of having a plurality of channels, it is possible to reliably and quickly identify a channel in which a short-circuit ground is generated, block this, and drive other normal channels as usual.

<Operation when switching time is long>
Next, overcurrent detection and protection when the switching time of the MOSFET (T1) is long will be described. As an example in which the switching time needs to be lengthened, there is a headlamp duty control performed for Day time running light. When duty control of 100 [Hz] and 20 [%] is performed, in order to suppress the generation of radio noise, the switching time is lengthened and the current waveform rises and falls smoothly.

  The switching time (transition period) at this time is about 200 [μs]. The waveform at that time is shown in FIG. Since the rising gradient of the voltage V2, that is, the determination value V4 becomes gentle, the time constant of C1 * R15 must be increased so that V4> V6 is satisfied, and the rising of the positive input voltage V6 of CMP1 must also be made gentle. .

  In FIG. 5, when R15 = 10 [KΩ], C1 = 1200 [pf]. If the switching time is increased, the drain-source voltage VDS of the MOSFET (T1) decreases gradually, so that even if a short-circuit grounding occurs, the current rising slope becomes gentle and the back electromotive force E1 exceeds the judgment value. Absent.

  Therefore, the occurrence of short-circuit grounding cannot be detected by detecting the back electromotive force E1. FIG. 6 shows a waveform when short-circuit grounding is performed with the same specifications as FIG. Compared to FIG. 4, the horizontal axis is displayed at a speed of 50 [μs / div] and 1/25. Since the initial decrease in the voltage V1 after the occurrence of the short-circuit ground is small, the decrease in the voltage V5 is also small, and the charging voltage of the capacitor C1, that is, the increasing gradient of the voltage V6 is not so much lower than that in the normal state.

  On the other hand, the increase gradient of the voltage V2 becomes gentler than that in the normal state due to short-circuit grounding. As a result, the period of V6> V2 becomes longer than that in FIG. In addition, when V4> V2, the increase gradient of the determination value voltage V4 may become gentle due to the decrease in the voltage V1, so that V4 = V6 and the MOSFET (T1) is cut off. That is, when the short-circuit grounding occurs, the increase gradient of the voltages V2 and V4 becomes gentler than normal, whereas the increase gradient of the voltage V6 decreases compared to the normal time, but the decrease amount is smaller than the voltages V2 and V4. Short circuit ground can be detected. FIG. 7 shows the waveforms of V2, V4, and V5 in FIG. 5 superimposed on those in FIG.

  As the short circuit ground becomes more severe, in other words, as the resistances Rw3 and L3 of the short circuit become smaller, the increasing slope of the voltage V2 becomes gentler. However, in the range where the slope of the voltage V2 falls below the slope of the voltage V6, the MOSFET (T1) The time from turning on to shutting off becomes almost constant.

  Also, as the degree of short-circuit grounding becomes lighter and the gradient of the voltage V2 becomes larger, the time until interruption becomes longer and lighter, and when it approaches the inrush current in the normal state, it is not detected. In such a case, an abnormality (minor short-circuit grounding) will be detected by another overcurrent detection method after the transition period ends. However, the degree of abnormality is minor, that is, close to normal current. It doesn't matter if shut off.

  Accordingly, even when the switching time is long and the short-circuit ground cannot be detected due to the magnitude of the back electromotive force E1, the MOSFET (T1) and the circuit are surely cut off. Can be protected.

  In the circuit shown in FIG. 1, the overcurrent is detected using the magnitude of the voltage VDS after the end of the transient period. That is, the overcurrent detection method in the transient period is different from the subsequent overcurrent detection method in the stable state, and two types of detection methods are switched and used. The switching is performed by turning on and off the transistor (T4). However, since the switching is performed instantaneously, a blank period for overcurrent detection does not occur. This is also a feature of the present invention.

  This is extremely useful for reliably protecting semiconductor switches and circuits when short-circuit grounding occurs.

It is a circuit diagram which shows the structure of the control apparatus of the semiconductor switch which concerns on one Embodiment of this invention. FIG. 4 is a circuit diagram for sequentially turning on a circuit including a plurality of FET channels. It is a characteristic view which shows the change of each signal in the normal time when switching time is normal. It is a characteristic view which shows the change of each signal at the time of short circuit earthing | grounding when switching time is normal. It is a characteristic view which shows the change of each signal in the normal time when switching time is long. It is a characteristic view which shows the change of each signal at the time of short circuit earthing | grounding when switching time is long. FIG. 7 is a characteristic diagram in which FIGS. 5 and 6 are superimposed. It is a circuit diagram of the control apparatus of the conventional semiconductor switch.

Explanation of symbols

11 Load 12 Amplifier circuit 13 Back electromotive force detection circuit 14 Capacitor charging circuit (attenuator)
DESCRIPTION OF SYMBOLS 15 Determination voltage generation circuit 16 Comparison circuit 17 Drive circuit 18 Timer 19 Driver 20 Charge pump 21 1st wiring 22 2nd wiring 23 3rd wiring VB Power supply (battery)
CMP1 comparator

Claims (8)

One end of the semiconductor switch is connected to the positive terminal of the power source by the first wiring, the other end is connected to the load by the second wiring, and the other end of the load is connected to the negative terminal of the power source. In a semiconductor switch control device for controlling a semiconductor switch,
By detecting whether or not the magnitude of the voltage (VDS) between the terminals of the semiconductor switch exceeds the first judgment value when an overcurrent flows due to a wiring abnormality occurring in the second wiring, Having a configuration to block,
When the semiconductor switch shifts from OFF to ON, an attenuator is used during a transient period in which the inter-terminal voltage (VDS) exceeds the first determination value (V4) even though the second wiring is normal. By operating, the terminal voltage (VDS) is attenuated so that the terminal voltage (VDS) is less than or equal to the first determination value;
When the second wiring is short-circuited or grounded while the attenuator is operating, the back electromotive force (E1) generated in the first wiring due to the short-circuit current When the magnitude is detected and the detected back electromotive force (E1) exceeds a second determination value set to a value larger than the back electromotive force generated by the transient current when the wiring is normal, the semiconductor switch A device for controlling a semiconductor switch, wherein   During the period in which the attenuator is operated, the voltage (V5) obtained by the amplification is amplified including the case where the voltage (VDS) between the terminals of the semiconductor switch is amplified and the amplified voltage is saturated due to the restriction of the power supply voltage. 2. The semiconductor switch control device according to claim 1, wherein the period exceeds the first determination value (V4). A comparator (CMP1) for comparing the voltage (V5) obtained by amplifying the voltage between the terminals and the first determination value (V4) via the attenuator;
The first determination value is input to a first input terminal of the comparator;
The second input terminal of the comparator receives the amplification result (V5) of the inter-terminal voltage via the first resistor (R15),
An attenuator capacitor (C1) is disposed between the second input terminal of the comparator and the ground level;
A second input terminal of the comparator (CMP1) is connected to a load side terminal of the semiconductor switch via a diode (D3) and a second resistor (R16);
3. The semiconductor switch according to claim 2, wherein the attenuator includes the first resistor (R15), an attenuator capacitor (C1), a diode (D3), and a second resistor (R16). Control device.   The function of the attenuator is removed when the voltage (V5) obtained by amplifying the voltage between the terminals becomes smaller than the first determination value (V4) after a transient period when the semiconductor switch is turned on. 4. The semiconductor switch control device according to claim 3, wherein the control device is a semiconductor switch control device.   During the period when the attenuator is operating, the magnitude of the back electromotive force generated in the first wiring is less than the second determination value even though the second wiring is short-circuited to ground. 4. If there is, the semiconductor switch is shut off by detecting that the increasing slope of the load side terminal voltage (V2) of the semiconductor switch is more gradual than when the wiring is normal. The control apparatus of the semiconductor switch of description.   The method for detecting that the increasing slope of the load-side terminal voltage (V2) of the semiconductor switch is more gradual than when the wiring is normal is that the load-side terminal voltage (V2) of the semiconductor switch is the output of the attenuator. 6. The method according to claim 5, wherein a period during which the period lower than the second input terminal voltage (V6) of the comparator is shorter than when the wiring is normal is longer when a short-circuit ground occurs in the second wiring. Semiconductor switch control device. 7. The semiconductor switch control device according to claim 1, wherein a plurality of circuits in which the semiconductor switch and the load are connected in series via the second wiring are connected in parallel. The semiconductor switch side is connected to the positive terminal of the power source only through the first wiring, and the load circuit side of the parallel circuit is connected to the power source negative terminal.
When the back electromotive force generated in the first wiring exceeds the second determination value, all of the plurality of semiconductor switches are temporarily turned off to interrupt the current flowing through the loads, and then By individually turning on the semiconductor switches again, only the semiconductor switch connected to the second short-circuited wiring is cut off, and the semiconductor element connected to the normal second wiring is operated normally. A control device for a semiconductor switch. 7. The semiconductor switch control device according to claim 1, wherein a plurality of circuits in which the semiconductor switch and the load are connected in series via the second wiring are connected in parallel. The semiconductor switch side is connected to the positive terminal of the power source only through the first wiring, and the load circuit side of the parallel circuit is connected to the power source negative terminal.
A control device for a semiconductor switch, wherein when a plurality of signals for turning on each of the semiconductor switches are simultaneously input, the semiconductor switches are individually turned on with a predetermined time difference.