JP2009081532A - Clock supply control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock supply control circuit capable of stopping supplying a clock signal while securing a clock pulse width when a supply voltage varies, and also restarting supplying the clock signal. <P>SOLUTION: A clock stop timing generating circuit 12 is composed of a flip-flop 14, an EXOR gate 13 and an AND gate 6, wherein the stop timing of supply of a clock signal CLK_OUT to a logic circuit 2 is synchronized to a trailing edge of a clock signal CLK and the restart timing of the supply thereof is synchronized to a leading edge of the clock signal CLK. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clock supply control circuit that monitors a change in power supply voltage and controls supply of a clock signal to a logic circuit.

Conventionally, a backup capacitor is provided to cope with a momentary interruption of power supplied to a digital circuit, and the capacitor is configured to supply power via a diode for preventing reverse current flow. . And in patent document 1, it replaces with said diode, MOSFET is inserted, and it employ | adopts the structure made into a low resistance at the time of normal operation, and functioning as a diode at the time of interruption | blocking of a power supply, Therefore The voltage drop of the minute is prevented.
Further, FIG. 5 of Patent Document 1 discloses a configuration that reduces power consumption at the time of backup by stopping the operation of the oscillator 16 that supplies a clock signal to the digital circuit 20A when the power is shut off. .

FIG. 3 shows a configuration example of a circuit having a function similar to that of the oscillator 16 described above. The power supply VDD is supplied to the logic circuit 2 (corresponding to the digital circuit 20A) via the diode 1 (corresponding to the MOSs 1 and 2). A backup capacitor 3 is connected in parallel to the logic circuit 2, and the backup capacitor 3 is charged by the power supply VDD and backs up the power supply for operation when power is cut off.
The oscillation circuit 4 oscillates and outputs the clock signal CLK and supplies it to the logic circuit 2 via the AND gate 5. When detecting that the voltage of the power supply VDD has fallen below the lower limit value, the voltage drop detection circuit 6 outputs a voltage drop detection signal VL (low active) to the other input terminal of the AND gate 5. The oscillator 16 of Patent Document 1 is presumed to correspond to the oscillation circuit 4, the AND gate 5, and the voltage drop detection circuit 6.
International Publication No. 2005/029675 Pamphlet

  In the configuration of Patent Document 1, when the power supply is interrupted and the oscillator 16 stops operating, the clock pulse width of the clock signal output at that time is not guaranteed. FIG. 4 is a timing chart showing an example of an operation corresponding to the configuration of FIG. When the voltage of the power supply VDD decreases and falls below the lower limit value, the voltage drop detection signal VL becomes active, and then when the power supply voltage starts to rise and exceeds the lower limit value, the voltage drop detection signal VL becomes inactive (FIG. 4). (See (a) and (b)). The high level of the clock signal CLK output from the oscillation circuit 4 changes in accordance with the fall and rise of the power supply VDD (see FIG. 4C).

The clock signal CLK_OUT supplied to the logic circuit 2 via the AND gate 5 is stopped during the period when the voltage drop detection signal VL is active (see FIG. 4D). Then, the timing at which the level of the voltage drop detection signal VL changes is asynchronous with the clock signal CLK. Therefore, in some cases, the clock pulse width cannot be guaranteed as shown in FIG.
When the supply is stopped or the supply is restarted in such a state where the clock pulse width is not guaranteed, the change state of the signal input to the logic circuit 2 is transmitted from the input stage of the internal logic gate to the output stage. Operation may become unstable. Then, even if the internal state of the digital circuit 2 is held by the backup capacitor 3 while the supply of the clock signal CLK_OUT is stopped, the continuity of the resumed operation may be uncertain.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a clock that can stop the supply of a clock signal while guaranteeing the clock pulse width and can restart the supply of the clock signal when the power supply voltage fluctuates. It is to provide a supply control circuit.

  According to the clock supply control circuit of claim 1, the control circuit synchronizes the timing of stopping the supply of the clock signal to the logic circuit with the falling edge of the clock signal and the timing of restarting the supply of the clock signal. Are synchronized with the rising edge of the clock signal. With this configuration, the clock pulse has an appropriate width determined according to the frequency and the duty ratio between the timing when the supply of the clock signal is stopped and the timing when the supply is resumed. Therefore, the logic circuit can reliably continue the operation from the state before the operation stop when the supply of the clock signal is resumed after the internal state is held by the means for performing backup when the power supply voltage decreases. .

  According to the clock supply control circuit of the second aspect, the control circuit is composed of a flip-flop, an EXOR gate, and an AND gate. Assuming that the voltage drop detection signal is low-active, if the signal is inactive, the output signal of the EXOR gate (flip-flop clock input) is synchronized with the fall of the clock signal within that period. Is output. Therefore, when the level of the voltage drop detection signal (flip-flop data input) changes from high to low, the output signal of the flip-flop changes to low level in synchronization with the fall of the next clock signal. The supply of the clock signal to is stopped after the high level pulse width is secured.

  On the other hand, during the period when the voltage drop detection signal is active, the output signal of the EXOR gate is output in synchronization with the rising edge of the clock signal, so that when the level of the voltage drop detection signal changes from low to high, Since the output signal changes to the high level in synchronization with the rising of the next clock signal, the supply of the clock signal to the logic circuit is started so as to ensure the high level pulse width. Therefore, the control circuit of the present invention can be configured very simply.

  An embodiment of the present invention will be described below with reference to FIGS. 3 that are the same as those in FIG. 3 are denoted by the same reference numerals, description thereof is omitted, and different portions are described below. FIG. 1 shows a configuration of the clock supply control circuit 11, which is configured by arranging a clock stop timing generation circuit (control circuit) 12 in place of the AND gate 5 shown in FIG. 3. However, the timing generation circuit 12 includes an AND gate 5 and an EXOR gate 13 and a flip-flop 14.

  The voltage drop detection signal VL is applied to the data input terminal D of the flip-flop 14, and the data output terminal Q (supply control signal VC) of the flip-flop 14 is applied to one of the input terminals of the AND gate 5. At the same time, it is given to one of the input terminals of the EXOR gate 13. The clock signal CLK is supplied to the other input terminal of the EXOR gate 13 together with the other input terminal of the AND gate 5, and the output terminal of the EXOR gate 13 is connected to the clock input terminal C of the flip-flop 14. .

  The logic circuit 2 is, for example, a gate array, a custom logic IC, or a CPU. Further, the lower limit value set in the voltage drop detection circuit 6 can be backed up from the time when the voltage of the power supply VDD tends to drop until the power-on reset circuit (not shown) is activated at a lower voltage level. Is set to have a predetermined time margin.

  Next, the operation of the present embodiment will be described with reference to FIG. When the power supply voltage VDD changes as in FIG. 4A, the output signal of the EXOR gate 13 (the clock input terminal C of the flip-flop 14) is the rising edge of the clock signal CLK while the voltage drop detection signal VL is high. It is output in synchronism with the fall (strictly, at the timing when it changes from the high level to the low level). Accordingly, when the level of the voltage drop detection signal VL (data input D of the flip-flop 14) changes from high to low (see FIG. 2C), the data output Q (supply control signal VC) of the flip-flop 14 Since it changes to the low level in synchronization with the fall of the next clock signal CLK, the clock signal CLK_OUT supplied to the logic circuit 2 is stopped after the high level pulse width is secured (FIG. 2 (d), ( e)).

  On the other hand, during the period when the voltage drop detection signal VL is at the low level, the output signal of the EXOR gate 13 is output in synchronism with the rise of the clock signal CLK (strictly, at the timing when the low level changes to the high level). When the level of the voltage drop detection signal VL changes from low to high, the output signal of the flip-flop 14 changes to high level in synchronization with the next rising of the clock signal CLK, so that the clock signal CLK_OUT for the logic circuit 2 Is started so that a high-level pulse width is secured.

  As described above, according to this embodiment, the clock stop timing generation circuit 12 synchronizes the timing of stopping the supply of the clock signal CLK to the logic circuit 2 with the falling edge of the clock signal CLK and restarts the supply. Since the timing to synchronize is synchronized with the rising edge of the clock signal CLK, the clock pulse has an appropriate width determined according to the frequency and duty ratio between the supply stop timing of the clock signal CLK and the timing at which the supply is restarted.

  Therefore, the voltage level of the logic circuit 2 fluctuates as in the case where an instantaneous interruption occurs in the power supply VDD. After the internal state is held by the diode 1 and the backup capacitor 3 (backup means), the clock signal CLK_OUT is supplied. When the operation is resumed, the operation can be reliably continued from the state before the operation is stopped. The clock stop timing generation circuit 12 can be made very simple by the flip-flop 14, the EXOR gate 13, and the AND gate 5.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The configuration of the control circuit is not limited to the timing generation circuit 12. In short, the timing for stopping the supply of the clock signal CLK is synchronized with the falling edge, and the timing for restarting the supply is synchronized with the rising edge. I just need it.
When the voltage drop detection signal VL is high active, a NOT gate may be inserted into the corresponding input terminal of the EXOR gate 13.

The figure which is one Example of this invention, and shows the structure of a clock supply control circuit Timing chart explaining operation of clock supply control circuit 1 equivalent diagram showing the prior art 2 equivalent diagram

Explanation of symbols

  In the drawings, 1 is a diode (backup means), 2 is a logic circuit, 3 is a backup capacitor (backup means), 4 is an oscillation circuit, 5 is an AND gate, 6 is a voltage drop detection circuit, 11 is a clock supply control circuit, 12 Is a clock stop timing generation circuit (control circuit), 13 is an EXOR gate, and 14 is a flip-flop.

Claims (2)

A voltage drop detection circuit that outputs a voltage drop detection signal when the power supply voltage falls below a lower limit; and
An oscillation circuit for supplying a clock signal to the logic circuit;
A control circuit for controlling the supply of the clock signal to stop when the voltage drop detection signal is output;
The control circuit synchronizes the timing of stopping the supply of the clock signal with the falling edge of the clock signal, and synchronizes the timing of restarting the supply of the clock signal with the rising edge of the clock signal. Clock supply control circuit. The control circuit includes a flip-flop, an EXOR gate, and an AND gate.
The flip-flop receives the voltage drop detection signal as data and the output signal of the EXOR gate as a clock.
The EXOR gate and the AND gate receive the output signal of the flip-flop and the clock signal output from the oscillation circuit,
2. The clock supply control circuit according to claim 1, wherein a clock signal is supplied to the logic circuit via the AND gate.

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