JP2009075578A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, capable of performing display while reducing a luminance inclination within a screen which is caused in accordance with polarity reversion of a common signal in frame reversing drive. <P>SOLUTION: A voltage level in a gate-off voltage VGL applied to a pixel transistor through a scanning line is changed by a change quantity of voltage level in the common signal Vcom synchronously with polarity reversion of the common signal Vcom. According to this, the change quantity of a pixel electrode potential Vs' which is changed according to the voltage level in the common signal Vcom can be equalized to the voltage level change quantity in the common signal Vcom, and the luminance inclination within the screen caused by polarity reversion can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device that changes a voltage level of a common electrode every predetermined frame.

  As a dot matrix type display panel used in a liquid crystal display device, a simple matrix type display panel and an active matrix type display panel are known. Among them, in an active matrix display panel, a plurality of scanning lines and a plurality of signal lines are arranged on the display panel so as to be orthogonal to each other, and a thin film transistor (Thin Film) is formed in the vicinity of the intersection of the scanning lines and the signal lines. A pixel electrode is arranged via a transistor (hereinafter referred to as TFT), a common electrode is disposed so as to face the pixel electrode, and a liquid crystal is filled between the pixel electrode and the common electrode to constitute a display pixel. is doing. Then, a display signal is applied from the signal line to the display pixel selected by the scanning signal input through the scanning line. A common signal is applied to the common electrode. At this time, a voltage corresponding to the difference between the display signal and the common signal is applied to the liquid crystal composing the display pixel, thereby changing the alignment state of the liquid crystal for display.

  Here, AC driving is essential for driving the liquid crystal for reasons such as extending the life. As this AC driving method, for example, frame inversion driving is known in which the polarity of the voltage applied to the liquid crystal is inverted for each frame (see, for example, Patent Document 1).

  11, FIG. 12A and FIG. 12B show applied voltage waveforms during frame inversion driving. FIG. 13 shows a model diagram during frame inversion driving.

By applying the scanning signal to the TFT, the display signal Vs is applied to the pixel electrode of the selected display pixel. At this time, the liquid crystal is applied with a voltage VLCD which is a difference between the pixel electrode potential Vs ′ as a display signal applied to the pixel electrode and the common signal Vcom applied to the common electrode, and display is performed. In the frame inversion driving, as shown in FIG. 11, the voltage level of both or one of the common signal Vcom and the display signal Vs applied to the common electrode is inverted for each frame around a predetermined center voltage. Yes.
JP 7-129127 A

In the case of frame inversion driving, as shown in FIGS. 12A and 12B, when the polarity of the common signal Vcom is inverted after the transition to the next frame period, the pixel electrode potential Vs is caused by the capacitive coupling effect. 'Changes by ΔV2. The amount of change ΔV2 at this time is CLcd as the equivalent capacitance of the liquid crystal filled between the pixel electrode and the common electrode, and Ccs as the capacitance of the auxiliary capacitance for holding the voltage applied to the liquid crystal until the next frame. The parasitic capacitance generated between the gate and the source of the TFT is Cgs, the amount of change in the voltage level of the common signal, that is, the common voltage level VcomH on the positive side and the common voltage level VcomL on the negative side with respect to the amplitude center voltage of the common signal. When the difference of Vcomp is Vcompp, it is expressed by the following equation. As shown in the following equation, ΔV2 becomes smaller than Vcompp due to the influence of the parasitic capacitance Cgs of the TFT, and as a result, the voltage applied to the liquid crystal after the polarity inversion of the common signal Vcom is applied to the liquid crystal before the polarity inversion. The voltage VLCD is smaller than the voltage VLCD by Vcompp−ΔV2.
ΔV2 = (CLcd + Ccs) × Vcompp / (Cgs + CLcd + Ccs)
Here, in a period T1 in which the voltage applied to the liquid crystal is reduced by Vcompp−ΔV2, the voltage polarity of the common signal Vcom is inverted, and then the TFT is turned on in the next frame, and the display signal Vs is again applied to the pixel electrode. This continues until the pixel electrode potential Vs ′ is updated. For this reason, for example, in the case of a liquid crystal display device that scans from the upper part of the screen toward the lower part of the screen, the TFT is turned on earlier in one frame period as the display pixel becomes the upper part of the screen, and the voltage applied to the liquid crystal Becomes shorter than the voltage VLCD to be originally applied by Vcompp−ΔV2. On the other hand, the period T1 in which the voltage applied to the liquid crystal is smaller than the voltage VLCD to be originally applied by Vcompp−ΔV2 becomes longer as the display pixel is at the lower part of the screen. Therefore, the effective voltage applied to the liquid crystal decreases in order from the display pixel at the top of the screen toward the display pixel at the bottom of the screen, and even when a display signal corresponding to the same display data is written to each display pixel. , A luminance gradient from the upper part of the screen to the lower part of the screen occurs.

  The present invention has been made in view of the above-described circumstances, and provides a display device capable of performing display while suppressing a luminance gradient in a screen that occurs due to polarity inversion of a common signal in frame inversion driving. For the purpose.

  In order to achieve the above object, the display device of the present invention has a liquid crystal between a pixel electrode to which a display signal is applied via a pixel transistor and a common electrode to which a common signal is applied between the display pixels. Each time a display signal having a sandwiched display panel and corresponding to display data for one screen is supplied to the display panel, the first voltage level is different from the first voltage level. In the display device in which the voltage level of the common signal is switched between the voltage conversion means for boosting the predetermined voltage and boosting the predetermined voltage to output from the voltage output terminal side of the smoothing capacitor; The voltage level at the reference voltage input terminal of the smoothing capacitor is synchronized with the voltage level change of the common signal and corresponds to the value corresponding to the first voltage level and the second voltage level. And switching means for switching to a value, characterized by comprising a scanning means for applying to the pixel transistor as the gate-off voltage boosted voltage output from the voltage output terminal side of the smoothing capacitor.

  According to the present invention, in frame inversion driving, it is possible to perform display while suppressing the luminance gradient in the screen that occurs in association with the polarity inversion of the common signal.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration of a liquid crystal display device as an example of a display device including a display driving device according to an embodiment of the present invention. The liquid crystal display device shown in FIG. 1 includes a display panel 10, a scan driver 20, a signal driver 30, a common signal generation circuit 40, a timing generator 50, a power supply circuit 60, and an input unit 70. .

  The display panel 10 includes a plurality of scanning lines arranged in the row direction and a plurality of signal lines arranged in the column direction, and the display shown in FIG. 2 is provided near each intersection of the scanning lines and the signal lines. A pixel is provided.

  FIG. 2 is a diagram showing an equivalent circuit of one display pixel provided in the display panel 10. A gate electrode of a thin film transistor (TFT) 11 is connected to the scanning line G shown in FIG. 2, and a drain electrode of the TFT 11 is connected to the signal line S. Further, a pixel electrode is connected to the source electrode of the TFT 11. A common electrode is disposed so as to face the pixel electrode, and liquid crystal is filled (sandwiched) between the pixel electrode and the common electrode. Further, a storage capacitor Ccs is connected in parallel to the liquid crystal capacitor CLcd configured as described above. In such a configuration, when a voltage is applied between the pixel electrode and the common electrode, the alignment state of the liquid crystal filled between the pixel electrode and the common electrode changes according to the voltage, and the liquid crystal layer The transmittance of light at is changed. Thereby, the transmission state of light from a light source (not shown) arranged on the back surface of the display pixel shown in FIG. 2 is changed, and image display is performed. FIG. 2 also shows parasitic capacitance Cgs generated between the gate electrode and the source electrode of the TFT 11 and between the scanning line and the pixel electrode.

  A scan line G in FIG. 2 is connected to the scan driver 20. For example, as illustrated in FIG. 3, the scan driver 20 performs each operation based on the vertical control signal Vsig output from the timing generator 50 and the first gate clock signal Hsig1 and the second gate clock signal Hsig2 as the horizontal control signal Hsig. A scanning signal is output to the scanning line. The first gate clock signal Hsig1 and the second gate clock signal Hsig2 are rectangular signals having opposite phases.

  As shown in FIG. 4, the schematic configuration of the main part of the scan driver 20 is configured by, for example, holding circuits 101, 102, 103, 104,... Corresponding to the number of scan lines (n stages) arranged in series. . Each holding circuit has an input terminal IN, an output terminal OUT, a reset terminal RST, a clock signal input terminal CK, a high potential power input terminal Th, and a low potential power input terminal Tl. . The vertical control signal Vsig is supplied to the input terminal IN of the first stage holding circuit 101 as the first stage input signal. Further, the output signal of the previous holding circuit is supplied to the input terminal IN of the second and subsequent holding circuits. Further, the output signal of the holding circuit at the next stage is supplied to the reset terminal RST of each holding circuit. Note that a reset signal END may be separately supplied to the reset terminal RST of the holding circuit (not shown) in the final stage (for example, the n-th stage), or the output signal of the holding circuit 101 in the first stage may be supplied. It is good also as a structure supplied.

  Further, the first gate clock signal Hsig1 is supplied to the clock signal input terminal CK of the odd-numbered holding circuit, and the clock signal input terminal CK of the even-numbered holding circuit is supplied to the first gate clock signal Hsig1. Thus, the second gate clock signal Hsig2 having an opposite phase is supplied. Further, the gate-on voltage VGH is supplied as the predetermined high voltage VGH to the high-potential power input terminal Th of each holding circuit, and the gate-off voltage VGL is supplied as the predetermined low voltage VGL to the low-potential power input terminal Tl of each holding circuit. Is done.

  As shown in FIG. 5, each holding circuit 101, 102, 103, 104,... Includes six MOS field effect transistors (hereinafter referred to as MOS transistors) T11 to T16, and a capacitor C. Have.

  As shown in FIG. 3, the scan driver 20 starts scanning in the frame in accordance with the vertical control signal Vsig, and in accordance with the first gate clock signal Hsig1 and the second gate clock signal Hsig2, During this period, voltage output such as switching from the gate-off voltage VGL to the gate-on voltage VGH is performed for each scanning line in order from the scanning line G (1) at the foremost stage to the scanning line G (n) at the last stage.

  That is, the scan driver 20 sequentially turns on the TFTs corresponding to the scan line for each scan line, and writes the display signal output to the signal line at this time to the corresponding pixel electrode.

Here, the scan driver 20 in the present embodiment is configured such that two types of off-voltage levels VGL_1 and VGL_2 can be alternately supplied in accordance with the timing of polarity inversion of the common signal Vcom as the gate-off voltage VGL of the scan signal. ing. Here, the relationship between VGL_1 and VGL_2 is
VGL_2 = VGL_1 + Vcomppp
It is.

  The two types of off-voltage levels of the scanning signal will be described in detail later. For example, the voltage generated by the power supply circuit 60 and supplied to the scanning driver 20 is VGL_1 and VGL_2 in accordance with the polarity inversion timing of the common signal Vcom. It can be obtained by controlling the power supply circuit 60 so that it is output with an amplitude between. That is, the power supply circuit 60 supplies the VGL_1 and VGL_2 as gate-off voltages to the scan driver 20 in a time-sharing manner, and the scan driver 20 outputs the supplied gate-off voltage to each scan line.

  2 is connected to the signal driver 30, and R (red) input from the input unit 70 based on the horizontal control signal Hsig output in synchronization with the horizontal synchronization signal from the timing generator 50. , G (green), and B (blue) display data for each line is taken in, and a display signal Vs corresponding to the fetched display data is generated and supplied to the signal line S. Further, the voltage level of the display signal Vs is inverted around a certain center voltage in accordance with the polarity inversion control signal Pol input from the timing generator 50 as the frame starts. That is, each time the signal driver 30 supplies a display signal corresponding to display data for one screen to the display panel 10, the voltage level of the display signal Vs becomes a voltage level that inverts the polarity of the voltage applied to the liquid crystal. The center voltage at the center is reversed.

  The common signal generation circuit 40 alternately selects two types of common voltages VcomH and VcomL supplied by the power supply circuit 60 in response to the polarity inversion control signal Pol input from the timing generator 50 at the start of the frame. A common signal Vcom is generated and supplied to the common electrode.

  The timing generator 50 generates the vertical control signal Vsig and the polarity inversion control signal Pol as described above based on the vertical synchronization signal input from the input unit 70, and based on the horizontal synchronization signal input from the input unit 70. The horizontal control signal Hsig is generated, and the generated control signals are supplied.

  The power supply circuit 60 generates and supplies various drive voltages in the scanning driver 20, the signal driver 30, and the common signal generation circuit 40, and includes a booster circuit that boosts the power supply voltage Vcc, which will be described in detail later. ing.

Next, the operation of the display device having the configuration as shown in FIG. 1 will be described.
When the vertical synchronization signal is supplied via the input unit 70, the timing generator 50 generates the polarity inversion control signal Pol and the vertical control signal Vsig. The vertical control signal Vsig is output to the scanning driver 20 and the signal driver 30, and the polarity inversion control signal Pol is output to the signal driver 30, the common signal generation circuit 40, and the power supply circuit 60. When a horizontal synchronization signal is supplied via the input unit 70, the timing generator 50 generates a horizontal control signal Hsig and outputs it to the scanning driver 20 and the signal driver 30.

  When the vertical control signal Vsig is input, the scan driver 20 starts scanning the scan line in the frame, and the signal driver 30 starts supplying the display signal corresponding to the display data in the frame to the signal line. .

  The scan driver 20 sequentially applies the gate-on voltage VGH to each scan line G for each scan line as a scan signal for turning on the TFTs 11 for one row in synchronization with the horizontal control signal Hsig. At this time, the gate off voltage VGL is applied as a scanning signal to the scanning line corresponding to the TFT 11 to be turned off. Then, as the off-voltage level of the gate-off voltage VGL, one of the values of VGL_1 and VGL_2 supplied from the power supply circuit 60 in a time division manner is automatically applied according to the timing. In addition, the signal driver 30 supplies a scanning signal corresponding to a display pixel for which the scanning driver 20 turns on the TFT 11 by the scanning signal.

  On the other hand, the common signal generation circuit 40 alternately applies the common voltages VcomL and VcomH having different voltage levels to the common electrode every time the polarity inversion control signal Pol is received. Here, the common signal generation circuit 40 supplies VcomL during the positive period (period where Vs> Vcom), and supplies VcomH during the negative period (period where Vs <Vcom). That is, the common signal generation circuit 40 uses the signal driver 30 as a signal line to display a display signal in which the voltage applied to the liquid crystal has a negative polarity, VcomH which is a positive voltage level with respect to the amplitude center voltage of the common signal Vcom. It outputs in the negative electrode period which is a supply period. In addition, the common signal generation circuit 40 outputs VcomL, which is a voltage level on the negative electrode side, in a positive period during which the signal driver 30 supplies a signal line with a display signal in which the voltage applied to the liquid crystal is positive. .

  In the display panel 10, when the display signal Vs is applied to the TFT 11 that is turned on by supplying the gate-on voltage in the scanning signal, the display signal Vs is applied to the pixel electrode via the TFT 11 in the display pixel. Held as. As a result, a voltage corresponding to the difference between the pixel electrode potential Vs ′ and the common signal Vcom (VcomL or VcomH) is applied to the liquid crystal. As a result, the alignment state of the liquid crystal is changed, and the light transmittance in the liquid crystal layer is changed to perform display.

  As described above, the scan driver 20 applies the off voltage VGL_1 or VGL_2 to the scan line G as the scan signal for turning off the TFTs 11 for one row at the timing when the writing of the display signal Vs to the display pixel is completed. . Here, in the present embodiment, the voltage level of the gate-off voltage in the scanning signal is switched from VGL_2 to VGL_1 at the timing when the voltage level of the common signal is switched from VcomH to VcomL, and is turned off at the timing when the voltage level of the common signal is switched from VcommL to VcomH. The voltage level is switched from VGL_1 to VGL_2.

  Note that even if the voltage level of the gate-off voltage applied to the gate electrode of the TFT 11 via the scan line is switched between VGL_1 and VGL_2, the TFT 11 is a value that can maintain the off state and is applied to the liquid crystal. The voltage is held by the auxiliary capacitor Ccs when the next display signal Vs is applied (that is, until the TFT 11 is turned on again in the next frame).

FIG. 6 shows a time-series change of the pixel electrode potential Vs ′ during the frame inversion driving in the present embodiment. FIG. 7 shows a model diagram during frame inversion driving in the present embodiment. As shown in FIG. 6, in the present embodiment, the scanning signal off-voltage level is switched from VGL_2 to VGL_1 in response to the common signal Vcom switching from the voltage level VcomH to VcomL, and the voltage level of the common signal Vcom is changed from VcomL. The off voltage level of the scanning signal is switched from VGL_1 to VGL_2 in accordance with the switching to VcomH. Thereby, the change amount ΔV2 of the pixel potential VLCD at the time of polarity inversion is
ΔV2 = Vcomppp
It can be.

  That is, in this embodiment, the same voltage level change as the voltage level change amount in the common signal Vcom is also applied to the gate-off voltage VGL of the scanning signal. Thereby, the change amount ΔV2 of the pixel electrode potential Vs ′ at the time of polarity inversion can be made the same as the change amount Vcompp of the voltage level in the common signal Vcom. Therefore, the applied voltage VLCD (applied voltage to the liquid crystal) applied to the liquid crystal, which is the difference between the pixel electrode potential Vs ′ and the common signal Vcom, does not change before and after the polarity inversion. As a result, even when the same luminance is displayed on one screen, a luminance gradient is not generated from the upper part of the screen to the lower part of the screen.

  Hereinafter, the generation of the voltage levels VcomL and VcomH of the common signal and the OFF voltage levels VGL_1 and VGL_2 of the scanning signal in the power supply circuit 60 will be described in detail based on FIGS. 8, 9, 10A, and 10B. Describe.

  As shown in FIGS. 8 and 9, the power supply circuit 60 is applied to the first voltage conversion unit 60 </ b> A that generates the negative voltage level VcomL applied to the common signal based on the power supply voltage Vcc, and the common signal. A positive voltage side voltage level VcomH, and a second voltage conversion unit 60B that generates OFF voltage levels VGL_1 and VGL_2 applied to the scanning signal.

  The first voltage conversion unit 60A includes, for example, a charge pump type booster circuit 61 (hereinafter referred to as the first inversion circuit 61 for the sake of convenience) that boosts the power supply voltage Vcc by about −1 times. For example, it includes four switches Sa1, Sa2, Sa3, Sa4, a boosting capacitor Ca1, and a smoothing capacitor Ca2. The first inversion circuit 61 includes a first connection state in which the switches Sa1 and Sa3 are on (short) and the switches Sa2 and Sa4 are off (open), and the switches Sa1 and Sa3 are off and the switches Sa2 and Sa4 In the second connection state. By switching between the first connection state and the second connection state at a predetermined cycle, the first inverting circuit 61 is controlled so that the voltage at the VcomL output terminal Ta is maintained at the target voltage level VcomL. The The first inverting circuit 61 further includes a regulator that DC adjusts the voltage output to the VcomL output terminal Ta, and further controls the voltage DC-adjusted by the regulator to the negative voltage level VcomL. May be configured to output.

  The second voltage conversion unit 60B includes four charge pump type booster circuits each of which outputs a predetermined voltage after boosting or polarity inversion, that is, a first booster circuit 62, a second booster circuit 63, and a third booster circuit. 64 and a second inversion circuit 65, which are connected in series.

  The first booster circuit 62, for example, boosts the power supply voltage Vcc by about twice to generate the voltage level VcomH, and generates the voltage level VcomH as a process of generating the off-voltage levels VGL_1 and VGL_2. The first booster circuit 62 includes four switches Sb1, Sb2, Sb3, and Sb4, a boost capacitor Cb1, and a smoothing capacitor Cb2. The first booster circuit 62 includes a third connection state in which the switches Sb1 and Sb3 are on and the switches Sb2 and Sb4 are off, and a fourth state in which the switches Sa1 and Sa3 are off and the switches Sa2 and Sa4 are on. Connection state. By switching between the third connection state and the fourth connection state at a predetermined cycle, the first booster circuit 62 can maintain the voltage at the VcomH output terminal Tb at a preset voltage level VcomH. Control is made. The first booster circuit 62 further includes a regulator that DC adjusts the voltage output to the VcomH output terminal Tb, and further controls the voltage DC-adjusted by the regulator to the negative voltage level VcomH. May be configured to output.

  The second booster circuit 63 boosts the first boosted voltage 2Vcc as the voltage level VcomH boosted and output by the first booster circuit 62 approximately twice, and outputs this as the second boosted voltage. It is composed of two switches Sc1, Sc2, Sc3, Sc4, a boosting capacitor Cc1, and a smoothing capacitor Cc2. The second booster circuit 63 includes a fifth connection state in which the switches Sc1 and Sc3 are on and the switches Sc2 and Sc4 are off, and a sixth connection state in which the switches Sc1 and Sc3 are off and the switches Sc2 and Sc4 are on. Connection state. By switching between the fifth connection state and the sixth connection state at a predetermined cycle, the second booster circuit 63 is controlled so that the output voltage is maintained at a preset voltage level, for example, 4 Vcc. .

  The third booster circuit 64 boosts the second boosted voltage 4Vcc boosted and output by the second booster circuit 63 approximately twice, and outputs the boosted voltage as a third boosted voltage. The third booster circuit Sd1, Sd2 , Sd3, Sd4, a boosting capacitor Cd1, and a smoothing capacitor Cd2. The third booster circuit 64 includes a seventh connection state in which the switches Sd1 and Sd3 are on and the switches Sd2 and Sd4 are off, and an eighth state in which the switches Sd1 and Sd3 are off and the switches Sd2 and Sd4 are on. Connection state. By switching between the seventh connection state and the eighth connection state at a predetermined cycle, the third booster circuit 64 is controlled so that the output voltage is maintained at a preset voltage level, for example, 8 Vcc. .

  The second inverting circuit 65 generates off voltage levels VGL_1 and VGL_2 based on the third boosted voltage 8Vcc boosted and output by the third booster circuit 64 and the VcomL and VcomH generated as described above. It is composed of five switches Se1, Se2, Se3, Se4, Sw1, an inverting capacitor Ce1, and a smoothing capacitor Ce2.

  Here, one end (voltage output terminal Tx side) of the smoothing capacitor Ce2 is connected to the off-voltage level output terminal To, and the other side (reference voltage input terminal Ty side) is the common signal voltage level input terminal Ti ( Hereinafter, it is connected to the input terminal Ti). The input terminal Ti is connected to either the VcomL output terminal Ta or the VcomH output terminal Tb by a switch Sw1 that switches connection between terminals in synchronization with the polarity inversion control signal Pol. Specifically, the switch Sw1 is connected to the terminal Ta as shown in FIG. 8 so that the voltage level at the terminal Ti becomes VcomL when the voltage level of the common signal Vcom applied to the common electrode is VcomL. Connected to the input terminal Ti. Further, the switch Sw1 has a terminal Tb and an input terminal as shown in FIG. 9 so that the voltage level at the input terminal Ti becomes VcomH when the voltage level of the common signal Vcom applied to the common electrode is VcomH. Connect to Ti.

  The second inversion circuit 65 includes a ninth connection state in which the switches Se1 and Se3 are on and the switches Se2 and Se4 are off, and a second connection circuit 65 in which the switches Se1 and Se3 are off and the switches Se2 and Se4 are on. 10 connection states are switched at a predetermined cycle. The switching cycle here is preferably sufficiently shorter than the switching cycle of the voltage level in the common signal Vcom.

  In the second voltage conversion unit 60B, the voltages as shown in FIGS. 10 (a) and 10 (b) corresponding to the two different voltage levels of the common signal applied to the common electrode in this way. Two types of off-voltage levels VGL_1 and VGL_2 having different levels can be generated and output in a time division manner. The potential difference between the OFF voltage levels VGL_1 and VGL_2 generated in this way is advantageously equal to the potential difference between the voltage levels VcomL and VcomH of the common signal Vcom.

  In the present embodiment, the off-level scanning signal voltages VGL_1 and VGL_2 are generated in a time-division manner by the common second voltage conversion unit 60B. Compared with the case where VGL_1 and VGL_2 are individually generated, the number of parts can be reduced and the circuit scale can be reduced, which is preferable.

  Although the present invention has been described based on the above embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention. For example, in the example shown in FIG. 6, the switching timing of the voltage level of the gate-off voltage VGL of the scanning signal is matched with the polarity inversion timing of the common signal Vcom. However, if the switching of the voltage level of the gate-off voltage VGL of the scanning signal and the polarity inversion of the common signal Vcom are performed within the vertical blanking period provided at the frame break, the off-voltage level of the gate-off voltage VGL in the scanning signal Even if the switching timing and the polarity inversion timing of the common signal Vcom deviate from each other, it is possible to prevent the occurrence of a luminance gradient in the screen without affecting the display state. In other words, if the switching of the off-voltage level of the gate-off voltage and the polarity inversion of the common signal Vcom in the scanning signal are performed within the vertical blanking period provided at the frame break, the switching timing of the off-voltage level is more than necessary. Even if the polarity reversal timing is not coincident, it is preferable because no inconvenience is caused in the display state.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

It is a figure which shows the structure of the liquid crystal display device as an example of a display apparatus provided with the display drive device which concerns on one Embodiment of this invention. It is a figure which shows the equivalent circuit of a display pixel. It is a timing chart for demonstrating the relationship of the switching timing of the voltage level in a scanning signal and a common signal. It is a figure which shows schematic structure in the principal part of a scanning driver. It is a figure which shows the structure of a holding circuit. It is a figure which shows the applied voltage waveform at the time of the frame inversion drive in one Embodiment of this invention. It is a model figure at the time of the frame inversion drive in one Embodiment of this invention. It is explanatory drawing of the power supply circuit in the case of producing | generating VGL_1 corresponding to VcomL. It is explanatory drawing of the power supply circuit in the case of producing | generating VGL_2 corresponding to VcomH. It is explanatory drawing of the pressure | voltage rise flow in a power supply circuit, (a) is a figure which shows the case where VGL_1 is produced | generated corresponding to VcomL, (b) is a figure which shows the case where VGL_2 is produced | generated corresponding to VcomH. is there. It is explanatory drawing of a common signal. It is a figure which shows the applied voltage waveform at the time of the conventional frame inversion drive, (a) is a figure which shows the applied voltage waveform of the display pixel in which writing is carried out comparatively ahead in each frame, (b) is each figure It is a figure which shows the applied voltage waveform of the display pixel in which writing is carried out relatively later in the frame. It is a model figure at the time of the conventional frame inversion drive.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display panel, 20 ... Scan driver, 30 ... Signal driver, 40 ... Common voltage generation circuit, 50 ... Timing generator, 60 ... Power supply circuit, 70 ... Input part

Claims (3)

A display panel in which liquid crystal is sandwiched between a pixel electrode to which a display signal is applied via a pixel transistor and a common electrode to which a common signal common to each display pixel is applied;
Each time a display signal corresponding to display data for one screen is supplied to the display panel, the voltage of the common signal is between a first voltage level and a second voltage level different from the first voltage level. In the display device where the level changes,
Voltage converting means for outputting a boosted voltage obtained by boosting a predetermined voltage from the voltage output terminal side of the smoothing capacitor;
The voltage level at the reference voltage input terminal of the smoothing capacitor is switched between a value corresponding to the first voltage level and a value corresponding to the second voltage level in synchronization with the voltage level change of the common signal. Switching means;
Scanning means for applying a boosted voltage output from the voltage output terminal side of the smoothing capacitor to the pixel transistor as a gate-off voltage;
A display device comprising:   The switching means is configured such that the voltage level applied to the common electrode is a value corresponding to the first voltage level when the voltage level applied to the common electrode is the first voltage level. 2. The display device according to claim 1, wherein the voltage level at the reference voltage input terminal of the smoothing capacitor is switched so as to be a value corresponding to the second voltage level at the second voltage level. . The voltage conversion means includes a plurality of booster circuits each connected in series,
3. The display device according to claim 1, wherein a first-stage booster circuit boosts a predetermined power supply voltage, and a final-stage booster circuit outputs the boosted voltage having a polarity different from that of the power supply voltage. .

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