JP2009071035A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can reliably manufacture a resistance element with a resistance value easily controlled at a low temperature coefficient, a capacity element which has a large capacity value per unit area, thereby reducing an occupied area, and has a small voltage dependency, and a MOS type semiconductor element on a same semiconductor substrate, and can be attempted to reduce a manufacturing process. <P>SOLUTION: The manufacturing method of the semiconductor device has the steps of: introducing a second p type impurity into an n well containing a gate electrode and the resistance element to form a p channel type MOSFET and adjust the resistance value of the resistance element; and introducing a third n type impurity into an upper layer electrode of a capacity element containing a first p type impurity to convert into an n type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a MOS type semiconductor element, a resistance element, and a capacitor as semiconductor circuit elements formed on a semiconductor substrate.

Some semiconductor devices incorporate a large number of various circuit elements necessary for the manifestation of their functions as elements built in a semiconductor substrate as their functions increase. In general, as circuit elements incorporated in a semiconductor substrate in this way, there are transistor elements such as MOSFETs, resistance elements, capacitance elements, etc., among these circuit elements, as for resistance elements and capacitance elements that are passive elements, There is a strong demand for keeping the occupied area small while ensuring high accuracy in the characteristic aspect, and further that the fluctuation of the characteristic value due to the use temperature and the use voltage is sufficiently low, ideally no characteristic fluctuation.
Under such circumstances, the manufacturing method of each of these circuit elements is made possible by simplifying the manufacturing process by integrating the configuration and sharing the process as much as possible, and improving the functionality of the semiconductor device and the electrical characteristics. Therefore, there is a demand for a manufacturing method that can achieve high accuracy. However, in recent years, miniaturization of each circuit element pattern has progressed, and while avoiding the influence of the complicated and refined manufacturing conditions accompanying the miniaturization as much as possible, maintaining quality and reliability. As described above, it has become increasingly difficult to achieve a manufacturing method that satisfies all conditions such as little or no characteristic variation in each circuit element. Two known examples of the manufacturing method for making such a semiconductor device with small characteristic variation are shown below.

As shown in FIG. 2A, the semiconductor device manufacturing method of the first example forms insulating films 99-1, 99-2 on a silicon substrate 100, and then these insulating films 99-1, 99-2. A step of laminating a non-doped polysilicon film on the substrate, and forming a MOSFET having an LDD (Lightly Doped Drain) structure and a polysilicon resistor having a temperature coefficient of zero on this non-doped polysilicon film. The present invention relates to a manufacturing method characterized in that it is used for forming an element and a capacitor element having a small voltage dependency (Patent Document 1).
According to Patent Document 1, a p-well region (not shown) and an n-well region 98 are formed in a surface layer of a silicon semiconductor substrate 100, and a thick oxide film 99-1 having a predetermined pattern is formed on the entire surface of the substrate. An oxide film 99-2 is provided, and the first phosphorus-doped polysilicon film formed over the oxide films 99-1 and 99-2 is formed under the gate electrode 101-2 and the capacitor 131. After processing into a predetermined pattern such as the electrode 101-1 (FIG. 2A), the nMOS (not shown) in the p-well region and the pMOS region 130 in the n-well 98 are used as a mask. each by performing an LDD (Lightly Doped Drain) ion implantation, n ^- regions (not shown) and p ^- to form a respective low-concentration diffusion layer regions 102, then the thickness of about 20nm to about 35nm In forming a thermal oxide film 103 over the entire surface (Figure 2 (b)). Next, a second non-doped polysilicon film 104 is laminated to a thickness of 200 nm and formed over the entire surface (FIG. 2C).

Next, the second-layer polysilicon film 104 is selectively processed into a predetermined pattern (FIG. 2D). At this time, sidewalls 104-3, which are part of the second non-doped polysilicon film 104, are sandwiched between the thermal oxide films 103 on both side walls of the first polysilicon film 101-2 as the gate electrode. Is formed as an etching residue. Further, a polysilicon film 104-1 serving as an upper layer electrode is formed on the polysilicon film 101-1 serving as a lower layer electrode of the capacitive element 131 with an insulating film 103 interposed therebetween (FIG. 2D). Next, a photoresist is formed by selectively opening a region to be an n-type MOS (not shown), and n-type impurity As is ion-implanted using the photoresist as a mask to form an n-type diffusion layer (FIG. Not shown). Similarly, as shown in FIG. 2E, a photoresist 106 is formed by selectively opening a region 130 to be a p-type MOS, a capacitive element 131, and a resistive element 132, and the photoresist 106 is used as a mask to form a p-type. BF ₂ as an impurity is ion-implanted to form a p-type diffusion layer 107 serving as a source and a drain. At the same time, the second layer for forming the capacitive element 131 and the second polysilicon film region 104-2 on the thick insulating film 99-1 and serving as the resistance element 132 having a zero temperature coefficient. BF _2, which is a p-type impurity, is also implanted from above the polysilicon film 104-1, and simultaneously with the formation of the p-type diffusion layer 107, the resistance of the upper electrode 104-1 of the capacitor 131 is reduced and the resistance of the temperature coefficient is zero. There is a description that ion implantation for forming the element 104-2 is performed (Patent Document 1).

Regarding the temperature coefficient of the resistance value of the polysilicon resistance element, Patent Document 1 generally determines the amount of BF ₂ ions implanted into the non-doped polysilicon film and the annealing temperature, and the resistance value depends on the amount of BF ₂ ions implanted and annealing. Determined by temperature and film thickness. For example, when the annealing temperature is 900 ° C., which is the reflow temperature of a BPSG (Boro Phospho Silicate Glass) film, when the thickness of the non-doped polysilicon film 104-2 is 200 nm, the implantation amount of BF ₂ ions is 5 When it is 0.0 × 10 ¹⁴ cm ⁻² , the resistance value of the polysilicon resistance element is 1.4 kΩ / □ to 1.6 kΩ / □, and the temperature coefficient of the resistance value is −1500 ppm / ° C. When the implantation amount of BF ₂ ions is 3.0 × 10 ¹⁵ cm ⁻² , the temperature coefficient of the resistance value becomes zero at 395Ω / □ to 405Ω / □. From the above, it is said that a polysilicon resistance element having a temperature coefficient of resistance value of zero or small can be formed by controlling the implantation amount and film thickness of BF ₂ ions (Patent Document 1).
Similarly, a second manufacturing method shown below is also known as a manufacturing method including the formation of a capacitive element with small characteristic fluctuation, for example, low voltage dependency (Patent Document 2). According to the capacitor formed by this manufacturing method, as shown in FIG. 3, the acceleration voltage is 15 KeV and the dose is 5 × 10 ¹⁵ / cm ² over the entire surface of the polysilicon film that becomes the upper electrode 108 of the capacitor. P (phosphorus) is ion-implanted under conditions, and impurities are added. On the other hand, the polysilicon film constituting the lower layer electrode sandwiching the capacitive insulating film 111 has a low concentration in which P (phosphorus) is ion-implanted under the conditions of an acceleration voltage of 15 KeV and a dose of 1 × 10 ¹⁵ / cm ^2. The region 109 and the high concentration region 110 into which P (phosphorus) is additionally implanted under the conditions of an acceleration voltage of 15 KeV and a dose of 7 × 10 ¹⁵ / cm ² , that is, the total dose is 8 × 10 ¹⁵ / cm ^2. A region to be implanted is selectively formed using a resist pattern, and an impurity is added. Therefore, the polysilicon film of the lower electrode has a configuration in which a region 109 having a low impurity concentration and a region 110 having a high impurity concentration are formed with respect to the impurity concentration in the polysilicon film 108 of the upper electrode. Among these, with respect to the impurity concentration in the polysilicon film of the upper layer electrode, the capacitance characteristics of the polysilicon film region 109 of the lower electrode with a low impurity concentration and the region 110 with a high impurity concentration have voltage dependence opposite to each other. For the sake of illustration, the polysilicon film 108 of the upper electrode covers the regions having different impurity concentrations through the capacitive insulating film 111, that is, the polysilicon films 109 and 110 of the lower electrode having the opposite voltage dependence, so that each voltage It is described that it is possible to form a capacitor element that works in the direction of canceling the dependency and has less voltage dependency (Patent Document 2).
JP 2001-196541 A JP-A-11-54700

  However, the two examples of the semiconductor device manufacturing method described above as known examples have the following problems. In the known example of the first example, referring to FIG. 2B, a film 103 obtained by thermally oxidizing the first polysilicon film 101-1 is used as a capacitor insulating film. Since the oxidation rate is as fast as 2 to 3 times that of the silicon semiconductor substrate, it is difficult to control the oxide film on the polysilicon film 101-1 to be a capacitive insulating film so as to be thinly formed. On the other hand, since the capacitance value is inversely proportional to the thickness of the capacitive insulating film, increasing the capacitive insulating film increases the area occupied by the capacitive element required to obtain the same capacitance value, which is a requirement for miniaturization. On the other hand, there is a problem that it is contrary. In addition, in order to make the first polysilicon film conductive, a high concentration impurity is added here. On the other hand, a polysilicon film containing a high concentration impurity is oxidized. The thermal oxide film formed in this manner has a poor quality because it contains a large amount of impurities, which causes a problem in terms of reliability. In addition, when the first polysilicon film is oxidized, non-uniform oxidation along the crystal grain boundary (grain boundary) of the polycrystalline body proceeds, and the unevenness of the surface of the first polysilicon film as the lower layer electrode is increased. Since local electric field concentration occurs in the local thin film portion of the oxide film generated in accordance with the size, deterioration of the breakdown voltage as a capacitive insulating film becomes a problem.

Further, as shown in FIG. 2D, when the second polysilicon film 104 is etched, the remaining portion is used as a spacer 104-3 for the first gate electrode. When it is necessary to form the second-layer polysilicon wiring across the second polysilicon, the second-layer polysilicon wiring is short-circuited, causing a problem that the circuit does not function. In addition, in order to form the second-layer polysilicon wiring with high accuracy, it is necessary to use an anisotropic etching apparatus. In this case, due to the characteristics of the etching method, As a result, the second-layer polysilicon film 104-3 hardly remains. Therefore, it is difficult to use the second-layer polysilicon as the spacer 104-3 that can obtain predetermined electrical characteristics. Further, in this first example, although a polysilicon resistance element having a low temperature coefficient or a low temperature coefficient or a high resistance polysilicon resistance element can be formed, as a capacitive element, as described above, a polysilicon film is used. Since the thermally oxidized oxide film becomes a capacitive insulating film, it is difficult to reduce the thickness, and there is a limit to increasing the capacity per unit area.
In the second known example described above, a capacitive element with low voltage dependency can be formed. However, as in the example described in Patent Document 2, for example, P (phosphorus) is used as an n-type impurity. ) Is high, and the effect of promoting the crystal growth of the polysilicon film is large, so that the sheet resistance is lower than the same dose amount of BF ₂ or B as p-type impurities. . For this reason, the area required for forming the same resistance value increases, and the problem remains that it is contrary to the miniaturization of elements. Further, in this example, a method for forming a polysilicon resistance element having a low temperature coefficient is not particularly described.

From the above description, in the conventional method for manufacturing a semiconductor device, in addition to a resistor having a low temperature coefficient and a resistor having a high resistance value, all the capacitor elements having a large capacitance value per unit area and a small voltage dependency are formed on the same substrate. However, the characteristics and performance of an analog circuit designed using these elements are not necessarily satisfactory and satisfactory.
The present invention has been made in view of the above-described problems. An object of the present invention is to provide a resistance element with a low temperature coefficient and easy resistance control on the same semiconductor substrate, and a capacitance per unit area. Providing a method for manufacturing a semiconductor device that can manufacture a capacitor element and a MOS type semiconductor element that have a large value and can occupy a small area and have a low voltage dependence, and can shorten the manufacturing process. There is to do.

According to the first aspect of the present invention, the thin insulating film covering the n-well surface and the p-well surface formed on the surface layer of the silicon substrate and the thick insulating film is formed so as to surround the thin insulating film. A first step of forming a first polysilicon film containing a first n-type impurity on the entire surface after forming each of the insulating films; and a gate electrode disposed on the thin insulating film. And a second step of processing each of the lower electrodes of the capacitive element disposed on the thick insulating film, a third step of forming a CVD oxide film serving as a capacitive insulating film on the lower electrode, and the entire surface. A fourth step of processing the second polysilicon film into an upper layer electrode of the capacitive element and a resistance element disposed on the insulating film after introducing a predetermined amount of the first p-type impurity into the second polysilicon film; The p-well including the gate electrode a fifth step of forming an n-channel MOSFET by introducing an n-type impurity; a second p-type impurity is introduced into the n-well including the gate electrode and the resistance element; A sixth step of adjusting the resistance value of each of the resistance elements; a seventh step of introducing a third n-type impurity into the upper electrode of the capacitive element containing the first p-type impurity to convert it into an n-type; , The object of the present invention can be achieved.
According to the invention of claim 2, a fourth n-type impurity is formed in the p-well including the gate electrode and a third p-type is formed in the n-well between the fourth step and the fifth step. A fourth step of forming a low-concentration region by introducing respective impurities; and a CVD insulating film is formed on the entire surface, and then the CVD insulating film is formed on both side walls of the gate electrode by anisotropic etching of the CVD insulating film. The method of manufacturing a semiconductor device according to claim 1, wherein a step 4-2 of forming an insulating film on the entire surface is inserted while leaving the substrate as a spacer.

According to a third aspect of the present invention, the first n-type impurity and the third n-type impurity are phosphorus, the second n-type impurity is arsenic, and the fourth n-type impurity. A method for manufacturing a semiconductor device according to claim 2, wherein is a phosphorus or arsenic.
According to a fourth aspect of the present invention, the impurity concentration of phosphorus, which is the first n-type impurity, is 1 × 10 ²⁰ / cm ³ or more, and the introduction of phosphorus, which is the third n-type impurity. Is performed by ion implantation, and the dose is 5 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .
According to the invention of claim 5, the introduction of arsenic as the second n-type impurity is performed by an ion implantation method, and the dose amount is 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ^16. / cm ^2, the introduction of phosphorus or arsenic is the fourth n-type impurity is performed by ion implantation, the dose is 3 × 10 ¹³ / cm ² to 5 × 10 ¹⁴ / cm ² at which claims A method of manufacturing a semiconductor device according to claim 3 in the range described above.
According to the invention described in claim 6, the p-type impurity is boron or boron fluoride. The method for manufacturing a semiconductor device according to claim 1 or 2.

According to a seventh aspect of the present invention, the introduction of the first p-type impurity is performed by an ion implantation method, the dose is 1 × 10 ¹⁵ / cm ² or less, and the second p-type impurity is introduced. The introduction of the third p-type impurity and the third p-type impurity is performed by an ion implantation method, and the dose is 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ¹⁵ / cm ^2. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by an ion implantation method, and the dose is 3 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁴ / cm ² .
According to the invention of claim 8, the method of manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the CVD oxide film is an HTO film or a TEOS film. And
According to the ninth aspect of the present invention, the thickness of the CVD oxide film is 10 nm to 40 nm. The method for manufacturing a semiconductor device according to the eighth aspect of the present invention is provided.
According to a tenth aspect of the present invention, the CVD insulating film is a silicon oxide film or a silicon nitride film. The semiconductor device manufacturing method according to the second aspect of the present invention is provided.
In order to achieve the object of the present invention, the first polycrystal of the first layer containing a predetermined amount of P (phosphorus) is formed through an insulating film formed on a silicon substrate. A step of forming a silicon film on the entire surface, a step of processing the first polysilicon film of the first layer into a predetermined shape, forming a gate electrode and a lower layer electrode of a capacitor element on the insulating film, and silicon by CVD Forming a capacitive insulating film by forming an oxide film on the entire surface; forming a second polysilicon film on the second layer; and boron as a p-type impurity on the entire surface of the second polysilicon film. A step of introducing a predetermined amount, a step of processing the second polysilicon film of the second layer into a predetermined shape, and a resist mask having an opening only in a region for forming an n-channel type element including the gate electrode. As a certain amount of arsenic And forming the n-type diffusion layer in the silicon substrate on both sides of the gate electrode, removing the resist mask, and forming the p-channel type element including the gate electrode and the predetermined shape 2 A predetermined amount of boron or boron fluoride is introduced as a p-type impurity by a resist mask having an opening in a partial region of the second polysilicon film of the layer, and a p-type diffusion layer is formed in the silicon substrate on both sides of the gate electrode. In addition, a step of making the second polysilicon film of the second layer a resistance element having a low temperature dependency, and a resist in which a part of the second polysilicon film of the second layer processed into the predetermined shape is opened A predetermined amount of phosphorus is introduced as an impurity by a mask, and a capacitor element having a small voltage dependency is formed using the second polysilicon film of the second layer containing the phosphorus impurity as an upper electrode.

  Alternatively, when the transistor structure is an LDD (Lightly Doped Drain) structure, an n-channel element including a gate electrode is formed on a semiconductor substrate in which the second polysilicon film of the second layer is processed into a predetermined shape. A step of introducing a low dose of an n-type impurity with a resist mask having an opening only in the region, and forming a low-concentration n-type diffusion layer in the silicon substrate on both sides of the gate electrode; removing the resist mask; A step of introducing a low dose amount of p-type impurities and forming a low-concentration p-type diffusion layer in the silicon substrate on both sides of the gate electrode by using a resist mask having an opening in a region for forming a p-channel device containing Forming an insulating film on the entire surface; etching the entire surface of the insulating film; and forming a CVD insulating film on both side walls of the gate electrode. A high concentration n-type diffusion layer is formed by introducing more than the low dose of arsenic as an n-type impurity by forming a pacer and a resist mask having an opening only in a region for forming an n-channel device including the gate electrode. Forming a source and drain region by separating the CVD insulating film spacer width from each other on the silicon substrate on both sides of the gate electrode, removing the resist mask, and forming a p-channel device including the gate electrode Boron is introduced as a p-type impurity in a larger amount than the low dose by a resist mask having an opening in a region and a part of the second polysilicon film processed into the predetermined shape. A type diffusion layer is formed in the silicon substrate on both sides of the gate electrode with the width of the CVD insulating film spacer spaced apart to form a source and drain region, and a second layer of second poly By using a recon film as a resistance element having a low temperature dependency and a resist mask having an opening in a partial region of the second polysilicon film processed into the predetermined shape, phosphorus is provided as an n-type impurity. A capacitor element having a small voltage dependency is formed by quantitatively introducing and using the second polysilicon film of the second layer containing phosphorus impurities as an upper layer electrode.

  According to the present invention, a resistance element having a low temperature coefficient and easy control of a resistance value, a capacitance value per unit area that is large, and can occupy a small area, and have a small voltage dependency on the same semiconductor substrate It is possible to provide a method for manufacturing a semiconductor device that can manufacture an element and a MOS semiconductor element with high reliability and shorten the manufacturing process.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1-1, FIG. 1-2, FIG. 8-1, and FIG. 8-2 are diagrams for each of the main manufacturing steps in order to describe the manufacturing method of the semiconductor device according to the first and second embodiments of the present invention, respectively. It is principal part sectional drawing of a semiconductor substrate. FIG. 4 is a characteristic relationship diagram showing the variation of the capacitance value with respect to the voltage applied to the polysilicon electrode with the dose amount of P (phosphorus) ion implantation into the polysilicon electrode of the capacitor element according to the present invention as a parameter. FIG. 5 is a characteristic relationship diagram showing a relationship between a dose amount of a capacitive element having a polysilicon upper layer electrode to which phosphorus is added at a high concentration and voltage dependency of a capacitance value. FIG. 6 is a characteristic relationship diagram showing the relationship between the dose amount and the voltage dependency of the capacitance value of the capacitive element having the polysilicon upper layer electrode to which As (arsenic) is added at a high concentration. FIG. 7 is a characteristic relationship diagram showing the relationship between the dose amount and the voltage dependence of the capacitance value of the capacitive element having the polysilicon upper layer electrode to which boron is added at a high concentration. FIGS. 9 and 10 are evaluation diagrams of the breakdown voltage of the capacitive element for comparing the conventional example with the present invention.

Hereinafter, embodiments according to a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings. FIGS. 1-1 and 1-2 are cross-sectional views of relevant parts on the surface side of a semiconductor substrate for explaining a method for manufacturing a semiconductor device according to the first embodiment. On the silicon semiconductor substrate 2 having a p-well region 51 and an n-well region 52 separated by a thick oxide film 1 on one surface of the silicon semiconductor substrate 2 and further having a thick oxide film 1 formed in a predetermined region. A silicon oxide film 3 having a thickness of 4 to 30 nm is formed on the entire surface. A polysilicon film having a P (phosphorus) (first n-type impurity) concentration of 1 × 10 ²⁰ / cm ³ or more is formed on the silicon oxide film 3. 4 is formed on the entire surface (FIG. 1-1A). As described above, the polysilicon film 4 containing phosphorus is formed by using, for example, SiH ₄ (monosilane) or Si ₂ H ₆ (disilane) as a main source gas by a low pressure CVD (Chemical Vapor Deposition) method. PH ₃ (phosphine) gas for doping impurities is added to SiH ₄ (monosilane) and Si ₂ H ₆ (disilane) by a method of ion implantation of P (phosphorus) into a non-doped polysilicon film or a low pressure CVD method. Alternatively, a doped polysilicon film formed using these as main source gases may be used.
Next, a photoresist is coated, and a resist 7 corresponding to the region 5 to be a gate electrode and the region 6 for forming the capacitor element on the thick oxide film 1 is left by photolithography. Using this resist 7 as a mask, the polysilicon film 4 is etched to form a polysilicon film 4-2 in the region 5 to be the gate electrode and a polysilicon film 4-1 to be the lower electrode of the capacitor element (FIG. 1). 1 (b)).

Next, the resist 7 in FIG. 1-1 (b) is removed, and a capacitive insulating film 8 is formed on the entire surface with a thickness of, for example, 10 to 40 nm (FIG. 1-1 (c)). As the capacitor insulating film 8, for example, when an HTO (High Temperature Oxide) film or a TEOS (Tetra Ethyl Ortho Silicate) film formed by a low pressure CVD method is used, it is excellent in terms of step coverage and dielectric strength characteristics. Good capacitance element characteristics can be obtained.
Next, a polysilicon film 9 is formed on the entire surface on which the capacitor insulating film 8 is formed, for example, with a thickness of 100 to 300 nm (FIG. 1-1D). The polysilicon film 9 is preferably a non-doped polysilicon film formed by SiH ₄ (monosilane) or Si ₂ H ₆ (disilane) as a main source gas, for example, by a low pressure CVD method. Next, the first p-type impurity B (boron) or BF ₂ is, for example, 1 × 10 ¹⁵ / cm ² or less, preferably 1 × 10 ¹⁴ / cm ² to the entire surface where the polysilicon film 9 is formed. Ions are implanted at a dose in the range of 1 × 10 ¹⁵ / cm ² to determine the characteristics of the polysilicon resistance element 32 having a high sheet resistance formed in the next process (FIG. 1-1 (e)). The reason for using B (boron) or BF ₂ as a p-type impurity as an impurity introduced here is that the activation rate of the impurity is low, for example, when compared with P (phosphorus) as an n-type impurity of the same dose amount. This is because the sheet resistance value of the polysilicon film 9 can be controlled to be high. However, even when P (phosphorus) which is an n-type impurity is used, a similar sheet resistance value can be obtained if the dose is made lower than B (boron) and BF ₂ which are p-type impurities. When phosphorus is used, the dose is reduced and the variation in sheet resistance is increased. Therefore, it is not preferable to B (boron) or BF ₂ described above.

Next, a photoresist is coated, and the resist 12 on the regions 10 and 11 where the resistive element 32 on the thick oxide film 1 is formed and on the region 6 where the capacitive element 31 is formed is left by photolithography. As a mask, the polysilicon film 9 is etched to form a polysilicon film 9-1 as an upper electrode of the capacitive element 31 and a polysilicon resistor 9-2 constituting the resistance element 32 (FIG. 1-1 (f)). ). As a result, the capacitive element 31 having the polysilicon film 4-1 as the lower layer electrode and the polysilicon film 9-1 as the upper layer electrode is formed in the region 6 via the capacitive insulating film 8. At this time, since the etching of the polysilicon film 9 shown in FIG. 1-1E is performed under conditions sufficiently larger than the etching rate of the capacitive insulating film 8, the thickness of the capacitive insulating film 8 is 10 nm or more. If so, the etching can be stopped at the semiconductor substrate 2 and the capacitive insulating film 8 existing on the surface of the polysilicon film 4-1 as the lower electrode processed into a predetermined shape.
Next, the resist 12 in FIG. 1-1 (f) is removed, the photoresist is again coated, and a resist 14 having an opening in the region 13 where the n-type MOSFET 33 is formed is formed by photolithography. The n-type impurity As (arsenic) is ion-implanted with a dose amount in the range of 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ¹⁵ / cm ² and an acceleration voltage of 20 to 80 KeV, and the source and drain of the n-type MOSFET 33 The diffusion layer 15 is formed (FIGS. 1-2 (g)). At this time, since the n-type impurity ion implantation into the silicon semiconductor substrate 2 is performed through the silicon oxide film 3 and the capacitor insulating film 8, the total thickness of the silicon oxide film 3 and the capacitor insulating film 8 becomes 40 nm or more. It is necessary to set the acceleration voltage for ion implantation to be high so that n-type impurity ions can surely enter the semiconductor substrate 2. However, when the acceleration voltage for ion implantation is high, n-type impurity ions penetrate through the polysilicon film 4-2 as the gate electrode and reach the lower gate oxide film 3 and further the lower semiconductor substrate 2, and the device characteristics. This may cause problems such as fluctuations in reliability and a decrease in reliability.

Next, the resist 14 in FIG. 1-2 (g) is removed, the photoresist 18 is coated again, and the region 16 where the p-type MOSFET 34 is formed by photolithography and the thick oxide film 1 in the above step. Of the processed polysilicon film 9-2, a resist 18 having an opening in the resistance element forming region 10 and a contact region of the polysilicon film 9 (not shown) is formed, and for example, B, which is a second p-type impurity, is formed. (Boron) or BF ₂ is ion-implanted at a dose in the range of 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ¹⁵ / cm ² (FIG. 1-2 (h)). At this time, the ion implantation of the p-type impurity is performed through the thin capacitive insulating film 8. As a result, the source and drain diffusion layers 40 of the p-type MOSFET 34 are formed, and at the same time, only the region 10 out of the resistance element formation regions 10 and 11 is formed. A polysilicon resistance element 32 having a small temperature coefficient is formed in the polysilicon film 9-2. The contact region (not shown) is a high-concentration p-type impurity region formed in a partial region of the high-resistance polysilicon 32. This is a contact resistance with a metal wiring formed in a later step. Is performed in order to reduce the variation and suppress the variation.
Next, the resist 18 in FIG. 1-2 (h) is removed, the photoresist 20 is coated again, and a resist 20 having an opening in the capacitor element region 19 is formed by photolithography, and a third n-type impurity is used. A certain amount of P (phosphorus) is ion-implanted, for example, at a dose of 4 × 10 ¹⁵ / cm ^{2 to} 1 × 10 ¹⁶ / cm ² (FIG. 1-2 (i)). As a result, a capacitive element 31 is formed in which the polysilicon film 4-1 containing phosphorus is used as a lower layer electrode, the capacitor insulating film 8 is sandwiched, and the polysilicon film 9-1 is used as an upper layer electrode. In this capacitive element 31, first, since the impurities in the polysilicon film of the lower layer electrode 4-1 and the upper layer electrode 9-1 are the same n-type impurity P (phosphorus), there is no work function difference between the two electrodes. Second, the P (phosphorus) concentration in the polysilicon film 4 as the lower layer electrode is 1 × 10 ²⁰ / cm ³ or more, and in addition, P (phosphorus) into the polysilicon film 9-1 as the upper layer electrode Since the dose amount of ion implantation is set to a high concentration as described above, depletion of the upper and lower polysilicon films is suppressed, so that it is possible to obtain capacitive element characteristics with low voltage dependency.

FIG. 4 relates to the semiconductor device described with reference to FIGS. 1-1 and 1-2 in the case where the dose amount of P (phosphorus) ion implantation into the polysilicon film 9-1 which is the upper layer electrode is changed. It is a characteristic relationship figure shown about capacity value change to applied voltage. 4 to 10, a phrase including a number such as 1.00E + 16 described as a dose amount or a mole current value is a simplified expression representing 1.00 × 10 ⁺¹⁶ in this case. The same applies to other similar descriptions. FIG. 4 is a characteristic relationship diagram in which the capacitance value change amount when a voltage is further applied to the polysilicon film 9-1 as the upper electrode is shown with reference to the capacitance value when the applied voltage is 0 V (the vertical axis indicates the capacitance). It can also be said that the applied voltage on the horizontal axis). From FIG. 4, as the dose amount to the upper electrode is larger, for example, when the dose amount is 4.5 × 10 ¹⁵ / cm ² or more, the variation of the capacitance with respect to the applied voltage becomes smaller (the voltage dependency of the capacitance is smaller). It is shown that. In the description with reference to FIG. 1-2 (i), since the dose amount of phosphorus to the upper electrode is 4 × 10 ¹⁵ / cm ^{2 to} 1 × 10 ¹⁶ / cm ^2, it is a capacitive element with small voltage dependency. I understand that. 5 to 7 are characteristic relationship diagrams showing the voltage dependency of the capacitance at various ion implantation doses. In FIG. 5 (the vertical axis indicates the phosphorus ion implantation dose (cm ⁻² ), and the horizontal axis indicates the voltage dependency (ppm / V) of the capacitance—the smaller the number, the smaller the voltage dependency). When the dose of P (phosphorus) ions implanted into -1 exceeds 4 × 10 ¹⁵ / cm ² or more, the voltage dependency of the capacitive element becomes 1200 ppm / V or less, and the dose is 7.5 × 10 By setting it to ¹⁵ / cm ² , the voltage dependency of the capacitive element is reduced to about 200 ppm / V. However, excessive P (phosphorus) ion implantation into the polysilicon film 9-1 causes damage to the capacitive insulating film, and acts to reduce the quality and reliability of the capacitive insulating film. Even if the implantation dose is higher than 9 × 10 ¹⁵ / cm ² or more, the voltage dependence shows a characteristic of being saturated in the vicinity of 0. Therefore, P (phosphorus) into the polysilicon film 9-1 It is desirable that ion implantation be limited to 1 × 10 ¹⁶ / cm ² or less in consideration of variations.

On the other hand, FIG. 6 shows a case where As (arsenic) which is the same n-type impurity is used instead of phosphorus shown in FIG. 5, or a case where BF ₂ which is a p-type impurity is used as shown in FIG. The vertical axis is the ion implantation dose of arsenic or boron (cm ^-2 ), and the horizontal axis is the voltage dependence of capacitance (ppm / V)). The dose is set to a high concentration similar to phosphorus. However, for the reasons described above, the voltage dependency of the capacitive element is limited to about 1200 ppm / V, which is not preferable because it does not become any smaller. Therefore, phosphorus is preferable for introducing impurities into the upper electrode of the capacitor.
Next, the resist 20 in FIG. 1-2 (i) is removed, and an interlayer insulating film 21 is formed on the entire surface (FIG. 1-2 (j)). At this time, the ion-implanted impurities are simultaneously activated by a heat treatment process for ensuring flatness performed in the process of forming the interlayer insulating film. Subsequently, a connection hole (contact hole), a metal wiring, and a protective film are sequentially formed. Since these steps are similar to the conventional manufacturing method, detailed steps are omitted here. Further, the present invention shows the same effect not only for one-layer metal wiring but also for multilayer metal wiring.

FIGS. 8A and 8B are schematic cross-sectional views of the surface side of the semiconductor substrate arranged for each main process in order to explain the method of manufacturing the semiconductor device according to the second embodiment of the present invention. The second embodiment is different from the manufacturing method according to the first embodiment in that it has a step of forming a spacer on the side surface of the gate electrode in order to form an LDD (Lightly Doped Drain) MOSFET. With respect to the previous steps until the step of etching the polysilicon film 9-1 shown in FIG. 8-1 (a), the steps from FIG. 1-1 (a) to FIG. 1-1 (f) are performed. Since it is the same as the process of, description is omitted.
Next, the photoresist 14 is coated, and a resist 14 having an opening in the region 13 where the n-type MOSFET 33 is formed is formed by photolithography. For example, P (phosphorus) or As (arsenic), which is a fourth n-type impurity, is formed. For example, ions are implanted at a low dose of 1 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁴ / cm ² to form the low-concentration diffusion layer 22 of the n-type MOSFET 33 (FIG. 8-1 (b)). At this time, for example, B (boron) or BF ₂ may be further ion-implanted as a reverse conductivity type p-type impurity to improve the breakdown voltage of the miniaturized element.
Next, the resist 14 in FIG. 8-1 (b) is removed, the photoresist 24 is coated again, and a resist 24 having an opening in the region 23 for forming the p-type MOSFET 34 is formed by photolithography. The third p-type impurity B (boron) or BF ₂ is ion-implanted at a low dose in the range of 1 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁴ / cm ² , for example. A concentration diffusion layer 25 is formed (No. 8-1 (c)). At this time, for example, P (phosphorus) may be ion-implanted as an n-type impurity of reverse conductivity type to improve the breakdown voltage of the miniaturized element.

Next, the resist 24 in the 8-1 (c) is removed, and a silicon oxide film 26 is formed on the entire surface by, for example, a low pressure CVD method (FIG. 8-1 (d)). Even when the silicon oxide film 26 is a silicon nitride film, the same result can be obtained. Next, the silicon oxide film 26 formed in the step of FIG. 8-1 (d) is subjected to RIE (Reactive Ion Etching) etching over the entire surface to obtain polysilicon films 4-1, 4-2, polysilicon film 9-1, Silicon oxide film spacers 27 are formed on the side walls of 9-2 (8-1 (e)). At this time, the silicon substrate 2, the polysilicon films 4-1 and 4-2, and the polysilicon films 9-1 and 9-2 exist below the silicon oxide film 26. Is extremely smaller than the etching rate of the silicon oxide film 26 and can be set to a condition with a high selection ratio. Therefore, the silicon substrate 2, the polysilicon films 4-1 and 4-2, and the polysilicon film 9 can be set. -1 and 9-2 remain in an almost intact shape.
On the other hand, according to this process flow, since the silicon oxide film spacer 27 is formed after the structure of the capacitive element 31 is formed, the surface of the polysilicon film 4-1 as the lower layer electrode of the capacitive element 31 is formed. Will not be damaged by etching. Next, in order to cover the surfaces of the silicon substrate 2, the polysilicon films 4-1 and 4-2, and the polysilicon films 9-1 and 9-2 exposed in the process of forming the silicon oxide film spacer 27, for example, heat A silicon thermal oxide film 28 is formed by oxidation (FIG. 8-2 (f)). The formation of the thermal oxide film 28 is performed for the purpose of protecting the silicon substrate from damage, contamination, etc. caused by ion implantation performed in the subsequent process, but may be omitted if the ion implantation conditions are low acceleration. is there.

On the other hand, even in this process, according to the process flow of the present invention, since the process is after the structure of the capacitive element 31 is formed, the polysilicon film (4-1 in the interface region in contact with the capacitive insulating film 8 above and below) 9-1) The surface is not oxidized, and irregularities on the surface of the polysilicon film 4-1 are generated due to the difference in the oxidation rate at the crystal grain boundary as described in the section of the problem to be solved. In other words, a very smooth surface can be obtained, and the capacitive element 31 with high quality and reliability can be formed. As an example, with respect to the case where the thickness of the capacitive insulating film 8 is 27 nm, the breakdown voltage evaluation result of the capacitive element 131 in which the surface of the polysilicon film 101 described in FIG. FIG. 9 shows a breakdown voltage evaluation result of the capacitive element 31 formed according to the present invention. 9 and 10, the horizontal axis represents voltage, and the vertical axis represents leakage current. In the conventional capacitive element 131 (FIG. 9) of FIG. 2D, the leakage current suddenly rises from around 5 V, the breakdown voltage is about 4 MV / cm, and the variation is large, whereas the capacitive element 31 ( In FIG. 10), the rise of the leak current is slow, a breakdown voltage of 8 MV / cm or more is obtained, and no defect with a significantly low breakdown voltage is observed.
Next, a photoresist is coated, and a resist 14 having an opening in the region 13 where the n-type MOSFET 33 is to be formed is formed by photolithography. For example, a second n-type impurity is formed using the resist 14 and the silicon oxide film spacer 27 as a mask. As (arsenic) is ion-implanted at a dose of 1 × 10 ¹⁵ / cm ² to 6 × 10 ¹⁵ / cm ² to form the source and drain diffusion layers 15 of the n-type MOSFET 33 (FIG. 8-2 g)). Next, the resist 14 in FIG. 8-2 (g) is removed, and the photoresist is coated again, and the region 23 where the p-type MOSFET 34 is formed by photolithography, polysilicon processed on the thick oxide film A resist 29 having an opening in the region 10 of the film 9-2 and a partial region of the polysilicon film (not shown) is formed, and, for example, B (boron) or BF ₂ as the second p-type impurity is changed to 1 × 10 ¹⁵ / Ions are implanted at a dose of cm ² to 6 × 10 ¹⁵ / cm ² (FIG. 8-2 (h)). Next, the resist 29 in FIG. 8-2 (h) is removed, the photoresist is coated again, and a resist 20 having an opening in the capacitor element region 19 is formed by photolithography, and a third n-type impurity is used. Certain P (phosphorus) is ion-implanted, for example, at a dose of 5 × 10 ¹⁵ / cm ² or more and 1 × 10 ¹⁶ / cm ² or less (FIG. 8-2 (i)). Next, the resist 20 in FIG. 8-2 (i) is removed, an interlayer insulating film 21 is formed on the entire surface, and subsequently connection holes (contact holes), metal wiring, and a protective film (not shown) are sequentially formed. (FIG. 8-2 (j)).

As described above, by using the method for manufacturing a semiconductor device according to the present invention, it is possible to simultaneously form a resistor element and a capacitor element constituting an analog element in addition to a transistor element such as a MOSFET. Among these, as for the resistance element, in addition to the high resistance element having a relatively high sheet resistance, a resistance element having a small temperature coefficient can be formed. By using a small resistance element, it is possible to configure a highly accurate circuit while ensuring a degree of design freedom. Furthermore, with regard to the capacitive element, it is possible to form a capacitive element having a large capacitance value per area and low voltage dependency by using the manufacturing method of the present invention. An accurate circuit can be configured. As a result, by using the manufacturing method of the present invention, it is possible to reduce the occupied area while ensuring high accuracy, and further to configure an analog circuit with sufficiently low fluctuations in characteristic values due to operating temperature and operating voltage. This makes it possible to increase the functionality of the semiconductor device.
According to the manufacturing method of the semiconductor device concerning Examples 1 and 2 demonstrated above, the merit shown below can be acquired. The first merit is that the first layer first polysilicon film, the capacitor insulating film, and the second layer second polysilicon film, which are the steps for forming the capacitor element, can be continuously formed. Since no unnecessary steps are involved, the influence of particles, contamination, etc. can be kept low. Further, in the conventional example, when forming the capacitor insulating film by thermally oxidizing the first polysilicon film of the first layer, the polysilicon film contains impurities at a high concentration and further along the crystal grain boundary. Unevenness on the surface of the first polysilicon film of the first layer formed by the difference in oxidation rate may cause local electric field concentration. As a result, in the conventional example, there is a problem in the quality and reliability as the capacitive insulating film, but in the present invention, since the capacitive insulating film is formed by the CVD method, the problem as in the conventional example does not occur, and the capacitive insulating film The quality and reliability of the film can be improved.

As a second merit, a polysilicon resistance element having a relatively high sheet resistance is formed by introducing p-type impurities over the entire surface after forming the second polysilicon film of the second layer. If the dose amount is 1 × 10 ¹⁵ / cm ² or less, it can be arbitrarily set without affecting other elements. Usually, there are a circuit that requires high accuracy including a temperature coefficient and a circuit that does not require high accuracy but requires a high resistance value. In general, in order to form a polysilicon resistance element having high accuracy including a temperature coefficient, it is necessary to introduce an impurity amount to a supersaturated region to reduce concentration variation and resistance value variation. In this case, since the impurity concentration is high, the sheet resistance value of the polysilicon resistance element is low. Accordingly, if only a high-precision polysilicon resistance element with a low temperature coefficient is used, the resistance value is low, so the area occupied by the resistance element increases and the number of chips per wafer decreases, which is disadvantageous in terms of productivity. become. On the other hand, in the present invention, a polysilicon resistor element having an arbitrarily high sheet resistance value can be formed by arbitrarily setting the impurity amount by introducing p-type impurities after forming the second polysilicon film of the second layer. It is possible, the degree of freedom of design is high, and the chip area can be reduced.
As a third merit, by forming the capacitor insulating film with a thickness of 10 nm or more and 40 nm or less by the CVD method, the capacitance value per area can be increased as the first, and as a result, the area occupied by the capacitor element Can be reduced. As the second, in the present invention, after processing the second polysilicon film of the second layer into a predetermined shape, various impurities are introduced to form the upper electrode of the capacitor element. Since the remaining film of the capacitive insulating film after processing the polysilicon film is as thin as at least 10 nm or more and 40 nm or less, this capacitive insulating film can be used as it is as a permeable film at the time of phosphorus ion implantation. As a result, P (phosphorus), which is an n-type impurity, is dosed at a dose of 4 × 10 ¹⁵ / cm ² using a resist mask having an opening in a partial region of the second polysilicon film of the second layer processed into a predetermined shape. Through the ion implantation of 1 to 10 × 10 ¹⁶ / cm ² , the voltage dependence when the p-type impurity or n-type impurity As (arsenic) is ion-implanted to form the upper electrode of the capacitor element is about 1200 ppm / V. However, it is possible to form a capacitor element with a small voltage dependency.

  As a fourth merit, a boron ion impurity introducing step for making the second polysilicon film of the second layer a resistance element having a low temperature coefficient and a p-type diffusion layer forming step for the p-channel type device are respectively provided. Since the required dose amounts are approximately equal, they can be performed simultaneously without being performed separately, and the number of processes may be reduced.

It is a schematic sectional drawing (the 1) of the semiconductor substrate for every manufacturing process of the semiconductor device concerning Example 1 of this invention. It is a schematic sectional drawing (the 2) of the semiconductor substrate for every manufacturing process of the semiconductor device concerning Example 1 of this invention. It is a schematic sectional drawing of the semiconductor substrate for every manufacturing process of the semiconductor device concerning the manufacturing method of the conventional semiconductor device. It is a schematic sectional drawing of the capacitive element part produced in the conventional semiconductor device. It is a characteristic relationship figure which shows the relationship of the capacitance value fluctuation | variation with respect to an applied voltage by making into a parameter the dose amount of P (phosphorus) ion implantation to a polysilicon electrode concerning this invention. It is a relationship figure which shows the voltage dependence of the dose amount at the time of ion-implanting P (phosphorus) to the upper layer electrode concerning this invention, and a capacitance value. FIG. 6 is a relational diagram showing voltage dependency of a dose amount and a capacitance value when As (arsenic) is ion-implanted into an upper layer electrode for comparison with FIG. 5 according to the present invention. FIG. 6 is a relational diagram showing voltage dependency of a dose amount and a capacitance value when BF ₂ is ion-implanted into an upper layer electrode for comparison with FIG. 5 according to the present invention. It is a schematic sectional drawing (the 1) of the semiconductor substrate for every manufacturing process of the semiconductor device concerning Example 2 of this invention. It is a schematic sectional drawing (the 2) of the semiconductor substrate for every manufacturing process of the semiconductor device concerning Example 2 of this invention. It is a pressure | voltage resistant evaluation figure which shows the relationship between the proof pressure of the capacitive element formed by the prior art example, and leakage current. It is a pressure | voltage resistant evaluation figure which shows the relationship between the proof pressure of the capacitive element formed with the manufacturing method of the semiconductor device of this invention, and leakage current.

Explanation of symbols

1. 1. Thick insulating film 2. Silicon substrate 4. Silicon oxide film, 4.1th layer polysilicon film 5. gate electrode region; 6. Capacitor element formation region Resist pattern, 8. 9. Capacitance insulating film 9.2 layer polysilicon film Resistance element formation region 11. 11. Resistance element formation region Resist pattern 13. 14. n-type MOSGET formation region; Resist pattern 15. 15. n-channel MOS source and drain diffusion layers; p channel type MOS formation region 17. 17. a partial region of the resistive element region 11, Resist pattern 19. A region including a capacitive element, 20. Resist pattern 21. Interlayer insulating film, 22. Low concentration diffusion layer of n-type MOSFET 23. p-type MOSFET formation region, 24. Resist pattern 25. 25. Lightly doped diffusion layer of p-type MOSFET Silicon oxide film 27. Silicon oxide film spacer, 28. Silicon oxide film 29. Resist pattern,
31. Capacitance element 32. Resistance element 33. n-channel MOS 34. p-channel MOS
40. p-channel MOS source and drain diffusion layers.

Claims (10)

After forming a thin insulating film covering the n-well surface and p-well surface formed on the surface layer of the silicon substrate and a thick insulating film formed so as to surround the thin insulating film, the first n-type is formed on the entire surface. A first step of forming a first polysilicon film containing impurities;
A second step of processing the first polysilicon film into a gate electrode disposed on the thin insulating film and a lower layer electrode of a capacitive element disposed on the thick insulating film;
A third step of forming a CVD oxide film serving as a capacitive insulating film on the lower electrode;
After introducing a predetermined amount of the first p-type impurity into the second polysilicon film deposited on the entire surface, the second polysilicon film is processed into an upper layer electrode of the capacitive element and a resistance element disposed on the insulating film. And a fourth step to
A fifth step of forming an n-channel MOSFET by introducing a second n-type impurity into the p-well including the gate electrode;
A sixth step of introducing a second p-type impurity into the n-well including the gate electrode and the resistance element to form a p-channel MOSFET and adjust a resistance value of the resistance element, respectively;
A seventh step of introducing a third n-type impurity into the upper electrode of the capacitive element containing the first p-type impurity to convert it into an n-type;
A method for manufacturing a semiconductor device, comprising: A fourth n-type impurity is introduced into the p-well including the gate electrode and a third p-type impurity is introduced into the n-well between the fourth and fifth steps to form a low concentration region. 1 process,
Forming a CVD insulating film on the entire surface, then leaving the CVD insulating film as a spacer on both side walls of the gate electrode by anisotropic etching of the CVD insulating film, and forming an insulating film on the entire surface;
The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is inserted. 3. The first n-type impurity and the third n-type impurity are phosphorus, the second n-type impurity is arsenic, and the fourth n-type impurity is phosphorus or arsenic. A method for manufacturing a semiconductor device. The impurity concentration of phosphorus as the first n-type impurity is 1 × 10 ²⁰ / cm ³ or more, the introduction of phosphorus as the third n-type impurity is performed by ion implantation, and the dose amount is 4 × 10 ^15. 4. The method of manufacturing a semiconductor device according to claim 3, wherein cm ^<-2 > to 1 * 10 ^{< 16} > cm ^<-2 >. Arsenic, which is the second n-type impurity, is introduced by an ion implantation method, and its dose is 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ¹⁵ / cm ² , and phosphorus, which is the fourth n-type impurity. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the introduction of arsenic is performed by an ion implantation method, and the dose is 3 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁴ / cm ² . 3. The method of manufacturing a semiconductor device according to claim 1, wherein each of the p-type impurities is boron or boron fluoride. The introduction of the first p-type impurity is performed by an ion implantation method, the dose is 1 × 10 ¹⁵ / cm ² or less, and the introduction of the second p-type impurity and the third p-type impurity is performed by an ion implantation method. The dose is 1 × 10 ¹⁵ / cm ^{2 to} 6 × 10 ¹⁵ / cm ² , the introduction of the third p-type impurity is performed by an ion implantation method, and the dose is 3 × 10 ^{13. 3. The} method of manufacturing a semiconductor device according to claim 1, wherein the method is / cm ² to 5 × 10 ¹⁴ / cm ² . The method for manufacturing a semiconductor device according to claim 1, wherein the CVD oxide film is an HTO film or a TEOS film. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the thickness of the CVD oxide film is 10 nm to 40 nm. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the CVD insulating film is a silicon oxide film or a silicon nitride film.

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